CN117542793A - Method for preparing semiconductor structure - Google Patents
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- CN117542793A CN117542793A CN202311539010.8A CN202311539010A CN117542793A CN 117542793 A CN117542793 A CN 117542793A CN 202311539010 A CN202311539010 A CN 202311539010A CN 117542793 A CN117542793 A CN 117542793A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 93
- 238000006243 chemical reaction Methods 0.000 claims abstract description 67
- 239000006227 byproduct Substances 0.000 claims abstract description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 229920000642 polymer Polymers 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims description 165
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 20
- 229910052799 carbon Inorganic materials 0.000 claims description 17
- 230000010363 phase shift Effects 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 15
- 230000003667 anti-reflective effect Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000004215 Carbon black (E152) Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000005284 excitation Effects 0.000 claims description 4
- 229930195733 hydrocarbon Natural products 0.000 claims description 4
- 150000002430 hydrocarbons Chemical class 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- -1 hydrocarbon fluoride Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application relates to a preparation method of a semiconductor structure, which comprises the steps of forming an anti-reflection layer and a graphical photoresist layer on the upper surface of an oxide layer included in an initial semiconductor structure; etching the oxide layer based on the anti-reflection layer and the patterned photoresist layer in a first preset etching atmosphere to form an opening, wherein the opening exposes the surface of part of the dielectric layer; the first preset etching atmosphere comprises a first gas and a second gas, part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching an oxide layer under the first preset etching atmosphere; and removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer. The method can improve the reliability of the chip.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
Currently, in the manufacturing process of a semiconductor structure, it is generally required to connect a gate electrode, a source electrode, a drain electrode, etc. of a transistor through an interconnection plug and a metal connection line to realize the function of a chip. In forming the interconnect plugs, it is generally necessary to form contact holes first, and then deposit metal (e.g., tungsten) or the like in the contact holes to form the interconnect plugs.
However, in the process of forming the contact hole, the etching process is stopped in advance due to accumulation of some reaction byproducts, and the aperture of the bottom of the formed contact hole is narrower, so that the formed interconnection plug is difficult to connect the transistor to generate a short circuit, and the reliability of the chip is lower.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing a semiconductor structure against the problem of low chip reliability in the prior art.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor structure, including:
providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, a conductive layer, a dielectric layer, an oxide layer and a plurality of gate structures which are arranged at intervals; wherein each gate structure is located over the substrate; the conductive layer is positioned on top of each gate structure and on top of the substrate between each gate structure; the dielectric layer covers the surface of the gate structure and the surface of the conductive layer; the oxide layer covers the surface of the dielectric layer and the surface of the substrate;
forming an anti-reflection layer and a graphical photoresist layer on the upper surface of the oxide layer;
etching the oxide layer based on the anti-reflection layer and the patterned photoresist layer in a first preset etching atmosphere to form an opening, wherein the opening exposes part of the surface of the dielectric layer; the first preset etching atmosphere comprises a first gas and a second gas, wherein part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching the oxide layer under the first preset etching atmosphere;
and removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer.
According to the preparation method of the semiconductor structure, the anti-reflection layer and the patterned photoresist layer are formed on the upper surface of the oxide layer, and the oxide layer is etched to form an opening based on the anti-reflection layer and the patterned photoresist layer under a first preset etching atmosphere, so that the surface of part of the dielectric layer is exposed out of the opening; the first preset etching atmosphere comprises a first gas and a second gas, part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching an oxide layer under the first preset etching atmosphere; and removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer. The unexpected technical effect of this application is: because in the process of removing the oxide layer by using the second gas, the first reaction by-product can be quickly removed by the reaction of the first gas and the first reaction by-product, the problem that the aperture of the bottom of the contact hole is narrower due to the fact that the first reaction by-product is accumulated on the surface of the oxide layer can be avoided, and the reliability of the chip can be improved.
In one embodiment, the first gas comprises oxygen and the second gas comprises a four carbon hexafluoride gas.
In one embodiment, in the first preset etching atmosphere, a ratio of the oxygen to the four carbon hexafluoride gas is 0.9: 1-1.1: 1.
in one embodiment, the step of etching the oxide layer to form an opening based on the anti-reflective layer and the patterned photoresist layer in a first predetermined etching atmosphere includes:
and under the first preset etching atmosphere, providing excitation for the first gas and the second gas by adopting preset low-frequency offset power so as to etch the oxide layer based on the reflecting layer and the patterned photoresist layer to form an opening.
In one embodiment, the preset low frequency offset power is 2400w to 2800w.
In one embodiment, the step of forming an anti-reflection layer and patterning the photoresist layer on the upper surface of the oxide layer includes:
forming an anti-reflection phase shift film layer, a dark anti-reflection layer, a photoetching oxide layer and a bottom anti-reflection layer on the upper surface of the oxide layer in sequence from bottom to top so as to form the anti-reflection layer, and forming a photoetching material layer on the upper surface of the anti-reflection layer;
removing a part of the photoresist layer based on a photomask to form the patterned photoresist layer, wherein the patterned photoresist layer comprises an initial opening, and the initial opening exposes the surface of the bottom anti-reflection layer;
and sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening, so that the initial opening exposes the surface of the oxide layer.
In one embodiment, the step of sequentially removing a portion of the bottom anti-reflective layer, a portion of the photo-resist oxide layer, a portion of the dark anti-reflective layer, and a portion of the anti-reflective phase shift film layer based on the initial opening includes:
sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening in a second preset etching atmosphere; the second preset etching atmosphere comprises the first gas, the second gas and the third gas, wherein the first gas is also used for generating chemical reaction with a second reaction byproduct, and the second reaction byproduct is a polymer generated by etching the bottom anti-reflection layer under the second preset etching atmosphere.
In one embodiment, the first gas comprises oxygen, the second gas comprises fluorocarbon gas, and the third gas comprises fluorocarbon gas.
In one embodiment, in the second preset etching atmosphere, the ratio of the oxygen to the mixed gas is 0.033: 1-0.05: 1, a step of; wherein the mixed gas is a mixed gas of the fluorocarbon gas and the hydrocarbon fluorocarbon gas.
In one embodiment, the step of etching the oxide layer to form an opening based on the anti-reflective layer and the patterned photoresist layer in a first predetermined etching atmosphere includes:
and in a first preset etching atmosphere, adjusting the gas flow direction to increase the diffusion ratio of the first gas and the second gas to the edge of the etching chamber so as to etch the oxide layer based on the anti-reflection layer and the patterned photoresist layer to form an opening.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic cross-sectional view of a contact hole formed in an initial semiconductor structure provided in the related art;
FIG. 2 is a schematic view of a scanning electron microscope of a cross section of a semiconductor structure provided in the related art;
fig. 3 is a schematic diagram showing the result of a detection image of dark voltage contrast (Dark Voltage Contrast, DVC) of a semiconductor structure provided in the related art;
FIG. 4 is a flow chart of a method of fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a schematic cross-sectional view of the structure obtained in step S101 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S102 in the method for fabricating a semiconductor structure according to one embodiment;
fig. 7 is a schematic cross-sectional structure of the structure obtained in step S103 in the method for manufacturing a semiconductor structure according to an embodiment;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S104 in the method for fabricating a semiconductor structure according to an embodiment;
FIG. 9 is a schematic view of a scanning electron microscope of a cross section of a semiconductor structure formed in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 10 is a schematic diagram showing the result of a detection image of dark voltage contrast of a semiconductor structure formed in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 11 is a flowchart illustrating the steps of step S102 in a method for fabricating a semiconductor structure according to one embodiment;
fig. 12 is a schematic cross-sectional structure of the structure obtained in step S1021 in the method for manufacturing a semiconductor structure according to an embodiment;
FIG. 13 is a schematic cross-sectional view of the structure obtained in step S1022 in the method for fabricating a semiconductor structure according to one embodiment;
fig. 14 is a schematic cross-sectional structure of a structure obtained in step S1023 in a method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate: 10-substrate, 20-conductive layer, 30-dielectric layer, 301-contact hole, 40-oxide layer, 401-polymer, 50-gate structure, 60-anti-reflection layer, 601-anti-reflection phase shift film layer, 602-dark anti-reflection layer, 603-lithography oxide layer, 604-bottom anti-reflection layer, 70-patterning photoresist layer, 701-lithography material layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of preferred embodiments (and intermediate structures) of the application, in which case variations in the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In the related art, during the formation of the contact hole, the etching process is stopped in advance due to the formation of some reaction by-products, and the aperture of the bottom of the formed contact hole is narrower. For example, in the related art, as shown in fig. 1, the contact hole 301 is generally formed by reacting an etching gas including a carbon element and a fluorine element with the oxide layer 40 to remove the oxide layer 40, but some polymer 401 is accumulated on the surface of the oxide layer 40 due to some elements (e.g., carbon element) in the etching gas during etching of the oxide layer 40. Particularly, during etching tail sound, the polymer 401 can completely cover the surface of the oxide layer 40, so that etching gas is difficult to further contact with the oxide layer 40, and thus the oxide layer 40 in the opening range is difficult to completely remove, and therefore, in an actual process preparation scene, the morphology as shown in fig. 1 is easy to form in the related technology, and the pore diameter at the bottom of the contact hole is too narrow.
In the subsequent process inspection flow, as shown by the dashed box in the scanning electron microscope (scanning electron microscope, SEM) of fig. 2, if the aperture of the bottom of the contact hole is too narrow, the interconnection plug will not contact the substrate, and an open defect will occur. As shown in fig. 3, when the dark voltage contrast (Dark Voltage Contrast, DVC) is detected on the chip after the interconnection plug is formed, it is found that the DVC defect is all on the detected image (map), which is just that the open defect in fig. 2 is too many to make the interconnection plug contact with the substrate, and the interconnection plug and the substrate are in an open state, and as a result, the DVC defect is distributed on the whole map as shown in fig. 3. Therefore, the reliability of the chip in the conventional technology is low.
Referring to fig. 4, the present application provides a method for manufacturing a semiconductor structure, which includes steps S101 to S104 as follows.
S101: providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, a conductive layer, a dielectric layer, an oxide layer and a plurality of grid structures which are arranged at intervals; wherein each gate structure is located over the substrate; the conductive layer is positioned on top of each gate structure and on top of the substrate between each gate structure; the dielectric layer covers the surface of the gate structure and the surface of the conductive layer; the oxide layer covers the surface of the dielectric layer and the surface of the substrate.
The topography of the initial semiconductor structure may be seen in fig. 5 and may be formed by a combination of suitable processes such as deposition, mechanical polishing, photolithography, etching, cleaning, and the like. Of course, in other suitable application scenarios, the initial semiconductor structure may have other shapes, which are not limited herein.
The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials may be mentioned: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures composed of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be Double polished silicon wafers (Double Side PolishedWafers, DSP), ceramic substrates such as aluminum oxide, quartz, or glass substrates, and the like, and the embodiment is not limited thereto.
The material of the conductive layer 20 may include nickel silicide (NiSi), and the conductive layer 20 may serve as a contact node between the substrate 10 and the gate structure 50 and the interconnect plug.
The material of the dielectric layer 30 may include at least one of silicon nitride, aluminum nitride, polyimide, or a combination of materials, however, the material of the dielectric layer 30 may also include any suitable material of the dielectric layer 30 known in the art, and the embodiment is not limited herein.
The material of oxide layer 40 may include at least one or a combination of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbide, although the material of oxide layer 40 may include any suitable oxide layer 40 material known in the art, and the embodiment is not limited herein.
The material of the gate structure 50 may be any suitable gate material known in the art, for example, polysilicon, or other suitable metal gate material, which is not limited herein. Further, the conductivity type of the polysilicon may be P-type or N-type, which is not limited herein.
S102: and forming an anti-reflection layer and a graphical photoresist layer on the upper surface of the oxidation layer.
As shown in fig. 6, a coating process and other suitable processes may be used to form an anti-reflective layer and a photoresist layer on the upper surface of the oxide layer 40, and then the patterned photoresist layer 70 may be formed by performing process steps such as exposure development and etching.
S103: etching the oxide layer based on the anti-reflection layer and the patterned photoresist layer in a first preset etching atmosphere to form an opening, wherein the opening exposes the surface of part of the dielectric layer; the first preset etching atmosphere comprises a first gas and a second gas, part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching the oxide layer under the first preset etching atmosphere.
Wherein the first gas and the second gas comprise different elements, for example, the first gas may comprise oxygen element and the second gas may comprise carbon element and fluorine element. The second gas may be used to react with the oxide layer 40 to remove the oxide layer 40 and the first gas may be used to react with the first reaction by-product to remove the first reaction by-product. Of course, in other suitable application scenarios, the constituent elements of the first gas and the second gas may be other suitable elements according to the difference of the material layers, which is not limited herein.
As shown in fig. 7, when the oxide layer 40 is etched in the first preset etching atmosphere, the dielectric layer 30 may be used as an etching stop layer of the oxide layer 40, and even if a portion of the first reaction by-product is generated during the process of removing the oxide layer 40 by reacting the second gas with the oxide layer 40, the first reaction by-product may be quickly removed by the reaction of the first gas and the first reaction by-product, so that the surface of the oxide layer 40 is not completely covered by the first reaction by-product, and the semiconductor structure meeting the process requirement as shown in fig. 7 may be prepared, so as to facilitate the development of the subsequent process.
S104: and removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer.
As shown in fig. 8, an etching process may be used to remove a portion of dielectric layer 30 and conductive layer 20 may be used as an etch stop layer for dielectric layer 30. Because the first reaction by-product is removed by the first gas in step S103, the oxide layer 40 within the opening range in step S103 can be basically etched and removed, so that the surface of the dielectric layer 30 located at the bottom can be completely exposed, and therefore, the dielectric layer 30 within the opening range can be completely removed, so that the aperture of the bottom of the finally formed contact hole 301 can meet the process requirement, and the surface of the conductive layer 20 located at the bottom of the contact hole 301 can be fully exposed, thereby being more beneficial to the contact between the conductive plug and the conductive layer 20 formed in the subsequent process and avoiding the disconnection problem between the conductive plug and the conductive layer 20, and further improving the reliability of the chip.
According to the preparation method of the semiconductor structure, the anti-reflection layer and the patterned photoresist layer are formed on the upper surface of the oxide layer, and the oxide layer is etched to form an opening based on the anti-reflection layer and the patterned photoresist layer in a first preset etching atmosphere, so that the surface of part of the dielectric layer is exposed out of the opening; the first preset etching atmosphere comprises a first gas and a second gas, part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching the oxide layer under the first preset etching atmosphere. And removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer. The unexpected technical effect of this application is: because in the process of removing the oxide layer by using the second gas, the first reaction by-product can be quickly removed by the reaction of the first gas and the first reaction by-product, the problem that the aperture of the bottom of the contact hole is narrower due to the fact that the first reaction by-product is accumulated on the surface of the oxide layer can be avoided, and the reliability of the chip can be improved.
In one embodiment, the first gas comprises oxygen and the second gas comprises tetra-carbon hexafluoride (C 4 F 6 ) And (3) gas.
In the process of etching and removing the oxide layer 40 by using the second gas of four carbon hexafluoride gas, the four carbon hexafluoride gas includes CF 3 The radicals are ion bombarded to dissociate into a plasma of elemental carbon (C) and a plasma of elemental fluorine (F), thereby readily forming some polymer with elemental fluorocarbon (i.e., the first reaction by-product) overlying the oxide layer 40 surface, resulting in a termination of the etching process. At this time, the first gas is selected as oxygen for etching, and the characteristic of higher combination energy of the C-O bond is utilized, so that the O element in the oxygen can be carried out with the C element in the polymerThe element F in the polymer is now able to bond more with oxide layer 40 to remove more of oxide layer 40.
In this embodiment, when the second gas is a tetra-carbon hexafluoride gas, the oxygen is used as the first gas to remove the first reaction by-product so as to avoid excessive accumulation of the first reaction by-product on the surface of the oxide layer 40, and simultaneously, the etching rate of the oxide layer can be accelerated, so that the oxide layer is removed more thoroughly, and the reliability of the chip can be further improved.
In one embodiment, in the first preset etching atmosphere, the ratio of oxygen to the four carbon hexafluoride gas is 0.9: 1-1.1: 1.
illustratively, the ratio of oxygen to four carbon hexafluoride gas is 0.9:1 as an example, etching the oxide layer 40, forming a contact hole 301, and filling metal in the contact hole 301 to form an interconnection plug, as shown in fig. 9, which is an SEM image of a cross section of the formed semiconductor structure, comparing the morphology of the semiconductor structure at the dashed line boxes of fig. 9 and 2, it can be seen that the ratio of oxygen to tetra carbon hexafluoride gas is 0.9:1 after the formation of the contact holes 301, the interconnect plugs can be brought into close contact with the conductive layer 20 on top of the substrate 10. Further, as shown in fig. 10, the map detected by DVC for the chip, as can be seen from comparing fig. 10 with fig. 2, the ratio of oxygen to four carbon hexafluoride gas is 0.9:1 after the contact holes 301 are formed, there are few DVC defects on the map, which means that all interconnect plugs on the chip are in close contact with the substrate 10 and no open circuit exists.
In this embodiment, the ratio of oxygen to the four carbon hexafluoride gas is set to 0.9 in the first preset etching atmosphere: 1-1.1: 1, thereby forming a contact hole meeting the process requirement, and further improving the reliability of the chip.
In one embodiment, the step S103 includes: and under a first preset etching atmosphere, providing excitation for the first gas and the second gas by adopting preset low-frequency offset power so as to etch the oxide layer based on the anti-reflection layer and the patterned photoresist layer to form an opening.
During etching the oxide layer, the first gas and the second gas are bombarded by ions to form a plasma, and the plasma exists in the etching chamber. The preset low-frequency offset power (Low Frequency Power, LF power) is capable of exciting the first gas and the second gas, so as to improve the directionality of the plasma formed by the first gas and the second gas, and thus, the surfaces of the oxide layer and the first reaction byproducts can be bombarded more violently to react with the oxide layer and the first reaction byproducts.
In this embodiment, excitation is provided for the first gas and the second gas by adopting the preset low-frequency offset power, so that the directionality of the first gas and the second gas can be improved, the first gas and the second gas can react with the oxide layer and the first reaction byproducts more rapidly, the morphology of the formed contact hole meets the process requirement, and the reliability of the chip can be further improved.
In one embodiment, the predetermined low frequency bias power is 2400W to 2800W.
In one embodiment, as shown in fig. 11, the step S102 includes the following steps S1021 to S1023.
S1021: an anti-reflection phase shift film layer, a dark anti-reflection layer, a photoetching oxide layer and a bottom anti-reflection layer are sequentially formed on the upper surface of the oxidation layer from bottom to top to form an anti-reflection layer, and a photoetching material layer is formed on the upper surface of the anti-reflection layer.
As shown in fig. 12, an Anti-reflection phase shift layer (BARC) 601, a Dark Anti-reflection layer (DARC) 602, a photo-resist oxide layer 603, a Bottom Anti-reflection layer (Anti-Reflective Phase Shift Film, APF) 604, and a photo-resist material layer 701 may be sequentially formed on the upper surface of the oxide layer 40 from Bottom to top by deposition and coating processes.
S1022: removing a portion of the photoresist layer based on the mask to form a patterned photoresist layer, the patterned photoresist layer including an initial opening exposing a surface of the bottom anti-reflective layer.
As shown in fig. 13, a portion of the photoresist layer 701 may be removed based on a reticle using an exposure, development, or the like process to form a patterned photoresist layer 70. Wherein the initial opening defines the opening and the position of the contact hole 301.
S1023: and sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening, so that the surface of the oxide layer is exposed by the initial opening.
As shown in fig. 14, an etching process may be used to sequentially remove a portion of the bottom anti-reflection layer 604, a portion of the photo-resist oxide layer 603, a portion of the dark anti-reflection layer 602, and a portion of the anti-reflection phase shift film layer 601.
In one embodiment, the step S1023 includes: sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening in a second preset etching atmosphere; the second preset etching atmosphere comprises a first gas, a second gas and a third gas, wherein the first gas is also used for generating chemical reaction with a second reaction byproduct, and the second reaction byproduct is a polymer generated by etching the bottom anti-reflection layer under the second preset etching atmosphere.
The second gas and the third gas may be used to etch and remove the anti-reflection phase shift film layer 601, the dark anti-reflection layer 602, the photo-etching oxide layer 603, and the bottom anti-reflection layer 604, and the first gas may be used to react with the second reaction byproduct to remove the second reaction byproduct. The formation of the second reaction by-product is similar to the formation of the first reaction by-product, and is also some of the high polymers formed due to the elements included in the second gas and the third gas. The build-up of the second reaction by-products may result in a narrowing of the initial opening and thus further in a narrowing of the aperture at the top of the contact hole 301 from the beginning of etching the oxide layer 40, and thus eventually in a narrowing of the entire aperture of the contact hole 301.
In this embodiment, the reaction between the first gas and the second reaction byproduct can avoid the accumulation of the second reaction byproduct, so that the aperture of the top of the contact hole 301 can be enlarged, and the reliability of the chip can be further improved.
In one embodiment, the first gas comprises oxygen and the second gas comprises fluorocarbon (C x F y ) The gas, the third gas includes hydrocarbon fluoride (C x H y F z ) And (3) gas.
In the process of forming the patterned photoresist layer by using the fluorocarbon gas as the second gas and using the fluorocarbon gas as the third gas, oxygen is used as the first gas, and similar to the process of forming the oxygen and the first reaction byproducts, the characteristic of higher bonding energy of the C-O bond is utilized, so that the oxygen can remove the second reaction byproducts, and the problem that the pore diameter of the initial opening is too small due to accumulation of the second reaction byproducts is avoided.
In this embodiment, the first gas includes oxygen, the second gas includes fluorocarbon gas, and the third gas includes fluorocarbon gas, so that the oxygen can remove the second reaction by-product, thereby avoiding the pore diameter of the initial opening from being too small due to the accumulation of the second reaction by-product, and further improving the reliability of the chip.
Alternatively, the second preset etching atmosphere may include only the second gas and the third gas, for example, the second preset etching atmosphere may include only a mixed gas of fluorocarbon gas and fluorocarbon gas, and the formation of the second reaction by-product is reduced by adjusting the ratio between the fluorocarbon gas and the fluorocarbon gas to be suitable.
In one embodiment, in the second preset etching atmosphere, the ratio of oxygen to the mixed gas is 0.033: 1-0.05: 1, a step of; wherein the mixed gas is a mixed gas of fluorocarbon gas and hydrocarbon fluorocarbon gas.
Alternatively, the formation of the second reaction by-product may also be reduced by increasing the ratio between fluorocarbon gas and fluorocarbon gas in the mixed gas. This is because the fluorocarbon gas is a gas having fewer impurities than the fluorocarbon gas, and the formation of the second reaction by-product can be further reduced by increasing the ratio between the fluorocarbon gas and the fluorocarbon gas in the mixed gas, so that the reliability of the chip can be further improved.
In one embodiment, the step S103 includes: and in the first preset etching atmosphere, adjusting the gas flow direction to increase the diffusion ratio of the first gas and the second gas to the edge of the etching chamber so as to etch the oxide layer based on the anti-reflection layer and the patterned photoresist layer to form an opening.
The flow direction of the gases can be adjusted by controlling the ratio of the distribution uniformity control (Radical Distribution Uniformity Control, RDC) of the radiation in the etching machine table, so that the first gases and the second gases diffuse to the edge of the etching chamber as much as possible, thereby reducing the load effect between the central area and the edge area of the etching chamber and reducing the occurrence of DVC defects frequently occurring in the edge area of the wafer.
In this embodiment, by adjusting the gas flow direction in the first preset etching atmosphere to increase the diffusion ratio of the first gas and the second gas to the edge of the etching chamber, the uniformity of the first gas and the second gas in the distribution in the center area and the edge area of the etching chamber can be improved, so that the occurrence of DVC defects in the edge area of the wafer is reduced, and the reliability of the chip can be further improved.
Alternatively, the proportion of RDC may comprise 25% to 35%.
The technical features of the above embodiments may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope described in the present specification.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, a conductive layer, a dielectric layer, an oxide layer and a plurality of gate structures which are arranged at intervals; wherein each gate structure is located over the substrate; the conductive layer is positioned on top of each gate structure and on top of the substrate between each gate structure; the dielectric layer covers the surface of the gate structure and the surface of the conductive layer; the oxide layer covers the surface of the dielectric layer and the surface of the substrate;
forming an anti-reflection layer and a graphical photoresist layer on the upper surface of the oxide layer;
etching the oxide layer based on the anti-reflection layer and the patterned photoresist layer in a first preset etching atmosphere to form an opening, wherein the opening exposes part of the surface of the dielectric layer; the first preset etching atmosphere comprises a first gas and a second gas, wherein part of the first gas is also used for generating chemical reaction with a first reaction byproduct, and the first reaction byproduct is a polymer generated by etching the oxide layer under the first preset etching atmosphere;
and removing part of the dielectric layer based on the opening to form a contact hole, wherein the contact hole exposes the surface of the conductive layer.
2. The method of claim 1, wherein the first gas comprises oxygen and the second gas comprises a four carbon hexafluoride gas.
3. The method of claim 2, wherein the ratio of the oxygen to the four carbon hexafluoride gas in the first predetermined etching atmosphere is 0.9: 1-1.1: 1.
4. the method of claim 1, wherein etching the oxide layer to form an opening based on the anti-reflective layer and the patterned photoresist layer in a first predetermined etching atmosphere comprises:
and under the first preset etching atmosphere, providing excitation for the first gas and the second gas by adopting preset low-frequency offset power so as to etch the oxide layer based on the reflecting layer and the patterned photoresist layer to form an opening.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein the preset low-frequency bias power is 2400w to 2800w.
6. The method of claim 1, wherein forming an anti-reflective layer and patterning a photoresist layer on the top surface of the oxide layer comprises:
forming an anti-reflection phase shift film layer, a dark anti-reflection layer, a photoetching oxide layer and a bottom anti-reflection layer on the upper surface of the oxide layer in sequence from bottom to top so as to form the anti-reflection layer, and forming a photoetching material layer on the upper surface of the anti-reflection layer;
removing a part of the photoresist layer based on a photomask to form the patterned photoresist layer, wherein the patterned photoresist layer comprises an initial opening, and the initial opening exposes the surface of the bottom anti-reflection layer;
and sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening, so that the initial opening exposes the surface of the oxide layer.
7. The method of claim 6, wherein sequentially removing a portion of the bottom anti-reflective layer, a portion of the photo-resist oxide layer, a portion of the dark anti-reflective layer, and a portion of the anti-reflective phase shift film layer based on the initial opening comprises:
sequentially removing part of the bottom anti-reflection layer, part of the photoetching oxide layer, part of the dark anti-reflection layer and part of the anti-reflection phase shift film layer based on the initial opening in a second preset etching atmosphere; the second preset etching atmosphere comprises the first gas, the second gas and the third gas, wherein the first gas is also used for generating chemical reaction with a second reaction byproduct, and the second reaction byproduct is a polymer generated by etching the bottom anti-reflection layer under the second preset etching atmosphere.
8. The method of claim 7, wherein the first gas comprises oxygen, the second gas comprises fluorocarbon gas, and the third gas comprises fluorocarbon gas.
9. The method of claim 8, wherein the ratio of oxygen to mixed gas in the second predetermined etching atmosphere is 0.033: 1-0.05: 1, a step of; wherein the mixed gas is a mixed gas of the fluorocarbon gas and the hydrocarbon fluorocarbon gas.
10. The method of claim 1, wherein etching the oxide layer to form an opening based on the anti-reflective layer and the patterned photoresist layer in a first predetermined etching atmosphere comprises:
and in a first preset etching atmosphere, adjusting the gas flow direction to increase the diffusion ratio of the first gas and the second gas to the edge of the etching chamber so as to etch the oxide layer based on the anti-reflection layer and the patterned photoresist layer to form an opening.
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