CN110648905A - Method for manufacturing semiconductor device - Google Patents
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- CN110648905A CN110648905A CN201910912435.6A CN201910912435A CN110648905A CN 110648905 A CN110648905 A CN 110648905A CN 201910912435 A CN201910912435 A CN 201910912435A CN 110648905 A CN110648905 A CN 110648905A
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- 238000000034 method Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 153
- 238000005530 etching Methods 0.000 claims abstract description 64
- 238000009966 trimming Methods 0.000 claims abstract description 61
- 230000008569 process Effects 0.000 claims abstract description 59
- 239000011248 coating agent Substances 0.000 claims abstract description 47
- 238000000576 coating method Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 abstract description 12
- 239000010410 layer Substances 0.000 description 266
- 239000006117 anti-reflective coating Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 12
- 238000012545 processing Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Abstract
The invention discloses a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top; trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension; and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer. The invention has the advantages of reducing the process complexity of semiconductor preparation, reducing the time for preparing the semiconductor and improving the productivity.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device.
Background
With the increasing precision of semiconductor manufacturing technology, the integrated circuit is also greatly handed over, so that the computing performance and the storage capacity of a computer are dramatically improved, and the rapid development of peripheral industries is driven. The semiconductor industry has also developed at a rate of doubling the number of transistors on integrated circuits every 18 months, as predicted by moore's law.
Thus, in the preparation of a semiconductor device, for example: in the process of fabricating a metal oxide semiconductor transistor (MOS transistor), forming a gate (gate) having a conductive property is an important step. In order to meet the requirement of miniaturization in the semiconductor industry, the current exposure process for manufacturing the gate electrode must be able to control the Critical Dimension (CD), and particularly, the exposure process needs to control the conductive layer (e.g., the polysilicon layer) to obtain a predetermined line width after the conductive layer is etched. However, because the current photolithography tool technology cannot expose the desired critical dimension, in some prior arts, the trimming (trimming) of the photoresist layer (PR) is used to achieve the purpose of reducing the line width of the gate.
The trim process for trimming the photoresist layer is a method commonly used in the art to adjust the CD BIAS (CD BIAS) in the etch step (ET process) to achieve a predetermined or target critical dimension (CD target). But as critical dimensions become smaller, for example: the photoresist layer used in the etching step of the shallow trench isolation Structure (STI) or the gate is thinner and thinner (for example, the thickness of the photoresist layer for preparing the shallow trench isolation structure is Arf and the maximum thickness of the photoresist layer for preparing the gate is 2850 angstroms), and because the trimming process for trimming the photoresist layer is isotropic, the photoresist on the top of the photoresist layer is consumed while the photoresist layer is laterally etched, so that the thickness of the photoresist layer is thinned, and if the thickness of the photoresist layer is not enough, the following etching process cannot be continued after the step of the trimming process for trimming the photoresist layer.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which is used for solving the problem that after the existing trimming process step of trimming a photoresist layer, the thickness of the photoresist layer is insufficient, so that the following etching process cannot be continued, namely, the subsequently formed semiconductor device cannot have the preset line width or critical dimension.
In order to solve the problems, the invention is realized by the following technical scheme:
a method of making a semiconductor device, comprising:
providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top;
trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension;
and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer.
Optionally, the thickness of the patterned photoresist layer ranges from 2700 angstroms to 3000 angstroms; the thickness range of the bottom anti-reflection coating is 800-1000 angstroms, and the thickness range of the hard mask layer is 400-500 angstroms.
Preferably, the trimming treatment of the patterned photoresist layer adopts a dry etching process.
Preferably, the etching gases used for the trimming process of the patterned photoresist layer are Cl2 and O2.
Preferably, the etching process parameters adopted for the trimming treatment of the patterned photoresist layer are as follows: the pressure is as follows: 40 mT-60 mT, 300W-500W of source power, 0V-10V of bias voltage and Cl2The gas flow rate of the gas is 30sccm to 50sccm, the gas flow rate of the O2 is 40sccm to 60sccm, and the etching time is 40s to 60 s. Preferably, the hard mask layer is etched by a dry etching process.
Preferably, the etching gas used for etching the hard mask layer is CF 4.
Further, the method also comprises the following steps: the grid oxide layer is positioned on the substrate, and the conducting layer is positioned between the grid oxide layer and the hard mask layer.
Further, the patterned hard mask layer is used as a mask, and the conducting layer is etched to obtain a grid electrode with a preset critical dimension.
Further, in the trimming process of the patterned photoresist layer, the critical dimension deviation value of the patterned photoresist layer is linearly related to the trimming time.
Compared with the prior art, the invention has the following advantages:
the invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top; trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension; and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer. Therefore, the method combines the steps of etching the bottom anti-reflection coating and trimming the patterned photoresist layer, so that only one step of consumption of the patterned photoresist layer exists before the hard mask is etched, and therefore, when the hard mask layer is etched by taking the patterned bottom anti-reflection coating as a mask, the patterned photoresist layer with the preset critical dimension has enough thickness. In addition, the purposes of etching the bottom anti-reflection coating and trimming the patterned photoresist layer can be realized in one processing step, so that the process complexity of semiconductor preparation is reduced, the time for preparing the semiconductor is shortened, the productivity is improved, the critical dimension of each unit has good uniformity, the critical dimension of the patterned photoresist layer has good linearity, and the trimming amount of the patterned photoresist layer is convenient to adjust.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to fig. 2d are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention during a manufacturing process of the semiconductor device;
fig. 3 is a schematic diagram illustrating a relationship between a trimming amount and a trimming time of a patterned photoresist layer in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, after the existing trimming process step of trimming the photoresist layer, the thickness of the photoresist layer is not sufficient, so that the following etching process cannot be continued, i.e., the problem that the subsequently formed semiconductor device cannot have a predetermined line width or critical dimension cannot be solved. Specifically, the conventional semiconductor manufacturing method includes the following steps: providing a substrate, and sequentially forming a gate oxide layer, a conductive layer, a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top;
performing main etching and over-etching on the bottom anti-reflection coating by taking the patterned photoresist layer as a mask to obtain a patterned bottom anti-reflection coating, wherein part of the hard mask layer is exposed out of the patterned bottom anti-reflection coating; typically, a dry etching process is used, i.e. CF4 and HBr are used as etching gases, and in this step, the photoresist layer on top of the patterned photoresist layer is consumed, and the thickness of the patterned photoresist layer is reduced for the first time.
Then, in order to obtain a semiconductor device with a preset critical dimension, for example, a gate with a preset line width dimension, step two, performing a trimming process on the patterned photoresist layer (or the patterned photoresist layer and the patterned bottom anti-reflection coating layer) so that the patterned photoresist layer and the patterned bottom anti-reflection coating layer have the preset critical dimension; in the second step, a dry etching process may be used, and the etching gases thereof generally adopt CH2F2 and O2. It follows that in this process the photoresist layer on top of the patterned photoresist layer is consumed again, i.e. the thickness of the patterned photoresist layer is reduced a second time.
Then, performing a third step of etching the hard mask layer by taking the trimmed patterned photoresist layer and the trimmed patterned bottom anti-reflection coating as masks to obtain a patterned hard mask layer;
and then, executing a fourth step, removing the trimmed patterned photoresist layer and the patterned bottom anti-reflection coating, and etching the conductive layer by taking the patterned hard mask layer as a mask to obtain a patterned conductive layer, wherein the patterned conductive layer is exposed out of the surface of the gate oxide layer. It can be seen that 1800A remains before step two is performed, the patterned photoresist layer is consumed twice before step three, and the remaining patterned photoresist layer has a thickness of, for example, only about 1000A, which is insufficient for performing step three, thereby causing a problem that the following etching process cannot be continued, i.e., the subsequently formed semiconductor device cannot have a predetermined line width or critical dimension.
Based on the above research, the present invention solves the above problems by providing a method for manufacturing a semiconductor device, which specifically includes the following processes: providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top; trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension; and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer. Therefore, the method combines the steps of etching the bottom anti-reflection coating and trimming the patterned photoresist layer, so that only one step of consumption of the patterned photoresist layer exists before the hard mask is etched, and therefore, when the hard mask layer is etched by taking the patterned bottom anti-reflection coating as a mask, the patterned photoresist layer with the preset critical dimension has enough thickness. In addition, the purposes of etching the bottom anti-reflection coating and trimming the patterned photoresist layer can be realized in one processing step, so that the process complexity of semiconductor preparation is reduced, the time for preparing the semiconductor is shortened, the productivity is improved, the critical dimension of each unit has good uniformity, the critical dimension of the patterned photoresist layer has good linearity, and the trimming amount of the patterned photoresist layer is convenient to adjust.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which a preferred embodiment of the invention is shown
Examples it will be appreciated that those skilled in the art can modify the invention herein described while still achieving the beneficial results of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
It is to be noted that the drawings are in a very simplified form and employ non-precise ratios for the purpose of facilitating and distinctly facilitating the description of one embodiment of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
As shown in fig. 1, the method for manufacturing a semiconductor device of the present embodiment includes:
step S100, providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top;
step S200, trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while enabling the patterned photoresist layer to have a preset critical dimension;
and step S300, etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer.
Therefore, in the embodiment, the steps of etching the bottom anti-reflective coating and trimming the patterned photoresist layer are combined, so that only one step of consumption of the patterned photoresist layer exists before the hard mask is etched, and thus, when the hard mask layer is etched by using the patterned photoresist layer and the patterned bottom anti-reflective coating as masks, the patterned photoresist layer with the preset critical dimension has enough thickness. In addition, the purposes of etching the bottom anti-reflection coating and trimming the patterned photoresist layer can be realized in one processing step, so that the process complexity of semiconductor preparation is reduced, the time for preparing the semiconductor is shortened, the productivity is improved, the critical dimension of each unit has good uniformity, the critical dimension of the patterned photoresist layer has good linearity, and the trimming amount of the patterned photoresist layer is convenient to adjust.
The method for manufacturing a semiconductor provided by the embodiment is applicable to any semiconductor device manufacturing process adopting the step of trimming (trimming) the patterned photoresist layer. For example, an integrated circuit device, which may include a memory, is prepared using the above-described method for manufacturing a semiconductor device. The integrated circuit device may include a microprocessor. Specifically, to better explain the method for manufacturing a semiconductor provided in this embodiment, the following process of forming a gate of an MOS transistor is taken as an example, and refer to fig. 2a to 2d, which show schematic cross-sectional structure diagrams of a device in the manufacturing process of a semiconductor device; embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention. In this embodiment, the situation of the implanted region is not considered, and therefore, the schematic cross-sectional structure of the device with the related band implant is omitted.
As shown in fig. 2a, a substrate 100 is provided, and a hard mask layer 400, a bottom anti-reflective coating 500 and a patterned photoresist layer 600 are sequentially formed on the substrate 100 from bottom to top; the method further comprises the following steps: the gate structure comprises a gate oxide layer 200 and a conductive layer 300, wherein the gate oxide layer 200 is positioned on the substrate 300, and the conductive layer 300 is positioned between the gate oxide layer 200 and the hard mask layer 400.
In the present embodiment, the term "substrate" as used herein refers not only to a semiconductor substrate, but also to any intermediate structure, conductive layer, dielectric layer or any other semiconductor structure underlying a metal layer. In particular, in the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductor material, including, but not limited to, bulk semiconductor material such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and layers of semiconductor material (either alone or in assemblies comprising other materials). The substrate 100 may be any substrate known to those skilled in the art for supporting a component of a semiconductor integrated circuit, and may be a bare chip or a wafer processed by an epitaxial growth process, and in detail, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate. Next, a (gate dielectric layer) coupling oxide layer 200 is formed on the surface of the substrate 100 by using methods such as low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation or molecular beam epitaxy, and a conductive layer 300 is formed on the gate dielectric layer 200 by using processes such as chemical vapor deposition or atomic layer deposition, the gate dielectric layer 200 is made of a material including but not limited to silicon dioxide, preferably silicon dioxide, which is beneficial to increasing the interface adhesion between layers, the gate dielectric layer 200 is used for isolating the substrate 100 and the conductive layer 300, the thickness of the gate dielectric layer can be changed according to specific process requirements, the conductive layer 300 is made of polysilicon, and is used for forming a gate subsequently, and the thickness of the conductive layer 300 can be determined according to process requirements. Next, a hard mask layer 400 is deposited on the conductive layer 300 by using a chemical vapor deposition process or a physical vapor deposition process. The hard mask layer 400 may be made of one or a combination of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, and 25 ultra-low-k dielectric. In this embodiment, the hard mask layer 400 is preferably silicon nitride, which is advantageous for manufacturing and has a relatively low cost. It is particularly noted that the hard mask layer 400 and the conductive layer 300 used to form the gate electrode need to have a high etch selectivity.
The step of forming the patterned photoresist layer 600 includes: a photoresist film (not shown) may be coated on the conductive layer 300 and exposed, developed, etc. using a gate mask to form the patterned photoresist layer 600 on the conductive layer 300. Forming a bottom anti-reflective coating (BARC) 500 between the patterned photoresist layer 600 and the conductive layer 300 may improve the critical dimension uniformity of the photolithography process.
It is noted that the thickness of the patterned photoresist layer 600 and the BARC layer 500 is relatively thin, and the relatively thin patterned photoresist layer 600 and the BARC layer 500 can improve the focus tolerance in the photolithography process and effectively control the critical dimension or critical dimension thereof, and furthermore, the relatively thin patterned photoresist layer 600 can prevent the photoresist layer from collapsing.
Optionally, the thickness of the patterned photoresist layer ranges from 2700 angstroms to 3000 angstroms; the thickness range of the bottom anti-reflection coating is 800-1000 angstroms, and the thickness range of the hard mask layer is 400-500 angstroms.
As shown in fig. 2b, a trimming (trimming) process is performed on the patterned photoresist layer 600 to obtain a patterned bottom anti-reflective coating 500 while the patterned photoresist layer 600 has a predetermined critical dimension; preferably, the trimming process for the patterned photoresist layer 600 adopts a dry etching process. Further, the etching gases used for the trimming process of the patterned photoresist layer 600 are Cl2 and O2. Preferably, the etching process parameters used for the trimming process of the patterned photoresist layer 600 are as follows: the pressure range is as follows: 40 mT-60 mT, source power or source electric field power (source power) range of 300W-500W, Bias voltage (Bias power) of-10V-0V, Cl2The gas flow range of (1) is 30sccm to 50sccm, the gas flow range of O2 is 40sccm to 60sccm, and the etching time range is 40s to 60 s.
Therefore, in the step of performing the trimming process on the patterned photoresist layer 600, not only the lateral etching on the patterned photoresist layer 600 can be realized by using the above etching method, but also the lateral etching on the patterned photoresist layer 600 can be realized, and at the same time, the vertical etching on the bottom anti-reflection coating 500 is realized, that is, the vertical etching is equivalent to the main Etching (ET) on the bottom anti-reflection coating 500, so as to form the patterned bottom anti-reflection coating 500, where the patterned bottom anti-reflection coating 500 exposes the surface of the hard mask layer 400, but at this time, the bottom anti-reflection coating 500 may remain on the exposed surface of the hard mask layer 400. In the process, the photoresist layer on the top portion of the patterned photoresist layer 600 is consumed, that is, when this step is completed, the etching process at this stage reduces the thickness integrity of the patterned photoresist layer 600, and the thickness of the trimmed patterned photoresist layer 600 is 2000 angstroms, so that this step only consumes a small amount of photoresist layer, and does not affect the subsequent etching process steps.
As shown in fig. 2c, the hard mask layer 400 is etched by using the patterned photoresist layer 600 and the patterned bottom anti-reflective coating 500 as masks, so as to obtain the patterned hard mask layer 400. Specifically, the patterned BARC layer 500 is used at this time, and the patterned BARC layer 500 is trimmed to have a predetermined critical dimension. The patterned photoresist layer 600 is trimmed and has a predetermined critical dimension of the patterned photoresist layer 600. In this process, an Over Etch (OE) process for the bottom anti-reflective coating 500 in the prior art is included, so that it is known that the process steps for semiconductor fabrication are further simplified, and the efficiency of semiconductor fabrication is improved, i.e., the productivity is improved.
In addition, since the patterned hard mask layer 400 is defined by the patterned BARC layer 500 as an etching mask, the thickness of the patterned BARC layer 500 is also consumed during the etching process. In this embodiment, preferably, the hard mask layer 400 is etched by a dry etching process. Preferably, the etching gas used for etching the hard mask layer 400 is CF 4. The etching process parameters are as follows: 5 mT-10 mT, source power or source electric field power (source power) range of 200W-300W, Bias voltage (Bias power) of-100V-80V, gas flow range of CF4 of 50 sccm-100 sccm, and etching time range of 70 s-78 s.
Therefore, in this embodiment, the steps of etching the bottom anti-reflective coating and trimming the patterned photoresist layer may be combined, so that there is only one step of consuming the patterned photoresist layer before etching the hard mask, and thus, when the hard mask layer is etched by using the patterned bottom anti-reflective coating as a mask, the patterned photoresist layer having a predetermined critical dimension has a sufficient thickness. In addition, the purposes of etching the bottom anti-reflection coating and trimming the patterned photoresist layer can be realized in one processing step, so that the process complexity of semiconductor preparation is reduced, the time for preparing the semiconductor is shortened, the productivity is improved, the critical dimension of each unit has good uniformity, the critical dimension of the patterned photoresist layer has good linearity, and the trimming amount of the patterned photoresist layer is convenient to adjust.
Further, the method for manufacturing a semiconductor device provided in this embodiment further includes a subsequent processing procedure, specifically, the following processing procedure is further included: since the patterned hard mask layer 400 and the conductive layer 300 must have a high etching selectivity (selectivity), as shown in fig. 2d, the patterned hard mask layer 400 is used as a mask to etch the conductive layer 300, so as to obtain the patterned conductive layer 300, in this embodiment, the patterned hard mask layer 400 defines a gate pattern, and thus the patterned conductive layer 300 is a gate with a predetermined critical dimension.
In this embodiment, before the step of etching the conductive layer 300 by using the patterned hard mask layer 400 as a mask is performed, the patterned photoresist layer 600 and the patterned bottom anti-reflective coating 500 need to be removed. The patterned photoresist layer 600 may be removed by an ashing process for a plurality of times, and specifically, the patterned photoresist layer 600 may be removed by reacting oxygen or the like with carbon, hydrogen, oxygen, and nitrogen elements in the patterned photoresist layer 600 to generate volatile substances such as carbon dioxide, water, and nitrogen, and then cleaned by using a weakly alkaline mixed solution.
Further, during the trimming process of the patterned photoresist layer 600, the critical dimension bias (CD bias) or the trimming amount of the patterned photoresist layer 600 is linearly related to the trimming time (trim time).
Specifically, referring to fig. 3, a diagram of the relationship between the trim amount and the trim time of a patterned photoresist layer is schematically shown; as shown in fig. 3, the relationship between the trim amount and the trim time of a patterned photoresist layer can be expressed by the following formula:
y＝0.4628x+16.15 (1)
where y represents the trim amount of the patterned photoresist layer and x represents the trim time.
The trim amount of the patterned photoresist layer specifically means a difference between a feature width value (critical dimension) of the patterned photoresist layer before trimming and a feature width value (critical dimension) of the patterned photoresist layer after trimming. Specifically, for example, the feature width of the original patterned photoresist layer after exposure and development is 1.5 micrometers, and it needs to be trimmed so that the feature width of the trimmed patterned photoresist layer becomes 1.2 micrometers, and then the trimming of the de-patterned photoresist layer is 1.5-1.2-0.3 micrometers.
It can be seen that, in this embodiment, not only can there be only one step of consumption of the patterned photoresist layer before the hard mask is etched by combining the steps of etching the bottom anti-reflective coating and performing the trimming process on the patterned photoresist layer, so that when the hard mask layer is etched by using the patterned photoresist layer and the patterned bottom anti-reflective coating as a mask, the patterned photoresist layer having the predetermined critical dimension has a sufficient thickness. In addition, as the purposes of etching the bottom anti-reflection coating and finishing the patterned photoresist layer can be realized in one processing step, the purposes of reducing the process complexity of semiconductor preparation, reducing the time for preparing the semiconductor, improving the productivity, ensuring that the key size of each prepared unit (chip) has good uniformity, realizing that the finishing of the key size of the patterned photoresist layer has good linearity and being convenient for adjusting the finishing amount of the patterned photoresist layer are realized.
It will also be appreciated that transferring the pattern from the first level to the second level involves forming features in the second level that substantially correspond to features on the first level. For example, the path of a line in the second level will generally follow the path of a line on the first level, and the locations of other features on the second level will correspond to the locations of similar features on the first level. However, the exact shape and size of the features of the first and second levels may be different due to, for example, trimming and growing steps. For example, depending on the etch chemistry and conditions, the size of the features forming the transferred pattern and the relative spacing between them may be enlarged or reduced relative to the pattern on the first level, while still being similar to the same initial "pattern".
It should be noted that the present embodiment focuses on describing a method for trimming the patterned photoresist layer before forming a gate on a substrate, and therefore, it is considered that, but not limited to, the following steps of forming an isolation trench on the substrate 100 and performing ion implantation and annealing on the substrate 100 have been completed on the substrate 100, but those skilled in the art should understand that, in order to make the figures clearly express the core idea of the present application, the forming of a gate on a substrate is only schematically illustrated in the drawings, and the subsequent manufacturing process is not illustrated, but the present invention is not intended to represent that the manufacturing method of a semiconductor device related to the present invention only includes these parts or steps, and well-known semiconductor device structures such as a MOS device structure and process steps can also be included therein. Thus, in the present embodiment, a shallow trench isolation Structure (STI) is formed on the substrate 100 for forming isolation between devices. Shallow trench isolation structures include isolation dielectrics such as silicon dioxide.
In summary, the present invention provides a method for manufacturing a semiconductor device, which includes the following steps: providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top; trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension; and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer. Therefore, the method combines the steps of etching the bottom anti-reflection coating and trimming the patterned photoresist layer, so that only one step of consumption of the patterned photoresist layer exists before the hard mask is etched, and therefore, when the hard mask layer is etched by taking the patterned bottom anti-reflection coating as a mask, the patterned photoresist layer with the preset critical dimension has enough thickness. In addition, the purposes of etching the bottom anti-reflection coating and trimming the patterned photoresist layer can be realized in one processing step, so that the process complexity of semiconductor preparation is reduced, the time for preparing the semiconductor is shortened, the productivity is improved, the critical dimension of each unit has good uniformity, the critical dimension of the patterned photoresist layer has good linearity, and the trimming amount of the patterned photoresist layer is convenient to adjust.
Also in the context of this document, the term "layer" encompasses both the singular and the plural, unless otherwise indicated. As used herein, the layer in which a semiconductor device, component, or part is formed or processed according to a pattern formed in an overlying hard mask may also be referred to collectively as a target layer. The target layer here may be part of the semiconductor substrate described above. The target layer may be formed of a metal, a semiconductor, and/or an insulator. In the target layer, portions of an integrated circuit device, such as a memory or microprocessor, may be formed. Although "processing" through the hard mask is described for the preferred embodiments as etching to transfer the hard mask pattern into the target layer, one of ordinary skill in the art will appreciate that processing in other embodiments may include, for example, oxidation, nitridation, selective deposition, doping, etc. through the hard mask.
As used herein, the term "conditioning" refers to cleaning the roughness of a layer or reducing the feature width of a layer in the lateral direction. The terms may be used interchangeably with "zoom out".
In the description above, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and sequentially forming a hard mask layer, a bottom anti-reflection coating and a patterned photoresist layer on the substrate from bottom to top;
trimming the patterned photoresist layer to obtain a patterned bottom anti-reflection coating while the patterned photoresist layer has a preset critical dimension;
and etching the hard mask layer by taking the patterned photoresist layer and the patterned bottom anti-reflection coating as masks to obtain the patterned hard mask layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the patterned photoresist layer has a thickness in a range of 2700 to 3000 angstroms; the thickness range of the bottom anti-reflection coating is 800-1000 angstroms, and the thickness range of the hard mask layer is 400-500 angstroms.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the trimming process for the patterned photoresist layer employs a dry etching process.
4. The method of claim 3, wherein the etching gas used to trim the patterned photoresist layer is Cl2And O2。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the etching process parameters for the trimming of the patterned photoresist layer are: the pressure is as follows: 40 mT-60 mT, 300W-500W of source power, 0V-10V of bias voltage and Cl2The gas flow rate of the gas is 30sccm to 50sccm, the gas flow rate of the O2 is 40sccm to 60sccm, and the etching time is 40s to 60 s.
6. The method for manufacturing a semiconductor device according to claim 1 or 5, wherein the etching of the hard mask layer employs a dry etching process.
7. The method for manufacturing a semiconductor device according to claim 6, wherein an etching gas used for etching the hard mask layer is CF 4.
8. The method for manufacturing a semiconductor device according to claim 7, further comprising: the grid oxide layer is positioned on the substrate, and the conducting layer is positioned between the grid oxide layer and the hard mask layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the patterned hard mask layer is used as a mask to etch the conductive layer, so as to obtain a gate having a predetermined critical dimension.
10. The method of claim 9, wherein a CD bias of the patterned photoresist layer is linearly related to a trim time during the trimming process of the patterned photoresist layer.
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