CN117541635A - Layout graph scaling correction method and device, electronic device and storage medium - Google Patents
Layout graph scaling correction method and device, electronic device and storage medium Download PDFInfo
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- G06T7/00—Image analysis
- G06T7/30—Determination of transform parameters for the alignment of images, i.e. image registration
- G06T7/33—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
- G06T7/337—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods involving reference images or patches
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
- G06T3/4038—Image mosaicing, e.g. composing plane images from plane sub-images
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Abstract
The application relates to a layout graph scaling correction method, a layout graph scaling correction device, an electronic device and a storage medium, wherein the method comprises the following steps: scaling the original layout graph to generate a first layout graph, namely a graph to be corrected; merging the original layout patterns to generate a second layout pattern; performing the scaling processing on the second layout graph to generate a third layout graph; and correcting the first layout graph according to the difference between the first layout graph and the third layout graph to obtain a corrected target layout. By the method and the device, the technical problem that gaps and steps in the scaled layout cannot be corrected in the prior art is solved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and apparatus for correcting layout scaling, an electronic device, and a storage medium.
Background
When the GDS (graphic design system ) is delivered, part of the process needs to scale the GDS, and most of the process is shrinkage (shrnk) to 90% of the original GDS.
The vertices of all graphics in the GDS are required to be on the grid points of the design grid (design grid), when the GDS is scaled, the original design grid is unchanged, when the vertices of the scaled graphics cannot fall on the grid points, the scaled graphics automatically increase or decrease in value and fall on the nearby grid points, so that some originally overlapped graphics in the layout are caused, gaps are formed, and some graphics are caused to have steps. Such gaps and steps violate DRC (design rule checking) and pose a risk to the process, thus requiring the scaled layout to be processed. In the prior art, gaps and steps in the scaled layout cannot be corrected.
Disclosure of Invention
The embodiment provides a layout graph scaling correction method, device, electronic device and storage medium.
In a first aspect, in this embodiment, a method for correcting layout graphic scaling is provided, where the method includes:
scaling the original layout graph to generate a first layout graph, namely a graph to be corrected;
merging the original layout patterns to generate a second layout pattern;
performing the scaling processing on the second layout graph to generate a third layout graph;
and correcting the first layout graph according to the difference between the first layout graph and the third layout graph to obtain a corrected target layout.
In some embodiments, the merging the original layout patterns to generate a second layout pattern includes:
merging graphs meeting preset relations of the same layer in the original layout graphs to generate a second layout graph; the preset relation is determined according to the position relation of the original layout graph.
In some embodiments, according to the difference between the first layout pattern and the third layout pattern, the first layout pattern is modified to obtain a modified target layout, including:
comparing the first layout pattern with the third layout pattern, and generating a difference pattern according to the difference between the first layout pattern and the third layout pattern;
and correcting the first layout graph by utilizing the difference graph and the first layout graph to obtain a corrected target layout.
In some embodiments, the difference pattern includes a first difference pattern and a second difference pattern;
the first difference graph is a graph part with the first layout graph being more than the third layout graph, and the second difference graph is a graph part with the third layout graph being more than the first layout graph.
In some embodiments, the correcting the first layout pattern by using the difference pattern and obtaining a corrected target layout includes:
and removing the first difference graph from the first layout graph, compensating the second difference graph to the corresponding position of the first layout graph, and generating the corrected first layout, namely the target layout.
In some of these embodiments, the method further comprises:
determining a target layer in the original layout;
and determining the graph of the target layer in the original layout as the original layout graph.
In some of these embodiments, the scaling process refers to a compression or magnification process.
In a second aspect, in this embodiment, there is provided a correction apparatus for layout graphic scaling, including:
the first generation module is used for carrying out scaling treatment on the original layout graph to generate a first layout graph, namely a graph to be corrected;
the second generation module is used for carrying out combination processing on the original layout figures to generate second layout figures;
the third generation module is used for carrying out the scaling processing on the second layout graph to generate a third layout graph;
the determining module is used for correcting the first layout graph according to the difference between the first layout graph and the third layout graph to obtain a corrected target layout.
In a third aspect, in this embodiment, there is provided an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to run the computer program to perform the method for correcting layout graphic scaling according to the first aspect.
In a fourth aspect, in this embodiment, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the layout pattern scaling correction method of the first aspect.
Compared with the prior art, the correction method, the correction device, the electronic device and the storage medium for the scaling of the layout patterns are provided in the embodiment, the original layout patterns are combined to generate the second layout pattern, scaling processing is carried out on the second layout pattern to generate the third layout pattern, the first layout pattern is corrected according to the difference between the first layout pattern and the third layout pattern, and the corrected target layout is obtained, so that the correction of the gaps and the steps occurring in the first layout pattern is carried out, and the technical problem that the correction of the gaps and the steps occurring in the scaled layout is not carried out in the prior art is solved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a hardware block diagram of a terminal that performs a layout scaling correction method according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for modifying layout graphical scaling in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram of an original layout pattern according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a first layout pattern according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a second layout pattern according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a third layout pattern according to an embodiment of the present application;
FIG. 7 is a flowchart of determining a modified target layout according to a first layout pattern and a third layout pattern according to an embodiment of the present application;
FIG. 8 is a schematic illustration of a difference pattern according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a modified target layout according to an embodiment of the present application;
FIG. 10 is a flow chart of a method for modifying layout graphical scaling in accordance with an embodiment of the present application;
fig. 11 is a block diagram of a layout pattern correction device according to an embodiment of the present application.
Detailed Description
For a clearer understanding of the objects, technical solutions and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and examples.
Unless defined otherwise, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and the like in this application are not intended to be limiting in number, but rather are singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used in the present application, are intended to cover a non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this application, merely distinguish similar objects and do not represent a particular ordering of objects.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or similar computing device. For example, the method runs on a terminal, and fig. 1 is a block diagram of a hardware structure of the terminal for executing a layout graph scaling correction method according to an embodiment of the present application. As shown in fig. 1, the terminal may include one or more (only one is shown in fig. 1) processors 102 and a memory 104 for storing data, wherein the processors 102 may include, but are not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and is not intended to limit the structure of the terminal. For example, the terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a layout graphic scaling correction method in the present embodiment, and the processor 102 executes the computer program stored in the memory 104 to perform various functional applications and data processing, that is, implement the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
In this embodiment, a method for correcting layout graphic scaling is provided, and fig. 2 is a flowchart of a method for correcting layout graphic scaling in the embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:
step S210, scaling the original layout graph to generate a first layout graph, namely a graph to be corrected.
Specifically, the integrated circuit design generates a GDS (Graphic Data System ) file, which is an industry standard data file for integrated circuit chip streaming, in which information for streaming is recorded for each layer of the chip, planar graphics within the layer, text labels, and the like. The GDS file includes a plurality of plane graphics (i.e., layout graphics of a plurality of layers), where the original layout graphics may be a layout graphics of a layer in the GDS file, and where a layer may be any layer in the GDS file. The layers in the GDS file may be layered according to the element type or according to other rules according to the user design. And scaling the layout pattern of a certain layer in the GDS file by using integrated circuit design software to generate a first layout pattern. The scaling process here includes a compression (krnk) process or an enlargement process on the original layout pattern. If the first layout pattern is a pattern obtained by compressing the patterns in the original layout pattern by a first preset proportion, the first preset proportion can be 80% -90%; for another example, the first layout pattern is a pattern obtained by performing a third preset proportion amplification treatment on the pattern in the original layout pattern, where the third preset proportion may be 110% -120%, and the third preset proportion is not specifically limited herein.
The vertexes of all graphics in the GDS are required to be on the grid points of the design grid, when the GDS, namely the original layout graphics, is subjected to scaling treatment, the original design grid is unchanged, when the vertexes of the scaled first layout graphics cannot fall on the grid points, the vertexes of the scaled first layout graphics automatically increase or decrease in value and fall on the nearby grid points, and therefore the first layout graphics generated after the scaling treatment are abnormal. The original layout graph is shown in fig. 3, the original layout graph comprises two graphs A1 and A2, the scaling treatment is carried out on the original layout graph shown in fig. 3, a first layout graph is generated, the graph A1 in fig. 3 is shown in fig. 4, the graph B1 in fig. 4 is generated after the scaling treatment is carried out on the graph A1 in fig. 3, the graph B2 in fig. 4 is generated after the scaling treatment is carried out on the graph A2 in fig. 3, a small gap (space) is generated between the graph B1 and the graph B2, no gap is reserved between the graph A1 and the graph A2 in the original layout graph, the graph B2 is higher than the graph B1, namely, the graph B2 generates a small step (step), and the heights of the graph A1 and the graph A2 in the original layout graph are the same. Because no gap exists between the graph A1 and the graph A2 in the original layout graph, the heights of the graph A1 and the graph A2 are consistent, and therefore, the first layout graph generated after the scaling processing is abnormal. Fig. 3 shows only a part of a layout pattern of a certain layer in the GDS file, and fig. 4 shows a part corresponding to fig. 3. It should be further noted that fig. 3 is only schematically illustrated by using the graphics A1 and the graphics A2, and it is understood that the original layout graphics may include a plurality of graphics, such as the graphics A1, the graphics A2, the graphics A3, the graphics A4, and the like, and the graphics A3 and the graphics A4 are not shown in fig. 3, and may be the same or different.
Step S220, merging (merge) is carried out on the original layout graph, and a second layout graph is generated.
Specifically, merging the original layout patterns according to a preset rule to generate a second layout pattern. Further, merging the layout patterns of a certain layer according to a preset rule to generate a second layout pattern. The preset rule can be that graphics which are in contact with or intersect with each other in the original layout graphics are combined into a larger graphic, and the preset rule can also be that the graphics are combined into a larger graphic according to the shape characteristics of the graphics. The graphics in the original layout graphics before combination are mutually independent, the boundaries of the graphics are calculated respectively during zooming, so that differences are generated, small gaps and steps are caused, the same graphics layer is combined into a whole after combination, and only new boundaries of the graphics are calculated during zooming after combination, so that differences are not generated. The merging operation merges the graphics contacted by the same layer into a single overall graphic. The integrated circuit design software can be used for merging the original layout graphs of the same layer. For example, two rectangles that touch or intersect each other are merged into one larger rectangle. Fig. 5 is a schematic diagram of a second layout pattern generated by merging the partial original layout pattern shown in fig. 3 according to a preset rule, wherein the preset rule is that the pattern A1 and the pattern A2 which are in contact with each other in fig. 3 are merged into a large pattern, and the merged pattern is shown as a pattern C1 in fig. 5. It should be noted that fig. 3 is only schematically illustrated by using two graphs A1 and A2 that are in contact with each other, and it is understood that the original layout graph may include a plurality of graphs that are in contact with each other, such as a graph A1, a graph A2, a graph A3, a graph A4, and the like, which may be the same or different. The patterns can be contacted with each other or two by two, for example, the pattern A1 is contacted with the pattern A2 and the pattern A4 respectively, the pattern A2 is contacted with the pattern A3 again, and the original layout patterns are combined at the moment, so that the pattern A1, the pattern A2, the pattern A3 and the pattern A4 are combined into a large pattern. The graphics A3 and the graphics A4 are not shown in fig. 3, and are only exemplary and not specifically limited herein.
And step S230, scaling the second layout pattern to generate a third layout pattern.
Specifically, the second layout pattern is scaled by using integrated circuit design software, and then a third layout pattern is generated. The third layout pattern is a pattern obtained by scaling the pattern in the second layout pattern by a second preset ratio, wherein the second preset ratio is the same as the first preset ratio in the step S210, the second preset ratio may be 80% -90%, or the second preset ratio is the same as the third preset ratio in the step S210, and the third preset ratio may be 110% -120%, which is not particularly limited herein. After the second layout pattern in fig. 5 is scaled, the generated third layout pattern is shown in fig. 6, and after the pattern C1 in fig. 5 is scaled by a second preset ratio, the pattern D1 in fig. 6 is generated, and since the pattern D1 in fig. 6 scales the whole pattern C1 in fig. 5 in the same ratio, the pattern D1 in fig. 6 will not generate gaps or steps. It should be noted that the third layout pattern cannot be directly used as the scaled layout pattern, because each pattern in the original layout pattern has its own information such as hierarchical relationship, scaling the original layout pattern cannot change the information such as the hierarchical relationship of the original layout pattern, and the pattern in the merged second layout pattern directly becomes a new whole pattern, so that the original layout information can be modified.
And step S240, correcting the first layout pattern according to the difference between the first layout pattern and the third layout pattern to obtain a corrected target layout.
Specifically, the difference between the first layout pattern and the third layout pattern is obtained, and the first layout pattern generated in the step S210 is corrected according to the difference between the first layout pattern and the third layout pattern, so as to obtain a corrected target layout.
In the embodiment, the original layout patterns are combined to generate the second layout pattern, scaling processing is carried out on the second layout pattern to generate the third layout pattern, and the first layout pattern is corrected according to the difference between the first layout pattern and the third layout pattern to obtain the corrected target layout, so that the gaps and steps occurring in the first layout pattern are corrected, and the technical problem that the gaps and steps occurring in the scaled layout cannot be corrected in the prior art is solved.
In some embodiments, merging the original layout patterns to generate a second layout pattern, including: merging graphs meeting the preset relation with the layers in the original layout graphs to generate a second layout graph; the preset relation is determined according to the position relation of the original layout graph.
Specifically, graphs meeting a preset relationship in the original layout graphs are obtained, wherein the preset relationship is determined according to the position relationship in the original layout graphs, for example, the preset relationship can be the graphs which are in contact with each other in the original layout graphs, and the preset relationship can also be the intersected graphs in the original layout graphs, for example, the graphs A1 and the graphs A2 in FIG. 3.
In this embodiment, the mutual contact or intersection patterns in the original layout patterns are combined, so that the layout patterns obtained after the combination are subjected to scaling treatment, the combination of the same layer of contact is integrated after the combination, and only new pattern boundaries are calculated when scaling is performed after the combination, so that no difference is generated.
In some embodiments, step S240, correcting the first layout pattern according to the difference between the first layout pattern and the third layout pattern to obtain a corrected target layout, includes the following steps, as shown in fig. 7:
step S242, comparing the first layout pattern with the third layout pattern, and generating a difference pattern according to the difference between the first layout pattern and the third layout pattern.
Specifically, a first layout pattern generated by scaling the original layout pattern is compared with a third layout pattern generated by scaling the second layout pattern, the difference between the first layout pattern and the third layout pattern is obtained according to a comparison result, and a difference pattern is generated according to the difference. The difference graph comprises more parts of the first layout graph than the third layout graph and/or the difference graph comprises more parts of the third layout graph than the first layout graph. The first layout pattern and the third layout pattern are compared by adopting the existing pattern comparison algorithm or method, the difference between the first layout pattern and the third layout pattern is obtained, and a difference pattern is generated according to the difference. The generated difference patterns are shown in fig. 8, and referring to fig. 4, fig. 6 and fig. 8, comparing fig. 4 and fig. 6, a portion of fig. 4 that is more than fig. 6 and a portion of fig. 6 that is more than fig. 4 may be obtained, that is, a portion of fig. 8 that includes a portion of the first layout pattern that is more than the third layout pattern, such as a pattern E1, and a portion of fig. 8 that includes a portion of the third layout pattern that is more than the first layout pattern, such as a pattern E2, where the pattern E1 is a step generated when the original layout pattern is scaled, and the pattern E2 is a void generated when the original layout pattern is scaled.
And step S244, correcting the first layout pattern by utilizing the difference pattern and the first layout pattern to obtain a corrected target layout.
Specifically, the first layout pattern is corrected according to the difference pattern generated in step S242, and the corrected target layout is obtained. Removing the part of the first layout pattern, which is more than the third layout pattern, from the first layout pattern, and compensating the part of the third layout pattern, which is more than the first layout pattern, to the corresponding position in the first layout pattern so as to realize the correction of the first layout pattern and obtain the corrected target layout. Illustratively, the graph of fig. 4 is modified using fig. 8, and a modified target layout is generated as shown in fig. 9. Referring to fig. 4, 6, 8 and 9, the modified target layout includes a pattern F1, a pattern F2 and a pattern F3. Since the pattern B1 in fig. 4 does not have a step, the pattern F1 in fig. 9 may be the same as the pattern B1 in fig. 4, since the pattern B2 in fig. 4 has a step, the pattern in fig. 9 may be generated according to the pattern E1 in fig. 8 and the pattern B2 in fig. 4, if the pattern B2 in fig. 4 is removed from the pattern E1 in fig. 8, the pattern F2 in fig. 9 is generated, and a gap between the pattern B1 in fig. 4 and the pattern B2 appears, which is the pattern E2 in fig. 8, that is, the pattern F3 in fig. 9 may be the same as the pattern E2 in fig. 8, and finally, a corrected target layout is generated as shown in fig. 9.
In the embodiment, the first layout pattern generated by scaling the original layout pattern is combined to generate the second layout pattern, scaling is performed on the second layout pattern to generate the third layout pattern, the difference pattern is generated according to the third layout pattern and the first layout pattern, and the first layout pattern is corrected according to the difference pattern to obtain the corrected target layout, so that the gap and the step which appear in the first layout pattern are corrected, and the technical problem that the gap and the step which appear in the scaled layout cannot be corrected in the prior art is solved.
In some embodiments, the difference pattern includes a first difference pattern and a second difference pattern; the first difference graph is a graph part with more first layout graphs than the third layout graphs, and the second difference graph is a graph part with more third layout graphs than the first layout graphs.
Specifically, the first difference pattern may refer to pattern E1 in fig. 8, and the second difference pattern may refer to pattern E2 in fig. 8.
In some embodiments, the obtaining the corrected target layout by using the difference graph and correcting the first layout graph includes: and removing the first difference graph from the first layout graph, and compensating the second difference graph to the corresponding position of the first layout graph to generate a corrected first layout, namely the target layout. In some of these embodiments, determining the modified target layout from the difference graphic and the first layout graphic includes: and compensating the overlapped part of the difference graph and the third graph into the first graph, and removing the non-overlapped part of the difference graph and the third graph from the first graph to generate a corrected target graph.
Specifically, an overlapping part and a non-overlapping part of the difference pattern and the third pattern are obtained, the overlapping part of the difference pattern and the third pattern is compensated into the first pattern, and the non-overlapping part of the difference pattern and the third pattern is removed from the first pattern, so that a corrected target pattern is generated. Illustratively, referring to fig. 6 and 8, the overlapping portion of the difference pattern and the third layout pattern is pattern E2, the non-overlapping portion of the difference pattern and the third layout pattern is pattern E1, the pattern E2 is compensated into fig. 4, the pattern E1 is removed from fig. 4, and the modified target layout as shown in fig. 9 is finally generated. In some embodiments, the layout graph scaling correction method further includes: determining a target layer in the original layout; and determining the graph of the target layer in the original layout as the original layout graph.
Specifically, the target layer may be any layer in the GDS file, and the target layer may be set according to the input of the user.
In this embodiment, a method for correcting layout graphic scaling is also provided, and fig. 10 is a flowchart of a method for correcting layout graphic scaling according to an embodiment of the present application, as shown in fig. 10, where the flowchart includes the following steps:
step S310, scaling the original layout pattern to generate a first layout pattern.
Step S320, merging the original layout patterns to generate a second layout pattern.
And step S330, scaling the second layout pattern to generate a third layout pattern.
And S340, comparing the first layout pattern with the third layout pattern, and generating a difference pattern according to the difference between the first layout pattern and the third layout pattern.
And step S350, determining the corrected target layout according to the difference graph and the first layout graph.
The specific implementation manner in this embodiment is described in detail in the foregoing embodiments, and will not be repeated here.
In the embodiment, the first layout pattern generated by scaling the original layout pattern is combined to generate the second layout pattern, scaling is performed on the second layout pattern to generate the third layout pattern, the difference pattern is generated according to the third layout pattern and the first layout pattern, and the first layout pattern is corrected according to the difference pattern to obtain the corrected target layout, so that the gap and the step which appear in the first layout pattern are corrected, and the technical problem that the gap and the step which appear in the scaled layout cannot be corrected in the prior art is solved.
It should be noted that the steps illustrated in the above-described flow or flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
The embodiment also provides a layout pattern correction device, which is used for realizing the above embodiment and the preferred implementation manner, and is not described again. The terms "module," "unit," "sub-unit," and the like as used below may refer to a combination of software and/or hardware that performs a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware, are also possible and contemplated.
Fig. 11 is a block diagram of a layout pattern correction device according to an embodiment of the present application, and as shown in fig. 11, the device includes:
the first generation module 10 is used for performing scaling processing on the original layout graph to generate a first layout graph, namely a graph of a to-be-corrected version graph;
the second generating module 20 is configured to combine the original layout patterns to generate a second layout pattern;
a third generating module 30, configured to perform the scaling processing on the second layout pattern, and generate a third layout pattern;
and the determining module 40 is configured to modify the first layout pattern according to the difference between the first layout pattern and the third layout pattern, so as to obtain a modified target layout.
The above-described respective modules may be functional modules or program modules, and may be implemented by software or hardware. For modules implemented in hardware, the various modules described above may be located in the same processor; or the above modules may be located in different processors in any combination.
There is also provided in this embodiment an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, scaling an original layout graph to generate a first layout graph, namely a graph to be corrected;
s2, merging the original layout patterns to generate a second layout pattern;
s3, performing the scaling processing on the second layout graph to generate a third layout graph;
s4, correcting the first layout pattern according to the difference between the first layout pattern and the third layout pattern, and obtaining a corrected target layout.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
In addition, in combination with the correction method for layout graphic scaling provided in the above embodiment, a storage medium may be further provided in this embodiment to implement the method. The storage medium has a computer program stored thereon; the computer program, when executed by a processor, implements the correction method for layout pattern scaling in any of the above embodiments.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present application, are within the scope of the present application in light of the embodiments provided herein.
It is evident that the drawings are only examples or embodiments of the present application, from which the present application can also be adapted to other similar situations by a person skilled in the art without the inventive effort. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as an admission of insufficient detail.
The term "embodiment" in this application means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A correction method for domain graphic scaling is characterized by comprising the following steps:
scaling the original layout graph to generate a first layout graph, namely a graph to be corrected;
merging the original layout patterns to generate a second layout pattern;
performing the scaling processing on the second layout graph to generate a third layout graph;
and correcting the first layout graph according to the difference between the first layout graph and the third layout graph to obtain a corrected target layout.
2. The method for correcting the scaling of the layout pattern according to claim 1, wherein the merging the original layout pattern to generate a second layout pattern comprises:
merging graphs meeting preset relations of the same layer in the original layout graphs to generate a second layout graph; the preset relation is determined according to the position relation of the original layout graph.
3. The correction method for domain graphic scaling according to claim 2, wherein correcting the first domain graphic according to the difference between the first domain graphic and the third domain graphic to obtain a corrected target domain comprises:
comparing the first layout pattern with the third layout pattern, and generating a difference pattern according to the difference between the first layout pattern and the third layout pattern;
and correcting the first layout graph by utilizing the difference graph and the first layout graph to obtain a corrected target layout.
4. A method for modifying a layout pattern according to claim 3, wherein the difference pattern comprises a first difference pattern and a second difference pattern;
the first difference graph is a graph part with the first layout graph being more than the third layout graph, and the second difference graph is a graph part with the third layout graph being more than the first layout graph.
5. The method for correcting layout pattern scaling according to claim 4, wherein the correcting the first layout pattern by using the difference pattern and obtaining a corrected target layout comprises:
and removing the first difference graph from the first layout graph, compensating the second difference graph to the corresponding position of the first layout graph, and generating the corrected first layout, namely the target layout.
6. The method for modifying a layout scale according to claim 1, further comprising:
determining a target layer in the original layout;
and determining the graph of the target layer in the original layout as the original layout graph.
7. The method for correcting layout graphic scaling according to claim 1, wherein the scaling process is a compression or amplification process.
8. A layout pattern scaling correction device, the device comprising:
the first generation module is used for carrying out scaling treatment on the original layout graph to generate a first layout graph, namely a graph to be corrected;
the second generation module is used for carrying out combination processing on the original layout figures to generate second layout figures;
the third generation module is used for carrying out the scaling processing on the second layout graph to generate a third layout graph;
the determining module is used for correcting the first layout graph according to the difference between the first layout graph and the third layout graph to obtain a corrected target layout.
9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of modifying layout graphical scaling of any of claims 1 to 7.
10. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the layout pattern scaling modification method of any one of claims 1 to 7.
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