CN115863203A - Method, system, device, computer equipment and medium for acquiring test pattern - Google Patents
Method, system, device, computer equipment and medium for acquiring test pattern Download PDFInfo
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Abstract
The invention relates to a method, a system, a device, a computer device and a storage medium for acquiring a test pattern. The method for obtaining the test pattern comprises the steps of firstly obtaining a plurality of scanning images of different test patterns on a wafer respectively, then overlapping each scanning image with a target layout respectively, correspondingly obtaining measuring distances between an edge outline of the target layout and edge outlines of the scanning images respectively, and then selecting the target test pattern from the test patterns based on the measuring distances. The characteristic dimension of the measuring distance from the edge outline reflects the difference between the wafer surface pattern and the target layout, so that the right angle of the wafer surface pattern is quantized. In addition, the right angle of the graph transferred to the surface of the wafer by the target test graph is high, so that the target test graph can be used as the graph after the target layout is corrected and compensated for the photoetching imaging of the wafer, the correction compensation of the target layout is realized, and the right angle of the graph on the surface of the wafer is improved.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method, a system, an apparatus, a computer device, and a medium for obtaining a test pattern.
Background
The patterning process (photolithography) is used to transfer the layout of a customer design to the surface of a wafer (wafer), which is a key process flow in the chip manufacturing process. The difference between the size of the wafer surface pattern and the design layout is a key index for measuring the patterning process performance. However, due to factors such as manufacturing errors caused by the fact that a complete 90 ° angle cannot be written on the photomask, and the limitation of the resolution of the machine, the pattern on the photomask becomes rounded (corner rounding) at a right angle when being transferred onto the wafer, and this corner rounding may cause the total Area of the pattern to be reduced, thereby affecting the performance of the chip, for example, the reduction of the pattern Area of some ion implantation layers (Active areas, ACT) may cause the reduction of the effective Area of ion implantation in the Active Area.
Because the rounding degree of the right angle of the graph is difficult to quantify, the original design layout is difficult to accurately compensate and correct, and therefore the corrected layout cannot be transferred to the surface of a wafer to have better right angle, and the performance of a chip is guaranteed.
Disclosure of Invention
In view of the foregoing, there is a need for a method, system, apparatus, computer device, storage medium, and program product for obtaining a test pattern that improves squareness of a pattern on a wafer surface.
In order to achieve the above object, in one aspect, the present invention provides a method for obtaining a test pattern. The method comprises the following steps:
correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the positions of all right angles of the test patterns, and the sizes of the rectangular compensation areas of all the test patterns are different;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring a measurement distance between an edge contour of the target layout and an edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the overlapping each of the scan images with the target layout respectively includes:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the method further comprises:
respectively and correspondingly acquiring the overlay distance between the preset edge of each scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the obtaining the measurement distance between the edge profile of the target layout and the edge profile of each of the scan images respectively includes:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to each candidate distance, correspondingly acquiring the measurement distance between the edge contour of the target layout and the edge contour of each scanned image.
In one embodiment, the determining a target test pattern from a plurality of test patterns according to each of the measurement distances includes:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
On the other hand, the application also provides a system for acquiring the test pattern. The system comprises:
the wafer placing table is used for placing wafers;
the scanning electron microscope is used for correspondingly acquiring a scanning image of each testing pattern on the wafer based on a plurality of testing patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the rectangular compensation patterns of the test patterns are different in size;
the machine station is used for respectively carrying out overlay on each scanning image and a target layout and respectively and correspondingly obtaining the measuring distance between the edge outline of the target layout and the edge outline of each scanning image; and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
On the other hand, the application also provides a device for acquiring the test pattern. The device comprises:
the first acquisition module is used for correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the rectangular compensation patterns of the test patterns are different in size;
the second acquisition module is used for respectively carrying out overlay on each scanning image and the target layout and respectively and correspondingly acquiring the measurement distance between the edge outline of the target layout and the edge outline of each scanning image;
and the determining module is used for determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
On the other hand, the application also provides computer equipment. The computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the test pattern acquisition method according to any one of the above embodiments when executing the computer program.
In another aspect, the present application further provides a computer storage medium. The computer-readable storage medium stores thereon a computer program, and when executed by a processor, the computer program implements the steps of the method for obtaining a test pattern according to any one of the above embodiments.
In another aspect, the present application also provides a computer program product. The computer program product includes a computer program, and the computer program realizes the steps of the method for acquiring the test pattern according to any one of the above embodiments when executed by a processor.
The method, the system, the device, the computer equipment, the storage medium and the program product for obtaining the test patterns are characterized in that firstly, scanning images of a plurality of different test patterns on a wafer are respectively obtained, then, each scanning image is respectively superposed with a target layout, the measuring distances between the edge outline of the target layout and the edge outline of each scanning image are respectively and correspondingly obtained, and then, the target test pattern is selected from the plurality of test patterns based on each measuring distance. The characteristic dimension of the measuring distance from the edge outline reflects the difference between the wafer surface pattern and the target layout, so that the right angle of the wafer surface pattern is quantized. In addition, the right angle of the graph transferred to the surface of the wafer by the target test graph is high, so that the target test graph can be used as the graph after the target layout is corrected and compensated for the photoetching imaging of the wafer, the correction compensation of the target layout is realized, and the right angle of the graph on the surface of the wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for obtaining a test pattern provided in an embodiment;
FIG. 2a is a schematic diagram of an L-shaped target layout provided in an embodiment;
FIG. 2b is a diagram illustrating an additional rectangular compensation area for a target layout according to an embodiment;
FIG. 2c is a schematic diagram of an L-shaped test pattern according to an embodiment;
FIG. 3 is a flowchart illustrating a method for obtaining a test pattern according to an embodiment;
FIG. 4 is a schematic flowchart illustrating a method for obtaining a test pattern according to another embodiment;
FIG. 5 is a flowchart illustrating a method for obtaining a test pattern according to yet another embodiment;
FIG. 6a is a schematic diagram of a measuring bar placed at a right-angle side of a target layout provided in an embodiment;
FIG. 6b is a schematic diagram of a measuring bar placed at a right-angle side of the target layout in another embodiment;
FIG. 7 is a flowchart illustrating a method for obtaining a test pattern according to an embodiment;
FIG. 8 is a flowchart illustrating a method for obtaining a test pattern according to another embodiment;
FIG. 9 is a schematic view of an SEM picture provided in one embodiment;
FIG. 10 is a graphical illustration of the relationship between different test patterns and EPE provided in one embodiment;
FIG. 11 is a block diagram illustrating an exemplary system for obtaining test patterns;
FIG. 12 is a block diagram illustrating an exemplary apparatus for obtaining a test pattern;
fig. 13 is a schematic internal structure diagram of a computer device provided in an embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As the background art, the rounding degree of the right angle of the wafer surface pattern is difficult to quantify, usually, the right angle of the pattern is corrected and compensated based on an empirical value, and this method is greatly influenced by subjective factors, has poor precision and low efficiency, and cannot ensure the right angle of the wafer surface pattern, thereby affecting the performance of the chip.
Therefore, the application provides a method, a system, a device, a computer device, a storage medium and a program product for obtaining a test pattern, which improve the right angle of the pattern on the surface of the wafer and ensure the performance of the chip.
In one embodiment, as shown in FIG. 1, a method for obtaining a test pattern is provided. The method for acquiring the test pattern may include the following steps S10 to S30.
S10: and correspondingly acquiring a scanning image of each test pattern on the wafer based on the plurality of test patterns.
The test pattern refers to an arbitrary pattern having a right angle, for example, an L shape, an F shape. And rectangular compensation areas are arranged at the right-angle positions of the test pattern. In other words, a rectangular compensation region is additionally arranged at each right angle of the target layout to obtain a corresponding test pattern. The sizes of the rectangular compensation areas of the test patterns are different, the sizes of the rectangular compensation areas of the same test pattern are the same, and the test patterns correspond to the same target layout.
The scanning image is an image obtained by writing a test pattern on a photomask, transferring the test pattern onto a wafer through the photomask, and scanning the pattern on the surface of the wafer. The Scanning image may be obtained by any image Scanning device, and for example, the Scanning Electron Microscope (SEM) may be used to scan the wafer to obtain the SEM picture.
S20: and overlapping each scanning image with the target layout respectively, and correspondingly acquiring the measurement distance between the edge outline of the target layout and the edge outline of each scanning image respectively.
Overlay refers to overlapping and aligning the pattern in the scanned image with the target layout. In this step, each scanned image needs to be overlaid with the target layout, so as to sequentially obtain the measurement distance corresponding to each test pattern.
The measurement distance is used for identifying the distance between the edge outline of the scanned image and the edge outline of the target layout. The larger the measurement distance, that is, the larger the distance between the edge profile of the scanned image and the edge profile of the target layout, indicates that the larger the difference between the test pattern and the wafer surface pattern, the lower the right angle of the wafer surface pattern. The smaller the measurement distance is, the smaller the distance between the edge profile of the scanned image and the edge profile of the target layout is, which indicates that the smaller the difference between the test pattern and the wafer surface pattern is, the higher the right angle of the wafer surface pattern is. The wafer surface pattern is a pattern formed on the wafer surface by photoetching of a test pattern.
S30: and determining a target test pattern from the plurality of test patterns according to the measurement distances.
The target test pattern is a test pattern of the target layout, or the target test pattern is a test pattern which is selected from a plurality of test patterns and corresponds to a wafer with a higher right angle, and the test pattern is used in a wafer patterning process.
For example, a test pattern corresponding to the minimum value may be selected from the measurement distances as a target test pattern, or a test pattern smaller than a measurement distance threshold may be selected from the measurement distances as a target test pattern. The measuring distance threshold is preset and used for identifying that the right angle of the wafer surface pattern meets the requirement, and can be obtained by measuring according to an empirical value or multiple experimental values.
The method for obtaining the test pattern provided in the above embodiment includes first obtaining scan images of a plurality of different test patterns on a wafer, then overlapping each scan image with a target layout, and obtaining measurement distances between an edge contour of the target layout and an edge contour of each scan image, respectively, and then selecting a target test pattern from the plurality of test patterns based on the measurement distances. The difference between the wafer surface pattern and the target layout is reflected by the characteristic dimension of the measuring distance from the edge profile, so that the right angle of the wafer surface pattern is quantized. In addition, the right angle of the graph transferred to the surface of the wafer by the target test graph is high, so that the target test graph can be used as the graph after the target layout is corrected and compensated for the photoetching imaging of the wafer, the correction compensation of the target layout is realized, and the right angle of the graph on the surface of the wafer is improved.
In one embodiment, the test pattern has a right-angled protruding position and a right-angled recessed position, for example, an E-shaped or a recessed test pattern, in which case the rectangular compensation region at the right-angled protruding position of the test pattern is provided with a rectangular compensation pattern, and the rectangular compensation region at the right-angled recessed position of the test pattern is notched with the rectangular compensation pattern. It should be noted that the test pattern may also have only right-angled protruding positions, for example, an I-shaped test pattern, in which case the rectangular compensation regions at the right-angled protruding positions of the test pattern are provided with rectangular compensation patterns. The rectangular compensation area or the notch of the rectangular compensation area in the test pattern can be determined according to the specific shape of the right angle of the test pattern, and is not limited herein.
The rectangular compensation area refers to an area which is formed by adding the test pattern relative to the target layout, and the rectangular compensation pattern refers to a difference pattern of the test pattern between the rectangular compensation area and the target layout. Correcting and compensating each right angle of the target layout based on the rectangular compensation pattern to obtain a plurality of test patterns, and selecting a test pattern with better correction and compensation from the plurality of test patterns for wafer photoetching patterning, so that the right angle of the wafer surface pattern is improved.
For better understanding, the target layout shown in fig. 2a is illustrated as L-shaped. As shown in fig. 2b, there are 6 right angles in the L-shaped target layout, including 5 right-angle male locations and 1 right-angle female locations. Specifically, rectangular compensation regions a1, a2, a3, a4, and a5 are respectively disposed at the right-angle protruding positions, and correspondingly, rectangular compensation patterns are disposed on the rectangular compensation regions a1, a2, a3, a4, and a5, wherein the rectangular compensation region a1 is provided with the rectangular compensation patterns as shown in a region a in fig. 2 c. Rectangular compensation patterns B are arranged at the right-angle recessed positions, and correspondingly, gaps of the rectangular compensation patterns are arranged in the rectangular compensation areas B, as shown in the areas B in fig. 2 c.
In one embodiment, as shown in fig. 3, the step S20 of overlapping each scanned image with the target layout may include the following steps S211 and S212.
S211: and respectively and correspondingly extracting the edge contour of each scanned image according to a preset pixel threshold value and the pixel value of each scanned image pixel point.
The pixel threshold is preset, and may be specifically set according to the actual situation of the scanned image, which is not limited herein. Specifically, the edge contour (contour) of the scanned image is extracted by comparing the pixel value of each pixel point of the scanned image with the pixel threshold value. Wherein the edge profile may comprise at least one of an outer profile and an inner profile.
S212: and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image and the edge contour of the target layout respectively.
The Critical Dimension (CD) is a special line pattern designed to reflect the line width of the features of the integrated circuit in order to evaluate and control the processing precision of the pattern in the integrated circuit photomask manufacturing and lithography process. The measured CD value is preset, and may be preset according to the wafer patterning process requirement, which is not limited in this application.
According to the method for obtaining the test pattern provided by the embodiment, because the contrast between the edge profile of the scanned image and the background is different, the edge profile of the pattern in the scanned image can be automatically extracted in a pixel threshold comparison mode, and based on the edge profile, overlay between the scanned image and the target layout is realized, so that measurement of the right angle of the pattern after the test image is transferred to the surface of the wafer can be realized.
Based on the method for acquiring the test pattern provided in the embodiment shown in fig. 3, as shown in fig. 4, the method for acquiring the test pattern may further include the following steps S213 and S214.
S213: and correspondingly acquiring the overlay distance between the preset edge of each scanning image and the edge outline of the target layout respectively.
S214: and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than the distance threshold.
The preset edge refers to at least one contour edge of a pre-designated test pattern. Taking the L-shaped test pattern shown in fig. 2c as an example, the predetermined sides may be 4 long sides of the L-shape. The distance threshold is preset and can be set according to precision requirements and experiments, for example, the distance threshold is set to be 2nm, and when the overlay distance between the preset edge of the scanned image and the edge outline of the target layout is smaller than 2nm, it is determined that the overlay between the scanned image and the target layout is successful.
According to the method for obtaining the test pattern, whether the overlay distance between the preset edge of the scanned image and the edge profile of the target layout is smaller than the distance threshold value or not is judged, so that the overlay accuracy between the scanned image and the target layout is guaranteed, the measurement accuracy of the measurement distance between the edge profile of the scanned image and the edge profile of the target layout is improved, and the right angle of the wafer surface pattern is further improved.
In an embodiment, as shown in fig. 5, step S20 may include the following steps S221 and S222, respectively corresponding to obtaining the measured distance between the edge profile of the target layout and the edge profile of each scanned image.
S221: and aiming at each scanning image, respectively and correspondingly measuring the candidate distance between the preset point on each measuring rod and the edge profile of each scanning image.
Wherein, each measuring rod is correspondingly positioned on each right-angle side of the target layout respectively. And the measuring bar (measurement bar) is used for measuring the distance between the target layout and the scanning image. The length of the measuring rod is not limited at all, and the measuring rod can be set according to the actual size of a scanned image.
Taking the area C of the test pattern shown in fig. 2C as an example, the area C includes two convex right angles and three right-angled sides, and accordingly, measuring rods m1, m2 and m3 can be respectively placed on the three right-angled sides, as shown in fig. 6 a. For another example, for the region B of the test pattern shown in fig. 2c, the region B includes a recessed right angle and two right-angled sides, and accordingly, measuring bars m4 and m5 can be disposed on the two right-angled sides, respectively, as shown in fig. 6B. Wherein x represents the edge contour of the target layout, and y represents the edge contour of the scanned image.
The preset points on each measuring rod can be any points on the measuring rod, the number of the preset points can be set according to actual measurement requirements, and the application does not limit the parameters such as the position, the number and the like of the preset points. The candidate distance is a straight-line distance between a preset point on the measuring rod and the edge profile of the scanned image. For example, the distance between two adjacent preset points may be set to be 1nm, and then the linear distance between the edge of the target layout and the edge profile of the scanned image may be measured every 1 nm.
S222: and according to the candidate distances, respectively and correspondingly obtaining the measuring distance between the edge outline of the target layout and the edge outline of each scanning image.
Based on the above S221, a plurality of candidate distances may be acquired for one scan image. For example, the plurality of candidate distances may be weighted and averaged to obtain a measurement distance (EPE) between the edge contour of the scanned image and the edge contour of the target layout. Based on this, for each scanned image, the respective EPE value can be acquired correspondingly.
According to the method for obtaining the test pattern, the difference between the edge profile of the target layout and the edge profile of the scanned image is effectively quantified by using the measuring rod, so that the target test pattern at the measuring distance corresponding to each scanned image can be obtained according to the measuring rod, and the right angle of the wafer surface pattern is improved.
In one embodiment, as shown in fig. 7, the step S30 of determining a target test pattern from a plurality of test patterns according to the respective measurement distances may include the following steps S310 and S320.
S310: and determining the minimum measuring distance according to the measuring distances. Specifically, the minimum EPE value is found from the EPE values of the respective scanned images.
S320: and determining the test pattern corresponding to the minimum measurement distance as a target test pattern.
The minimum measurement distance, namely the minimum EPE value, indicates that the distance between the edge outline of the scanned image and the edge outline of the target layout is shortest, namely the difference between the edge outline of the scanned image and the edge outline of the target layout is minimum, and the correction compensation effect of the test pattern corresponding to the scanned image on the target layout is good, so that the method can be used for wafer photoetching patterning.
According to the method for obtaining the test pattern, the test pattern corresponding to the minimum measurement distance is determined as the target test pattern, and the target test pattern has a good correction compensation effect on the target pattern, so that the right angle of the pattern formed on the surface of the wafer is high after the wafer is subjected to photoetching patterning based on the target test pattern, the right angle of the pattern on the surface of the wafer is guaranteed, and the performance of a chip is guaranteed.
For better understanding, taking the L-shaped target layout shown in fig. 2a as an example, another method for obtaining the test pattern is provided. As shown in fig. 8, the method for acquiring the test pattern may include the following steps S801 to S809.
S801: and respectively and correspondingly acquiring a scanning image of each test pattern on the wafer by utilizing the SEM based on the plurality of test patterns. For example, scanning the test pattern shown in fig. 2C with SEM, the SEM picture corresponding to the area C is shown in fig. 9.
S802: and respectively and correspondingly extracting the edge contour of each scanned image according to a preset pixel threshold value and the pixel value of each scanned image pixel point.
S803: and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image and the edge contour of the target layout respectively.
S804: and correspondingly acquiring the overlay distance between the preset edge of the scanned image and the edge outline of the target layout respectively.
S805: and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than the distance threshold.
S806: and aiming at each scanning image, correspondingly measuring the candidate distance between the preset point on each measuring rod and the edge profile of each scanning image, wherein each measuring rod is positioned on each right-angle side of the target layout.
S807: and according to the candidate distances, respectively and correspondingly obtaining the measuring distance between the edge outline of the target layout and the edge outline of each scanning image. The measurement distance EPE of each scan image is shown in fig. 10, in which the abscissa represents different test patterns and the ordinate represents the EPE value.
S808: and determining the minimum measuring distance according to the measuring distances. Specifically, the minimum EPE value is found from the EPE values of the respective scanned images.
S809: and determining the test pattern corresponding to the minimum measuring distance as the target test pattern.
The method for obtaining the test pattern provided by the embodiment can quantify the rounding degree of the right angle of the pattern on the surface of the wafer, improve the measurement precision, process a large number of SEM pictures in batches and effectively improve the working efficiency.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
Based on the same inventive concept, the embodiment of the application also provides a test pattern acquisition system for realizing the test pattern acquisition method. The implementation scheme for solving the problem provided by the system is similar to the implementation scheme described in the method, so the specific limitations in the following embodiment of the system for acquiring one or more test patterns may refer to the limitations on the method for acquiring test patterns in the foregoing description, and details are not repeated here.
In one embodiment, as shown in FIG. 11, a test pattern acquisition system is provided. The test pattern acquisition system 1100 may include a wafer stage 1101, a scanning electron microscope 1102, and a machine 1103.
The wafer stage 1101 is used for placing a wafer. The scanning electron microscope 1102 is configured to correspondingly obtain a scanning image of each test pattern on the wafer based on the plurality of test patterns, where rectangular compensation patterns are disposed at right-angle positions of the test patterns, and sizes of the rectangular compensation patterns of the test patterns are different. The machine 1103 is connected to the scanning electron microscope 1102, and the machine 1103 is configured to overlay each of the scanned images with the target layout, respectively and correspondingly obtain a measurement distance between an edge profile of the target layout and an edge profile of each of the scanned images, and determine a target test pattern from the plurality of test patterns according to each measurement distance, where the target test pattern is a test pattern of the target layout.
The system for acquiring the test pattern provided by the embodiment comprises a wafer placing table, a scanning electron microscope and a machine table. After the test patterns are transferred onto the wafer, the wafer is placed on a wafer placing table, then scanning images of different test patterns on the wafer are respectively obtained through a scanning electron microscope, each scanning image is respectively overlapped with the target layout through an SEM (scanning electron microscope), measuring distances between the edge outline of the target layout and the edge outline of each scanning image are respectively and correspondingly obtained, and then the target test pattern is selected from the test patterns based on the measuring distances. The characteristic dimension of the measuring distance from the edge outline reflects the difference between the wafer surface pattern and the target layout, so that the right angle of the wafer surface pattern is quantized. In addition, the right angle of the graph transferred to the surface of the wafer by the target test graph is high, so that the target test graph can be used as the graph after the target layout is corrected and compensated for the photoetching imaging of the wafer, the correction compensation of the target layout is realized, and the right angle of the graph on the surface of the wafer is improved.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the machine 1103 is further configured to:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the machine 1103 is further configured to:
respectively and correspondingly acquiring the overlay distance between the preset edge of each scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the machine 1103 is further configured to:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle side of the target layout;
and according to each candidate distance, correspondingly acquiring the measurement distance between the edge contour of the target layout and the edge contour of each scanned image.
In one embodiment, the machine 1103 is further configured to:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
Based on the same inventive concept, the embodiment of the present application further provides an apparatus for acquiring a test pattern, which is used for implementing the method for acquiring a test pattern. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so specific limitations in the following embodiments of the apparatus for acquiring one or more test patterns may refer to the limitations in the above method for acquiring test patterns, and details are not described herein again.
In one embodiment, a device for acquiring a test pattern is also provided. As shown in fig. 12, the apparatus 1200 for acquiring a test pattern may include a first acquiring module 1201, a second acquiring module 1202, and a determining module 1203.
The first obtaining module 1201 is configured to obtain, based on a plurality of test patterns, a scan image of each test pattern on a wafer; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the rectangular compensation patterns of the test patterns are different in size. The second obtaining module 1202 is configured to overlay each of the scan images with a target layout, and correspondingly obtain a measurement distance between an edge contour of the target layout and an edge contour of each of the scan images. The determining module 1203 is configured to determine a target test pattern from the multiple test patterns according to each of the measurement distances, where the target test pattern is a test pattern of the target layout.
The device for acquiring the test pattern provided by the embodiment comprises a first acquiring module, a second acquiring module and a determining module. Firstly, a first acquisition module is used for respectively acquiring scanning images of a plurality of different test patterns on a wafer, then a second acquisition module is used for respectively overlapping each scanning image with a target layout, the measurement distances between the edge outline of the target layout and the edge outline of each scanning image are respectively and correspondingly acquired, and then a determination module is used for selecting the target test pattern from the plurality of test patterns based on each measurement distance. The characteristic dimension of the measuring distance from the edge outline reflects the difference between the wafer surface pattern and the target layout, so that the right angle of the wafer surface pattern is quantized. In addition, the right angle of the graph transferred to the surface of the wafer by the target test graph is high, so that the target test graph can be used as the graph after the target layout is corrected and compensated for the photoetching imaging of the wafer, the correction compensation of the target layout is realized, and the right angle of the graph on the surface of the wafer is improved.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the second obtaining module 1202 is further configured to:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the determining module 1203 is further configured to:
respectively and correspondingly acquiring the overlay distance between the preset edge of each scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the second obtaining module 1202 is further configured to:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle side of the target layout;
and according to the candidate distances, correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image.
In one embodiment, the determining module 1203 is further configured to:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
The modules in the above test pattern obtaining device may be wholly or partially implemented by software, hardware, or a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 13. The computer apparatus includes a processor, a memory, a communication interface, a display unit, and an input device connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a test pattern acquisition method. The display unit of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 13 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the rectangular compensation areas of the test patterns are different in size;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring a measurement distance between an edge contour of the target layout and an edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
respectively and correspondingly acquiring the overlay distance between the preset edge of the scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle side of the target layout;
and according to each candidate distance, correspondingly acquiring the measurement distance between the edge contour of the target layout and the edge contour of each scanned image.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the rectangular compensation areas of the test patterns are different in size;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring a measurement distance between an edge profile of the target layout and an edge profile of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly acquiring the overlay distance between the preset edge of the scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to each candidate distance, correspondingly acquiring the measurement distance between the edge contour of the target layout and the edge contour of each scanned image.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:
correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the rectangular compensation areas of the test patterns are different in size;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring a measurement distance between an edge contour of the target layout and an edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation region at the right-angle protruding position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly acquiring the overlay distance between the preset edge of the scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle side of the target layout;
and according to the candidate distances, correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a minimum measuring distance according to each measuring distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
It should be noted that the data referred to in the present application (including but not limited to data for analysis, stored data, presented data, etc.) are information and data authorized by the user or sufficiently authorized by each party.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include a Read-Only Memory (ROM), a magnetic tape, a floppy disk, a flash Memory, an optical Memory, a high-density embedded nonvolatile Memory, a resistive Random Access Memory (ReRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a Phase Change Memory (PCM), a graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims (10)
1. A method for acquiring a test pattern is characterized by comprising the following steps:
correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the positions of all right angles of the test patterns, and the sizes of the rectangular compensation areas of all the test patterns are different;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring a measurement distance between an edge contour of the target layout and an edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
2. The method as claimed in claim 1, wherein the rectangular compensation region at the right-angle protruded position of the test pattern is provided with a rectangular compensation pattern, and the rectangular compensation region at the right-angle recessed position of the test pattern is provided with a notch having the rectangular compensation pattern.
3. The method for obtaining the test pattern according to claim 1, wherein the overlay of each of the scan images with the target layout respectively comprises:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each pixel point of the scanning image;
and zooming each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and overlapping the edge contour of each scanning image with the edge contour of the target layout respectively.
4. The method for obtaining a test pattern according to claim 3, further comprising:
respectively and correspondingly acquiring the overlay distance between the preset edge of each scanning image and the edge outline of the target layout;
and determining that the overlay between each scanning image and the target layout is successful under the condition that the overlay distance between the preset edge of each scanning image and the edge outline of the target layout is smaller than a distance threshold value.
5. The method for obtaining the test pattern according to claim 1, wherein the correspondingly obtaining the measurement distance between the edge profile of the target layout and the edge profile of each of the scan images respectively comprises:
respectively and correspondingly measuring a candidate distance between a preset point on each measuring rod and the edge profile of each scanning image aiming at each scanning image; wherein, each measuring rod is respectively positioned on each right-angle side of the target layout;
and according to each candidate distance, correspondingly acquiring the measurement distance between the edge contour of the target layout and the edge contour of each scanned image.
6. The method for obtaining the test pattern according to claim 1, wherein the determining a target test pattern from the plurality of test patterns according to each of the measurement distances includes:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
7. A system for obtaining a test pattern, comprising:
the wafer placing table is used for placing wafers;
the scanning electron microscope is used for correspondingly acquiring a scanning image of each testing pattern on the wafer based on a plurality of testing patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the sizes of the rectangular compensation patterns of the test patterns are different;
the machine station is used for respectively carrying out overlay on each scanning image and a target layout and respectively and correspondingly obtaining the measuring distance between the edge outline of the target layout and the edge outline of each scanning image; and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
8. An apparatus for acquiring a test pattern, comprising:
the first acquisition module is used for correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the rectangular compensation patterns of the test patterns are different in size;
the second acquisition module is used for respectively carrying out overlay on each scanning image and the target layout and respectively and correspondingly acquiring the measurement distance between the edge outline of the target layout and the edge outline of each scanning image;
and the determining module is used for determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method for obtaining a test pattern according to any one of claims 1 to 6 when executing the computer program.
10. A computer storage medium on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of acquiring a test pattern of any one of claims 1 to 6.
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