CN115863203B - Test pattern acquisition method, system, device, computer equipment and medium - Google Patents
Test pattern acquisition method, system, device, computer equipment and medium Download PDFInfo
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Abstract
The invention relates to a test pattern acquisition method, a test pattern acquisition system, a test pattern acquisition device, a test pattern acquisition computer device and a test pattern storage medium. According to the test pattern acquisition method, firstly, scanning images of a plurality of different test patterns on a wafer are respectively acquired, then each scanning image is respectively overlapped with a target layout, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are respectively acquired correspondingly, and then the target test pattern is selected from the plurality of test patterns based on each measuring distance. The measuring distance represents the difference between the wafer surface pattern and the target layout from the characteristic dimension of the edge profile, so that the quantification of the straight angle of the wafer surface pattern is realized. In addition, the straight angle of the pattern transferred to the surface of the wafer by the target test pattern is higher, so that the target test pattern can be used as the pattern subjected to correction and compensation of the target layout for photoetching and imaging of the wafer, correction and compensation of the target layout are realized, and the straight angle of the pattern on the surface of the wafer is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method, a system, an apparatus, a computer device, and a medium for acquiring a test pattern.
Background
Patterning (photolithography) is used to transfer the layout of the customer design to the surface of a wafer (wafer), which is a critical process in the chip manufacturing process. The difference between the wafer surface pattern size and the design layout is a key indicator for measuring the patterning process performance. However, due to manufacturing errors caused by the fact that the mask cannot write a complete 90 ° angle, limitations of the resolution of the machine, and other factors, the pattern on the mask becomes round (counter round) at a right angle when being transferred onto the wafer, and the counter round can lead to a reduction of the total Area of the pattern, so that the performance of the chip is affected, for example, a reduction of the pattern Area of some ion implantation layers (Active Area) can lead to a reduction of the Active Area of Active Area (ACT) ion implantation.
Because the rounding degree of the right angle of the graph is difficult to quantify, the original design layout is difficult to accurately compensate and correct, so that the corrected layout can not be ensured to be transferred to the surface of the wafer, and the wafer has a good straight angle so as to ensure the performance of the chip.
Disclosure of Invention
In view of the foregoing, there is a need for a method, a system, an apparatus, a computer device, a storage medium, and a program product for acquiring a test pattern, which improve the straightness of a wafer surface pattern.
In order to achieve the above object, in one aspect, the present invention provides a method for acquiring a test pattern. The method comprises the following steps:
respectively and correspondingly acquiring a scanning image of each test pattern on a wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the rectangular compensation areas of each test pattern are different in size;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the overlapping each of the scanned images with the target layout includes:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the method further comprises:
respectively and correspondingly acquiring the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the obtaining the measured distances between the edge contours of the target layout and the edge contours of the scanned images respectively includes:
for each scanning image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanning image correspondingly; wherein, each measuring bar is respectively positioned on each right-angle edge of the target layout;
And according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the determining a target test pattern from the plurality of test patterns according to each measured distance includes:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
On the other hand, the application also provides a test pattern acquisition system. The system comprises:
the wafer placing table is used for placing wafers;
the scanning electron microscope is used for respectively and correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the sizes of the rectangular compensation patterns of the test patterns are different;
the machine is used for respectively overlapping each scanning image with the target layout and respectively correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image; and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
On the other hand, the application also provides a test pattern acquisition device. The device comprises:
the first acquisition module is used for correspondingly acquiring a scanning image of each test pattern on the wafer based on the plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, and the sizes of the rectangular compensation patterns of the test patterns are different;
the second acquisition module is used for overlapping each scanning image with the target layout respectively and correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image respectively;
and the determining module is used for determining a target test pattern from the plurality of test patterns according to each measured distance, wherein the target test pattern is the test pattern of the target layout.
In another aspect, the present application also provides a computer device. The computer device includes a memory storing a computer program and a processor implementing the steps of the test pattern acquisition method described in any of the above embodiments when the processor executes the computer program.
In another aspect, the present application also provides a computer storage medium. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the test pattern acquisition method described in any one of the above embodiments.
In another aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the steps of the test pattern acquisition method according to any one of the embodiments described above.
The method, the system, the device, the computer equipment, the storage medium and the program product for acquiring the test patterns are characterized in that firstly, scanning images of a plurality of different test patterns on a wafer are respectively acquired, then each scanning image is respectively overlapped with a target layout, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are respectively and correspondingly acquired, and then the target test pattern is selected from the plurality of test patterns based on each measuring distance. The measuring distance represents the difference between the wafer surface pattern and the target layout from the characteristic dimension of the edge profile, so that the quantification of the straight angle of the wafer surface pattern is realized. In addition, the straight angle of the pattern transferred to the surface of the wafer by the target test pattern is higher, so that the target test pattern can be used as the pattern subjected to correction and compensation of the target layout for photoetching and imaging of the wafer, correction and compensation of the target layout are realized, and the straight angle of the pattern on the surface of the wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for acquiring test patterns according to an embodiment;
FIG. 2a is a schematic diagram of an L-shaped target layout provided in one embodiment;
FIG. 2b is a schematic diagram of adding a rectangular compensation region to a target layout according to one embodiment;
FIG. 2c is a schematic diagram of an L-shaped test pattern according to one embodiment;
FIG. 3 is a flowchart illustrating a method for acquiring a test pattern according to an embodiment;
FIG. 4 is a flowchart of a method for acquiring a test pattern according to another embodiment;
FIG. 5 is a flowchart of a method for acquiring a test pattern according to another embodiment;
FIG. 6a is a schematic diagram of a target layout right angle side placement measurement bar provided in one embodiment;
FIG. 6b is a schematic diagram of a target layout right angle side placement metrology bar provided in another embodiment;
FIG. 7 is a flowchart of a method for acquiring a test pattern according to an embodiment;
FIG. 8 is a flowchart of a method for acquiring a test pattern according to another embodiment;
FIG. 9 is a schematic diagram of an SEM image provided in an embodiment;
FIG. 10 is a graph showing the relationship between different test patterns and EPEs provided in one embodiment;
FIG. 11 is a block diagram of a test pattern acquisition system provided in one embodiment;
FIG. 12 is a block diagram of a test pattern acquisition apparatus provided in one embodiment;
fig. 13 is a schematic diagram of an internal structure of a computer device according to an embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As to the background art, the degree of rounding at the right angle of the wafer surface pattern is difficult to quantify, and correction and compensation are usually carried out on the right angle of the pattern based on an empirical value.
In this regard, the present application proposes a method, a system, an apparatus, a computer device, a storage medium, and a program product for obtaining a test pattern, which improve the straight angle of a wafer surface pattern, and ensure the performance of a chip.
In one embodiment, as shown in FIG. 1, a method of acquiring a test pattern is provided. The test pattern acquisition method may include the following steps S10 to S30.
S10: and respectively and correspondingly acquiring a scanning image of each test pattern on the wafer based on the plurality of test patterns.
The test pattern refers to any pattern having a right angle, for example, L-shape, F-shape. Rectangular compensation areas are arranged at the right-angle positions of the test patterns. In other words, the rectangular compensation areas are additionally arranged at the right angles of the target layout to obtain the corresponding test patterns. The rectangular compensation areas of the test patterns are different in size, the rectangular compensation areas of the same test pattern are the same in size, and the test patterns correspond to the same target layout.
The scanning image is an image obtained by writing a test pattern on a photomask, transferring the test pattern to a wafer through the photomask, and then scanning the surface pattern of the wafer. The scanned image may be obtained using any image scanning device, and illustratively, a scanning electron microscope (Scanning Electron Microscope, SEM) may be used to scan the wafer to obtain an SEM image.
S20: and overlapping each scanning image with the target layout respectively, and correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image.
Overlay refers to overlapping and aligning graphics in a scanned image with a target layout. In this step, each scan image needs to be overlapped with the target layout, so as to obtain the measurement distance corresponding to each test pattern in turn.
The measured distance is used to identify a distance between an edge contour of the scanned image and an edge contour of the target layout. The larger the measurement distance, i.e. the larger the distance between the edge contour of the scanned image and the edge contour of the target layout, the larger the difference between the test pattern and the wafer surface pattern, which indicates that the lower the straight angle of the wafer surface pattern. The smaller the measurement distance, i.e. the smaller the distance between the edge contour of the scanned image and the edge contour of the target layout, the smaller the difference between the test pattern and the wafer surface pattern, which means that the higher the straight angle of the wafer surface pattern. The wafer surface pattern is a pattern formed on the wafer surface by photolithography from the test pattern.
S30: and determining a target test pattern from the plurality of test patterns according to each measured distance.
The target test pattern is a test pattern of a target layout, or the target test pattern is a test pattern with a higher corresponding wafer angle selected from a plurality of test patterns, and is used in a wafer patterning process.
For example, a test pattern corresponding to the minimum value may be selected from the measured distances as the target test pattern, or a test pattern smaller than the measured distance threshold may be selected from the measured distances as the target test pattern. The measurement distance threshold is preset, is used for marking that the straight angle of the wafer surface graph meets the requirement, and can be measured according to an empirical value or a plurality of experimental values.
According to the test pattern acquisition method provided by the embodiment, firstly, the scanning images of a plurality of different test patterns on the wafer are respectively acquired, then each scanning image is respectively overlapped with the target layout, the measuring distances between the edge contour of the target layout and the edge contour of each scanning image are respectively correspondingly acquired, and then the target test pattern is selected from the plurality of test patterns based on each measuring distance. The measuring distance represents the difference between the wafer surface pattern and the target layout from the characteristic dimension of the edge profile, so that the quantification of the straight angle of the wafer surface pattern is realized. In addition, the straight angle of the pattern transferred to the surface of the wafer by the target test pattern is higher, so that the target test pattern can be used as the pattern subjected to correction and compensation of the target layout for photoetching and imaging of the wafer, correction and compensation of the target layout are realized, and the straight angle of the pattern on the surface of the wafer is improved.
In one embodiment, the test pattern has a right-angle convex position and a right-angle concave position, for example an E-shaped, concave-shaped test pattern, in which case the rectangular compensation area of the right-angle convex position of the test pattern is provided with a rectangular compensation pattern, and the rectangular compensation area of the right-angle concave position of the test pattern is notched with a rectangular compensation pattern. It should be noted that the test pattern may also have only a right-angle convex position, for example, an I-shaped test pattern, in which case the rectangular compensation area at the right-angle convex position of the test pattern is provided with a rectangular compensation pattern. The rectangular compensation area or the notch for setting the rectangular compensation area in the test pattern may be determined according to the specific shape of the right angle of the test pattern, which is not limited in any way.
The rectangular compensation area refers to an area in which the test pattern is additionally arranged relative to the target layout, and the rectangular compensation pattern refers to a difference pattern of the test pattern between the rectangular compensation area and the target layout. And correcting and compensating each right angle position of the target layout based on the rectangular compensation pattern to obtain a plurality of test patterns, so that a test pattern with better correction and compensation is selected from the plurality of test patterns and used for photoetching and patterning of the wafer, and the straight angle of the pattern on the surface of the wafer is improved.
For better understanding, the target layout shown in fig. 2a is illustrated as L-shaped. As shown in fig. 2b, there are 6 right angles in the L-shaped target layout, including 5 right angle convex positions and 1 right angle concave position. Specifically, rectangular compensation areas a1, a2, a3, a4 and a5 are respectively arranged at the right-angle convex positions, and correspondingly rectangular compensation patterns are arranged at the rectangular compensation areas a1, a2, a3, a4 and a5, wherein the rectangular compensation area a1 is provided with the rectangular compensation patterns as shown in the area A in fig. 2 c. Rectangular compensation patterns B are arranged at right-angle recessed positions, and correspondingly, gaps of the rectangular compensation patterns are arranged in the rectangular compensation areas B, as shown in an area B in fig. 2 c.
In one embodiment, as shown in fig. 3, step S20, overlapping each scanned image with the target layout, respectively, may include the following steps S211 and S212.
S211: and respectively and correspondingly extracting the edge contour of each scanning image according to the preset pixel threshold value and the pixel value of each scanning image pixel point.
The pixel threshold is preset, and may be specifically set according to the actual situation of the scan image, which is not limited herein. Specifically, the pixel value of each pixel of the scanned image is compared with the pixel threshold value to extract the edge contour (contour) of the scanned image. Wherein the edge profile may comprise at least one of an outer profile and an inner profile.
S212: and scaling each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
The critical dimensions (Critical Dimension, CD) refer to the pattern processing precision of the evaluation and control process in the integrated circuit photomask manufacturing and lithography process, and a special line pattern reflecting the line width of the integrated circuit features is specially designed. The measured CD value is preset, and may be preset according to the wafer patterning process requirement, which is not limited in this application.
According to the method for acquiring the test pattern, the contrast between the edge profile of the scanned image and the background is different, so that the pattern edge profile in the scanned image can be automatically extracted in a pixel threshold comparison mode, and based on the pattern edge profile, the overlay between the scanned image and the target layout is realized through the edge profile, and therefore the measurement of the straight angle of the pattern after the test image is transferred to the surface of the wafer can be realized.
The test pattern acquisition method provided based on the embodiment shown in fig. 3 described above may further include the following steps S213 and S214 as shown in fig. 4.
S213: and respectively and correspondingly acquiring the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout.
S214: and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than the distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
The preset edge refers to at least one contour edge of a pre-designated test pattern. Taking the L-shaped test pattern shown in fig. 2c as an example, the preset sides may be 4 long sides of the L-shape. The distance threshold is preset and can be set according to the precision requirement and experiments, for example, the distance threshold is set to be 2nm, and under the condition that the overlapping distance between the preset edge of the scanned image and the edge contour of the target layout is smaller than 2nm, successful overlapping of the scanned image and the target layout is determined.
According to the test pattern acquisition method provided by the embodiment, whether the overlapping distance between the preset edge of the scanning image and the edge contour of the target layout is smaller than the distance threshold is judged, so that the overlapping precision between the scanning image and the target layout is ensured, the measuring precision of the measuring distance between the edge contour of the scanning image and the edge contour of the target layout is improved, and the straight angle of the wafer surface pattern is further improved.
In one embodiment, as shown in fig. 5, step S20, which respectively corresponds to obtaining the measured distances between the edge contour of the target layout and the edge contour of each scanned image, may include the following steps S221 and S222.
S221: and for each scanned image, measuring the candidate distance between the preset point on each measuring rod and the edge contour of each scanned image correspondingly.
Wherein, each measuring rod is respectively and correspondingly positioned on each right-angle side of the target layout. A measurement bar (measurement bar) is used to measure the distance between the target layout and the scanned image. The length of the measuring rod is not limited, and the measuring rod can be set according to the actual size of a scanned image.
For example, taking the area C of the test pattern shown in fig. 2C as an example, the area C includes two protruding right angles and three right angle sides, and accordingly, the measuring bars m1, m2 and m3 may be respectively placed on the three right angle sides, as shown in fig. 6 a. For another example, for the region B of the test pattern shown in fig. 2c, the region B includes a recessed right angle, and two right angle sides, and accordingly, measuring bars m4 and m5 may be respectively placed on the two right angle sides, as shown in fig. 6B. Where x represents the edge contour of the target layout and y represents the edge contour of the scanned image.
The preset points on each measuring rod can be any points on the measuring rod, the number of the preset points can be set according to actual measurement requirements, and the parameters such as the positions, the number and the like of the preset points are not limited. The candidate distance refers to the linear distance between the preset point on the measuring bar and the edge contour of the scanned image. For example, candidate distances between preset points on each measuring bar at equal intervals and the edge contour of each scanned image may be measured, for example, the interval between two adjacent preset points may be set to 1nm, and then the straight line distance between the edge of the target layout and the edge contour of the scanned image is measured every 1 nm.
S222: and respectively and correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image according to each candidate distance.
Based on S221 described above, a plurality of candidate distances may be acquired correspondingly for one scan image. Illustratively, the plurality of candidate distances may be weighted averaged to serve as a measured distance (edge placement error, EPE) between the edge contour of the scanned image and the edge contour of the target layout. Based on this, for each scanned image, a respective EPE value may be acquired correspondingly.
According to the test pattern acquisition method provided by the embodiment, the measuring rod is utilized to realize effective quantification of the difference between the edge contour of the target layout and the edge contour of the scanning image, so that the target test pattern at the position can be determined according to the measuring distance corresponding to each scanning image by the measuring rod, and the straight angle of the wafer surface pattern can be improved.
In one embodiment, as shown in fig. 7, step S30, determining a target test pattern from a plurality of test patterns according to each measured distance, may include the following steps S310 and S320.
S310: and determining the minimum measurement distance according to each measurement distance. Specifically, the EPE minimum value is found from the EPE values of the respective scanned images.
S320: and determining the test pattern corresponding to the minimum measurement distance as a target test pattern.
The minimum measurement distance, namely the EPE minimum value, shows that the distance between the edge contour of the scanning image and the edge contour of the target layout is the shortest, namely the difference between the edge contour of the scanning image and the edge contour of the target layout is the smallest, and the correction compensation effect of the test pattern corresponding to the scanning image on the target layout is good, so that the method can be used for wafer photoetching patterning.
According to the test pattern acquisition method provided by the embodiment, the test pattern corresponding to the minimum measurement distance is determined as the target test pattern, and because the target test pattern has a good correction and compensation effect on the target layout, the straight angle of the pattern formed on the surface of the wafer is high after the wafer is subjected to photoetching patterning based on the target test pattern, so that the straight angle of the pattern on the surface of the wafer is ensured, and the performance of chips is ensured.
For better understanding, taking the L-shaped target layout shown in fig. 2a as an example, another test pattern acquisition method is provided. As shown in fig. 8, the test pattern acquisition method may include the following steps S801 to S809.
S801: based on the plurality of test patterns, scanning images of each test pattern on the wafer are correspondingly acquired by using the SEM. For example, the test pattern shown in fig. 2C is scanned by SEM, and the SEM image corresponding to the region C is shown in fig. 9.
S802: and respectively and correspondingly extracting the edge contour of each scanning image according to the preset pixel threshold value and the pixel value of each scanning image pixel point.
S803: and scaling each scanning image according to a preset measurement critical dimension value and a pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
S804: and respectively and correspondingly acquiring the overlapping distance between the preset edge of the scanning image and the edge contour of the target layout.
S805: and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than the distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
S806: and for each scanning image, measuring the candidate distance between the preset point on each measuring rod and the edge contour of each scanning image correspondingly, wherein each measuring rod is positioned on each right-angle side of the target layout.
S807: and respectively and correspondingly acquiring the measuring distance between the edge contour of the target layout and the edge contour of each scanning image according to each candidate distance. The measured distance EPE of each scanned image is shown in fig. 10, wherein the abscissa represents the different test patterns and the ordinate represents the EPE value.
S808: and determining the minimum measurement distance according to each measurement distance. Specifically, the EPE minimum value is found from the EPE values of the respective scanned images.
S809: and determining the test pattern corresponding to the minimum measurement distance as a target test pattern.
The test pattern acquisition method provided by the embodiment can quantify the degree of rounding at the right angle of the wafer surface pattern, improves the measurement accuracy, can also process a large number of SEM pictures in batches, and effectively improves the working efficiency.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a test pattern acquisition system for realizing the test pattern acquisition method. The implementation of the solution provided by the system is similar to the implementation described in the above method, so the specific limitation in the embodiment of the system for acquiring one or more test patterns provided below may be referred to the limitation of the method for acquiring a test pattern hereinabove, and will not be described herein.
In one embodiment, as shown in FIG. 11, a test pattern acquisition system is provided. The test pattern acquisition system 1100 may include a wafer stage 1101, a scanning electron microscope 1102, and a machine 1103.
Wherein the wafer stage 1101 is configured to hold a wafer. The scanning electron microscope 1102 is configured to obtain a scan image of each test pattern on the wafer based on the plurality of test patterns, where rectangular compensation patterns are disposed at right angle positions of the test patterns, and the dimensions of the rectangular compensation patterns of each test pattern are different. The machine 1103 is connected with the scanning electron microscope 1102, and the machine 1103 is used for overlapping each scanning image with the target layout respectively, correspondingly obtaining the measuring distances between the edge contour of the target layout and the edge contour of each scanning image respectively, and determining a target test pattern from a plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
The test pattern acquisition system provided by the embodiment comprises a wafer object placing table, a scanning electron microscope and a machine table. After a plurality of test patterns are transferred onto a wafer, the wafer is placed on a wafer placing table, then scanning images of a plurality of different test patterns on the wafer are respectively obtained through a scanning electron microscope, each scanning image is respectively overlapped with a target layout through an SEM, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are respectively and correspondingly obtained, and then the target test pattern is selected from the plurality of test patterns based on each measuring distance. The measuring distance represents the difference between the wafer surface pattern and the target layout from the characteristic dimension of the edge profile, so that the quantification of the straight angle of the wafer surface pattern is realized. In addition, the straight angle of the pattern transferred to the surface of the wafer by the target test pattern is higher, so that the target test pattern can be used as the pattern subjected to correction and compensation of the target layout for photoetching and imaging of the wafer, correction and compensation of the target layout are realized, and the straight angle of the pattern on the surface of the wafer is improved.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the machine 1103 is further configured to:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the machine 1103 is further configured to:
respectively and correspondingly acquiring the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the machine 1103 is further configured to:
for each scanning image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanning image correspondingly; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the machine 1103 is further configured to:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
Based on the same inventive concept, the embodiment of the application also provides a test pattern acquisition device for realizing the test pattern acquisition method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiment of the device for acquiring one or more test patterns provided below may refer to the limitation of the method for acquiring a test pattern, which is not described herein.
In one embodiment, a test pattern acquisition apparatus is also provided. As shown in fig. 12, the test pattern acquisition apparatus 1200 may include a first acquisition module 1201, a second acquisition module 1202, and a determination module 1203.
The first obtaining module 1201 is configured to correspondingly obtain a scan image of each test pattern on the wafer based on the plurality of test patterns; and rectangular compensation patterns are arranged at the right angle positions of the test patterns, and the sizes of the rectangular compensation patterns of the test patterns are different. The second obtaining module 1202 is configured to overlay each of the scanned images with a target layout, and correspondingly obtain a measurement distance between an edge contour of the target layout and an edge contour of each of the scanned images. The determining module 1203 is configured to determine a target test pattern from the plurality of test patterns according to each of the measured distances, where the target test pattern is a test pattern of the target layout.
The test pattern acquisition device provided by the embodiment comprises a first acquisition module, a second acquisition module and a determination module. Firstly, respectively acquiring scanning images of a plurality of different test patterns on a wafer by using a first acquisition module, then respectively overlapping each scanning image with a target layout by using a second acquisition module, respectively correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image, and then selecting the target test pattern from the plurality of test patterns by using a determination module based on each measuring distance. The measuring distance represents the difference between the wafer surface pattern and the target layout from the characteristic dimension of the edge profile, so that the quantification of the straight angle of the wafer surface pattern is realized. In addition, the straight angle of the pattern transferred to the surface of the wafer by the target test pattern is higher, so that the target test pattern can be used as the pattern subjected to correction and compensation of the target layout for photoetching and imaging of the wafer, correction and compensation of the target layout are realized, and the straight angle of the pattern on the surface of the wafer is improved.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the second acquisition module 1202 is further configured to:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the determining module 1203 is further configured to:
respectively and correspondingly acquiring the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the second acquisition module 1202 is further configured to:
for each scanned image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanned image correspondingly; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
And according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the determining module 1203 is further configured to:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
The above-described respective modules in the test pattern acquisition apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a terminal, and the internal structure thereof may be as shown in fig. 13. The computer device includes a processor, a memory, a communication interface, a display unit, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a method of acquiring a test pattern. The display unit of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in fig. 13 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the computer device to which the present application applies, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of:
respectively and correspondingly acquiring a scanning image of each test pattern on a wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the size of each rectangular compensation area of each test pattern is different;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the processor when executing the computer program further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the processor when executing the computer program further performs the steps of:
respectively and correspondingly acquiring the overlapping distance between the preset edge of the scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the processor when executing the computer program further performs the steps of:
for each scanning image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanning image correspondingly; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the processor when executing the computer program further performs the steps of:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
respectively and correspondingly acquiring a scanning image of each test pattern on a wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the size of each rectangular compensation area of each test pattern is different;
Overlapping each scanning image with a target layout respectively, and correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the computer program when executed by the processor further performs the steps of:
Respectively and correspondingly acquiring the overlapping distance between the preset edge of the scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the computer program when executed by the processor further performs the steps of:
for each scanned image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanned image correspondingly; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
In one embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, performs the steps of:
Respectively and correspondingly acquiring a scanning image of each test pattern on a wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, and the size of each rectangular compensation area of each test pattern is different;
overlapping each scanning image with a target layout respectively, and correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image respectively;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
In one embodiment, the rectangular compensation area at the right-angle convex position of the test pattern is provided with the rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch with the rectangular compensation pattern.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
In one embodiment, the computer program when executed by the processor further performs the steps of:
respectively and correspondingly acquiring the overlapping distance between the preset edge of the scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
In one embodiment, the computer program when executed by the processor further performs the steps of:
for each scanned image, measuring candidate distances between preset points on each measuring rod and the edge contour of each scanned image correspondingly; wherein, each measuring rod is respectively positioned on each right-angle edge of the target layout;
and according to the candidate distances, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained.
In one embodiment, the computer program when executed by the processor further performs the steps of:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
The data (including, but not limited to, data for analysis, data stored, data displayed, etc.) referred to in this application are information and data authorized by the user or sufficiently authorized by the parties.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (MagnetoresistiveRandom Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PhaseChange Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (StaticRandom Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. The method for acquiring the test pattern is characterized by comprising the following steps of:
respectively and correspondingly acquiring a scanning image of each test pattern on a wafer based on a plurality of test patterns; rectangular compensation areas are arranged at the right-angle positions of the test patterns, the size of each rectangular compensation area of each test pattern is different, and each test pattern corresponds to the same target layout;
Superposing each scanning image with the target layout, and correspondingly measuring candidate distances between preset points on each measuring rod and edge contours of each scanning image for each scanning image; wherein, each measuring bar is respectively positioned on each right-angle edge of the target layout;
according to each candidate distance, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained;
and determining a target test pattern from the plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout.
2. The method for obtaining the test pattern according to claim 1, wherein the rectangular compensation area at the right-angle convex position of the test pattern is provided with a rectangular compensation pattern, and the rectangular compensation area at the right-angle concave position of the test pattern is provided with a notch having the rectangular compensation pattern.
3. The method for obtaining a test pattern according to claim 1, wherein the overlapping each of the scanned images with the target layout respectively includes:
Respectively and correspondingly extracting the edge contour of each scanning image according to a preset pixel threshold value and the pixel value of each scanning image pixel point;
scaling each scanning image according to a preset measurement critical dimension value and a preset pixel value of each scanning image pixel point, and respectively overlapping the edge contour of each scanning image with the edge contour of the target layout.
4. A method of obtaining a test pattern according to claim 3, further comprising:
respectively and correspondingly acquiring the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout;
and under the condition that the overlapping distance between the preset edge of each scanning image and the edge contour of the target layout is smaller than a distance threshold value, determining that each scanning image and the target layout are successfully overlapped.
5. The method for obtaining a test pattern according to claim 1, wherein the obtaining the measured distances between the edge contour of the target layout and the edge contour of each scanned image according to each candidate distance includes:
and carrying out weighted average on each candidate distance according to each scanning image to respectively obtain the measured distance between the edge contour of the target layout and the edge contour of each scanning image.
6. The method according to claim 1, wherein determining a target test pattern from a plurality of test patterns according to each of the measured distances comprises:
determining a minimum measurement distance according to each measurement distance;
and determining the test pattern corresponding to the minimum measurement distance as the target test pattern.
7. A test pattern acquisition system, comprising:
the wafer placing table is used for placing wafers;
the scanning electron microscope is used for respectively and correspondingly acquiring a scanning image of each test pattern on the wafer based on a plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, the rectangular compensation patterns of the test patterns are different in size, and the test patterns correspond to the same target layout;
the machine is used for respectively overlapping each scanning image with the target layout, and for each scanning image, respectively and correspondingly measuring candidate distances between preset points on each measuring rod and the edge contour of each scanning image; according to each candidate distance, measuring distances between the edge contour of the target layout and the edge contour of each scanning image are correspondingly obtained; determining a target test pattern from a plurality of test patterns according to each measuring distance, wherein the target test pattern is the test pattern of the target layout; wherein, each measuring bar is respectively positioned on each right-angle edge of the target layout.
8. An acquisition device of a test pattern, characterized by comprising:
the first acquisition module is used for correspondingly acquiring a scanning image of each test pattern on the wafer based on the plurality of test patterns; rectangular compensation patterns are arranged at the right-angle positions of the test patterns, the rectangular compensation patterns of the test patterns are different in size, and the test patterns correspond to the same target layout;
the second acquisition module is used for respectively overlapping each scanning image with the target layout, correspondingly measuring candidate distances between preset points on each measuring rod and the edge contour of each scanning image aiming at each scanning image, and correspondingly acquiring measuring distances between the edge contour of the target layout and the edge contour of each scanning image according to each candidate distance; wherein, each measuring bar is respectively positioned on each right-angle edge of the target layout;
and the determining module is used for determining a target test pattern from the plurality of test patterns according to each measured distance, wherein the target test pattern is the test pattern of the target layout.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, carries out the steps of the test pattern acquisition method according to any one of claims 1 to 6.
10. A computer storage medium having stored thereon a computer program, characterized in that the computer program, when executed by a processor, realizes the steps of the test pattern acquisition method according to any one of claims 1 to 6.
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| CN117274366B (en) * | 2023-11-22 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Line edge distance determining method and device |
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