CN117539805A

CN117539805A - Sideband access method, memory controller, core particle and computer equipment

Info

Publication number: CN117539805A
Application number: CN202310800236.2A
Authority: CN
Inventors: 宋明辉; 王少峰
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2024-02-09

Abstract

The embodiment of the application provides a sideband access method, a memory controller, a core particle and computer equipment, wherein the method is executed by hardware logic of the memory controller and comprises the following steps: acquiring sideband access information written by a memory physical layer interface, wherein the sideband access information is used for initiating sideband access of a memory module by the memory physical layer interface; generating a sideband access command corresponding to the sideband access information according to the sideband access information at least according to a command protocol of a communication host; the communication host and the memory module communicate through a sideband access; and sending the sideband access command to the communication host to control the communication host to access a memory module. The embodiment of the application can accelerate the processing of the sideband access through hardware and improve the sideband access efficiency.

Description

Sideband access method, memory controller, core particle and computer equipment

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a sideband access method, a memory controller, a core particle and computer equipment.

Background

In a computer system, a core may interface with a memory module such as a DIMM (Dual Inline Memory Module, dual in-line memory module) through a memory interface IP (Intellectual Property ). The memory interface IP mainly comprises a memory controller and a memory physical layer (PHY) interface; the memory physical layer interface is used as a bridge between the memory controller and the memory module and can be used for transmitting data between the memory controller and the memory module.

During operation of a computer system, the computer system has a need to access memory modules through a memory physical layer interface. One way of accessing the memory module by the memory physical layer interface is through a Side Band (Side Band), that is, performing Side Band access (Side Band access for short) to the memory module. In this context, how to improve the efficiency of sideband access becomes a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a sideband access method, a memory controller, a core, and a computer device, so as to improve the efficiency of sideband access.

In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions.

In a first aspect, an embodiment of the present application provides a sideband access method, which is performed by hardware logic of a memory controller, the method comprising:

Acquiring sideband access information written by a memory physical layer interface, wherein the sideband access information is used for initiating sideband access of a memory module by the memory physical layer interface;

generating a sideband access command corresponding to the sideband access information according to the sideband access information at least according to a command protocol of a communication host; the communication host and the memory module communicate through a sideband access;

and sending the sideband access command to the communication host to control the communication host to access a memory module.

In a second aspect, an embodiment of the present application provides a memory controller, where the memory controller is provided with a sideband communication processing module, and the sideband communication processing module is hardware logic of the memory controller; the sideband communication processing module is configured to perform the sideband access method as described in the first aspect above.

In a third aspect, an embodiment of the present application provides a core granule, including a memory controller, a memory physical layer interface, and a communication host; the memory controller is the memory controller according to the second aspect.

In a fourth aspect, embodiments of the present application provide a computer device comprising a core particle as described in the third aspect above.

The sideband access provided by the embodiment of the application can be implemented by hardware logic in the memory controller, and when the memory physical layer interface initiates the sideband access of the memory module, the hardware logic can acquire the sideband access information written by the memory physical layer interface; therefore, the hardware logic can generate a sideband access command corresponding to sideband access information at least according to a command protocol of a communication host according to the sideband access information written by the memory physical layer interface; and further, the sideband access command is sent to the communication host, so that the communication host can access the memory module by controlling the communication host through the sideband access command, and the sideband access of the memory physical layer interface to the memory module is realized.

It can be seen that, in the embodiment of the present application, after the memory physical layer interface initiates the sideband access, the processing of the sideband access is implemented by the hardware logic in the memory controller and the communication host (the communication host is a hardware device for sideband communication), so that the processing of the sideband access is implemented by hardware, and participation of system software is not required; because the processing speed of the hardware is higher than that of the system software, the implementation of the method and the system can reduce the time consumption of the processing of the sideband access, so that the processing of the sideband access can be accelerated through the hardware, and the sideband access efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

FIG. 1 is a block diagram of a computer system.

FIG. 2 is another block diagram of a computer system.

Fig. 3 is a flow chart of a sideband access method.

FIG. 4 is a flow chart for generating a sideband access command.

Fig. 5 is another flow chart of a sideband access method.

Fig. 6 is a state example diagram of a sideband communication processing module.

Fig. 7 is a block diagram of a sideband communication processing module.

FIG. 8A is a block diagram of a first register set.

FIG. 8B is a block diagram of a second register set.

FIG. 9A is an exemplary diagram of a process for sideband write access.

FIG. 9B is an exemplary diagram of a process for sideband read access.

FIG. 10 is a block diagram of still another architecture of a computer system.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Fig. 1 illustrates a block diagram of a computer system, which may include a die 01 and a memory module 02, as shown in fig. 1. The core 01 may include a memory controller 110, a memory physical layer interface 120, a processor core 130, a communication host 140, and the like. The memory controller 110 and the memory physical layer interface 120 may communicate with each other through physical layer interface protocols such as DFI (DDR PHY Interface, DDR physical layer interface) protocols, and the memory controller 110 and the memory physical layer interface 120 form a memory interface IP of the core 01, so that the core 01 may interface with the memory module 02 through the memory interface IP. Processor cores 130, e.g., CPU (Central Processing Unit, central processor) cores; the communication host 140, such as an I2C (Inter-Integrated Circuit, integrated circuit bus)/I3C (Improved Inter Integrated Circuit, modified integrated circuit bus) host, or the like, may be used for hardware devices for sideband communication. Communication between the processor core 130, the communication host 140, and the memory interface IP may be through a communication bus of the core.

In the core 01, the physical layer interface 120 in the memory interface IP may serve as a bridge for connecting the memory controller 110 and the memory module 02, and perform protocol conversion on data transmitted between the memory controller 110 and the memory module 02, so as to ensure data transmission between the core 01 and the memory module 02.

In one example, the core 01 may constitute a Chip System such as a SOC (System On Chip), and the memory interface IP is, for example, DDR (Double Data Rate) IP; memory Controller 110, e.g., a DDR Controller in DDR IP, memory physical layer interface 120, e.g., a DDR PHY interface (i.e., DDR physical layer interface) in DDR IP; the memory module 02 is, for example, a DIMM (Dual Inline Memory Module, dual in-line memory module), which is a main memory device in a computer system, and in order to adapt to different application scenarios, the DIMM may be classified into a UDIMM (Unbuffered dual in-line memory module), an RDIMM (Registered DIMM), an LRDIMM (Load Reduced DIMM, low load dual in-line memory module), and the like.

In the above example, the DDR PHY interface serves as a bridge connecting the DIMM and the DDR Controller, and can convert data sent by the DDR Controller into data conforming to the DDR protocol and send the data to DDR particles in the DIMM for storage; correspondingly, the DDR PHY interface can also convert the data sent by the DIMM into data conforming to the DFI protocol and send the data to the DDR Controller, so that the data transmission between the SOC and the DIMM is ensured.

The memory module is provided with various devices, and the computer system has a need to access the memory module through the memory physical layer interface for the purposes of managing, configuring and querying the state of the memory module and the like for the devices arranged on the memory module. In one example, taking a memory module as a DIMM, the DIMM is provided with devices such as a DRAM (Dynamic Random Access Memory ), an RCD (Register Clock Driver, register clock driver, also called register Buffer), a DB (Data Buffer ), a PMIC (Power Management IC, power management chip), an SPD (Serial Presence Detect, serial presence detection) chip, a TS (Temperature Sensor ), and the like, and the operation of the computer system involves reading product information from the DIMM, configuring a register for the device provided on the DIMM, querying a status of the DIMM, and the like, so that the computer system needs to access the DIMM through the DDR PHY interface during operation.

Referring to fig. 1, the access to the memory module 02 by the memory physical layer interface 120 may be in two ways:

first, the direct access, for example, the memory physical layer interface 120 accesses the memory module 02 through a direct access manner between the memory physical layer interface 120 and the memory module 02, such as a command and address bus (CA) signal, a data bus (DQ) signal, and a Chip Select (CS) signal of the memory module 02; the command and address buses and the data buses of the memory module 02 may be regarded as direct access paths between the memory physical layer interface 120 and the memory module 02;

Second, a sideband access, such as the memory physical layer interface 120, accesses the memory module 02 through a sideband path between the communication host 140 and the memory module 02; the sideband access is based on protocols such as SMBus (System Management Bus ), I2C, I C, etc., and can be regarded as an access path between the communication host 140 (e.g., I2C/I3C host, etc.) for sideband communication and the memory module 02 in the computer system, and does not belong to a direct access path between the memory physical layer interface and the memory module.

By way of sideband access, accessing a memory module may involve the following scenarios:

before the memory training is finished, the reliability of command and address buses and chip selection signals of the memory module cannot be guaranteed, and the memory module needs to be accessed in a side-band access mode so as to manage equipment arranged on the DIMM;

after the memory training is completed, the memory module may be queried for status information using a side-band access, for example, the temperature information of a temperature sensor disposed on the DIMM may be queried using a side-band access to monitor the DIMM temperature.

It should be noted that, the memory training refers to a process of performing delay adjustment on a DRAM signal, a CS signal, a CA signal, a DQ signal, a DQs (data selection pulse) signal, and the like before the memory module performs normal data transmission, so as to compensate for signal offset between DRAM interface signals (signal offset between DRAM interface signals may be generated due to different routing inside the core and on the circuit board, etc.), and the purpose of the memory training is to ensure that commands and data of the memory module can be correctly and efficiently transmitted. After the memory training is completed, the CS signal, the CA signal, etc. can already correctly transmit data, so that the memory module can be accessed without using a side-band access mode. That is, before the memory training is completed, the memory module may be accessed using a side-band access manner. Of course, the embodiment of the application may also support that the memory module is accessed by using a side-band access mode after the memory training is completed, for example, the memory module is queried for state information such as temperature by using the side-band access mode after the memory training is completed.

It can be seen that, during operation of the computer system, the computer system has a need to access the memory module through the memory physical layer interface (for example, data is read from or written to the memory module through the memory physical layer interface), and one of the ways in which the memory physical layer interface accesses the memory module is sideband access.

One implementation of sideband access is: when the memory physical layer interface initiates the sideband access of the memory module, the sideband access is processed by the processor core executing the system software and interacted with the communication host to control the communication host to access the memory module. However, the system software takes longer to process the sideband access, resulting in less efficient sideband access.

Based on this, the embodiment of the application provides a novel sideband access scheme, by improving the hardware logic of the memory controller, when the sideband access of the memory module is initiated by the memory physical layer interface, the hardware logic of the memory controller processes the sideband access, and realizes the interaction with the communication hosts such as the I2C/I3C host, so that the processing process of the sideband access does not need software response and participation, but is realized by hardware processing, the processing time consumption of the sideband access is reduced, and the sideband access efficiency is improved.

Based on the above-mentioned thought, in the embodiments of the present application, hardware logic that interacts with the memory physical layer interface and the communication host may be set in the memory controller, and the sideband access method provided in the embodiments of the present application is executed by the hardware logic in the memory controller. As an alternative implementation, fig. 2 illustrates another block diagram of a computer system, and in conjunction with fig. 1 and fig. 2, in the computer system illustrated in fig. 2, a sideband communication processing module 200 is disposed in a memory controller 110, where the sideband communication processing module 200 may be regarded as hardware logic disposed in the memory controller for performing a sideband access method provided in an embodiment of the present application; and the sideband communication processing module 200 and the memory physical layer interface 120 are interconnected through a communication bus.

That is, a communication bus is provided between the sideband communication processing module 200 and the memory physical layer interface 120, so that the memory controller 110 can communicate with the memory physical layer interface 120 through a physical layer interface protocol such as a DFI protocol, and can also realize communication between the sideband communication processing module 200 and the memory physical layer interface 120 through the additionally provided communication bus. In one example, the communication Bus between the sideband communication processing module 200 and the memory physical layer interface 120 may be based on an APB (Advanced Peripheral Bus ), an AHB (Advanced High-performance Bus), an AXI (Advanced eXtensible Interface ), or other communication protocols, which are not limited in the embodiments of the present application.

In this embodiment of the present application, the sideband communication processing module 200 needs to process sideband access initiated by the memory physical layer interface and implement interaction with the communication host 140 such as the I2C/I3C host, so that the sideband communication processing module 200 may access the system management network of the computer system through the system management bus based on the AXI protocol, so as to interact with the communication host 140.

Based on the computer system shown in fig. 2, when the memory physical layer interface initiates the sideband access of the memory module, the sideband communication processing module in the memory controller can execute the sideband access method provided in the embodiment of the present application. Optionally, in the chip design stage, the sideband communication processing module may be designed in the memory controller (for example, the functional design, the interface design, etc. of the sideband communication processing module are performed in the memory controller), so that the sideband communication processing module has the capability of executing the sideband access method provided in the embodiment of the present application. As an alternative implementation, fig. 3 illustrates an alternative flowchart of a sideband access method, which may be performed by hardware logic of a memory controller (e.g., by a sideband communication processing module in the memory controller), and referring to fig. 3, the method flowchart may include the following steps.

In step S310, sideband access information written by the memory physical layer interface is obtained, where the sideband access information is used by the memory physical layer interface to initiate sideband access of the memory module.

When the memory physical layer interface initiates the sideband access to the memory module, the memory physical layer interface may write the sideband access information into the sideband communication processing module. In an alternative implementation, the sideband communication processing module may set a register address space accessible by the memory physical layer interface, so that when the memory physical layer interface initiates sideband access, sideband access information may be written in the register address space through a communication bus between the sideband communication processing module and the memory physical layer interface. For ease of illustration, the register address space provided in the sideband communication processing module that is accessible by the memory physical layer interface may be referred to as a first register set.

In an alternative implementation, the sideband access information written into the sideband communication processing module by the memory physical layer interface may carry at least address information.

Optionally, the sideband access initiated by the memory physical layer interface to the memory module may be sideband write access or sideband read access; the sideband write access can be regarded as the sideband access of the memory physical layer interface for the write operation initiated by the memory module, and is used for writing the write data into the memory module; the sideband read access may be considered a sideband access of a read operation initiated by the memory physical layer interface for the memory module for reading read data from the memory module. Accordingly, when the memory physical layer interface initiates the sideband write access of the memory module, the sideband access information written by the memory physical layer interface may include address information of the sideband write access and write data. When the memory physical layer interface initiates the sideband read access of the memory module, the sideband access information written by the memory physical layer interface may include address information of the sideband read access.

In step S311, a sideband access command corresponding to the sideband access information is generated according to the sideband access information at least in accordance with the command protocol of the communication host.

When the memory physical layer interface initiates the sideband access of the memory module, the embodiment of the application uses hardware logic (such as a sideband communication processing module) in the memory controller to interact with the communication host based on the sideband access information written in the memory physical layer interface, so as to control the communication host to access the memory module; hardware logic in the memory controller (e.g., a sideband communication processing module) is required to generate commands to be sent to the communication host to control the communication host. In order to enable the communication host to access the memory module through the sideband access, the command generated by the sideband communication processing module may include at least a sideband access command for instructing the communication host to access the memory module.

In an alternative implementation, the sideband access command needs to be generated in accordance with the command protocol of the communication host, as the sideband access command needs to be sent to the communication host. Based on this, as an optional implementation, the sideband communication processing module may generate, according to the sideband access information written by the memory physical layer interface, a sideband access command corresponding to the sideband access information at least according to a command protocol of the communication host, so that the communication host may access the memory module based on an indication of the sideband access command.

In an alternative implementation, the sideband access command generated by the sideband communication processing module may carry at least access address information, which may be used for addressing by the communication host when accessing the memory module. Alternatively, the access address information may be generated based on address information in the sideband access information written by the memory physical layer interface. In an alternative implementation, if the address information in the side-band access information is directly used for addressing when the communication host accesses the memory module, the address information in the side-band access information may be used as the access address information carried by the side-band access command.

Optionally, if the memory physical layer interface initiates the sideband write access, the sideband access command generated by the sideband communication processing module may be a sideband write access command, for instructing the communication host to write the write data into the memory module; correspondingly, the access address information in the sideband access command can include write access address information (i.e., the sideband write access command carries write access address information), and further, the sideband write access command can also carry write data; the write access address information may be considered as a write address of write data at the memory module.

If the memory physical layer interface initiates the sideband read access, the sideband access command generated by the sideband communication processing module can be the sideband read access command and is used for indicating the communication host to read the read data from the memory module; accordingly, the access address information in the sideband access command may include read access address information (i.e., the sideband read access command carries the read access address information), which may be considered a read address for reading data from the memory module.

In step S312, the sideband access command is sent to the communication host to control the communication host to access a memory module.

Hardware logic (e.g., sideband communication processing module) in the memory controller may send sideband access commands to the communication host over the AXI-based protocol-based system management bus; thus, the communication host may execute the sideband access command to access the memory module through the sideband pathway. In an alternative implementation, the communication host may access the memory module through the sideband access according to the indication of the access address information carried by the sideband access command.

In an alternative implementation, if the sideband access command is a sideband write access command, after the communication host acquires the sideband write access command, the communication host can write the write data into the memory module through the sideband access according to the write access address information carried by the sideband write access command, so that the memory physical layer interface writes the data into the memory module.

If the side band access command is a side band read access command, the communication host can read the read data from the memory module through the side band access according to the read access address information carried by the side band read access command after the side band read access command is acquired. Furthermore, the communication host can feed back the read data to the sideband communication processing module, so that the sideband communication processing can store the read data into the first register set accessible to the memory physical layer interface, and the memory physical layer interface can read the read data from the first register set, and the memory physical layer interface can read the data to the memory module.

In an alternative implementation, sideband access to the memory module requires the format information of the sideband access command to be followed. Based on this, in an alternative implementation, when generating the sideband access command sent to the communication host, the embodiment of the application may further combine the format information required by the sideband access command in addition to the command protocol of the communication host. Alternatively, fig. 4 illustrates an alternative flow chart for generating a sideband access command, and referring to fig. 4, the method flow may include the following steps.

In step S410, the current protocol mode of the communication host is determined.

The communication host may have a plurality of protocol modes, and command protocols corresponding to the communication host in different protocol modes may be different, so in the embodiments of the present application, when generating a sideband access command, it is necessary to determine a current protocol mode of the communication host, so that the generated sideband access command is adapted to a command protocol corresponding to the current protocol mode. For example, the I2C/I3C host has an I2C mode and an I3C mode, and the I2C/I3C host has different command protocols corresponding to the I2C mode and the I3C mode; therefore, when the I2C/I3C host is in the I2C mode, a command sent to the I2C/I3C host needs to be generated according to a command protocol corresponding to the I2C mode; when the I2C/I3C host is in the I3C mode, a command sent to the I2C/I3C host needs to be generated according to a command protocol corresponding to the I3C mode.

In an alternative implementation, the current protocol mode of the communication host may pertain to a type of configuration information provided by the system software of the computer system, which may write the configuration information to the hardware logic (e.g., sideband communication processing module) of the memory controller at system initialization. In one implementation example, the sideband communication processing module may set a second set of registers accessible by the system software such that the system software may write the current protocol mode of the communication host in the second set of registers; further, the sideband communication processing module may confirm a current protocol mode of the communication host from the second set of registers.

In step S411, a sideband access command corresponding to the sideband access information is generated according to the sideband access information, at least according to the current protocol mode of the communication host, and format information required by the sideband access command.

When the sideband access command is generated, the embodiment of the application can generate the sideband access command at least according to the current protocol mode of the communication host and the format information required by the sideband access command and based on the sideband access information provided by the memory physical layer interface.

The sideband access command may carry at least access address information for addressing by the communication host when accessing the memory module, the access address information may be determined according to an address format requirement for sideband access to the memory module. In alternative implementations, multiple memory modules (e.g., multiple DIMMs) may be provided in a computer system, each memory module may be provided with a different device such as DRAM, RCD, DB, PMIC, SPD chip, TS, etc., and the devices of the memory modules may have multiple channels with separate registers; thus, when performing sideband access to a memory module, access address information in the sideband access command needs to be able to address a device to be accessed (the device to be accessed is located in the memory module to be accessed) and indicate an internal address of the device to be accessed (e.g., a channel address, a register address, etc. of the device to be accessed) according to an address format requirement.

Based on the above, when the memory physical layer interface initiates the sideband access, the sideband access information written by the memory physical layer interface can carry the address information, so that when the sideband communication processing module generates the sideband access command, the sideband communication processing module can determine the access address information carried by the sideband access command based on the address information in the sideband access information. In an alternative implementation, the address information in the sideband access information may include: the memory module address of the memory module to be accessed (e.g., DIMM address), the device address of the device to be accessed (e.g., device address of the device on the DIMM such as RCD, PMIC, etc., the device to be accessed may be located in the memory module to be accessed), the register address (e.g., address of the register of the device on the DIMM such as RCD, PMIC, etc.), the channel address (e.g., channel address corresponding to the register of the device on the DIMM), etc. The register address and the channel address may be regarded as an example of an internal address of a device that needs to be accessed, where the internal address may further include a page address, and the like, and the embodiment of the present application is not limited.

In one implementation example, when the memory module is subjected to side-band access, the slave address and the internal address of the device to be accessed are generated according to the address format requirement; thus, the access address information carried by the sideband access command may include the slave address, as well as the internal address of the device to be accessed. Optionally, the slave address is used for addressing the device to be accessed (the device to be accessed is located in the memory module to be accessed), and may be determined based on the memory module address and the device address in the sideband access information provided by the memory physical layer interface; the internal address of the device to be accessed may be directly provided by the memory physical layer interface, for example, the internal address of a register address, a channel address, etc. in the sideband access information provided by the memory physical layer interface is used as the internal address of the device to be accessed in the access address information.

In a further alternative implementation, the slave address may include an HID (Host identifier) and a LID (Local identification, local identifier), e.g., the slave address is formed by the HID and the LID; the HID is used for addressing the memory module to be accessed, and can be determined based on the memory module address in the sideband access information provided by the memory physical layer interface; the LID is used to address the device to be accessed, and may be determined based on the device address of the device to be accessed (provided by the sideband access information written by the memory physical layer interface), e.g., with the device address in the sideband access information as the LID.

In one implementation example, the HID may be determined based on HID configuration information of the memory module to be accessed and the memory module address; alternatively, the memory module address of the memory module to be accessed may be provided by sideband access information written by the memory physical layer interface, and HID configuration information of the memory module to be accessed may be configured by system software. For example, the HID configuration information of the memory module is used as a configuration information of the system software, and the system software can write the HID configuration information of each memory module in the second register set of the sideband communication processing module, so that the sideband communication processing module can determine the HID configuration information of the memory module to be accessed from the second register set, and combine the HID configuration information with the memory module address of the memory module to be accessed provided by the memory physical layer interface to obtain the HID in the slave address.

Based on this, in an alternative implementation, the embodiments of the present application may further combine HID configuration information of the memory module that needs to be accessed when generating the sideband access command. Optionally, according to the sideband access information, according to the current protocol mode of the communication host, HID configuration information of the memory module to be accessed and format information required by the sideband access command, the embodiment of the present application may generate the sideband access command corresponding to the sideband access information; the HID configuration information of the memory module to be accessed is combined with the memory module address of the memory module to be accessed, so as to obtain the HID in the slave address.

In a further alternative implementation, the sideband access command needs to provide information such as access byte information (e.g., the number of bytes involved in accessing the data, the number of bytes involved in reading the data, etc.) in addition to access address information (e.g., the slave address, the internal address of the device to be accessed, etc.) in accordance with the format information required by the sideband access command. Further, if the sideband access command is a sideband write access command, the sideband write access command also needs to provide write data.

In an alternative implementation, the sideband communication processing module can control the communication host to access the memory module by sending a sideband access command after obtaining the control right of the communication host; and releasing the control right of the communication host after the access data is transmitted. Optionally, fig. 5 illustrates another alternative flowchart of a sideband access method, and referring to fig. 5, the method flowchart may include the following steps.

In step S510, sideband access information written by the memory physical layer interface is obtained, where the sideband access information is used by the memory physical layer interface to initiate sideband access of the memory module.

In step S511, control right is requested from the communication host.

In an alternative implementation, the sideband communication processing module may generate a request command (the request command being for requesting control of the communication host) to enable requesting control of the communication host by sending the request command to the communication host. The request command may be generated in accordance with a command protocol of the communication host (e.g., a current protocol mode of the communication host).

In a further alternative implementation, the sideband communication processing module may request control from the communication host upon detecting that sideband access is triggered. For example, the sideband communication processing module may consider that the sideband access is triggered when detecting the triggering information of the sideband access written by the memory physical layer interface, thereby requesting control right from the communication host. In one implementation example, the memory physical layer interface may further write triggering information of the sideband access after the sideband communication processing module writes the sideband access information to trigger the sideband access. That is, the sideband communication processing module may further obtain the trigger information of the sideband access written by the memory physical layer interface after obtaining the sideband access information written by the memory physical layer interface, so as to request the control right to the communication host.

In an alternative implementation, the triggering information of the sideband access may be written by the memory physical layer interface into the first set of registers of the sideband communication processing module. Taking the example that the memory physical layer interface initiates the sideband write access of the memory module, after the memory physical layer interface writes the sideband write access information (such as the address information of the sideband write access and the write data) of the sideband write access in the first register set, the memory physical layer interface can write the trigger information of the sideband write access in the first register set to trigger the sideband write access, so that the sideband communication processing module can request the control right to the communication host. Taking the example that the memory physical layer interface initiates the sideband read access of the memory module, after the sideband read access information (such as the address information of the sideband read access) of the sideband read access is written into the first register set, the memory physical layer interface can write the trigger information of the sideband read access into the first register set to trigger the sideband read access, so that the sideband communication processing module can request the control right to the communication host.

In an alternative implementation, the sideband communication processing module may also consider that the sideband access is triggered when at least the sideband access information written by the memory physical layer interface is detected, and is not limited to requiring the memory physical layer interface to further write trigger information.

In alternative implementations, the communication host may be shared by multiple memory channels, where one memory channel has an independent memory controller, memory physical layer interface, and memory module; therefore, for the memory controller of any memory channel, the sideband communication processing module in the memory controller can judge whether the communication host is in an idle state at present before requesting the control right of the communication host; for example, before the sideband access is triggered and the control right of the communication host needs to be requested, judging whether the communication host is in an idle state currently or not;

if the communication host is in an idle state, the communication host can be requested for control rights so as to realize access to the memory module by using the communication host;

if the communication host is in a busy state, the communication host needs to wait for the communication host to become an idle state, and then request control right from the communication host.

The communication host being in a busy state indicates: sideband communication processing modules of memory controllers of other memory channels are acquiring control rights of a communication host. In order to avoid that the sideband access is performed by the memory physical layer interfaces of the memory channels, no conflict is generated at the communication host, the sideband channel module of the memory controller of any memory channel needs to wait for the communication host to be in an idle state, and then requests to obtain the control right of the communication host.

It should be noted that, in the case of multiple memory channels, the memory controller in each memory channel may be provided with a sideband communication processing module, so that when the memory physical layer interface of the present memory channel initiates a sideband access to the memory module of the present memory channel, the memory module of the present memory channel is accessed by controlling the communication host, so as to implement the sideband access to the memory module of the present memory channel. That is, the memory controller of each memory channel may be provided with a sideband communication processing module, and the sideband access method provided by the embodiment of the present application may implement that the memory physical layer interface of the present memory channel performs sideband access to the memory module of the present memory channel.

In step S512, when the control right of the communication host is obtained, a sideband access command corresponding to the sideband access information is generated according to at least the command protocol of the communication host based on the sideband access information.

In an alternative implementation, the communication host may generate a response signal in response to a request command of the sideband communication processing module to cause the sideband communication processing module to confirm that control of the communication host is obtained, thereby triggering generation of the sideband access command. In one implementation instruction, the communication host may generate a response signal in a high level state (for example, a response signal having a value of 1), so that the sideband communication processing module may be regarded as obtaining control right of the communication host after detecting the response signal in the high level state of the communication host.

In step S513, a sideband access command is sent to the communication host to control the communication host to access the memory module.

In step S514, when the access data is completed to be transferred, the control right of the communication host is released.

After the sideband communication processing module sends the sideband access command to the communication host, the communication host can access the memory module through a sideband access according to the sideband access command. Therefore, the sideband communication processing module can release the control right of the communication host when waiting for the access data corresponding to the sideband access command to finish transmission. Optionally, the sideband communication processing module may generate a release command (the release command is used to release the control right of the communication host), and send the release command to the communication host, so as to implement the control right of the release communication host.

In an alternative implementation, the access data corresponding to the sideband access command is, for example, write data corresponding to the sideband write access command and read data corresponding to the sideband read access command.

If the sideband access command is a sideband write access command, the communication host finishes writing the write data into the memory module, and the communication host is regarded as that the access data corresponding to the sideband write access command is transmitted, so that the sideband communication processing module can release the control right of the communication host.

If the sideband access command is a sideband read access command, reading read data from the memory module by the communication host, and after the sideband communication processing module stores the read data read by the communication host into a local storage space of the sideband communication processing module, completing transmission of the access data corresponding to the sideband read access command; so that the sideband communication processing module can release the control right of the communication host. Optionally, a local memory space for holding read data (e.g., a read data register for holding read data) may be provided in the first register set of the sideband communication processing module.

In an alternative implementation, when the communication host finishes writing the write data into the memory module, or reads the read data from the memory module, the communication host can indicate to the sideband communication processing module that the access data is transmitted on the communication host side through an interrupt signal in a high level state. In one implementation example, the interrupt signal of the high level state may indicate through the high level state of the access end state register of the communication host (e.g., the value of the access end state register is 1, which is regarded as the high level state), so that the sideband communication processing module may confirm that the access data is completed to be transmitted on the communication host side when detecting the high level state of the access end state register of the communication host. The completion of the transfer of the access data at the communication host side may be, for example, the completion of writing the write data into the memory module by the communication host or the completion of reading the read data from the memory module; the node for completing the access data transmission at the communication host side can be determined according to whether the sideband access command is for writing data or reading data.

As an alternative implementation, the sideband communication processing module may have other implementations besides determining, through the access end status register of the communication host, whether the transmission of the access data is completed on the communication host side. For example, a self-zero register is added in the memory controller (the self-zero register can be arranged in the sideband communication processing module) to indicate the access ending state of the communication host; when the access data is transferred on the communication host side (for example, the communication host completes writing the write data into the memory module, or completes reading the read data from the memory module), the communication host may set a self-zero register added in the memory controller to 1; therefore, the sideband communication processing module can detect whether the access data is transmitted on the communication host side according to the writing value of the communication host to the self-zero register; optionally, after one clock cycle, the value of the self-zero register will be automatically cleared.

For another example, a hardware signal is added between the memory controller and the communication host to indicate that the access data is transferred to the communication host; when the access data is transmitted on the communication host side, the communication host can place the hardware signal in a high level state or generate a corresponding signal pulse, so that the sideband communication processing module can detect whether the access data is transmitted on the communication host side through the hardware signal in the high level state or the signal pulse corresponding to the hardware signal.

In the case of sideband write access, the communication host completes writing the write data into the memory module, and may be regarded as the access data completes transmission. For the sideband communication processing module, under the condition of sideband read access, the communication host reads the read data from the memory module, and does not indicate that the access data is transmitted (only the communication host side finishes the transmission of the read data at the moment), and the sideband communication processing module is required to store the read data into a local storage space, so that the communication host can be regarded as the sideband communication processing module to finish the transmission of the access data.

In a further alternative implementation, upon completion of the transfer of the access data (for the sideband communication processing module), the sideband communication processing module may generate a sideband access completion identification to indicate to the memory physical layer interface that sideband access execution is complete. In an alternative implementation, the sideband communication processing module may generate a sideband access completion identification and record in the first set of registers. Further, if the sideband access command is a sideband read access command, the memory physical layer interface may read data from a local storage space of the sideband communication processing module when detecting the sideband access completion identifier.

It can be seen that, in an alternative implementation, after the sideband access is triggered, the hardware logic (such as the sideband communication processing module) of the memory controller implements the sideband access method provided in the embodiments of the present application through different sideband access processing stages (such as a stage of requesting the control right of the communication host, generating and sending a sideband access command, waiting for the access data to complete transmission, releasing the control right of the communication host, and the like). In order to facilitate sideband communication processing to enter different sideband access processing stages, the embodiments of the present application may set multiple states for a sideband communication processing module; when the sideband access is triggered, the sideband communication processing module can respond to the triggering of the sideband access to start state jump in a plurality of states so as to trigger to enter different sideband access processing stages, and further processing of a sideband access method in different sideband access processing stages is achieved.

In an alternative implementation, fig. 6 illustrates an example diagram of the state of the sideband communication processing module, as illustrated in fig. 6, where the plurality of states of the sideband communication processing module may include an idle state 61, a request host control status 62, a transmit state 63, a wait for transmission complete state 64, and a release host control status 65.

The idle state 61 is the starting state of the sideband communication processing module, and when the sideband access is triggered (e.g., when the trigger information of the memory physical layer interface writing the sideband access is detected), the transition from the idle state 61 to the requesting host control authority state 62 is started.

The request host control status 62 is used to trigger a request for control from the communication host, for example, when the request host control status 62 is entered, the sideband communication processing module generates a request command and sends it to the communication host. Further, if the communication host is shared by multiple memory channels, the request host control status 62 may be re-entered while the communication host is in an idle state.

When control of the communication host is obtained (e.g., when a response signal of a high level state of the communication host is detected), the transition from the request host control state 62 to the transfer state 63 is made.

The transmission state 63 is at least used to trigger the generation of a sideband access command and to be sent to the communication host.

In an alternative implementation, as shown in connection with FIG. 6, the transfer state 63 may include a write transfer state 631 when the sideband access command is a sideband write access command. The write transfer state 631 is at least used for triggering the generation of a sideband write access command and sending the sideband write access command to the communication host; therefore, the communication host writes the write data into the memory module according to the write access address information carried by the sideband write access command.

In an alternative implementation, if the sideband access command is a sideband read access command, then in the transmit state 63, the sideband communication processing module needs to transmit the sideband read access command to the communication host and save the read data to the local storage space of the sideband communication processing module when the communication host reads the read data from the memory module. As shown in connection with fig. 6, when the sideband access command is a sideband read access command, the transfer state 63 may include a read transfer state 632 and a read data save state 633.

The read transmission state 632 is at least used for triggering generation of a sideband read access command and sending the sideband read access command to the communication host; thus, the communication host reads the read data from the memory module according to the read access address information carried by the sideband read access command;

the read data storage state 633 is at least used for triggering the read data read by the communication host to be stored in the local storage space of the sideband communication processing module; optionally, after entering the read transfer state 632, if it is detected that the communication host has read data from the memory module in its entirety (e.g., a high state of the access end state register of the communication host is detected), the read transfer state 632 jumps to the read data save state 633.

Optionally, the next state of the transmission state 63 is a waiting for transmission completion state 64, and for the sideband communication processing module, when the access data completes transmission, the state jumps from the waiting for transmission completion state 64 to the release host control authority state 65.

In an alternative implementation, the wait for transfer complete state 64 is a state between the transfer state 63 and the release host control state 64, and for the sideband communication processing module, the wait for transfer complete state 64 may be considered as a waiting phase for the access data to have begun triggering transfer to transfer completion.

If the sideband access command is a sideband write access command, for the sideband communication processing module, the communication host can be regarded as the completion of transmission of the access data after the writing of the write data into the memory module is completed, so that the sideband communication processing module sends the sideband write access command to the communication host, and the communication host can be regarded as the triggering transmission of the access data (namely, under the triggering of the sideband write access command, the communication host starts to write the write data into the memory module); therefore, when the sideband write access command is sent to the communication host, the sideband communication processing module can jump from the write transmission state to the state waiting for transmission completion; further, when it is detected that the communication host completes writing the write data into the memory module, the state may be skipped from the wait for transmission completion state to the release host control right state.

If the sideband access command is a sideband read access command, for the sideband communication processing module, the sideband communication processing module needs to store the read data locally and is regarded as the sideband communication processing module finishes the transmission of the access data, so that the sideband communication processing module starts to store the read data into a local transmission space and can be regarded as the access data starts to trigger the transmission; therefore, when the sideband communication processing module starts to store the read data into the local storage space, the sideband communication processing module can jump from the read data storage state to the state waiting for transmission completion; further, when the read data is completely stored in the local memory space of the sideband communication processing module, the state is changed from the state of waiting for transmission completion to the state of releasing the host control right.

The release host control status 65 is used to trigger release of control of the communication host, for example, when the release host control status 65 is entered, the sideband communication processing module generates a release command and sends the release command to the communication host. Further, after releasing control of the communication host (e.g., after sending a release command to the communication host), the idle state 61 may be skipped from the release host control state 65.

It can be seen that in an alternative implementation, if the sideband access command is a sideband write access command, then a jump may be made in sequence between an idle state, a request host control status, a write transfer status, a wait for transfer complete status, a release host control status, and the release host control status then jumps back to the idle state. If the sideband access command is a sideband read access command, the method can sequentially skip among an idle state, a host control right requesting state, a read transmission state, a read data storage state, a transmission waiting completion state and a host control right releasing state, and skip back to the idle state after the host control right releasing state is released.

In a further alternative implementation, the waiting for transmission completion state is between the transmission state and the release host control right state, which may be regarded as an optional state, and the waiting for transmission completion state may not be set in the embodiment of the present application. For example, after entering the transfer state, when waiting for the access data to complete the transfer, the host control right state is directly released.

In the embodiment of the application, when the memory physical layer interface initiates the sideband access of the memory module, the processing process of the sideband access is realized by hardware logic in the memory controller and communication host hardware, the participation of system software is not needed, acceleration can be carried out through the hardware, the processing time consumption of the sideband access is reduced, and the sideband access efficiency is improved.

As an example of an alternative implementation, an alternative hardware architecture of the sideband communication processing module is described below. It should be noted that, based on the functions of the sideband communication processing module described above, the architecture design of the sideband communication processing module for implementing the functions may be varied, and the embodiments of the present application are not limited according to the design situation of the designer, and the hardware architecture of the sideband communication processing module described below is only shown as an alternative. Alternatively, fig. 7 illustrates an alternative block diagram of a sideband communication processing module, which may include, in conjunction with fig. 2 and 7: a first register set 710, a command sequence module 720, a command sending module 730.

The first register set 710 is at least used for storing sideband access information written by the memory physical layer interface.

The command sequence module 720 is at least used to generate commands to be sent to the communication host. The command sequence module 720 may generate a command to be sent to the communication host based on the sideband communication processing module's need to generate a sideband access command. As an alternative implementation, the command sequence module 720 may be configured to generate the sideband access command according to the sideband access information, at least according to a command protocol of the communication host, when generating the sideband access command.

The command sending module 730 is configured to send the command generated by the command sequence module 720 to the communication host.

As an alternative implementation, the first register set 710 may be a register address space formed by a plurality of registers. In one aspect, the first register set is used as a register address space which is set in the sideband communication processing module and can be accessed by a memory physical layer interface, and the memory physical layer interface can access the first register set through a communication bus so as to write sideband access information in the first register set; furthermore, after writing the sideband access information in the first register set, the memory physical layer interface may further write trigger information of the sideband access in the first register set to trigger the sideband access. In one example, the memory physical layer interface may access the first set of registers via a communication bus based on a protocol such as APB, AHB, AXI to write sideband access information and trigger information in the first set of registers. On the other hand, the sideband communication processing module may write the sideband access completion identification into the first register set when the access data completes transmission.

As an alternative implementation, the first set of registers may hold different information through different registers. Fig. 8A illustrates an alternative block diagram of a first set of registers, which may include an address register 810, a data register 820, a trigger register 830, and an access completion identification register 840, as shown in fig. 8A.

The address register 810 may be used to store address information of the sideband access information written by the memory physical layer interface. For example, the address information of the corresponding sideband access information is accessed by sideband write; for another example, the sideband read accesses address information of the corresponding sideband access information.

As an alternative implementation, the address information may include a memory module address of a memory module to be accessed, a device address of a device to be accessed, and an internal address of the device to be accessed; internal addresses such as register addresses, channel addresses, etc. As an alternative implementation, as shown in connection with fig. 8A, address registers 810 may include a memory module address register 811, a device address register 812, a register address register 813, and a channel address register 814. The memory physical layer interface may write corresponding address information in the memory module address register 811, the device address register 812, the register address register 813, and the channel address register 814, respectively, when initiating the sideband access.

Optionally, the memory module address register 811 may be used to store the memory module address written by the memory physical layer interface to indicate the memory module that needs to be accessed. The device address register 812 may be used to hold the device address written by the memory physical layer interface to indicate the device that needs access. Register address register 813 may be used to hold the register address written by the memory physical layer interface to indicate the registers of the device that need to be accessed. The channel address register 814 may be configured to store a channel address written by the memory physical layer interface to indicate a channel address corresponding to a register of a device to be accessed. It should be noted that the register address register and the channel address register are optional forms of internal address registers, and the internal address registers may be used to store the internal address of the device to be accessed; based on the possible form of the internal address, the register specifically set in the internal address register may be adjusted accordingly, which is not limited in this embodiment of the present application.

The data register 820 may be used to hold access data. Optionally, the access data is, for example, sideband write access corresponding write data, and is, for example, sideband read access corresponding read data. As an alternative implementation, as shown in connection with fig. 8A, the data registers 820 may include a write data register 821 and a read data register 822. The write data register 821 is used for storing write data, and the memory physical layer interface can write the write data into the write data register when initiating sideband write access. The read data register 822 is used to hold read data and may be a local memory space in the sideband communication processing module used to hold read data.

The trigger register 830 may be used to hold trigger information for sideband accesses written by the memory physical layer interface. Alternatively, as shown in connection with FIG. 8, trigger registers 830 may include write trigger register 831 and read trigger register 832 based on a division of sideband accesses into sideband write accesses and sideband read accesses.

The write trigger register 831 is used for storing trigger information of sideband write access; optionally, after writing the sideband access information (address information and write data) corresponding to the sideband write access, the memory physical layer interface may write trigger information of the sideband write access in the write trigger register to trigger the sideband communication processing module to start subsequent sideband write access processing. The read trigger register 832 is used for storing trigger information of sideband read access; optionally, after writing the sideband access information (address information) corresponding to the sideband read access, the memory physical layer interface may write trigger information of the sideband read access in the read trigger register, so as to trigger the sideband communication processing module to start subsequent sideband read access processing.

In an alternative implementation, the trigger information may be a first value (e.g., 1) so that the memory physical layer interface may write the first value in the trigger register 830 to trigger a sideband access. Further, the trigger information written in the trigger register 830 may be automatically cleared after one clock cycle, for example, the first value written in the trigger register 830 may be automatically cleared after one clock cycle. Of course, embodiments of the present application may also support writing a zeroth value (e.g., 0) in the trigger register 830 by the memory physical layer interface to clear the trigger information. The mode of writing the trigger information through the first value and clearing the trigger information through the zero value is suitable for the situations of sideband write access and sideband read access.

It should be noted that, in the embodiment of the present application, the trigger register may be an optional device of the sideband communication processing module. That is, the physical layer interface of the memory is not necessarily required to write trigger information in the trigger register to trigger the sideband access, and other triggering modes are also possible. In an alternative implementation, the sideband communication processing module may be considered to be triggered by a sideband access when at least the presence of new address information in the address register is detected.

The access completion identification register 840 may be used to hold a sideband access completion identification to indicate to the memory physical layer interface that sideband access execution is complete. Optionally, the memory physical layer interface may periodically read whether the sideband access completion flag exists in the access completion flag register 840 to confirm whether the sideband access is completed. Alternatively, the sideband access completion flag may be a first value (e.g., 1), for example, the sideband communication processing module may write the first value in the access completion flag register 840 when the access data completes transmission, so that the memory physical layer interface may periodically read whether the first value is written in the access completion flag register 840 to confirm whether the sideband access is completed. In the case of sideband read access, if the memory physical layer interface confirms that sideband read access is complete by accessing the completion identification register, then read data may be read from the read data register.

In a further alternative implementation, returning to FIG. 7, the sideband communication processing module can also include a second set of registers 740; the second set of registers 740 may be used to hold configuration information provided by the system software. Alternatively, the configuration information may include a current protocol mode of the communication host. Thus, the command sequence module may be configured to generate the sideband access command according to the sideband access information stored in the first register set, at least according to the current protocol mode of the communication host indicated by the second register set, and format information required by the sideband access command when generating the sideband access command.

In alternative implementations, the second set of registers 740 may be configured with different registers to hold different configuration information. Optionally, fig. 8B illustrates an alternative block diagram of the second register set, and as shown in fig. 8B, the second register set may include at least a protocol configuration register 851, where the protocol configuration register 851 may store a current protocol mode of the communication host. Thus, the command sequence module may be configured to generate, when generating the sideband access command, the sideband access command corresponding to the sideband access information according to the sideband access information, at least according to the current protocol mode of the communication host indicated by the protocol configuration register 851, and the format information required by the sideband access command.

In a further alternative implementation, as shown in connection with FIG. 8B, the second set of registers may also include HID configuration registers 852, where HID configuration registers 852 may be HID configuration information for each memory module. In one implementation example, the HID configuration registers may have multiple HID configuration registers, one HID configuration register holding HID configuration information for one memory module. Thus, when generating the sideband access command, the command sequence module may be configured to generate the sideband access command according to the sideband access information, the current protocol mode of the communication host indicated by the protocol configuration register 851, the HID configuration information of the memory module to be accessed indicated by the HID configuration register 852, and the format information required by the sideband access command.

Alternatively, the format information required by the sideband access command may be preset in the corresponding register. For example, a format register may be preset in the second register set to store format information required by the sideband access command.

As an optional implementation, when the sideband access command is generated according to format information required by the sideband access command, access address information in the sideband access command comprises a slave address and an internal address of a device to be accessed; the slave address comprises an HID and an LID; the HID may be determined based on HID configuration information of the memory module to be accessed indicated by HID configuration register 852, and the address of the memory module written in memory module address register 811.

In a further alternative implementation, returning to FIG. 7, the sideband communication processing module can also include a sideband communication processing state machine 750 and a host state parsing module 760.

As an alternative implementation, the sideband communication processing state machine 750 may be used for state hopping of the sideband communication processing module. For example, the sideband communication processing state machine 750 may be configured to initiate a state jump in multiple states in response to a sideband access being triggered to trigger entry into a different sideband access processing stage.

The host state parsing module 760 may be configured to parse information of a communication host such as an I2C/I3C host, and send the information of the communication host back to the sideband communication processing state machine 750, so as to trigger the sideband communication processing state machine 750 to perform a partial state jump.

In conjunction with the state example of the sideband communication processing module shown in fig. 6, in an alternative implementation, the sideband communication processing state machine may jump the state from the idle state to the requesting host control right state when detecting trigger information with sideband access written in the trigger register (e.g., 1 written in the trigger register). For example, in the case of a sideband write access, where a 1 is written to the write trigger register, the state is skipped from the idle state to the requesting host control state. For another example, in the case of a sideband read access, a read trigger register is written with a 1, and the state is then jumped from the idle state to the requesting host control state. In an alternative implementation, the host state analysis module may detect whether the communication host is in an idle state, so that when the communication host is in the idle state, the sideband communication processing state machine is triggered to jump to the request host control right state based on the triggering information of the sideband access.

The request host control status may trigger the command sequence module to generate a request command, such that the command sending module may send the request command to the communication host to request control of the communication host.

The host state parsing module may trigger the sideband communication processing state machine to jump the state from the requesting host control status to the transmitting state upon detecting a response signal (e.g., a response signal having a value of 1) for a high level state from the communication host.

The transmission state may be at least used to trigger the command sequence module to generate a sideband access command, so that the command sending module may send the sideband access command to the communication host to control the communication host to access the memory module.

It should be noted that, in an alternative implementation, if the sideband access command is a sideband write access command, the transmission state is a write transmission state; the write transmission state is at least used for triggering the command sequence module to generate a sideband write access command, so that the command sending module can send the sideband write access command to the communication host so as to control the communication host to write data into the memory module through a sideband channel according to the write access address information.

In an alternative implementation, if the sideband access command is a sideband read access command, the transmission state may include a read transmission state and a read data save state; the read transmission state is at least used for triggering the command sequence module to generate a sideband read access command, so that the command sending module sends the sideband read access command to the communication host to control the communication host to read data from the memory module through a sideband access according to the read access address information; the read data storage state is at least used for triggering the sideband communication processing module to store the read data read by the communication host into the read data register;

When the communication host reads the read data from the memory module, the access end state register of the communication host may be set to a high level state (for example, a first value is written in the access end state register), so that the host state analysis module may detect the high level state of the access end state register of the communication host, and further trigger the sideband communication processing state machine to jump the read transmission state to the read data storage state.

The next state of the transfer state is a waiting transfer completion state (optional state). Under the condition of sideband write access, when a sideband write access command is sent to a communication host, a sideband communication processing state machine jumps to a state waiting for transmission completion; and when the host state analysis module detects the high level state of the access end state register of the communication host, the communication host can be confirmed to complete writing the writing data into the memory module, so that the host state analysis module can trigger the sideband communication processing state machine to jump from the state waiting for transmission completion to the state releasing the host control right.

Under the condition of sideband read access, when the state of reading data storage is entered and reading data storage to a reading data register is started, the sideband communication processing state machine jumps from the state of reading data storage to the state of waiting for transmission completion; further, when the read data is completely saved in the read data register, the sideband communication processing state machine jumps from the wait for transmission completion state to the release host control right state.

It can be seen that the sideband communication processing state machine jumps from the wait for transfer completion state to the release host control state when the access data completes the transfer. The release host control right state is used for triggering the command sequence module to generate a release command, so that the command sending module can send the release command to the communication host to release the control right of the communication host. After releasing the control right of the communication host, the sideband communication processing state machine jumps back to the idle state from the state of releasing the control right of the host.

In one implementation example, taking the DDR PHY interface to initiate a sideband write access to a DIMM as an example, FIG. 9A illustrates an example diagram of a process for sideband write access, as shown in FIG. 9A, which may include the following steps.

In step S910, the DDR PHY interface writes the DIMM address, device address, register address, channel address, write data for the sideband write access to corresponding registers in the first register set, respectively.

Wherein the DIMM address may be written into a DIMM address register (an example of a memory module address register) for indicating a DIMM corresponding to the sideband write access to identify the DIMM to be accessed among the plurality of DIMMs; the device address can be written into a device address register and is used for indicating the devices on the DIMM corresponding to the sideband write access, and a plurality of different devices are arranged on a sideband bus of the DIMM, so that the devices on the DIMM which need to be accessed are identified through the device address; the register address may be written to a register address register for register addressing within the device; the channel address may be written to a channel address register to indicate the channel of the register within the device (some devices are divided into multiple channels, different channels have separate registers, e.g., part of the registers within the RCD need to distinguish the zeroth channel from the first channel). Simultaneously, the DDR PHY interface writes the write data into the write data register.

In step S911, the DDR PHY interface writes a 1 in a write trigger register in the first register set to trigger a sideband write access.

After the DDR PHY interface finishes writing the address information and the write data of the sideband write access, the sideband access information corresponding to the sideband write access can be regarded as the write completion, so that the DDR PHY interface can write 1 in a write trigger register in the first register set to trigger the sideband write access; the write trigger register may be implemented in a self-zeroing manner, for example, the DDR PHY interface triggers a sideband write access by writing 1 in the write trigger register, and after one clock cycle, the value in the write trigger register is automatically zeroed; of course, the DDR PHY interface may also write a 0 in the write trigger register to zero out the value in the write trigger register. The DDR PHY interface may periodically read whether the access completion identification register is written to 1 after triggering the sideband access (e.g., after writing to trigger register write 1 to trigger the sideband write access) to confirm whether the sideband access is complete.

In step S912, the sideband communication processing module generates a sideband write access command.

As an optional implementation, after detecting that the write trigger register is written into 1, the sideband communication processing module may combine HID configuration information in the first register set according to the DIMM address written into by the DDR PHY interface to determine the HID of the DIMM to be accessed corresponding to the sideband write access. It should be noted that, the HID of each DIMM on the motherboard is unique, and for DDR5 memory, HID may be assigned to each DIMM; during system initialization, the system software may write HID configuration information (e.g., HID values) for each DIMM into the HID configuration registers corresponding to the DIMM, and the HID configuration registers are set in the second register set, thereby implementing that the HID configuration information is defined for each DIMM in the HID configuration registers of the sideband communication processing module.

Further, the sideband communication processing module can determine the LID of the equipment to be accessed according to the equipment address written by the DDR PHY interface, so that the slave address is obtained by combining the HID of the DIMM to be accessed and the LID of the equipment to be accessed; further, the sideband communication processing module may generate a sideband write access command carrying information such as a slave address, access byte information, an internal address (e.g., register address, channel address, etc.), write data, etc., according to the current protocol mode of the I2C/I3C host (indicated by the protocol configuration register in the second register set) based on the format information required for sideband write access to the DIMM.

In step S913, the sideband communication processing module sends a sideband write access command to the I2C/I3C host.

Alternatively, the sideband communication processing module may send sideband write access commands to a transmit FIFO (First In First Out, first-in-first-out queue) of the I2C/I3C host via the system management bus.

In step S914, the I2C/I3C host writes the write data to the corresponding DIMM via the sideband pathway according to the sideband write access command.

After the I2C/I3C host acquires the sideband write access command, write data can be written into the corresponding DIMM through the sideband access according to the slave address and the internal address of the sideband write access command. For example, the I2C/I3C host may serially send information related to the sideband write access command in the transmit FIFO to the DIMM sideband interface to enable writing of write data into the DIMM memory space corresponding to the slave address and the internal address.

In step S915, the I2C/I3C host writes 1 to the internal access completion status register.

When the I2C/I3C host writes all of the write data to the corresponding DIMM (e.g., when the I2C/I3C host writes all of the write data in the transmit FIFO to the corresponding DIMM through the DIMM sideband interface), the I2C/I3C host may write a 1 to the access end status register internally to set the access end status register high.

In step S916, the sideband communication processing module writes 1 in the access completion identification register in the first register set.

Optionally, after sending the sideband write access command to the communication host, the sideband communication processing module may periodically read the access end status register of the I2C/I3C host, so as to determine whether the I2C/I3C host completes writing the write data into the corresponding DIMM by determining whether the access end status register is written into 1. Thus, when the sideband communication processing module detects an access completion status register write 1 of the I2C/I3C host, an access completion identification register write 1 (an example of a sideband access completion identification) in the first register set may be written to indicate to the DDR PHY interface that sideband write access execution is complete (e.g., the DDR PHY interface reads writing 1 into the access completion identification register, then confirming that sideband write access execution is complete for the memory module).

It should be noted that, the sideband communication processing module may enter different sideband access processing stages through state jump, so as to implement the related process in fig. 9A; the content of the state jump may refer to the description of the corresponding parts in the foregoing, and will not be repeated here.

In one implementation example, taking the DDR PHY interface to initiate a sideband read access to a DIMM as an example, FIG. 9B illustrates an example diagram of a process for sideband read access, as shown in FIG. 9B, which may include the following steps.

In step S920, the DDR PHY interface writes the DIMM address, the device address, the register address, and the channel address of the sideband read access to corresponding registers in the first register set, respectively.

In step S921, the DDR PHY interface writes a 1 in a read trigger register in the first register set to trigger a sideband read access.

In step S922, the sideband communication processing module generates a sideband write access command.

As an alternative implementation, the sideband communication processing module may generate a sideband read access command carrying information such as a slave address, access byte information, an internal address (e.g., register address, channel address, etc.) according to the current protocol mode of the I2C/I3C host (by configuring the registers by the protocol in the second register set) according to the format information required for sideband read access to the DIMM.

In step S923, the sideband communication processing module sends a sideband read access command to the I2C/I3C host.

Alternatively, the sideband communication processing module may send sideband read access commands to the transmit FIFO of the I2C/I3C host via the system management bus.

In step S924, the I2C/I3C host reads read data from the corresponding DIMM via the sideband pathway in accordance with the sideband read access command.

Optionally, after the I2C/I3C host obtains the sideband read access command, the I2C/I3C host may read the read data from the corresponding DIMM through the sideband channel according to the slave address and the internal address of the sideband read access command. For example, the I2C/I3C host may serially send information related to sideband read access commands in a transmit FIFO to the DIMM sideband interface to receive read data returned by the corresponding DIMM via the DIMM sideband interface; the read data returned by the DIMM may be saved to the receive FIFO of the I2C/I3C host.

In step S925, the I2C/I3C host writes 1 to the internal access completion status register.

When the I2C/I3C host reads all read data (e.g., a stop flag is present on a signal on the DIMM sideband interface, indicating that the DIMM returns to read data to end, the I2C/I3C host reads all read data), the I2C/I3C host may write a 1 to the internal end-of-access status register to set the end-of-access status register high.

In step S926, the sideband communication processing module saves the read data read by the I2C/I3C host to the read data register of the first register set.

In an alternative implementation, when the sideband communication processing module detects that the access end state register of the I2C/I3C host is written to 1, the sideband communication processing module may read the read data from the receive FIFO of the I2C/I3C host via the system management bus and save the read data to the read data register in the first register set.

Optionally, after the sideband communication processing module sends the sideband read access command to the communication host, the sideband communication processing module may periodically read the access end status register of the I2C/I3C host, so as to determine whether all the I2C/I3C hosts read the read data by determining whether the access end status register is written with 1.

In step S927, the sideband communication processing module writes 1 in the access completion identification register in the first register set.

After the sideband communication processing module completely saves the read data to the read data register, 1 can be written in an access completion identification register in the first register set, so that the completion of sideband read access execution is indicated to the DDR PHY interface.

In step S928, the DDR PHY interface reads read data from the read data register.

Optionally, when the DDR PHY interface detects that the access completion identification register is written to 1, the read data returned from the DIMM may be read from the read data register, thereby enabling the DDR PHY interface to obtain the read data for the sideband read access requirement.

It should be noted that, the sideband communication processing module may enter different sideband access processing stages through state jump, so as to implement the related process in fig. 9B; the content of the state jump may refer to the description of the corresponding parts in the foregoing, and will not be repeated here.

The embodiment of the application also provides a core particle, which can comprise a memory controller, a memory physical layer interface and a communication host; the memory controller may be a memory controller provided with hardware logic of a sideband communication processing module according to an embodiment of the present application, and configured to perform the sideband access method according to the embodiment of the present application.

In a further optional implementation, the core may have a plurality of memory channels, one memory channel including a memory controller and a memory physical layer interface, where the memory controller and the memory physical layer interface of one memory channel are connected to a memory module corresponding to the memory channel; and the memory modules of the memory channels share the communication host. In one implementation example, fig. 10 is a block diagram exemplarily showing still another structure of a computer system, as shown in fig. 2 and fig. 10, where in the computer system shown in fig. 10, a core has a plurality of memory channels, and the memory channels are divided into a memory channel 1 to a memory channel n, where n is the number of memory channels may be determined according to practical situations; the memory modules of the memory channels share the same communication host.

When the same communication host is shared by a plurality of memory channels, the method of executing the sideband access by the sideband communication processing module in the memory controller of each memory channel is the same. Further, for any memory channel, the sideband communication processing module in the memory controller of the memory channel needs to interact with the communication host when the communication host is in an idle state, so as to avoid collision between sideband accesses of multiple memory channels at the communication host.

The embodiment of the application also provides a computer device, such as a terminal device or a server device, which may include the core particle provided by the embodiment of the application.

The foregoing describes a number of embodiments provided by embodiments of the present application, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible, all of which may be considered embodiments disclosed and disclosed by embodiments of the present application.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.

Claims

1. A method of sideband access, the method performed by hardware logic of a memory controller, the method comprising:

2. The method of claim 1, wherein the sideband access information carries address information written by a memory physical layer interface; the side band access command carries access address information, and the access address information is determined according to the address information.

3. The method of claim 2, wherein generating the sideband access command corresponding to the sideband access information according to the sideband access information at least in accordance with a command protocol of a communication host comprises:

And generating a sideband access command corresponding to the sideband access information according to the sideband access information at least according to the current protocol mode of the communication host and format information required by the sideband access command.

4. The method of claim 3, wherein generating the sideband access command corresponding to the sideband access information based on the sideband access information, at least in accordance with a current protocol mode of a communication host, and format information required by the sideband access command, comprises:

and generating a sideband access command corresponding to the sideband access information according to the sideband access information, host identifier configuration information of a memory module which needs to be accessed and format information required by the sideband access command according to the current protocol mode of the communication host.

5. The method of claim 4, wherein the address information includes a memory module address of a memory module to be accessed, a device address of a device to be accessed, and an internal address of a device to be accessed; the device to be accessed is positioned in the memory module to be accessed;

the access address information comprises a slave address and an internal address of equipment to be accessed;

Wherein the slave address includes a master identifier and a local identifier; the host identifier is used for addressing the memory module to be accessed, and the host identifier is determined according to the host identifier configuration information of the memory module to be accessed and the memory module address; the local identifier is used for addressing the equipment to be accessed, and the local identifier is determined according to the equipment address of the equipment to be accessed.

6. The method of claim 1, wherein prior to performing the step of generating the sideband access command corresponding to the sideband access information, the method further comprises:

requesting control rights from the communication host;

triggering and executing the step of generating the sideband access command corresponding to the sideband access information when the control right of the communication host is obtained;

and when the access data is transmitted, releasing the control right of the communication host.

7. The method of claim 6, wherein prior to performing the step of requesting control from the communication host, the method further comprises:

and after acquiring the sideband access information written by the memory physical layer interface, acquiring the triggering information of the sideband access written by the memory physical layer interface.

8. The method according to any one of claims 2-7, further comprising:

in response to the sideband access being triggered, a state jump in multiple states is initiated to trigger entry into a different sideband access processing stage.

9. The method of claim 8, wherein the plurality of states includes an idle state, a request host control state, a transfer state, and a release host control state.

10. The method of claim 9, wherein initiating a state jump in a plurality of states to trigger entry into a different sideband access processing stage in response to a sideband access being triggered comprises:

responsive to the sideband access being triggered, initiating a jump from an idle state to a requesting host control state; the request host control right state is used for triggering the request of control right to the communication host;

when the control right of the communication host is obtained, jumping from a request host control right state to a transmission state; the transmission state is at least for: triggering generation of the sideband access command and sending of the sideband access command to the communication host;

when the access data is transmitted, jumping to a state of releasing the control right of the host; the control right releasing state of the host is used for triggering the control right releasing of the communication host;

After releasing the control of the communication host, jumping from the state of releasing the control of the host back to the idle state.

11. The method of claim 10, wherein the plurality of states further comprises: a wait for transmission completion state between a transmission state and a release host control right state; the step of jumping to the state of releasing the control right of the host when the access data is transmitted comprises the following steps:

when the access data is transmitted, the state is jumped from the state of waiting for transmission completion to the state of releasing the control right of the host.

12. The method of claim 11, wherein the sideband access command comprises a sideband write access command, the access address information comprising write access address information, the sideband write access command further carrying write data;

the transmission state includes: writing a transmission state; the write transfer state is at least for: triggering to generate the sideband write access command and sending the sideband write access command to the communication host, so that the communication host writes write data into a memory module according to the write access address information.

13. The method of claim 12, wherein starting state jumps in a plurality of states to trigger entry into different sideband access processing stages in response to a sideband access being triggered further comprises:

When the sideband write access command is sent to the communication host, jumping to a state waiting for transmission completion;

the step of jumping from the waiting transmission completion state to the release host control right state when the access data completes transmission comprises the following steps:

when the communication host is detected to finish writing the writing data into the memory module, jumping from a state waiting for transmission completion to a state releasing the control right of the host; and the communication host finishes writing the write data into the memory module, and then the communication host finishes transmitting the access data corresponding to the sideband write access command.

14. The method of claim 11, wherein the sideband access command comprises a sideband read access command and the access address information comprises read access address information;

the transmission state includes: a read transmission state and a read data storage state;

the read transfer state is at least for: triggering to generate the sideband read access command and sending the sideband read access command to the communication host, so that the communication host reads read data from a memory module according to the read access address information;

the read data retention state is at least for: triggering read data read by a communication host and storing the read data in a local storage space of the hardware logic; when detecting that the communication host computer reads the read data from the memory module, the read transmission state jumps to the read data storage state.

15. The method of claim 14, wherein starting state jumps in a plurality of states in response to a sideband access being triggered to trigger entry into a different sideband access processing stage further comprises:

when the read data starts to be stored in the local storage space of the hardware logic, jumping to a state waiting for transmission completion;

when the read data is completely stored in the local storage space of the hardware logic, jumping from a state waiting for transmission completion to a state releasing host control right; and the read data is completely stored in the local storage space of the hardware logic, and the access data corresponding to the sideband read access command is transmitted.

16. The method of claim 6, wherein prior to performing the step of requesting control from the communication host, the method further comprises:

judging whether the communication host is in an idle state currently; the communication host is shared by a plurality of memory channels, and one memory channel is provided with an independent memory controller, a memory physical layer interface and a memory module;

If the communication host is in an idle state, entering the step of requesting control right from the communication host;

waiting for the communication host to become an idle state if the communication host is in a busy state; the communication host being in a busy state indicates: the hardware logic of the memory controller of the other memory channel is gaining control of the communication host.

17. The method according to claim 13 or 15, characterized in that the method further comprises:

and when the access data is transmitted, generating a sideband access completion identification to indicate the completion of sideband access execution to the memory physical layer interface.

18. The memory controller is characterized by being provided with a sideband communication processing module, wherein the sideband communication processing module is hardware logic of the memory controller; the sideband communication processing module configured to perform the sideband access method of any one of claims 1-17.

19. The memory controller of claim 18, wherein the sideband communication processing module communicates with the memory physical layer interface via a communication bus added by the memory controller, the sideband communication processing module communicating with the communication host via a system management bus; the communication host communicates with the memory module through a sideband pathway.

20. The memory controller of claim 19, wherein the sideband communication processing module comprises: the device comprises a first register set, a command sequence module and a command sending module;

the first register set is at least used for storing sideband access information written by a memory physical layer interface;

the command sequence module is at least used for generating a command sent to the communication host; wherein the command sent to the communication host includes a sideband access command corresponding to the sideband access information; the command sequence module is used for generating the side band access command according to the side band access information and at least according to a command protocol of a communication host when the side band access command is generated;

the command sending module is used for sending the command generated by the command sequence module to the communication host.

21. The memory controller of claim 20, wherein the sideband access information carries address information written by a memory physical layer interface; the first register set includes: an address register for storing the address information; the sideband access command carries access address information, and the access address information is determined according to the address information.

22. The memory controller of claim 21, wherein the sideband communication processing module further comprises: and the second register set is used for storing configuration information provided by system software.

23. The memory controller of claim 22, wherein the second set of registers includes at least a protocol configuration register, the protocol configuration register holding a current protocol mode of the communication host;

and the command sequence module is used for generating the sideband access command corresponding to the sideband access information according to the sideband access information, at least according to the current protocol mode of the communication host indicated by the protocol configuration register and the format information required by the sideband access command when the sideband access command is generated.

24. The memory controller of claim 23, wherein the second set of registers further comprises a host identifier configuration register, the host identifier configuration register holding host identifier configuration information for each memory module;

and the command sequence module is used for generating the sideband access command corresponding to the sideband access information according to the sideband access information, the current protocol mode of the communication host indicated by the protocol configuration register, the host identifier configuration information of the memory module which is required to be accessed and indicated by the host identifier configuration register, and the format information required by the sideband access command.

25. The memory controller of claim 21, wherein the address information includes a memory module address of a memory module to be accessed, a device address of a device to be accessed, and an internal address of a device to be accessed;

the address register includes: memory module address registers, device address registers, and internal address registers; the memory module address register is used for storing the memory module address, the equipment address register is used for storing the equipment address, and the internal address register is used for storing the internal address;

the access address information comprises a slave address and an internal address of equipment to be accessed; wherein the slave address includes a master identifier and a local identifier; the host identifier is used for addressing the memory module to be accessed, and the host identifier configuration information and the memory module address of the memory module to be accessed are determined according to the host identifier configuration information and the memory module address of the memory module to be accessed; the local identifier is used for addressing the equipment to be accessed and is determined according to the equipment address of the equipment to be accessed.

26. The memory controller of claim 25, wherein the internal addresses include register addresses of registers to be accessed and channel addresses of channels corresponding to registers to be accessed; the register to be accessed is located in the equipment to be accessed;

The internal address register at least comprises a register address register and a channel address register; the register address register is used for storing the register address, and the channel address register is used for storing the channel address.

27. The memory controller of claim 21, wherein the first set of registers further comprises at least one of: a data register, a trigger register, and an access completion identification register;

the data register is used for storing access data;

the trigger register is used for storing the triggering information of the sideband access written in by the memory physical layer interface;

the access completion identification register is used for storing a sideband access completion identification, wherein when the transmission of the access data is completed, the sideband communication processing module writes the sideband access completion identification into the access completion identification register.

28. The memory controller of claim 27, wherein the data registers comprise a write data register and a read data register; the write data register is used for storing write data written by the memory physical layer interface when the memory physical layer interface initiates sideband write access of the memory module; the read data register is used for storing read data read from the memory module when the memory physical layer interface initiates sideband read access of the memory module;

The trigger register comprises a write trigger register and a read trigger register; the write trigger register is used for storing trigger information of sideband write access written by the memory physical layer interface; the read trigger register is used for storing the trigger information of the sideband read access written in the memory physical layer interface.

29. The memory controller of any one of claims 20-28, wherein the sideband communication processing module further comprises: a sideband communication processing state machine and a host state analyzing module;

the sideband communication processing state machine is used for starting state jump in a plurality of states in response to the triggering of the sideband access so as to trigger the entering of different sideband access processing stages;

the host state analysis module is used for analyzing information of the communication host, and feeding back the information of the communication host to the sideband communication processing state machine so as to trigger the sideband communication processing state machine to carry out partial state jump.

30. The memory controller of claim 29, wherein the plurality of states includes an idle state, a request host control state, a transfer state, and a release host control state.

31. The memory controller of claim 30, wherein the sideband communication processing state machine is to:

Responsive to the sideband access being triggered, initiating a jump from an idle state to a requesting host control state; the request host control right state is used for triggering the command sequence module to generate a request command, and the request command is used for requesting the control right of the communication host;

based on the response signal of the communication host to the request command detected by the host state analysis module, jumping from the request host control right state to the transmission state; the transmission state is at least used for triggering the command sequence module to generate the sideband access command;

when the access data is transmitted, jumping to a state of releasing the control right of the host; the control right state of the release host is used for triggering the command sequence module to generate a release command, and the release command is used for releasing the control right of the communication host;

32. The memory controller of claim 31, wherein the plurality of states further comprises: a wait for transmission completion state between a transmission state and a release host control right state; when the access data is transmitted, the sideband communication processing state machine jumps to a state of releasing host control right from a state of waiting for transmission completion.

33. The memory controller of claim 32, wherein the sideband access command comprises a sideband write access command, the access address information comprising write access address information, the sideband write access command further carrying write data;

the transmission state includes: writing a transmission state; the write transfer state is at least for: triggering the command sequence module to generate the sideband write access command, so that the command sending module sends the sideband write access command to the communication host to control the communication host to write data into the memory module according to the write access address information.

34. The memory controller of claim 33 wherein the sideband communication processing state machine jumps to a wait for transmission completion state when the sideband write access command is sent to the communication host; the sideband communication processing state machine confirms that the communication host finishes writing the writing data into the memory module based on the high level state of the access end state register of the communication host detected by the host state analysis module so as to jump the state waiting for completing transmission to the state releasing the control right of the host; and the communication host finishes writing the write data into the memory module, and then the communication host finishes transmitting the access data corresponding to the sideband write access command.

35. The memory controller of claim 32, wherein the sideband access command comprises a sideband read access command, and the access address information comprises read access address information;

the transmission state includes: a read transmission state and a read data storage state; the read transfer state is at least for: triggering the command sequence module to generate the sideband read access command, so that the command sending module sends the sideband read access command to the communication host to control the communication host to read data from the memory module according to the read access address information;

the read data retention state is at least for: triggering the sideband communication processing module to store read data read by a communication host into a read data register;

the sideband communication processing state machine confirms that the communication host completely reads read data from the memory module based on the high level state of the access end state register of the communication host detected by the host state analysis module so as to jump the read transmission state to the read data storage state;

when the read data starts to be stored in the read data register, jumping to a state waiting for transmission completion; when the read data is completely stored in the read data register, the state of waiting for transmission completion is jumped to the state of releasing the control right of the host; and completely storing the read data into a read data register, and completing transmission of the access data corresponding to the sideband read access command.

36. The core particle is characterized by comprising a memory controller, a memory physical layer interface and a communication host; the memory controller is a memory controller as claimed in any one of claims 18 to 35.

37. The core particle of claim 36, wherein the core particle has a plurality of memory channels, one memory channel comprising a memory controller and a memory physical layer interface, the memory controller and the memory physical layer interface of one memory channel being coupled to a memory module corresponding to the memory channel; and, a plurality of memory channels share a communication host.

38. A computer device comprising the core of any of claims 36-37.