CN117526585A - Phase demodulation circuit, wireless power transmitting end and wireless charging system - Google Patents
Phase demodulation circuit, wireless power transmitting end and wireless charging system Download PDFInfo
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- CN117526585A CN117526585A CN202410004037.5A CN202410004037A CN117526585A CN 117526585 A CN117526585 A CN 117526585A CN 202410004037 A CN202410004037 A CN 202410004037A CN 117526585 A CN117526585 A CN 117526585A
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- 238000010168 coupling process Methods 0.000 claims abstract description 12
- 238000005859 coupling reaction Methods 0.000 claims abstract description 12
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
- H02J50/80—Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
- H02J7/00036—Charger exchanging data with battery
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
- H02J7/00714—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery charging or discharging current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
- H02J7/007182—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
- H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The application provides a phase demodulation circuit, wireless power transmitting terminal and wireless charging system, include: the device comprises a first capacitor, a signal acquisition module and a signal processing module, wherein the signal processing module comprises a first mixing filtering branch and a second mixing filtering branch; the first capacitor is arranged between the coupling coil of the wireless power transmitting end and the inverter; the first end and the second end of the signal acquisition module are respectively connected with the first pole and the second pole of the first capacitor, and the output end of the signal acquisition module is respectively connected with the first input ends of the two mixing filtering branches; the second input end of the first mixing filtering branch is used for being connected with a first reference clock signal, the second input end of the second mixing filtering branch is used for being connected with a second reference clock signal, and the phase difference between the first reference clock signal and the second reference clock signal is 90 degrees; the output ends of the two mixing filtering branches are used for being connected with a post-stage circuit. The stability of power transmission can be effectively enhanced, the product compatibility is improved, and the user experience is improved.
Description
Technical Field
The application relates to the field of wireless charging, in particular to a phase demodulation circuit, a wireless power transmitting end and a wireless charging system.
Background
The traditional electric energy transmission is mainly carried out through a wire, and due to the defects of the traditional electric energy transmission, the wired charging has the limitation in special environments such as humidity, inflammability, medical implantation and the like, and various inconveniences are brought in daily life.
The wireless charging technology avoids the defects of the traditional wired charging mode, is paid more attention to, and has more and more wide application in the fields of consumer electronics, industrial products, medical services and the like. At present, wireless charging equipment such as a smart phone, a wireless earphone and a wearable digital product has more and more powerful functions, so that the convenience in charging a battery is more important, and the charging power of the battery is continuously increased.
With the development of wireless charging markets, more and more devices capable of supporting wireless charging are available, and compatibility requirements among products are stronger. The demodulated signal is important for achieving charging device compatibility as an adaptation signal in a wireless charging system. How to provide a stable demodulation signal becomes a problem of interest to those skilled in the art.
Disclosure of Invention
An objective of the present invention is to provide a phase demodulation circuit, a wireless power transmitting terminal and a wireless charging system, so as to at least partially improve the above-mentioned problems.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, embodiments of the present application provide a phase demodulation circuit, including: the device comprises a first capacitor, a signal acquisition module and a signal processing module, wherein the signal processing module comprises two mixing filtering branches, namely a first mixing filtering branch and a second mixing filtering branch;
the first capacitor is used for being arranged between the coupling coil of the wireless power transmitting end and the inverter;
the first end of the signal acquisition module is connected with the first pole of the first capacitor, the second end of the signal acquisition module is connected with the second pole of the first capacitor, and the output ends of the signal acquisition module are respectively connected with the first input ends of the two frequency mixing filtering branches;
the second input end of the first mixing filtering branch is used for being connected with a first reference clock signal, the second input end of the second mixing filtering branch is used for being connected with a second reference clock signal, and the phase difference between the first reference clock signal and the second reference clock signal is 90 degrees;
the output ends of the two frequency mixing filtering branches are used for being connected with a post-stage circuit.
In a second aspect, an embodiment of the present application provides a wireless power transmitting terminal, where the wireless power transmitting terminal includes the phase demodulation circuit described above.
In a third aspect, an embodiment of the present application provides a wireless charging system, where the wireless charging system includes the wireless power transmitting terminal described above.
Compared with the prior art, the embodiment of the application provides a phase demodulation circuit, wireless power transmitting terminal and wireless charging system, the phase demodulation circuit includes: the signal processing module comprises two mixing filtering branches, namely a first mixing filtering branch and a second mixing filtering branch; the first capacitor is arranged between the coupling coil of the wireless power transmitting end and the inverter; the first end of the signal acquisition module is connected with the first pole of the first capacitor, the second end of the signal acquisition module is connected with the second pole of the first capacitor, and the output end of the signal acquisition module is respectively connected with the first input ends of the two frequency mixing filtering branches; the second input end of the first mixing filtering branch is used for being connected with a first reference clock signal, the second input end of the second mixing filtering branch is used for being connected with a second reference clock signal, and the phase difference between the first reference clock signal and the second reference clock signal is 90 degrees; the output ends of the two mixing filtering branches are used for being connected with a post-stage circuit. The stability of power transmission can be effectively enhanced, the product compatibility is improved, and the user experience is improved. The problem of power transmission interruption in the wireless charging process is solved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a wireless charging system according to an embodiment of the present application;
fig. 2 is a schematic diagram of a phase demodulation circuit according to an embodiment of the present application;
fig. 3 is a second schematic diagram of a phase demodulation circuit according to an embodiment of the present disclosure;
fig. 4 is a third schematic diagram of a phase demodulation circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a phase demodulation circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a mixing filtering branch according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a post-stage circuit according to an embodiment of the present application.
In the figure: 10-a wireless power transmitting end; 20-a wireless power receiving end; 30-loading; 40-power supply; 110-an inverter; a 120-phase demodulation circuit; 121-a signal acquisition module; 122-a signal processing module; 123-post-stage circuitry; 130-coupling coils; 1221-a first mixing filtering branch; 1222-a second mixing filter branch; 122A-a first transmission gate; 122B-a second transmission gate; 122C-analog switch; 122D-filtering unit; 122E-logic gates; 1231-an amplification module; 1232-comparison module.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
In an alternative scenario voltage amplitude and current amplitude signals may be used as demodulation signals, but there are significant limitations to the use of voltage amplitude and current amplitude signals for communication demodulation. To overcome this limitation, the present application introduces phase demodulation in the communication demodulation mode.
The main disadvantages of using voltage amplitude and current amplitude for demodulation include:
first, after the coupling between coils is changed, the modulation amplitude is extremely low or zero, so that the demodulation performance is poor and the communication is failed;
second, in the charging process, the power fluctuation of the load affects the voltage amplitude and the current amplitude, so that the demodulation performance is poor, and the communication is failed;
third, when the modulation mode (capacitance modulation or resistance modulation) or the modulation position (AC node or Vrect node) of the wireless power receiving end changes, the change of the voltage amplitude and the current amplitude is affected, resulting in poor demodulation performance and communication failure.
Because the demodulation by adopting the voltage amplitude and the current amplitude has the defects, the demodulation circuit of the voltage amplitude and the current amplitude cannot be compatible with partial wireless equipment on the market, and the conditions of communication failure, charging interruption or incapacity of charging and wireless power receiving end damage occur in the use process of users, so that the use of customers is seriously influenced.
In order to overcome the above problems, an embodiment of the present application provides a wireless charging system, please refer to fig. 1, and fig. 1 is a schematic structural diagram of the wireless charging system according to the embodiment of the present application.
As shown in fig. 1, the wireless charging system includes a wireless power transmitting terminal 10 and a wireless power receiving terminal 20. The wireless power transmitting terminal 10 and the wireless power receiving terminal 20 are provided with one or more groups of mutually coupled coils, the wireless power transmitting terminal 10 can output electric energy to the wireless power receiving terminal 20 through the one or more groups of mutually coupled coils, the wireless power receiving terminal 20 is connected with the load 30 at the rear end, and the load 30 can be charged.
The receiving end modulation module of the wireless power receiving end 20 can adjust the variable load inside the receiving end modulation module to change the current amplitude, the voltage amplitude, the phase information and the like in one or more groups of mutually coupled coils, and the wireless power receiving end 20 can acquire and analyze the information to obtain corresponding demodulation signals so as to change any one or more of output power, output current and output voltage.
With continued reference to fig. 1, the wireless power transmitting terminal 10 includes an inverter 110, a phase demodulation circuit 120 and a coupling coil 130. The first and second input terminals of the inverter 110 are connected to the positive and negative poles of the power source 40, respectively.
The phase demodulation circuit 120 includes: the signal processing module 122 includes two mixing filter branches, namely a first mixing filter branch 1221 and a second mixing filter branch 1222.
The first capacitor C1 is disposed between the coupling coil 130 of the wireless power transmitting terminal 10 and the inverter 110.
The first output terminal of the inverter 110 is connected to one end of the coupling coil 130, the other end of the coupling coil 130 is connected to the second pole of the first capacitor C1, and the first pole of the first capacitor C1 is connected to the second output terminal of the inverter 110.
The first end of the signal acquisition module 121 is connected to the first pole of the first capacitor C1, the second end of the signal acquisition module 121 is connected to the second pole of the first capacitor C1, and the output ends of the signal acquisition module 121 are respectively connected to the first input ends of the two mixing filtering branches.
A second input of the first mixing filter branch 1221 is for accessing a first reference clock signal and a second input of the second mixing filter branch 1222 is for accessing a second reference clock signal, the first reference clock signal being 90 ° out of phase with the second reference clock signal.
Optionally, the first reference clock signal and the second reference clock signal are at the same frequency as the switches of the inverter 110.
It should be noted that the circuit structures of the first mixing filter branch 1221 and the second mixing filter branch 1222 may be identical, and only the reference clock signal is accessed differently.
The output ends of the two mixing filtering branches are used for being connected with a post-stage circuit 123.
In an alternative embodiment, the signal acquisition module 121 is configured to acquire voltage information between two poles of the first capacitor C1, generate a corresponding first-order signal, and transmit the first-order signal to the first input ends of the two mixing filtering branches.
The first mixing filtering branch 1221 is configured to perform mixing processing on the first order signal and the first reference clock signal to obtain a first mixed signal, and perform filtering processing on the first mixed signal to filter out a fundamental frequency signal and a harmonic signal therein, so as to obtain a first demodulation signal.
The second mixing filter branch 1222 is configured to perform mixing processing on the first-order signal and the second reference clock signal to obtain a second mixed signal, and perform filtering processing on the second mixed signal to filter out the fundamental frequency signal and the harmonic signal therein, so as to obtain a second demodulated signal.
It should be noted that the first demodulation signal and the second demodulation signal each include envelope information required for demodulation, which includes both amplitude information (voltage amplitude and current amplitude) and phase information.
The post-stage circuit 123 is configured to process the received first demodulation signal and the received second demodulation signal, and transmit the processed signals to the controller of the wireless power transmitting terminal 10, where the controller adjusts the inverter 110 according to the phase information in the received signals, or adjusts the inverter 110 according to the phase information, the voltage amplitude information, and the current amplitude information in the received signals.
Referring to fig. 1, regarding a specific structure of the signal acquisition module 121, an alternative implementation manner is further provided in the embodiment of the present application, and referring to fig. 2, fig. 2 is a schematic diagram of a phase demodulation circuit 120 in the embodiment of the present application.
As shown in fig. 2, the signal collecting module 121 includes a second operational amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a second capacitor C2.
The first end of the first resistor R1 is connected to the output end of the second operational amplifier U2, and the second end of the first resistor R1 is connected to the inverting input end of the second operational amplifier U2.
One pole of the second capacitor C2 is connected to the first end of the first resistor R1, and the second pole of the second capacitor C2 is connected to the second end of the first resistor R1.
The first end of the second resistor R2 is connected to the inverting input end of the second operational amplifier U2, and the first end of the third resistor R3 is connected to the non-inverting input end of the second operational amplifier U2.
The first end of the fourth resistor R4 is connected to the non-inverting input end of the second op-amp U2, and the second end of the fourth resistor R4 is used for accessing the reference Voltage (VREF).
The second end of the second resistor R2 is connected to the second pole of the first capacitor C1 as the second end of the signal acquisition module 121.
The second end of the third resistor R3 is connected to the first pole of the first capacitor C1 as the first end of the signal acquisition module 121.
Optionally, the output end of the second operational amplifier U2 is used as the output end of the signal acquisition module 121, and is connected to the first input ends of the two mixing filtering branches respectively.
The signal acquisition module 121 shown in fig. 2 may be used as a signal attenuator, where the signal attenuator attenuates a large signal in equal proportion to a low-amplitude signal that is convenient to process, i.e. a first-order signal in the present application. The large signal here means that after the output of the inverter 110 passes through the coupling coil 130 (inductance) and the first capacitor C1, a sinusoidal-like ac signal is generated at the first capacitor C1. The phase information means that the alternating current signal formed on the capacitor by modulation and non-modulation at the receiving end has phase difference.
With continued reference to fig. 2, in an alternative embodiment, the phase demodulation circuit 120 further includes a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a twenty-third resistor R23, and a twenty-fourth resistor R24.
One pole of the thirteenth capacitor C13 is connected to the second end of the second resistor R2, the other pole of the thirteenth capacitor C13 is connected to the first end of the twenty-third resistor R23, and the second end of the twenty-third resistor R23 is connected to the second pole of the first capacitor C1.
One pole of the fourteenth capacitor C14 is connected to the second end of the third resistor R3, the other pole of the fourteenth capacitor C14 is connected to the first end of the twenty-fourth resistor R24, and the second end of the twenty-fourth resistor R24 is connected to the first pole of the first capacitor C1.
One pole of the tenth capacitor C10 is grounded, and the other pole of the tenth capacitor C10 is connected between the twenty-third resistor R23 and the thirteenth capacitor C13.
One pole of the eleventh capacitor C11 is connected between the twenty-fourth resistor R24 and the fourteenth capacitor C14, and the other pole of the eleventh capacitor C11 is connected between the twenty-third resistor R23 and the thirteenth capacitor C13.
One pole of the twelfth capacitor C12 is grounded, and the other pole of the twelfth capacitor C12 is connected between the twenty-fourth resistor R24 and the fourteenth capacitor C14.
The tenth capacitor C10, the eleventh capacitor C11, and the twelfth capacitor C12 are used for filtering, the thirteenth capacitor C13 and the fourteenth capacitor C14 are used as blocking capacitors, and the twenty-third resistor R23 and the twenty-fourth resistor R24 are used as current limiting resistors.
With reference to fig. 2, regarding a specific structure of the signal acquisition module 121, an alternative implementation manner is further provided in this embodiment, please refer to fig. 3, and fig. 3 is a second schematic diagram of a phase demodulation circuit in this embodiment.
As shown in fig. 3, the signal acquisition module 121 further includes a first comparator U1 and a fifteenth capacitor C15.
One end of the fifteenth capacitor C15 is connected to the output end of the second operational amplifier, and the other end of the fifteenth capacitor C15 is connected to the inverting input end of the first comparator U1.
The inverting input of the first comparator U1 is connected to a common mode bias based on a reference voltage.
The non-inverting input terminal of the first comparator U1 is used for accessing the reference voltage.
The output end of the first comparator U1 is used as the output end of the signal acquisition module.
It should be noted that, the first comparator U1 may obtain a Vctx square wave signal, that is, a first-order signal, and may remove the amplitude information in the envelope information, and only retain the phase information.
In an alternative embodiment, a twenty-fifth resistor R25 is further disposed at the output end of the first comparator U1, one end of the twenty-fifth resistor R25 is connected to the output end of the first comparator U1, and the other end of the twenty-fifth resistor R25 is connected to the input end of the mixing filtering branch.
Referring to fig. 3, regarding a specific structure of the mixing filtering branch, an alternative implementation manner is further provided in the embodiment of the present application, please refer to fig. 4, fig. 4 is a third schematic diagram of the structure of the phase demodulation circuit 120 in the embodiment of the present application.
As shown in fig. 4, the mixing filter branch includes a logic gate 122E and a filter unit 122D.
The first end of the logic gate 122E is used as a first input end of the mixing filtering branch, the second end of the logic gate 122E is used as a second input end of the mixing filtering branch for accessing the first reference clock signal or the second reference clock signal, the third end of the logic gate 122E is connected to an input end of the filtering unit 122D, and an output end of the filtering unit 122D is used as an output end of the mixing filtering branch for connecting the post-stage circuit 123.
The logic gate 122E is configured to perform mixing according to the received reference clock signal and the first-order signal (the square wave signal output by the first comparator U1) received at the first end, so as to obtain a mixed signal, and transmit the mixed signal to the filtering unit 122D.
The filtering unit 122D is configured to perform filtering processing on the received signal, and filter out the fundamental frequency signal and the harmonic signal therein.
Referring to fig. 1, regarding a specific structure of the mixing filtering branch, an alternative implementation manner is further provided in the embodiment of the present application, and referring to fig. 5, fig. 5 is a second schematic diagram of a structure of a phase demodulation circuit 120 in the embodiment of the present application.
As shown in fig. 5, the mixing filter leg may be any one of the first mixing filter leg 1221 and the second mixing filter leg 1222. The mixing filter branch includes a first transmission gate 122A, a second transmission gate 122B, an analog switch 122C, and a filter unit 122D.
A first connection terminal is led out at the connection position between the input end of the first transmission gate 122A and the input end of the second transmission gate 122B, and is used as a first input end of the mixing filtering branch and connected to the output end of the signal acquisition module 121. The input of the first transmission gate 122A and the input of the second transmission gate 122B may each receive a first order signal.
The output end of the first transmission gate 122A is connected to the first end of the analog switch 122C, the output end of the second transmission gate 122B is connected to the second end of the analog switch 122C, the output end of the analog switch 122C is connected to the input end of the filtering unit 122D, and the output end of the filtering unit 122D is used as the output end of the mixing filtering branch for connecting the post-stage circuit 123.
The control terminal of the analog switch 122C is used as a second input terminal of the mixing filter branch for accessing the first reference clock signal or the second reference clock signal.
The first transmission gate 122A is used to pass the received signal (first-order signal) to the analog switch 122C.
The second transmission gate 122B is configured to invert the received signal (first-order signal) and transmit the inverted signal to the analog switch 122C.
The analog switch 122C is configured to switch a conductive relationship between the first end, the second end and the output end according to the received reference clock signal (the first reference clock signal or the second reference clock signal), so as to complete the mixing process and obtain a mixed signal (the first mixed signal or the second mixed signal).
And a filtering unit 122D for filtering the received signal to remove the fundamental frequency signal and the harmonic signal.
It should be noted that the first reference clock signal and the second reference clock signal in the present application may be PWM reference signals.
In an alternative embodiment, when the PWM reference signal is high (+1), the first-order signal is transmitted to the back-end through the first transmission gate 122A, and when the PWM reference signal is low (-1), the first-order signal is transmitted to the back-end through the second transmission gate 122B, resulting in a mixed signal.
On the basis of fig. 5, regarding the specific structure of each module in the mixing filtering branch, an alternative implementation manner is further provided in the embodiment of the present application, please refer to fig. 6, and fig. 6 is a schematic structural diagram of the mixing filtering branch provided in the embodiment of the present application.
As shown in fig. 6, the first transmission gate 122A includes a fifth resistor R5, one end of the fifth resistor R5 is used as an input end of the first transmission gate 122A, and is connected to a first-order signal, and the other end of the fifth resistor R5 is used as an output end of the first transmission gate 122A and is connected to a first end of the analog switch 122C.
And/or, the second transmission gate 122B includes a third capacitor C3, a fourth capacitor C4, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a third operational amplifier U3.
The resistance of the fifth resistor R5 is equal to that of the eighth resistor R8, so as to ensure the impedance consistency of the two paths of signals sent to the analog switch 122C. The fourth capacitor C4 is used as a blocking capacitor to remove the dc component.
The first end of the sixth resistor R6 is connected to the output end of the third operational amplifier U3, the second end of the sixth resistor R6 is connected to the inverting input end of the third operational amplifier U3, one pole of the third capacitor C3 is connected to the first end of the sixth resistor R6, and the other pole of the third capacitor C3 is connected to the second end of the sixth resistor R6.
The first end of the seventh resistor R7 is connected to the inverting input terminal of the third op-amp U3, the second end of the seventh resistor R7 is connected to one pole of the fourth capacitor C4, and the other pole of the fourth capacitor C4 is used as the input terminal of the second transmission gate 122B.
One end of the eighth resistor R8 is connected to the output end of the third op-amp U3, and the other end of the eighth resistor R8 is used as the output end of the second transmission gate 122B.
One end of the ninth resistor R9 is connected to the non-inverting input end of the third operational amplifier U3, and the other end of the ninth resistor R9 is used for being connected with a reference Voltage (VREF).
With continued reference to fig. 6, in an alternative embodiment, the analog switch 122C includes a first subunit U4A, a second subunit U4B, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.
The first end of the first subunit U4A is connected to the output end of the first transmission gate 122A as a first end of the analog switch 122C.
The first terminal of the second subunit U4B is connected to the output terminal of the second transmission gate 122B as the second terminal of the analog switch 122C.
A second connection terminal is led out from the connection between the second end of the first subunit U4A and the second end of the second subunit U4B, and is used as an output end of the analog switch 122C, and is connected to an input end of the filtering unit 122D.
One end of the tenth resistor R10 is connected to the control end of the first subunit U4A, one end of the eleventh resistor R11 is grounded, the other end of the eleventh resistor R11 is connected to the other end of the tenth resistor R10, and a third connecting terminal is led out from the joint of the tenth resistor R10 and the eleventh resistor R11.
One end of the twelfth resistor R12 is connected to the control end of the second subunit U4B, one end of the thirteenth resistor R13 is grounded, the other end of the thirteenth resistor R13 is connected to the other end of the twelfth resistor R12, and a fourth connecting terminal is led out from the joint of the thirteenth resistor R13 and the twelfth resistor R12.
The third connection terminal and the fourth connection terminal are used together as a control end of the analog switch 122C and as a second input end of the mixing filtering branch for accessing the first reference clock signal or the second reference clock signal. It should be noted that, the reference clock signals received by the first subunit U4A and the second subunit U4B in the same mixing filtering branch are the same.
When the same reference clock signal is received, the first end and the second end of the first subunit U4A are turned on, or the first end and the second end of the second subunit U4B are turned on, and the first end and the second end cannot be turned on at the same time.
With continued reference to fig. 6, in an alternative embodiment, the filtering unit 122D includes a fourteenth resistor R14 and a fifth capacitor C5. One end of the fourteenth resistor R14 is used as an input end of the filtering unit 122D and is connected to an output end of the analog switch 122C, the other end of the fourteenth resistor R14 is connected to one pole of the fifth capacitor C5, a fifth connecting terminal is led out from a connection position of the fourteenth resistor R14 and the output end of the filtering unit 122D, and the output end of the fourteenth resistor R is used for being connected to the rear-stage circuit 123, and the other pole of the fifth capacitor C5 is grounded.
An alternative implementation manner is also provided in this embodiment regarding the specific structure of the post-stage circuit 123 on the basis of fig. 1, please refer to fig. 7, fig. 7 is a schematic diagram of the structure of the post-stage circuit provided in this embodiment.
As shown in fig. 7, the phase demodulation circuit 120 further includes a post-stage circuit 123, and the post-stage circuit 123 includes an amplifying module 1231 and a comparing module 1232.
The input end of the amplifying module 1231 is connected to the output end of the mixing filtering branch, and the output end of the amplifying module 1231 is connected to the input end of the comparing module 1232.
With continued reference to fig. 7, in an alternative embodiment, the amplifying module 1231 includes a fifth operational amplifier U5, a sixth capacitor C6, a seventh capacitor C7, a fifteenth resistor R15, and a sixteenth resistor R16.
One end of a fifteenth resistor R15 is connected to the output end of the fifth operational amplifier U5, the other end of the fifteenth resistor R15 is connected to the inverting input end of the fifth operational amplifier U5, and two ends of a sixth capacitor C6 are respectively connected to two ends of the fifteenth resistor R15.
One end of a sixteenth resistor R16 is connected to the inverting input end of the fifth op-amp U5, the other end of the sixteenth resistor R16 is connected to one pole of a seventh capacitor C7, and the other pole of the seventh capacitor C7 serves as the input end of the amplifying module 1231 and is connected to the output end of the mixing filtering branch.
The non-inverting input terminal of the fifth operational amplifier U5 is used for accessing the reference Voltage (VREF).
With continued reference to fig. 7, in an alternative embodiment, the comparison module 1232 includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty first resistor R21, a twenty second resistor R22, a sixth op-amp U6, and a ninth capacitor C9.
One end of the eighteenth resistor R18 is connected to the inverting input end of the sixth op-amp U6, and the other end of the eighteenth resistor R18 is used as the input end of the comparison module 1232 and is connected to the output end of the amplifying module 1231.
One end of the nineteenth resistor R19 is connected to the non-inverting input end of the sixth operational amplifier U6, and the other end of the nineteenth resistor R19 is used for accessing a reference Voltage (VREF).
One end of the twentieth resistor R20 is connected to the non-inverting input end of the sixth operational amplifier U6, and the other end of the twentieth resistor R20 is connected to the output end of the sixth operational amplifier U6.
One end of the twenty-first resistor R21 is connected to the output end of the sixth operational amplifier U6, and the other end of the twenty-first resistor R21 is connected to one end of the twenty-second resistor R22 and one pole of the ninth capacitor C9 together to serve as the output end of the comparison module 1232.
The other end of the twenty-second resistor R22 and the other end of the ninth capacitor C9 are grounded.
With continued reference to fig. 7, in an alternative embodiment, the phase demodulation circuit 120 further includes a seventeenth resistor R17 and an eighth capacitor C8, wherein two ends of the seventeenth resistor R17S are respectively connected to the output end of the amplifying module 1231 and the input end of the comparing module 1232, one pole of the eighth capacitor C8 is grounded, and the other pole of the eighth capacitor C8 is connected to the input end of the comparing module 1232.
In summary, the embodiment of the present application provides a phase demodulation circuit, a wireless power transmitting terminal and a wireless charging system, where the phase demodulation circuit includes: the signal processing module comprises two mixing filtering branches, namely a first mixing filtering branch and a second mixing filtering branch; the first capacitor is arranged between the coupling coil of the wireless power transmitting end and the inverter; the first end of the signal acquisition module is connected with the first pole of the first capacitor, the second end of the signal acquisition module is connected with the second pole of the first capacitor, and the output end of the signal acquisition module is respectively connected with the first input ends of the two frequency mixing filtering branches; the second input end of the first mixing filtering branch is used for being connected with a first reference clock signal, the second input end of the second mixing filtering branch is used for being connected with a second reference clock signal, and the phase difference between the first reference clock signal and the second reference clock signal is 90 degrees; the output ends of the two mixing filtering branches are used for being connected with a post-stage circuit. The stability of power transmission can be effectively enhanced, the product compatibility is improved, and the user experience is improved. The problem of power transmission interruption in the wireless charging process is solved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A phase demodulation circuit, characterized in that the phase demodulation circuit comprises: the device comprises a first capacitor, a signal acquisition module and a signal processing module, wherein the signal processing module comprises two mixing filtering branches, namely a first mixing filtering branch and a second mixing filtering branch;
the first capacitor is used for being arranged between the coupling coil of the wireless power transmitting end and the inverter;
the first end of the signal acquisition module is connected with the first pole of the first capacitor, the second end of the signal acquisition module is connected with the second pole of the first capacitor, and the output ends of the signal acquisition module are respectively connected with the first input ends of the two frequency mixing filtering branches;
the second input end of the first mixing filtering branch is used for being connected with a first reference clock signal, the second input end of the second mixing filtering branch is used for being connected with a second reference clock signal, and the phase difference between the first reference clock signal and the second reference clock signal is 90 degrees;
the output ends of the two frequency mixing filtering branches are used for being connected with a post-stage circuit.
2. The phase demodulation circuit as claimed in claim 1, wherein,
the signal acquisition module is used for acquiring voltage information between two poles of the first capacitor, generating corresponding primary signals and transmitting the primary signals to first input ends of the two frequency mixing filtering branches;
the first mixing filtering branch is used for carrying out mixing processing on the primary signal and the first reference clock signal to obtain a first mixing signal, and carrying out filtering processing on the first mixing signal to filter out fundamental frequency signals and harmonic signals in the first mixing signal to obtain a first demodulation signal;
the second mixing filtering branch is used for carrying out mixing processing on the primary signal and the second reference clock signal to obtain a second mixing signal, and carrying out filtering processing on the second mixing signal to filter out fundamental frequency signals and harmonic signals in the second mixing signal to obtain a second demodulation signal.
3. The phase demodulation circuit of claim 1, wherein the signal acquisition module comprises a second op-amp, a first resistor, a second resistor, a third resistor, a fourth resistor, and a second capacitor;
the first end of the first resistor is connected with the output end of the second operational amplifier, and the second end of the first resistor is connected with the inverting input end of the second operational amplifier;
one pole of the second capacitor is connected to the first end of the first resistor, and the second pole of the second capacitor is connected to the second end of the first resistor;
the first end of the second resistor is connected with the inverting input end of the second operational amplifier, and the first end of the third resistor is connected with the non-inverting input end of the second operational amplifier;
the first end of the fourth resistor is connected with the non-inverting input end of the second operational amplifier, and the second end of the fourth resistor is used for accessing reference voltage;
the second end of the second resistor is used as the second end of the signal acquisition module and is connected with the second pole of the first capacitor;
the second end of the third resistor is used as the first end of the signal acquisition module and is connected to the first pole of the first capacitor.
4. The phase demodulation circuit of claim 3 wherein the signal acquisition module further comprises a first comparator and a fifteenth capacitor;
one end of the fifteenth capacitor is connected with the output end of the second operational amplifier, and the other end of the fifteenth capacitor is connected with the inverting input end of the first comparator;
an inverting input terminal of the first comparator is connected with a common mode bias based on a reference voltage;
the non-inverting input end of the first comparator is used for accessing reference voltage;
the output end of the first comparator is used as the output end of the signal acquisition module.
5. The phase demodulation circuit of claim 4 wherein the mixing filter branch comprises a logic gate and a filter unit;
the first end of the logic gate is used as a first input end of the frequency mixing filtering branch, the second end of the logic gate is used as a second input end of the frequency mixing filtering branch and is used for being connected with a first reference clock signal or a second reference clock signal, the third end of the logic gate is connected with the input end of the filtering unit, and the output end of the filtering unit is used as an output end of the frequency mixing filtering branch and is used for being connected with a later-stage circuit;
the logic gate is used for carrying out frequency mixing according to the received reference clock signal and the first-order signal received by the first end so as to obtain a frequency mixing signal, and transmitting the frequency mixing signal to the filtering unit;
the filtering unit is used for filtering the received signals and filtering out fundamental frequency signals and harmonic signals.
6. The phase demodulation circuit of claim 1 wherein the mixing filter branch comprises a first transmission gate, a second transmission gate, an analog switch, and a filter unit;
a first connecting terminal is led out from the connection part of the input end of the first transmission gate and the input end of the second transmission gate and is used as the first input end of the frequency mixing filtering branch;
the output end of the first transmission gate is connected with the first end of the analog switch, the output end of the second transmission gate is connected with the second end of the analog switch, the output end of the analog switch is connected with the input end of the filtering unit, and the output end of the filtering unit is used as the output end of the mixing filtering branch and is used for being connected with a post-stage circuit;
the control end of the analog switch is used as a second input end of the mixing filtering branch and is used for accessing the first reference clock signal or the second reference clock signal;
the first transmission gate is used for transmitting the received signal to the analog switch;
the second transmission gate is used for inverting the received signal and transmitting the inverted signal to the analog switch;
the analog switch is used for switching the conduction relation among the first end, the second end and the output end in the analog switch according to the received reference clock signal;
and the filtering unit is used for filtering the received signals and filtering out fundamental frequency signals and harmonic signals.
7. The phase demodulation circuit as claimed in claim 6, wherein the first transmission gate includes a fifth resistor, one end of the fifth resistor being an input terminal of the first transmission gate, and the other end of the fifth resistor being an output terminal of the first transmission gate;
and/or the second transmission gate comprises a third capacitor, a fourth capacitor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a third operational amplifier;
the first end of the sixth resistor is connected with the output end of the third operational amplifier, the second end of the sixth resistor is connected with the inverting input end of the third operational amplifier, one pole of the third capacitor is connected with the first end of the sixth resistor, and the other pole of the third capacitor is connected with the second end of the sixth resistor;
the first end of the seventh resistor is connected to the inverting input end of the third operational amplifier, the second end of the seventh resistor is connected to one pole of the fourth capacitor, and the other pole of the fourth capacitor is used as the input end of the second transmission gate;
one end of the eighth resistor is connected to the output end of the third operational amplifier, and the other end of the eighth resistor is used as the output end of the second transmission gate;
one end of the ninth resistor is connected to the non-inverting input end of the third operational amplifier, and the other end of the ninth resistor is used for being connected with a reference voltage.
8. The phase demodulation circuit of claim 7 wherein the analog switch includes a first subunit, a second subunit, a tenth resistor, an eleventh resistor, a twelfth resistor, and a thirteenth resistor;
the first end of the first subunit is used as the first end of the analog switch and is connected with the output end of the first transmission gate;
the first end of the second subunit is used as a second end of the analog switch and is connected with the output end of the second transmission gate;
a second wiring terminal is led out from the connection part of the second end of the first subunit and the second end of the second subunit and is used as the output end of the analog switch;
one end of the tenth resistor is connected to the control end of the first subunit, one end of the eleventh resistor is grounded, the other end of the eleventh resistor is connected to the other end of the tenth resistor, and a third connecting terminal is led out from the joint of the tenth resistor and the eleventh resistor;
one end of the twelfth resistor is connected to the control end of the second subunit, one end of the thirteenth resistor is grounded, the other end of the thirteenth resistor is connected to the other end of the twelfth resistor, and a fourth connecting terminal is led out from the joint of the thirteenth resistor and the twelfth resistor;
the third connecting terminal and the fourth connecting terminal are used as a control end of the analog switch together.
9. A wireless power transmitting terminal, characterized in that the wireless power transmitting terminal comprises the phase demodulation circuit of any one of claims 1-8.
10. A wireless charging system comprising the wireless power transmitting end of claim 9.
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