CN117524985A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117524985A
CN117524985A CN202210900981.XA CN202210900981A CN117524985A CN 117524985 A CN117524985 A CN 117524985A CN 202210900981 A CN202210900981 A CN 202210900981A CN 117524985 A CN117524985 A CN 117524985A
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China
Prior art keywords
side wall
forming
region
core layer
layer
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CN202210900981.XA
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Chinese (zh)
Inventor
苏柏青
王俊
郁扬
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210900981.XA priority Critical patent/CN117524985A/en
Publication of CN117524985A publication Critical patent/CN117524985A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate comprising a first region for forming a first type device; the substrate comprises a target layer for forming a target pattern, wherein the target layer of the first area comprises a plurality of first preset areas and second preset areas positioned among the first preset areas; forming a discrete core layer on a substrate, wherein in a first region, the line width of the core layer positioned in a first preset region is the same as that of the core layer positioned in a second preset region; forming a first side wall on the side wall of the core layer; removing the core layer; forming a second side wall on the side wall of the first side wall, wherein the second side wall positioned on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall; removing the first side wall; removing the sacrificial side wall, and using the remaining second side wall as a mask side wall; and using the mask side wall as a mask, and patterning the target layer to form a plurality of target patterns. The embodiment of the invention improves the degree of freedom and flexibility of the patterning.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the continued shrinking of feature sizes (Critical Dimension, CD), self-aligned quad patterning (Self-Aligned Quadruple Patterning, SAQP) methods have evolved.
The density of the patterns formed on the substrate by the self-aligned double patterning method is twice that of the patterns formed on the substrate by utilizing the photoetching process, namely, the 1/2 minimum pitch (1/2 pitch) can be obtained, while the density of the patterns formed on the substrate by the self-aligned quadruple patterning method is four times that of the patterns formed on the substrate by utilizing the photoetching process on the premise of not changing the current photoetching technology (namely, the size of a photoetching window is unchanged), namely, the 1/4 minimum pitch (1/4 pitch) can be obtained, thereby greatly improving the density of a semiconductor integrated circuit, reducing the feature size of the patterns and further being beneficial to improving the performance of devices.
However, the degree of freedom and flexibility of patterning are still to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which improves the degree of freedom and flexibility of patterning.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region for forming a first type device; the substrate comprises a target layer for forming a target pattern, wherein the target layer of the first area comprises a plurality of first preset areas and second preset areas positioned between the first preset areas; forming a discrete core layer on the substrate, wherein in the first region, the line width of the core layer positioned in the first preset region is the same as the line width of the core layer positioned in the second preset region; forming a first side wall on the side wall of the core layer; removing the core layer; forming a second side wall on the side wall of the first side wall, wherein the second side wall positioned on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall; removing the first side wall; removing the sacrificial side wall, and using the remaining second side wall as a mask side wall; and patterning the target layer by taking the mask side wall as a mask to form a plurality of target patterns.
Optionally, in the step of forming the core layer, in the first region, a space between the core layer located in the first preset region and the core layer located on a second preset region adjacent to the first preset region is larger than a line width of the core layer.
Optionally, the substrate further comprises a second region for forming a second type device; the target layer of the second region comprises a plurality of third preset regions and a fourth preset region positioned between the third regions; in the step of forming the core layer, in the second region, a line width of the core layer located in the third preset region is larger than a line width of the core layer located in the fourth preset region.
Optionally, in the step of forming the core layer, in the second region, a space between the core layer located in the third preset region and the core layer on a fourth preset region adjacent to the third preset region is the same as a line width of the core layer of the fourth preset region.
Optionally, the target layer is a dielectric layer; the mask side wall is used as a mask, the target layer is patterned, and the step of forming a plurality of target patterns comprises the following steps: and patterning the dielectric layer by taking the mask side wall as a mask to form a plurality of dielectric interlayer, and enclosing a groove between the adjacent dielectric interlayer.
Optionally, the first preset area is a power supply area of the first type device, and the second preset area is a standard cell area.
Optionally, the first type device comprises a high performance computational logic device.
Optionally, the method for forming the semiconductor structure further includes: and filling conductive materials in the grooves.
Optionally, the operation speed of the second type device is lower than the operation speed of the first type device.
Optionally, the second type device is a low voltage logic device.
Optionally, after removing the first side wall, removing the sacrificial side wall.
Optionally, the process of removing the sacrificial sidewall includes an isotropic process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming a core layer, in the first region, the line width of the core layer located in the first preset region is the same as the line width of the core layer located in the second preset region; in the step of forming the second side wall, the second side wall located on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall, then the sacrificial side wall is removed, the remaining second side wall is used as a mask side wall, correspondingly, the interval between the mask side walls of the first preset area is larger than the interval between the mask side walls of the second preset area, after the mask side walls are used as masks for patterning the target layer, after a plurality of target patterns are formed, the interval between the target patterns located in the first preset area is larger than the interval between the target patterns located in the second preset area, so that different types of target pattern intervals can be obtained in the first area, and the degree of freedom and flexibility of patterning are improved.
Drawings
Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIG. 8 is a schematic illustration of a process in an embodiment of a method of forming a semiconductor structure in accordance with the present invention;
fig. 9 to 17 are schematic cross-sectional views illustrating steps corresponding to the method of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the degree of freedom and flexibility of patterning are still to be improved. The method for forming the semiconductor structure is combined, and the reasons that the degree of freedom and flexibility of the current patterning are still to be improved are analyzed.
Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a layer 1 to be etched is provided; a discrete core layer 2 is formed on the layer 1 to be etched.
Referring to fig. 2, a first sidewall 3 is formed on the sidewall of the core layer 2.
Referring to fig. 3, the core layer 2 is removed.
Referring to fig. 4 to 5, a second sidewall 4 is formed on the sidewall of the first sidewall 3.
Referring to fig. 6, after the second sidewall 4 is formed, the first sidewall 3 is removed, and the first sidewall 3 is used as an etching mask for patterning the layer 1 to be etched.
Referring to fig. 7, the second sidewall 4 is used as a mask to pattern the layer 1 to be etched, a target pattern 5 is formed in the layer 1 to be etched, and a trench 6 is defined between adjacent target patterns 5.
In the above forming method, the target patterns 5 are generally formed in the substrate 1 to have the same Critical Dimension (CD), and the spaces (spaces) 6 between the target patterns 5 are also the same, so that it is difficult to form the target patterns 5 having different critical dimensions and spaces, resulting in low degree of freedom and flexibility of patterning.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region for forming a first type device; the substrate comprises a target layer for forming a target pattern, wherein the target layer of the first area comprises a plurality of first preset areas and second preset areas positioned between the first preset areas; forming a discrete core layer on the substrate, wherein in the first region, the line width of the core layer positioned in the first preset region is the same as the line width of the core layer positioned in the second preset region; forming a first side wall on the side wall of the core layer; removing the core layer; forming a second side wall on the side wall of the first side wall, wherein the second side wall positioned on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall; removing the first side wall; removing the sacrificial side wall, and using the remaining second side wall as a mask side wall; and patterning the target layer by taking the mask side wall as a mask to form a plurality of target patterns.
In the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming a core layer, in the first region, the line width of the core layer located in the first preset region is the same as the line width of the core layer located in the second preset region; in the step of forming the second side wall, the second side wall located on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall, then the sacrificial side wall is removed, the remaining second side wall is used as a mask side wall, correspondingly, the interval between the mask side walls of the first preset area is larger than the interval between the mask side walls of the second preset area, after the mask side walls are used as masks for patterning the target layer, after a plurality of target patterns are formed, the interval between the target patterns located in the first preset area is larger than the interval between the target patterns located in the second preset area, so that different types of target pattern intervals can be obtained in the first area, and the degree of freedom and flexibility of patterning are improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
FIG. 8 is a schematic illustration of a process in an embodiment of a method of forming a semiconductor structure in accordance with the present invention; fig. 9 to 17 are schematic cross-sectional views illustrating steps corresponding to the method of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 8 and 9, a substrate is provided including a first region I for forming a first type device; the substrate includes a target layer 100 for forming a target pattern, and the target layer of the first region I includes a plurality of first preset regions I (a) and second preset regions I (B) located between the first preset regions I (a).
The target layer 100 is a film layer to be patterned to form a target pattern.
As one example, the target layer 100 is a dielectric layer; the target pattern is a dielectric spacer.
Specifically, after the dielectric layers are patterned subsequently to form dielectric spacers, a trench is defined between adjacent dielectric spacers, the trench is used to provide a spatial location for filling the conductive material, and the dielectric spacers are correspondingly used to realize isolation between adjacent conductive materials.
Accordingly, the dielectric layer is made of an insulating dielectric material and includes one or more of a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride and silicon oxynitride.
Accordingly, in the present embodiment, various semiconductor devices may be formed in the substrate, for example: a MOS transistor.
In other embodiments, the target layer may be other layers and the target pattern may be of other types based on actual process requirements.
As an example, the first preset area I (a) is a power supply area of the first type device, and a space between dielectric spacers of the power supply area is used to form a power rail (power rail); the second preset area I (B) is a Standard cell (Standard cell) region of the first type device, and a space between dielectric spacers of the Standard cell region is used for forming an interconnection layer.
Wherein the power rail is used for accessing VDD or VSS.
Referring to fig. 8 in combination, in this embodiment, the substrate further includes a second region II for forming a second type device; the target layer 100 of the second region II includes a plurality of third preset regions II (a) and fourth preset regions II (B) located between the third regions II (a).
As an example, in the second region II, the third preset region II (a) is a power supply region of the second type device, and the fourth preset region II (B) is a standard cell region of the second type device.
As an example, the first region I is used to form a first type device and the second region II is used to form a second type device, which operates at a lower speed than the first type device. The operation speeds of the first type device and the second type device are different, and the performances are also different, so that target patterns with different intervals can be formed in the first area I and the second area II based on the requirements of the different performance devices.
As one example, the first type of device is a high performance computing (High Performance Computing, HPC) logic device and the second type of device is a Low voltage (Low power) logic device. Compared to LP logic devices, HPC logic devices have the ability to process data at high speed and perform complex calculations, thus placing higher demands on device performance. In other embodiments, the first type device and the second type device may also be other different types of devices based on actual process requirements.
With continued reference to fig. 8 and 9, a discrete core layer 110 is formed on the substrate, and in the first region I, the line width of the core layer 110 located in the first preset region I (a) is the same as the line width of the core layer 110 located in the second preset region I (B).
The core layer 110 is used to provide support for the subsequent formation of the first sidewall.
The core layer 110 is also subsequently removed, and thus the core layer 110 is a material that is easy to remove. The material of the core layer 110 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the core layer 110 is amorphous silicon.
In this embodiment, the core layers 110 are arranged along the Y direction.
In this embodiment, in the step of forming the core layer 110, in the first region I, a space S1 between the core layer 110 located in the first preset region I (a) and the core layer 110 located in a second preset region I (B) adjacent to the first preset region I (a) is larger than a line width W1 of the core layer 110.
Therefore, the first side wall is formed on the side wall of the core layer 110, the core layer 110 and the first side wall located on the side wall of the core layer 110 form a graphic unit, the first side wall located on the same side wall of the core layer 110 forms a side wall group, in the first region I, the interval between the graphic unit of the first preset region I (a) and the graphic unit on the second preset region I (B) adjacent to the first preset region I (a) is larger than the interval between the adjacent first side walls in the graphic unit, then the second side wall is formed on the side wall of the first side wall, in the second preset region I (B), the interval between the second side walls close to the first preset region I (a) is larger than the interval between the second side walls far away from the first preset region I (a), and correspondingly, different types of target graphic intervals are realized in the second preset region I (B), so that the flexibility and the freedom degree of the target graphic interval design are further improved.
In this embodiment, in the step of forming the core layer 110, in the second region II, the line width of the core layer 110 located in the third preset region II (a) is greater than the line width of the core layer 110 located in the fourth preset region II (B). Therefore, after the first side wall is formed on the side wall of the core layer 110, the core layer is removed, and the second side wall is formed on the side wall of the first side wall, in the second region II, the interval between the second side walls of the third preset region II (a) is larger than the interval between the second side walls of the fourth preset region II (B), and further, after the target layer 100 is patterned by using the mask side wall as a mask to form a target pattern, in the second region II, the interval between the target patterns of the third preset region II (a) is larger than the interval between the target patterns of the fourth preset region II (B), so that different types of target pattern intervals are correspondingly realized in the second region II, and the flexibility and the freedom of the target pattern interval design are further improved.
More specifically, in the present embodiment, the target layer 100 is a dielectric layer; the target pattern is a dielectric interlayer; the third preset area II (A) is a power supply area of the second type device, and the interval between dielectric interlayer of the power supply area is used for forming a power supply rail; the fourth preset region II (B) is a standard cell region of the second type device, and the space between the dielectric spacers of the second type device is used to form an interconnect layer.
Correspondingly, after the conductive material is filled in the interval between the dielectric interlayer, in the second area II, the line width of the power rail is larger than that of the interconnection layer, so that the volume of the power rail is increased, the resistance and the power supply resistance of the power rail are reduced, and the voltage drop (IR drop) is correspondingly improved.
As an embodiment, in the step of forming the core layer 110, in the second region II, a space between the core layer 110 located in the third preset region II (a) and the core layer 110 on the fourth preset region II (B) adjacent to the third preset region II (a) is the same as a line width of the core layer 110 of the fourth preset region II (B). Therefore, after the first side wall is formed on the side wall of the core layer 110, the core layer is removed, and the second side wall is formed on the side wall of the first side wall, the interval between the second side walls is the same in the fourth preset area II (B), and after the mask side wall is used as a mask, the target layer is patterned to form the target pattern, the uniform target pattern interval can be obtained in the fourth preset area II (B).
It should be noted that, in the present embodiment, after the substrate is provided and before the core layer 110 is formed, the method for forming a semiconductor structure further includes: an adhesion layer 101, a hard mask layer 102, and an etch stop layer 103 are sequentially formed on a substrate.
The adhesion layer 101 is used to improve adhesion between the hard mask layer 102 and the target layer 100, thereby improving the accuracy of pattern transfer. As an example, the material of the adhesion layer 101 is silicon oxide.
The pattern of the second side wall is transferred to the hard mask layer 102, so that the hard mask layer 102 can be used as an etching mask for etching the target layer 100, and although the second side wall is consumed in the process of patterning the target layer 100, the process of patterning the target layer 100 by using the hard mask layer 102 as a mask can be continued, and further, the stability of a patterning process and the accuracy of pattern transfer are improved.
The material of the hard mask layer 102 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the hard mask layer 102 is silicon nitride.
The etching stop layer 103 is used for defining an etching stop position in the steps of forming the core layer 110, the first side wall, removing the core layer 110, thinning the side wall of the first side wall, and forming the second side wall, so as to improve the stability and the pattern transfer precision of the subsequent patterned target layer 100.
The material of the etch stop layer 103 includes silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. In this embodiment, the material of the etching stop layer 103 is silicon oxide.
In the present embodiment, only the cross-sectional configuration of the first region I is shown for simplicity of explanation.
Referring to fig. 8 and 10 in combination, a first sidewall 120 is formed on the sidewall of the core layer 110.
The first sidewall 120 is used to provide support for the subsequent formation of the second sidewall.
The first sidewall 120 is made of a material having etching selectivity with the core layer 110. In this embodiment, the material of the first sidewall 120 includes silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride or titanium oxide.
In this embodiment, the core layer 110 and the first sidewall 120 located on the sidewall of the core layer 110 form a graphic unit C, the first sidewall 120 located on the same sidewall of the core layer 110 forms a sidewall group D, and in the first area I, a space S2 between the graphic unit of the first preset area I (a) and the graphic unit C on the second preset area I (B) adjacent to the first preset area I (a) is greater than a space W1 between adjacent first sidewalls 120 in the sidewall group D in the graphic unit C.
In this embodiment, the step of forming the first sidewall 120 includes: forming a first sidewall material layer (not shown) on top of and sidewalls of the core layers 110 and on top of the substrate between the core layers 110; the first sidewall material layer on top of the core layers 110 and on top of the substrate between the core layers 110 is removed, and the remaining first sidewall material layer on the sidewalls of the core layers 110 is used as the first sidewall 120.
As one example, the first sidewall material layer is formed using an atomic layer deposition process.
As an example, the first sidewall material layer on top of the core layers 110 and on top of the substrate between the core layers 110 is removed using an anisotropic dry etching process.
Referring to fig. 11, the core layer 120 is removed.
The core layer 110 is removed to expose all sidewalls of the first sidewall 120, so that a second sidewall is formed on the sidewalls of the first sidewall 120.
Referring to fig. 8 and 12 in combination, a second sidewall 130 is formed on a sidewall of the first sidewall 120, and the second sidewall 130 located on an opposite sidewall of the adjacent first sidewall 120 of the first preset region I (a) is used as a sacrificial sidewall 130a.
After the first sidewall 120 and the sacrificial sidewall 130a are removed, the remaining second sidewall 130 is used as a mask sidewall to serve as a mask for patterning the target layer 100.
The sacrificial side wall 130a is removed later, so that a larger interval is realized between mask side walls of the first preset area I (a) in the first area I, and further, different types of target pattern intervals can be obtained in the first area I, which is beneficial to improving the degree of freedom and flexibility of target interval design.
The second sidewall 130 is made of a material having etching selectivity with the first sidewall 120, so as to reduce the difficulty of removing the first sidewall 120 subsequently. The material of the second sidewall 130 includes silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride or amorphous silicon. In this embodiment, the material of the second sidewall 130 is amorphous silicon.
As an embodiment, in the step of forming the core layer 110, in the second region II, a space between the core layer 110 located in the third preset region II (a) and the core layer 110 on the fourth preset region II (B) adjacent to the third preset region II (a) is the same as a line width of the core layer 110 of the fourth preset region II (B). Accordingly, after forming the second sidewall on the sidewall of the first sidewall 120, in the fourth preset area II (B), the intervals between the second sidewalls 130 are the same, and after patterning the target layer 100 with the mask sidewall as a mask to form a target pattern, a consistent target pattern interval can be obtained in the fourth preset area II (B).
Referring to fig. 13, the first side wall 120 is removed. The first sidewall 120 is removed to expose the substrate under the first sidewall 120, so that the target layer 100 is patterned with the second sidewall 130 as a mask.
Referring to fig. 8 and 14 in combination, the sacrificial sidewall 130a is removed, and the remaining second sidewall 130 is used as a mask sidewall 180.
Mask sidewall 180 is used as an etch mask for patterning target layer 100.
In this embodiment, in the step of forming the core layer 110, in the first region I, the line width of the core layer 110 located in the first preset region I (a) is the same as the line width of the core layer 110 located in the second preset region I (B); the second sidewall 130 located on the opposite sidewall of the adjacent first sidewall 120 of the first preset area I (a) is used as a sacrificial sidewall 130a, then the sacrificial sidewall 130a is removed, the remaining second sidewall 130 is used as a mask sidewall, and correspondingly, the interval between the mask sidewalls of the first preset area I (a) is larger than the interval between the mask sidewalls of the second preset area I (B).
Correspondingly, after the mask side wall is used as a mask for patterning the target layer 100 to form a plurality of target patterns, the interval between the target patterns in the first preset area I (A) is larger than the interval between the target patterns in the second preset area I (B), so that different types of target pattern intervals can be obtained in the first area I, and the degree of freedom and flexibility of patterning are improved.
As one embodiment, the target layer 100 is a dielectric layer; the target pattern is a dielectric interlayer; the first preset area I (A) is a power supply area of the first type device, and the interval between dielectric interlayer of the power supply area is used for forming a power supply rail; the second preset region I (B) is a standard cell region of the first type device, and the space between the dielectric spacers of the first type device is used to form an interconnect layer.
Correspondingly, after the conductive material is filled in the interval between the dielectric interlayer, the line width of the power rail is larger than that of the interconnection layer in the first area I, so that the volume of the power rail is increased, the resistance and the power supply resistance of the power rail are reduced, and the voltage drop (IR drop) is correspondingly improved.
In this embodiment, the step of removing the sacrificial sidewall 130a includes: forming a cover layer 125 on the substrate, covering the remaining second side walls 130 except the sacrificial side walls 130a in the first region I and covering the second region II, wherein the cover layer 125 exposes the sacrificial side walls 130a; sacrificial sidewall 130a is removed using cap layer 125 as a mask.
Mask layer 125 is used as an etch mask for removing sacrificial sidewall 130a.
Specifically, the material of the mask layer 125 may include spin-on carbon, an organic dielectric layer, and the like.
In this embodiment, the process of removing the sacrificial sidewall 130a includes an isotropic process. The isotropic etching process has the characteristic of isotropic etching, and can etch the sacrificial sidewall 130a along the direction parallel to the substrate and the direction perpendicular to the substrate, so that the sacrificial sidewall 130a can be removed cleanly.
In particular embodiments, the isotropic etching process may include one or both of an isotropic dry etching and a wet etching process.
In this embodiment, after the first sidewall 120 is removed, the sacrificial sidewall 130a is removed, so that the sidewalls of the sacrificial sidewall 130a can be exposed, so that the sacrificial sidewall 130a can be removed cleanly. In other embodiments, the sacrificial sidewall may also be removed prior to removing the first sidewall.
Referring to fig. 15, the forming method further includes: after the sacrificial sidewall 130a is removed, the mask layer 125 is removed to expose the first region I and the second region II, and then the target layer 100 is patterned using the mask sidewall 180 as a mask.
Specifically, the mask layer 125 may be removed using one or both of ashing and wet photoresist removal.
Referring to fig. 8 and 16 in combination, the target layer 100 is patterned with the mask sidewall 180 as a mask, so as to form a plurality of target patterns 140.
In this embodiment, in the step of forming the core layer 110, in the first region I, the line width of the core layer 110 located in the first preset region I (a) is the same as the line width of the core layer 110 located in the second preset region I (B); in the step of forming the second sidewall 130, the second sidewall 130 located on the opposite sidewall of the adjacent first sidewall 120 of the first preset area I (a) is used as a sacrificial sidewall 130a, then the sacrificial sidewall 130a is removed, and the remaining second sidewall 130 is used as a mask sidewall 180, and accordingly, the interval between the mask sidewalls 180 located in the first preset area I (a) is greater than the interval between the mask sidewalls 180 located in the second preset area I (B).
Therefore, after the mask spacers 180 are used as masks to pattern the target layer 100 to form a plurality of target patterns 100, the intervals between the target patterns 140 in the first preset area I (a) are larger than the intervals between the target patterns 140 in the second preset area I (B), so that different types of target pattern 140 intervals can be obtained in the first area I, and the degree of freedom and flexibility of patterning are improved.
In this embodiment, in the second preset area I (B) of the first area I, the interval between the target patterns 140 close to the first preset area I (a) is larger than the interval between the target patterns far from the first preset area I (a), so that the second preset area I (B) of the first area I can have different types of target pattern intervals, thereby further improving the flexibility and the degree of freedom of the interval design between the target patterns 140.
In this embodiment, in the second area II, the interval between the target patterns 140 in the third preset area II (a) is greater than the interval between the target patterns 140 in the fourth preset area II (B), so that different types of target pattern 140 intervals can be realized in different areas in the second area II based on the process requirement, and the degree of freedom and flexibility of the design of the target pattern 140 intervals are further improved.
In the present embodiment, in the fourth preset area II (B) of the second area II, the intervals between the target patterns 140 are the same.
In this embodiment, the target layer 100 is a dielectric layer; the step of patterning the target layer 100 with the mask sidewall 180 as a mask includes: and patterning the dielectric layer by taking the mask side wall 180 as a mask to form a plurality of dielectric spacers, wherein grooves are formed between adjacent dielectric spacers.
In the first area I, the trench located in the first preset area I (a) is used as the first trench 201, and the trench located in the second preset area I (B) is used as the second trench 202, and accordingly, the opening width of the first trench 201 is larger than the opening width of the second trench 202 along the width direction of the trench (as shown in the Y direction in fig. 8).
In this embodiment, in the second area II, the groove located in the third preset area II (a) is used as a third groove (not shown), and the groove located in the fourth preset area II (B) is used as a fourth groove (not shown), and accordingly, the opening width of the third groove is greater than the opening width of the fourth groove along the width direction of the groove.
More specifically, in the present embodiment, the target layer 100 is a dielectric layer; the target pattern 140 is a dielectric spacer; the first preset area I (A) is a power supply area, and the intervals between dielectric interlayer of the power supply area are used for forming a power supply rail; the second preset area I (B) is a standard cell area, and the interval between dielectric interlayer of the second preset area I (B) is used for forming an interconnection layer.
Correspondingly, after the conductive material is filled in the groove, the line width of the power rail is larger than that of the interconnection layer in the first area I or the second area II, so that the volume of the power rail is increased, the resistance and the power supply resistance of the power rail are reduced, and the voltage drop (IR drop) is correspondingly improved.
Note that, in the present embodiment, in the first preset region I, the core layer 110 is formed only on the first power supply region P1, but not on the second power supply region P2. Therefore, by reasonably setting the distance between the adjacent core layers 110 in the standard cell group, the adjacent dielectric spacers can enclose the second trench 202 with a larger opening width in the second power supply region P2 after forming the dielectric spacers.
In addition, in the second preset region I (B) of the first region I, the second trench 202 has different types of opening widths; in the fourth preset region II (B) of the second region II, the opening width of the second trench 202 is the same.
In this embodiment, in the fourth preset area II (B) of the second area II, the intervals between the adjacent target patterns 140 are all the same, so as to achieve uniform target pattern intervals.
More specifically, in this embodiment, in the second preset area I (B) of the first area I, the interval between the target patterns 140 close to the first preset area I (a) is larger than the interval between the target patterns 140 far from the first preset area I (a), so that the second preset area I (B) of the first area I can have different types of target pattern 140 intervals, and the flexibility and the degree of freedom of the interval design between the target patterns 140 are further improved.
In this embodiment, the interval between the target patterns 140 in the second preset area I (B) of the first area I, which is far from the first preset area I (a), is the same as the interval between the adjacent target patterns 140 in the fourth preset area II (B) of the second area II. That is, the interval between the target patterns 140 in the second preset region I (B) of the first region I, which is close to the first preset region I (a), is greater than the interval between the adjacent target patterns 140 in the fourth preset region II (B) of the second region II.
Specifically, in this embodiment, the mask sidewall 180 is used as a mask to sequentially etch the etching stop layer 103, the hard mask layer 102, the adhesion layer 101, and the target layer 100.
As an example, the target layer 100 is patterned using an anisotropic dry etching process with the mask sidewall 180 as a mask to form the plurality of target patterns 140. The anisotropic dry etching process has the characteristic of anisotropic etching, and is beneficial to improving the accuracy of pattern transfer.
In this embodiment, for convenience of illustration and description, a mask sidewall 180 with a residual partial thickness is also illustrated in fig. 16 as an example.
In other embodiments, the mask sidewall 180 may be completely consumed during the process of patterning the target layer 100, and the hard mask layer 102 may be used as an etching mask for patterning the target layer.
Referring to fig. 8 and 17 in combination, in this embodiment, the method for forming a semiconductor structure further includes: the trench is filled with a conductive material.
In this embodiment, the trenches are filled with a conductive material, and in a first region I, a first power rail 150 is formed in the first trench 201, and a first interconnect layer 160 is formed in the second trench 202; the trenches are filled with a conductive material and in the second region II, a second power rail 170 is formed in the third trench and a second interconnect layer 190 is formed in the fourth trench.
The first power rail 150 is used to power a first type of device and the second power rail 170 is used to power a second type of device. The first interconnect layer 160 and the second interconnect layer 190 are used to make electrical connections between devices or between different components in a device to meet circuit design requirements.
In this embodiment, the line width of the first power rail 150 is larger than the line width of the first interconnection layer 160, the first power rail 150 is used for supplying power to the first device, and the wider first power rail 150 is beneficial to increasing the volume of the first power rail 150, so that the resistance of the first power rail 150 is reduced, the power supply resistance is correspondingly reduced, and the power supply efficiency of the device is improved and the voltage drop (IR drop) is improved.
In this embodiment, the line width of the second power rail 170 is larger than the line width of the second interconnection layer 190, the second power rail 170 is used for supplying power to the second device, and the wider second power rail 170 is beneficial to increasing the volume of the second power rail 170, so that the resistance of the second power rail 170 is reduced, the power supply resistance is correspondingly reduced, and the power supply efficiency of the device is improved and the voltage drop (IR drop) is improved.
In this embodiment, the first power rail 150, the first interconnect layer 160, the second power rail 170, and the second interconnect layer 190 all extend in the X direction.
Specifically, the materials of the first power rail 150, the first interconnect layer 160, the second power rail 170, and the second interconnect layer 190 are the same. The materials of the first power rail 150, the first interconnect layer 160, the second power rail 170, and the second interconnect layer 190 are all conductive materials, such as: copper, cobalt, etc.
In this embodiment, the method for forming a semiconductor structure generally further includes: forming a first conductive plug (not shown) on top of the first interconnect layer 160 to contact the first interconnect layer 160; a second conductive plug is formed on top of the second interconnect layer 190 in contact with the second interconnect layer 190.
The first conductive plugs are used to make electrical connection between the first interconnect layer 160 and an external circuit or other interconnect structure. The second conductive plugs are used to make electrical connection between the second interconnect layer 190 and an external circuit or other interconnect structure.
In this embodiment, in the second preset region I (B) of the first region I, the second trench 202 has different opening widths, that is, the opening width of a portion of the second trench 202 is larger, which is beneficial to increasing the line width of the first interconnection layer 160, further beneficial to increasing the contact area between the first conductive plug and the first interconnection layer 160, reducing the contact resistance between the first conductive plug and the first interconnection layer 160, and improving the back-end RC delay.
Specifically, in this embodiment, the interval between the target patterns 140 in the second preset area I (B) of the first area I, which is close to the first preset area, is greater than the interval between the adjacent target patterns 140 in the fourth preset area II (B) of the second area II. That is, compared to the line width of the interconnect layer 160 of the second region II, the line width of a portion of the first interconnect layer 160 in the first region I is larger, which is advantageous to increase the line width of the first interconnect layer 160 of the first region I, thereby being advantageous to increase the contact area between the first conductive plug and the first interconnect layer 160, reduce the contact resistance between the first conductive plug and the first interconnect layer 160, and improve the back-end RC delay.
More specifically, in the present embodiment, the first region I is used to form a high-performance computing logic device, which is advantageous to significantly improve the problems of RC delay and electromigration (Electro migration) in the back-end of the high-performance computing logic device by increasing the line width of the first interconnect layer 160 of the high-performance computing logic device, thereby improving the performance of the high-performance computing logic device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region for forming a first type device; the substrate comprises a target layer for forming a target pattern, wherein the target layer of the first area comprises a plurality of first preset areas and second preset areas positioned between the first preset areas;
forming a discrete core layer on the substrate, wherein in the first region, the line width of the core layer positioned in the first preset region is the same as the line width of the core layer positioned in the second preset region;
forming a first side wall on the side wall of the core layer;
removing the core layer;
forming a second side wall on the side wall of the first side wall, wherein the second side wall positioned on the opposite side wall of the adjacent first side wall of the first preset area is used as a sacrificial side wall;
removing the first side wall;
removing the sacrificial side wall, and using the remaining second side wall as a mask side wall;
and patterning the target layer by taking the mask side wall as a mask to form a plurality of target patterns.
2. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the core layer, a space between the core layer located in the first predetermined region and the core layer on a second predetermined region adjacent to the first predetermined region is larger than a line width of the core layer in the first region.
3. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises a second region for forming a second type device; the target layer of the second region comprises a plurality of third preset regions and a fourth preset region positioned between the third regions;
in the step of forming the core layer, in the second region, a line width of the core layer located in the third preset region is larger than a line width of the core layer located in the fourth preset region.
4. The method of forming a semiconductor structure according to claim 3, wherein in the step of forming the core layer, a space between the core layer located in the third predetermined region and the core layer on a fourth predetermined region adjacent to the third predetermined region in the second region is the same as a line width of the core layer of the fourth predetermined region.
5. The method of forming a semiconductor structure as claimed in any one of claims 1 to 4, wherein the target layer is a dielectric layer;
the mask side wall is used as a mask, the target layer is patterned, and the step of forming a plurality of target patterns comprises the following steps: and patterning the dielectric layer by taking the mask side wall as a mask to form a plurality of dielectric interlayer, and enclosing a groove between the adjacent dielectric interlayer.
6. The method of claim 5, wherein the first predetermined region is a power supply region of a first device type and the second predetermined region is a standard cell region.
7. The method of forming a semiconductor structure of claim 6, wherein the first type device comprises a high performance computational logic device.
8. The method of forming a semiconductor structure of claim 5, further comprising: and filling conductive materials in the grooves.
9. The method of forming a semiconductor structure according to claim 3 or 4, wherein an operation speed of the second type device is lower than an operation speed of the first type device.
10. The method of forming a semiconductor structure of claim 9, wherein said second type device is a low voltage logic device.
11. The method of forming a semiconductor structure of claim 1, wherein the sacrificial sidewall is removed after the first sidewall is removed.
12. The method of forming a semiconductor structure of claim 1, wherein removing said sacrificial sidewall comprises an isotropic process.
CN202210900981.XA 2022-07-28 2022-07-28 Method for forming semiconductor structure Pending CN117524985A (en)

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