CN117521821A - Quantum circuit generation method and device, storage medium and electronic device - Google Patents
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Abstract
The invention discloses a quantum circuit generation method, a device, a storage medium and an electronic device, wherein the method comprises the following steps: obtaining a target unitary matrix; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; a target quantum wire is generated that includes the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a quantum circuit generation method, a quantum circuit generation device, a storage medium and an electronic device.
Background
The quantum computing simulation is a simulation computation which simulates and follows the law of quantum mechanics by means of numerical computation and computer science, and is taken as a simulation program, and the high-speed computing capability of a computer is utilized to characterize the space-time evolution of the quantum state according to the basic law of quantum bits of the quantum mechanics.
Currently, algorithms for quantum computing are typically represented by quantum circuits, which include a qubit and quantum logic gates acting on the qubit, and typically a continuous quantum circuit may contain hundreds or even thousands of quantum logic gates.
Unitary matrix decomposition is a widely used method for mapping quantum algorithms to any set of quantum logic gates. This decomposition allows the conversion of a larger unitary matrix into a basic quantum logic gate combination, which is the key to executing and validating quantum algorithms on existing quantum computers or real quantum chips. However, the more the number of qubits operated by the quantum logic gate in the quantum algorithm, the more complex the calculation process, thus resulting in lower simulation efficiency of the quantum circuit and failure to simulate on a real quantum chip, which is a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a quantum route generation method, a device, a storage medium and an electronic device, which are used for solving the defects in the prior art, and reducing the depth of a quantum circuit by reducing the number of quantum bits operated by a quantum logic gate, improving the simulation efficiency of the quantum circuit and ensuring the fidelity of the decomposed quantum circuit executed on a quantum chip.
One embodiment of the present application provides a quantum wire generation method, including:
obtaining a target unitary matrix;
when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
a target quantum wire is generated that includes the target quantum logic gate.
Optionally, the decomposing the first, second, and third matrices respectively to obtain a plurality of target quantum logic gates includes:
Respectively recursively decomposing the first matrix and the second matrix by using the first preset decomposition rule until the order of diagonal blocks in the decomposed first matrix and second matrix is the preset value;
obtaining the target quantum logic gate based on the decomposed first matrix and second matrix;
and decomposing the third matrix to obtain the target quantum logic gate.
Optionally, the obtaining the target quantum logic gate based on the decomposed first matrix and the decomposed second matrix includes:
according to the decomposed first matrix and the decomposed second matrix, a plurality of uniform control gates and a plurality of uniform control revolving gates are obtained;
decomposing each uniform control door by using a second preset decomposition rule to obtain a plurality of uniform control revolving doors;
and decomposing each uniform control revolving door by utilizing a uniform control revolving door decomposition rule to obtain a plurality of target quantum logic gates.
Optionally, said decomposing said third matrix to obtain a plurality of said target quantum logic gates includes:
and recursively decomposing the third matrix by using the uniform control rotation gate decomposition rule to obtain m single-bit controlled gates of the specific type and m rotation logic gates, wherein m=d/2 and d is the order of the third matrix.
Optionally, decomposing the target unitary matrix by using a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, including:
decomposing the target unitary matrix by the following formula to obtain a first matrix, a second matrix and a third matrix:
wherein U is the target unitary matrix,for the first matrix, the A 1 、A 2 Diagonal blocks in the first matrix, respectively +.>For the second matrix, the B 1 、B 2 Diagonal blocks in said second matrix, respectively,>for the third matrix, the C, S are sub-blocks in the third matrix, respectively, and c=diag (cos (θ 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ),…)。
Optionally, the method further comprises:
and decomposing the target unitary matrix when the order of the target unitary matrix is equal to the preset value, so as to obtain the rotary logic gate.
Optionally, the decomposing the target unitary matrix to obtain the rotation logic gate includes:
decomposing the target unitary matrix by the following formula to obtain the rotary logic gate:
U(2)＝e iΦ R z (α) y (β)R z (γ)
wherein 2 is the order of the target unitary matrix, phi is the phase, alpha, beta and gamma are the rotation angles, R z 、R y Are all the rotary logic gates.
Yet another embodiment of the present application provides a quantum wire generating apparatus, the apparatus including:
The acquisition module is used for acquiring a target unitary matrix;
the first decomposition module is used for decomposing the target unitary matrix by utilizing a first preset decomposition rule when the order of the target unitary matrix is larger than a preset value to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
the second decomposition module is used for respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
and the generation module is used for generating a target quantum circuit containing the target quantum logic gate.
Optionally, the second decomposition module includes:
the first decomposition unit is used for recursively decomposing the first matrix and the second matrix respectively by utilizing the first preset decomposition rule until the order of diagonal blocks in the decomposed first matrix and second matrix is the preset value;
an obtaining unit, configured to obtain the target quantum logic gate based on the decomposed first matrix and second matrix;
And the second decomposition unit is used for decomposing the third matrix to obtain the target quantum logic gate.
Optionally, the obtaining unit is specifically configured to:
according to the decomposed first matrix and the decomposed second matrix, a plurality of uniform control gates and a plurality of uniform control revolving gates are obtained;
decomposing each uniform control door by using a second preset decomposition rule to obtain a plurality of uniform control revolving doors;
and decomposing each uniform control revolving door by utilizing a uniform control revolving door decomposition rule to obtain a plurality of target quantum logic gates.
Optionally, the second decomposition unit is specifically configured to:
and recursively decomposing the third matrix by using the uniform control rotation gate decomposition rule to obtain m single-bit controlled gates of the specific type and m rotation logic gates, wherein m=d/2 and d is the order of the third matrix.
Optionally, the first decomposition module is specifically configured to:
decomposing the target unitary matrix by the following formula to obtain a first matrix, a second matrix and a third matrix:
wherein U is the target unitary matrix,for the first matrix, the A 1 、A 2 Diagonal blocks in the first matrix, respectively +. >For the second matrix, the B 1 、B 2 Diagonal blocks in said second matrix, respectively,>for the third matrix, the C, S are sub-blocks in the third matrix, respectively, and c=diag (cos (θ 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ),…)。
Optionally, the apparatus further includes:
and the third decomposition module is used for decomposing the target unitary matrix when the order number of the target unitary matrix is equal to the preset value, so as to obtain the rotary logic gate.
Optionally, the third decomposition module is specifically configured to:
decomposing the target unitary matrix by the following formula to obtain the rotary logic gate:
U(2)＝e iv R z (α)E y (β)E z (γ)
wherein 2 is the order of the target unitary matrix, phi is the phase, alpha, beta and gamma are the rotation angles, R z 、R y Are all the rotary logic gates.
An embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is configured to perform, when run, the method of any of the above.
An embodiment of the application provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the method of any of the above.
Compared with the prior art, the method and the device have the advantages that firstly, the target unitary matrix is obtained; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; then, respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; and finally, generating a target quantum circuit containing the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced by reducing the number of quantum bits operated by the quantum logic gate, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal of a quantum circuit generating method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a quantum circuit generating method according to an embodiment of the present invention;
FIG. 3a is a schematic diagram of a quantum circuit of a uniform control gate of 3 control qubits according to an embodiment of the present invention;
FIG. 3b is a schematic diagram of another quantum circuit of the 3 uniform control gates for controlling qubits according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an equivalent quantum circuit of a uniform control gate of 3 control qubits according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a quantum circuit corresponding to a uniform control gate according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an equivalent quantum circuit corresponding to a second preset decomposition rule according to an embodiment of the present invention;
fig. 7 is a schematic diagram of an equivalent quantum circuit of a 3-qubit uniform rotation control gate according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an equivalent quantum circuit corresponding to a ucry gate according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an equivalent quantum circuit after primary decomposition of a target unitary matrix according to an embodiment of the present invention;
fig. 10 is a schematic diagram of an equivalent quantum circuit after primary decomposition of a first matrix according to an embodiment of the present invention;
fig. 11 is a schematic diagram of another equivalent quantum circuit of the target unitary matrix according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a quantum circuit generating device according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a quantum circuit generation method which can be applied to electronic equipment such as computer terminals, in particular to common computers, quantum computers and the like.
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum wire generation method in the embodiments of the present application, and the processor 102 executes the software programs and modules stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
The quantum computing is a novel computing mode for regulating and controlling the quantum information unit to compute according to a quantum mechanical law, wherein the most basic principle based on the quantum computing is a quantum mechanical state superposition principle, and the quantum mechanical state superposition principle enables the state of the quantum information unit to be in a superposition state with multiple possibilities, so that quantum information processing has greater potential compared with classical information processing in efficiency. A quantum system comprises a number of particles which move according to the laws of quantum mechanics, known as a quantum state of the system in a state space.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs, also weigh sub-logic circuits, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, the composition of which includes qubits, circuits (timelines), and various quantum logic gates, and finally the results often need to be read out by quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. The quantum logic gate can evolve quantum state, and the quantum logic gate is the basis for forming quantum circuit, and the quantum logic gate comprises single bit quantum logic gate, such as Hadamard gate (H gate, aldar Ma Men), brix gate (X gate), brix gate (Y gate), brix gate (Z gate), R x Door, R y Door, R z A door, etc.; two ratios ofA t or multi-bit quantum logic gate such as a CNOT gate, CR gate, CZ gate, issnap gate, toffoli gate, etc. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.
Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum circuit generating method according to an embodiment of the present invention, which may include the following steps:
s201: and obtaining the target unitary matrix.
It should be noted that, the target unitary matrix may correspond to a quantum program corresponding to a quantum algorithm for solving a certain problem, or may correspond to a part of the quantum program, and specifically may be determined according to an actual application scenario. The order of the target unitary matrix is proportional to the corresponding number of qubits, and exemplary, the number of qubits is 4, then the order of the target unitary matrix is 2 4 =16. The target unitary matrix can be obtained by receiving the information sent by other devices, can be generated by the target unitary matrix, and can be obtained by calling the stored information of the target unitary matrix.
S202: when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix.
The preset value may be determined according to an empirical value, or may be determined according to a decomposition rule, for example, the first preset decomposition rule decomposes a matrix above 2 steps, where the preset value is 2, and of course, may be determined in other manners.
The blocking matrix is a matrix, which is divided into a plurality of small sub-matrices according to the horizontal and vertical directions. Each small matrix is then considered an element. Illustratively, the form of the blocking matrix may be as follows:
wherein A is a block matrix; e (E) 1 、E 2 Each of O, B is a sub-block of a and is a small matrix of 2 x 2.
Illustratively, the form of a partitioned diagonal matrix may be as follows:
the partitioned diagonal matrix has zero elements in all sub-blocks except the sub-blocks on the diagonal (including a single diagonal element).
In the embodiment of the invention, the first matrix, the second matrix and the third matrix are multiplied to obtain the target unitary matrix, for example, the third matrix is multiplied by the first matrix to the left and the second matrix is multiplied by the second matrix to obtain the target unitary matrix; the first matrix is multiplied left by the third matrix, and multiplied right by the target unitary matrix that the second matrix is, and the first to third matrices have other arrangements, which are not listed here one by one.
And decomposing the target unitary matrix by utilizing a first preset decomposition rule, wherein no matter what decomposition mode is adopted, only the first to third matrixes can be obtained. For example, a first to third matrices are obtained by decomposing a target unitary matrix using QR (orthogonal triangular); gradually decomposing the target unitary matrix according to the arrangement sequence of the decomposed first to third matrixes and the properties of the three matrixes; of course, there are other ways that are not listed here.
S203: and decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types.
The rotary logic gate refers to a quantum logic gate with a rotary function and acting on single quantum bits and comprises R x Door, R y Door, R z One or more of the doors, R x Door, R y Door, R z The three doors can be mutually converted.
The single-bit controlled gate refers to a quantum logic gate with only one target bit and one control bit, namely the two-bit quantum logic gate, and the specific type of single-bit controlled gate can be a CNOT gate or a two-bit quantum logic gate with other functions.
For the first to third matrices, decomposition may be performed according to different manners, for example, the first matrix and the second matrix may use the same decomposition manner, and the decomposition of the second matrix may use another decomposition manner; the first to third matrices are decomposed using different decomposition modes, respectively. Decomposing the first to third matrixes to obtain a target quantum logic gate, so that the number of control bits of the quantum logic gate corresponding to the target unitary matrix is gradually reduced until the number of control bits of the quantum logic gate obtained by decomposition is only 0 and 1, and if the number of control bits is 1, the quantum logic gate is a single-bit controlled gate of a specific type, for example, a CNOT gate; if the number of control bits is 0, it is a single quantum logic gate, for example, it may be a rotary logic gate. Decomposing the first to third matrices to obtain target quantum logic gates, but decomposing different matrices may obtain the same type of rotary logic gates, or different types of rotary logic gates, e.g. decomposing the first matrix to obtain rotary logic gates R y Door and R z A gate for decomposing the second matrix to obtain a rotary logic gate R y And (3) a door.
S204: a target quantum wire is generated that includes the target quantum logic gate.
In one possible implementation manner of the present invention, the first matrix is decomposed to obtain the target quantum logic gate, the first sub-quantum circuit including the target quantum logic gate is generated, and similarly, the second sub-quantum circuit corresponding to the second matrix is obtained, and the third sub-quantum circuit corresponding to the third matrix is obtained. And determining the connection sequence of the first sub-quantum line to the third sub-quantum line according to the sequence of the first matrix to the third matrix which form the target unitary matrix and connecting the first sub-quantum line to the third sub-quantum line in sequence. For example, the first to third matrices are ordered into a first matrix, a third matrix, and a second matrix, and then the second sub-quantum wire is connected to the third sub-quantum wire, and the third sub-quantum wire is connected to the first sub-quantum wire.
In another possible implementation manner of the present invention, the corresponding target quantum logic gates may be sequentially applied to the qubits according to the preset sequences corresponding to the first to third matrices, respectively, to obtain the quantum circuits.
Therefore, the embodiment of the invention firstly obtains the target unitary matrix; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; then, respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; and finally, generating a target quantum circuit containing the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced by reducing the number of quantum bits operated by the quantum logic gate, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
In one possible embodiment of the present invention, the decomposing the first, second, and third matrices to obtain a plurality of target quantum logic gates may include:
respectively recursively decomposing the first matrix and the second matrix by using the first preset decomposition rule until the order of diagonal blocks in the decomposed first matrix and second matrix is the preset value;
obtaining the target quantum logic gate based on the decomposed first matrix and second matrix;
and decomposing the third matrix to obtain the target quantum logic gate.
In the embodiment of the invention, the first matrix and the second matrix adopt the same decomposition rule as the target unitary matrix, and the first matrix and the second matrix are subjected to iterative decomposition until the order of diagonal blocks in the decomposed first matrix and second matrix is a preset value. Taking the first matrix as an example, decomposing the first matrix by using a first preset decomposition rule, at this time, the first matrix is equivalent to the target unitary matrix, decomposing the first matrix to obtain new first to third matrices, decreasing the orders of the sub-blocks in the first to third matrices, and continuing to decompose the new first matrix and the second matrix until the orders of the sub-blocks in the decomposed first matrix are preset values.
The first matrix and the second matrix after decomposition have the same form, and the target quantum logic gate can be obtained based on the first matrix after decomposition. The equivalent matrix corresponding to the target quantum logic gate obtained by decomposing the first matrix is the first matrix, and the equivalent matrix corresponding to the target quantum logic gate obtained by decomposing the second matrix is the second matrix.
In the embodiment of the present invention, the third matrix may be an equivalent matrix of the multiple-quantum bit rotation gate, and iteratively decompose the multiple-quantum bit rotation gate until a target quantum logic gate is obtained.
In one possible embodiment of the present invention, obtaining the target quantum logic gate based on the decomposed first matrix and the decomposed second matrix may include:
according to the decomposed first matrix and the decomposed second matrix, a plurality of uniform control gates and a plurality of uniform control revolving gates are obtained;
decomposing each uniform control revolving door by using a second preset decomposition rule to obtain a plurality of uniform control revolving doors;
and decomposing each uniform control revolving door by utilizing a uniform control revolving door decomposition rule to obtain a plurality of target quantum logic gates.
The uniform control gate (Uniformly Controlled Gate or Multiplexed gates) is a generalization of a conditional unitary gate with any number of control qubits, with different unitary operators applied to the target qubit for each different bit configuration of control qubits. The control qubit refers to a qubit as a control bit, and an exemplary unitary matrix corresponding to a uniform control gate of 3 control qubits is shown below, and such a matrix form corresponds to a uniform control gate with control bits at the top and target bits at the bottom.
Each block U is a unitary operator that acts on the same number of qubits. Here, each block is marked with a corresponding control state, for example, when the control bit is |011>When in use, U 011 Acting on the target bit.
The control qubits of the uniform control gates are generally represented by half-fills or boxes on the circuit diagram, and exemplary 3 control qubits of the uniform control gates can be shown in fig. 3a or fig. 3 b. For an n-bit controlled uniform control gate, this is equivalent to 2 n The 3 control qubits of the uniform control gate can be decomposed into 8 uniform rotation control gates with control information, as illustrated in fig. 4. If each diagonal block in the matrix corresponding to the uniform control gate is a matrix of 2 x 2, the uniform control gate is called a uniform control single gate.
Uniform control doorThe corresponding quantum circuit of (c) may be as shown in fig. 5, where \ represents 1 or more control bits, u if \ is 1 bit 1 、u 2 The sizes of the control gates are 2 x 2, and the uniform control gates are uniform control single gates; if \is 3 bits, u 1 、u 2 The sizes of (2) are all 8 x 8. Taking 1 bit as an example, when the control bit is |0>When applying u 1 When the control bit is |1>When applying u 2 。
When the subblocks in the uniform control gate are R y Door or R z The equivalent matrix of gates, where the uniform control gate is a uniform control rotation gate, the matrix of n uniform control rotation gates controlling qubits can be expressed as:
because the first matrix and the second matrix are decomposed recursively, after the first matrix is decomposed recursively, 2 uniform control gates and a plurality of uniform control turngates can be obtained for the first matrix, and 2 uniform control gates and a plurality of uniform control turngates can be obtained for the second matrix.
And decomposing the uniform control door into uniform control revolving doors according to a second preset decomposition rule. The second preset decomposition rule may be exemplified as shown in fig. 6, in which the uniformity control gate is decomposed into a combination of a uniformity control rotating gate containing a uniformity rotation control R and a diagonal gate z Door, uniform rotation control R y Door, uniform rotation control R z The combination of gates, the dashed boxes in the figures represent gates that are not of any substantial and uncontrolled,representing a diagonal door. In the embodiment of the invention, for the uniform control door, the uniform control revolving door is obtained by utilizing a second preset decomposition rule. The first matrix and the second matrix are decomposed by utilizing a first preset decomposition rule, so that a matrix which is shaped like a third matrix is necessarily generated, and the generated matrix is the matrix corresponding to the uniform control revolving door.
In one possible embodiment of the present invention, the uniformly controlled revolving door decomposition rule is: for a 1 n qubit uniform control turnstile, it can be decomposed into 2 n-1 qubit uniform control turnstiles and 2 CNOT gates, and by way of example, taking one uniform control turnstile as an example, the following formulas illustrate that the logic gate effect before and after decomposition is equivalent:
wherein, the unitary matrix corresponding to CNOT isI is an identity matrix, X is a matrix corresponding to an X gate, and specifically +.>R k Is R y Door or R z Door, then XR k (λ 1 ) X is equivalent to R k (-λ 1 )，θ 0 ＝λ 0 +λ 1 ，θ 1 ＝λ 0 -λ 1 。
Exemplary, as shown in FIG. 7, for a 3-bit uniform rotation control gate R k Decomposing the uniform control revolving door to finally obtain 4R k The gates and the 4 CNOT gates are arranged in parallel if part of CNOT gates act on the quantum wires in the decomposition process, so that after the quantum wires pass through the CNOT gates, quantum states are not changed, and effects are counteracted, therefore, the quantum wires do not contain CNOT gates with the effects counteracted each other, and the uniform control revolving gate of n quantum bits is decomposed, so that the result is 2 n-1 Sum of 2 of rotary logic gates n-1 And CNOT gates. The recursive decomposition is performed according to such decomposition rules, with finally only the rotation logic gate and the CNOT gate.
In one possible embodiment of the present invention, said decomposing said third matrix to obtain a plurality of said target quantum logic gates comprises:
and recursively decomposing the third matrix by using the uniform control rotation gate decomposition rule to obtain m single-bit controlled gates of the specific type and m rotation logic gates, wherein m=d/2 and d is the order of the third matrix.
The third matrix may be a uniform control R y The matrix corresponding to the gate (ucry gate) can be expressed asAnd c=diag (cos (θ) 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ) …). Thus, for a 2-qubit ucry gate, the equivalent quantum circuit is shown in FIG. 8, and the circuit is equivalent as determined by the derivation of the following equation:
/>
wherein,
the third matrix has the same order as the target unitary matrix, and is d, where d=2 n N is the number of qubits, and the third matrix is decomposed to obtain m rotary logic gates and m CNOT gates, i.e., m=2 n-1 。
In one possible embodiment of the present invention, decomposing the target unitary matrix using a first preset decomposition rule to obtain a first matrix, a second matrix, and a third matrix includes:
decomposing the target unitary matrix by the following formula to obtain a first matrix, a second matrix and a third matrix:
Wherein U is the target unitary matrix,for the first matrix, the A 1 、A 2 Diagonal blocks in the first matrix, respectively +.>For the second matrix, the B 1 、B 2 Diagonal blocks in said second matrix, respectively,>for the third matrix, the C, S are sub-blocks in the third matrix, respectively, and c=diag (cos (θ 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ),…)。
Note that C, S is a real diagonal matrix, andthe third matrix is the ucry gate targeting the first qubit, it being understood that such a matrix is the reverse of the ucry on the control bit. Taking a target unitary matrix with 4 qubits as an example, the target unitary matrix can be decomposed into an equivalent circuit diagram as shown in fig. 9 by one-time decomposition, wherein +.>
When the order of diagonal blocks in the first matrix is greater than a preset value, namely A 1 、A 2 When the order of the diagonal blocks in the decomposed matrix is equal to the preset value, the first matrix is decomposed continuously by utilizing the formula. If the order of diagonal blocks in the first matrix is larger than the preset value at this time, the first matrix is decomposed by reusing a first preset decomposition rule, and the decomposition process is as follows:
based on fig. 9 and the above decomposition process, the first matrix is decomposed again, and the resulting equivalent circuit is shown in fig. 10. The decomposition principle of the second matrix is the same as that of the first matrix. For the first matrix or the third matrix, decomposition to the end results in 2 uniform control gates and a number of uniform control turnstiles, the number of uniform control turnstiles obtained being related to the order of the first matrix. The uniform control gate can be decomposed by using a second decomposition rule to obtain a plurality of uniform control revolving gates. And decomposing the uniformly controlled revolving gate to obtain the target quantum logic gate.
In one possible embodiment of the present invention, the method may further comprise:
and decomposing the target unitary matrix when the order of the target unitary matrix is equal to the preset value, so as to obtain the rotary logic gate.
When the order of the target unitary matrix is equal to a preset value, the target unitary matrix cannot be decomposed by using a first preset decomposition rule, and the target unitary matrix may correspond to a single-bit U gate, the U gate is decomposed into a plurality of rotary logic gates, and the matrix corresponding to the rotary logic gates obtained by decomposition is equivalent to the target unitary matrix.
In one possible embodiment of the present invention, the decomposing the target unitary matrix to obtain the rotary logic gate includes:
decomposing the target unitary matrix by the following formula to obtain the rotary logic gate:
U(2)＝e iΦ R z (α)R y (β)R z (γ)
wherein 2 is the order of the target unitary matrix, phi is the phase, alpha, beta and gamma are the rotation angles, R z 、R y Are all the rotary logic gates.
In the embodiment of the invention, the quantum circuit equivalent to the target unitary matrix is shown in fig. 11, e iΦ Since the global phase acts on all quantum logic gates in the quantum wire, and the final result obtained through the quantum wire is not substantially changed, there is virtually no quantum logic gate corresponding to the quantum wire, and the quantum wire is indicated by a dotted frame.
By applying the method provided by the embodiment of the invention, the target unitary matrix is decomposed, and the number of CNOT gates obtained is 4 n -2*2 n The same target unitary matrix is decomposed by using a QR method, and the number of CNOT gates obtained is 2 x 4 n -(2n+3)*2 n +2n, a significant reduction in the number of CNOTs can be seen. By using the method provided by the embodiment of the invention, the overall depth of the synthetic line of the unitary matrix through decomposition in the process of executing the quantum algorithm can be effectively reduced, and the fidelity of executing the quantum algorithm on a chip can be ensured. And the classical algorithm time consumption of the quantum algorithm process through decomposing the unitary matrix synthetic line is reduced, and in short, less time is spent, and less CNOT is obtained.
The method provided by the embodiment of the invention can be applied to a quantum circuit with a quantum logic gate for operating a plurality of quantum bits, further, can be applied to a scene of quantum calculation by utilizing the quantum circuit, for example, can be applied to a scene of solving a linear equation by utilizing the quantum circuit, can be applied to a scene of chemical simulation by utilizing the quantum circuit, can be applied to a scene of financial calculation by utilizing the quantum circuit, can be applied to a scene of data classification by utilizing the quantum circuit, and the like, and is not listed one by one.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a quantum circuit generating device according to an embodiment of the present invention, corresponding to the flow shown in fig. 2, where the device includes:
an obtaining module 1201, configured to obtain a target unitary matrix;
a first decomposition module 1202, configured to decompose the target unitary matrix by using a first preset decomposition rule when an order of the target unitary matrix is greater than a preset value, to obtain a first matrix, a second matrix, and a third matrix, where the first matrix and the second matrix are both block diagonal matrices, and the third matrix is a block matrix;
a second decomposition module 1203, configured to decompose the first, second, and third matrices respectively to obtain a plurality of target quantum logic gates, where the target quantum logic gates include a rotary logic gate and a single-bit controlled gate of a specific type;
a generating module 1204, configured to generate a target quantum wire including the target quantum logic gate.
In one possible embodiment of the present invention, the second decomposition module 1203 may include:
the first decomposition unit is used for recursively decomposing the first matrix and the second matrix respectively by utilizing the first preset decomposition rule until the order of diagonal blocks in the decomposed first matrix and second matrix is the preset value;
An obtaining unit, configured to obtain the target quantum logic gate based on the decomposed first matrix and second matrix;
and the second decomposition unit is used for decomposing the third matrix to obtain the target quantum logic gate.
In a possible embodiment of the invention, the obtaining unit may be specifically configured to:
according to the decomposed first matrix and the decomposed second matrix, a plurality of uniform control gates and a plurality of uniform control revolving gates are obtained;
decomposing each uniform control door by using a second preset decomposition rule to obtain a plurality of uniform control revolving doors;
and decomposing each uniform control revolving door by utilizing a uniform control revolving door decomposition rule to obtain a plurality of target quantum logic gates.
In a possible embodiment of the present invention, the second decomposition unit may be specifically configured to:
and recursively decomposing the third matrix by using the uniform control rotation gate decomposition rule to obtain m single-bit controlled gates of the specific type and m rotation logic gates, wherein m=d/2 and d is the order of the third matrix.
In one possible embodiment of the present invention, the first decomposition module 1202 may be specifically configured to:
Decomposing the target unitary matrix by the following formula to obtain a first matrix, a second matrix and a third matrix:
wherein U is the target unitary matrix,for the first matrix, the A 1 、A 2 Diagonal blocks in the first matrix, respectively +.>For the second matrix, the B 1 、B 2 Diagonal blocks in said second matrix, respectively,>to be the instituteThe third matrix, the C, S are sub-blocks in the third matrix, respectively, and c=diag (cos (θ 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ),…)。
In one possible embodiment of the present invention, the apparatus may further include:
and the third decomposition module is used for decomposing the target unitary matrix when the order number of the target unitary matrix is equal to the preset value, so as to obtain the rotary logic gate.
In a possible embodiment of the present invention, the third decomposition module may be specifically configured to:
decomposing the target unitary matrix by the following formula to obtain the rotary logic gate:
U(2)＝e iΦ R z (α)R y (β)R z (γ)
wherein 2 is the order of the target unitary matrix, phi is the phase, alpha, beta and gamma are the rotation angles, R z 、R y Are all the rotary logic gates.
Therefore, the embodiment of the invention firstly obtains the target unitary matrix; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; then, respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; and finally, generating a target quantum circuit containing the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced by reducing the number of quantum bits operated by the quantum logic gate, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
The embodiment of the invention also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the method embodiments described above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
s201: obtaining a target unitary matrix;
s202: when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
s203: decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
s204: a target quantum wire is generated that includes the target quantum logic gate.
Therefore, the embodiment of the invention firstly obtains the target unitary matrix; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; then, respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; and finally, generating a target quantum circuit containing the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced by reducing the number of quantum bits operated by the quantum logic gate, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
The present invention also provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s201: obtaining a target unitary matrix;
s202: when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
s203: decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
S204: a target quantum wire is generated that includes the target quantum logic gate.
Therefore, the embodiment of the invention firstly obtains the target unitary matrix; when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix; then, respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types; and finally, generating a target quantum circuit containing the target quantum logic gate. By using the embodiment of the invention, the depth of the quantum circuit can be reduced by reducing the number of quantum bits operated by the quantum logic gate, the simulation efficiency of the quantum circuit can be improved, and the fidelity of the decomposed quantum circuit executed on the quantum chip can be ensured.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method of quantum wire generation, the method comprising:
obtaining a target unitary matrix;
when the order of the target unitary matrix is larger than a preset value, decomposing the target unitary matrix by utilizing a first preset decomposition rule to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
decomposing the first matrix, the second matrix and the third matrix respectively to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
a target quantum wire is generated that includes the target quantum logic gate.
2. The method of claim 1, wherein decomposing the first, second, and third matrices, respectively, to obtain a plurality of target quantum logic gates, comprises:
respectively recursively decomposing the first matrix and the second matrix by using the first preset decomposition rule until the order of diagonal blocks in the decomposed first matrix and second matrix is the preset value;
obtaining the target quantum logic gate based on the decomposed first matrix and second matrix;
And decomposing the third matrix to obtain the target quantum logic gate.
3. The method of claim 2, wherein the obtaining the target quantum logic gate based on the decomposed first matrix and second matrix comprises:
according to the decomposed first matrix and the decomposed second matrix, a plurality of uniform control gates and a plurality of uniform control revolving gates are obtained;
decomposing each uniform control door by using a second preset decomposition rule to obtain a plurality of uniform control revolving doors;
and decomposing each uniform control revolving door by utilizing a uniform control revolving door decomposition rule to obtain a plurality of target quantum logic gates.
4. A method according to claim 3, wherein said decomposing said third matrix to obtain a plurality of said target quantum logic gates comprises:
and recursively decomposing the third matrix by using the uniform control rotation gate decomposition rule to obtain m single-bit controlled gates of the specific type and m rotation logic gates, wherein m=d/2 and d is the order of the third matrix.
5. The method of claim 4, wherein decomposing the target unitary matrix using a first predetermined decomposition rule to obtain a first matrix, a second matrix, and a third matrix comprises:
Decomposing the target unitary matrix by the following formula to obtain a first matrix, a second matrix and a third matrix:
wherein U is the target unitary matrix, (A) 1 A 2 ) For the first matrix, the A 1 、A 2 Respectively diagonal blocks in the first matrix, (B) 1 B 2 ) For the second matrix, the B 1 、B 2 Respectively diagonal blocks in the second matrix,for the third matrix, the C, S are sub-blocks in the third matrix, respectively, and c=diag (cos (θ 0 ),cos(θ 1 ),…)，S＝diag(sin(θ 0 ),sin(θ 1 ),…)。
6. The method according to any one of claims 1-5, further comprising:
and decomposing the target unitary matrix when the order of the target unitary matrix is equal to the preset value, so as to obtain the rotary logic gate.
7. The method of claim 6, wherein the decomposing the target unitary matrix to obtain the rotary logic gate comprises:
decomposing the target unitary matrix by the following formula to obtain the rotary logic gate:
U(2)＝e iΦ R z (α)R y (β)R z (γ)
wherein 2 is the order of the target unitary matrix, phi is the phase, alpha, beta and gamma are the rotation angles, R z 、R y Are all the rotary logic gates.
8. A quantum wire generating device, the device comprising:
the acquisition module is used for acquiring a target unitary matrix;
The first decomposition module is used for decomposing the target unitary matrix by utilizing a first preset decomposition rule when the order of the target unitary matrix is larger than a preset value to obtain a first matrix, a second matrix and a third matrix, wherein the first matrix and the second matrix are both block diagonal matrixes, and the third matrix is a block matrix;
the second decomposition module is used for respectively decomposing the first matrix, the second matrix and the third matrix to obtain a plurality of target quantum logic gates, wherein the target quantum logic gates comprise rotary logic gates and single-bit controlled gates of specific types;
and the generation module is used for generating a target quantum circuit containing the target quantum logic gate.
9. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when run.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 7.
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