CN108154240B - Low-complexity quantum line simulation system - Google Patents

Low-complexity quantum line simulation system Download PDF

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CN108154240B
CN108154240B CN201711470556.7A CN201711470556A CN108154240B CN 108154240 B CN108154240 B CN 108154240B CN 201711470556 A CN201711470556 A CN 201711470556A CN 108154240 B CN108154240 B CN 108154240B
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朱美珍
杨夏
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Origin Quantum Computing Technology Co Ltd
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Abstract

The invention discloses a low-complexity quantum circuit simulation system, belongs to the field of quantum computation, and solves the technical problems of overlarge simulation storage space and overlong computation time of a quantum circuit in the prior art. The system comprises an input module, a storage module and an output module, wherein the storage module stores data as follows: (1) establishing a mathematical model to represent quantum state and quantum logic gate operation; (2) grouping the quantum bits, and rearranging the serial numbers of the quantum bits; (3) to the total operation matrix U0And reducing the order and calculating an output state. The invention utilizes the implicit internal rule of the quantum logic gate to directly operate the matrix elements of the quantum state vector, and meanwhile, the method has expandability and can use a super computer to simulate a quantum computer with more bits in the future.

Description

Low-complexity quantum line simulation system
Technical Field
The invention belongs to the field of quantum computation, in particular relates to a program language description system based on a quantum circuit model, which is a low-time and space complexity system for simulating a quantum circuit by a computer.
Background
A quantum algorithm described in a quantum wire model is a method of manipulating a quantum computer to process input states and output specific measurement values. Quantum computers are a key technology under study when running quantum algorithms because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, the time to break RSA keys can be accelerated from hundreds of years to hours. The processing speed of a quantum computer increases exponentially with the number of quantum bits, and it is expected that above 50 bits, the processing speed of a quantum computer on a particular problem will be faster than the sum of the processing speeds of all supercomputers in the world. However, the prototypes of quantum computers at present have a small number of qubits, and the actual processing speed is not as fast as that of classical computers. In order to solve the problem, people predict the behavior of the quantum computer by using a theoretical analysis method, and the method is usually used for verifying the correctness of the behavior of the quantum algorithm or the quantum computer and guiding the design of the quantum algorithm and the quantum computer.
In the past, the change of quantum state was analyzed and simulated by using the product of a unitary transformation matrix representing a quantum logic gate and a complex vector representing the quantum state. However, the time and space complexity of such calculation increases with the number of qubits by a quadratic exponential function, and when the qubits reach 20 bits, the matrix dimension required for representing one quantum logic gate reaches 1048576, and for example, a double-precision floating-point data type requires 16384GB of memory for storage, which occupies a huge storage space. In addition, quantum algorithms are described by using a quantum circuit diagram, and the method has the defect of poor expandability.
Disclosure of Invention
1. Problems to be solved
Aiming at the problem that in the prior art, the quantum line cannot be calculated due to the fact that a storage space is too large for matrix operation, or the quantum line cannot be simulated due to the fact that the storage space is enough but the calculation time is too long, the invention provides a low-complexity simulation system for simulating the quantum line. The invention utilizes the implicit internal rule of the quantum logic gate to directly operate the matrix elements of the quantum state vector, and meanwhile, the method has expandability and can use a super computer to simulate a quantum computer with more bits in the future.
2. Technical scheme
In order to solve the above problems, the present invention adopts the following technical solutions.
The invention principle is as follows: and reducing the complex redundant matrix multiplication into a plurality of low-dimensional matrix multiplications by using the matrix characteristics of the quantum logic gate.
A low-complexity quantum wire simulation system comprises an input module, a data processing module and an output module, wherein the data processing module processes data as follows:
(1) establishing a mathematical model to characterize quantum states and quantum logic gate operations
For single-quantum bits, the mathematical model is a 1 x 2 complex vector; for N qubits, by direct product operationCalculating to obtain 1 x 2NA complex vector of (a); using two 1 x 2NDimensional vectors which respectively store the real part and the imaginary part of a quantum state and represent the corresponding quantum logic gate by any given quantum logic gate U and bit number of operation;
(2) grouping the qubits, rearranging the numbering of the qubits
And dividing the qubits into two groups according to whether the qubits are control bits or controlled bits as a judgment condition: the quantum bit which is not the control or controlled bit is marked as a cycle bit, and the control or controlled quantum bit is marked as an operation bit; arranging the serial number of all operation bits behind the cyclic bit, and storing the vector of quantum state and the total operation matrix U according to the serial number0Rearranging, said overall operation matrix U0The direct product of the matrix form of the quantum logic gate corresponding to each quantum bit is obtained, and the matrix form of the quantum logic gate corresponding to the cyclic bit is an identity matrix;
(3) to the total operation matrix U0Reducing order, calculating output state
Using rearranged total operation matrix U0The rule of the arrangement of the medium matrix elements is 2N+2NBy a matrix multiplication of order 2N-m2 eachm*2mCompleting the data processing process by matrix multiplication;
where m is the dimension of a given qubit logic gate, m is 1 for a single qubit logic gate, m is 2 for a two qubit logic gate, and so on.
Further, in the step (2), the method for grouping the qubits and rearranging the numbering of the qubits is as follows:
for N-bit qubits, the overall operation matrix U0Is 2N*2NOutput quantum state | θ>outBy the total operation matrix U0And input quantum state | theta>inBy multiplication, i.e. | θ>out＝U0*|θ>in(ii) a Specifically, the method comprises the following steps:
1) for single quantum bit logic gate UiOverall operation matrix U0Can be expressed as:
Figure BDA0001531925060000021
wherein, I is a 2 x 2 unit matrix; after the ith quantum bit is shifted to the nth quantum bit, the positions of the rest quantum bits are unchanged and are arranged according to the sequence of the numbers from small to large, namely:
Figure BDA0001531925060000022
i is any integer between 1 and 2>inThe number of the code is correspondingly adjusted;
input quantum state | θ>inThe rewrite is: [ theta ]>in＝|q1q2...qi-1qi+1...qNqi>；q1、q2...qi-1、qi+1...qNFor cyclic bits, qiIs an operation bit;
the result of the direct product of the identity matrix is still the identity matrix, so the overall operation matrix U0The rewrite is:
Figure BDA0001531925060000031
2) for a two-qubit logic gate UijThe grouping principle is the same as that of a single-bit quantum logic gate, and after the ijth quantum bit is shifted to the Nth quantum bit by the method, the positions of the rest quantum bits are unchanged and are arranged in the sequence of the numbers from small to large. General operation matrix U0The rewrite is:
Figure BDA0001531925060000032
input quantum state | θ>inThe rewrite is: [ theta ]>in＝|q1q2...qi-1qi+1...qj-1qj+1...qNqiqj>；q1、q2...qi-1、qi+1...qj-1qj+1...qNFor cyclic bits, qi、qjIs an operation bit;
note: for convenience of expression, in the symbolic representation of the two qubit logic gates in the method, i < j and i +1 < j-1 are defaulted, but the requirement is not met in the practical problem treatment, and the description can be met.
3) Similarly, the method extends to multi-bit qubit logic gate operations of more than three bits.
Further, the step (3) is to sum the operation matrix U0The order reduction method comprises the following steps:
1) for single quantum bit logic gates
Traversing the cyclic bits from 00.. 00 to 11.. 11 according to the number according to the arrangement result of the step (2), wherein the step length is 1; corresponding quantum logic gate calculation is carried out on the operation bits, specifically as follows:
Figure BDA0001531925060000033
wherein | q1q2...qi-1qi+1...qN0>in，|q1q2...qi-1qi+1...qN1>inRepresenting the input quantum state component as | q1q2...qi-1qi+1...qN0>，|q1q2...qi-1qi+1...qN1>The coefficient of (a); | q1q2...qi-1qi+1...qN>out，|q1q2...qi-1qi+1...qN1>outRepresenting the output quantum state component as | q1q2...qi-1qi+1...qN0>，|q1q2...qi- 1qi+1...qN1>The coefficient of (a);
therefore will 2N*2NIs reduced to 2N-12-2 matrix multiplication is carried out, and each 2-2 matrix is completed in sequence to obtain a result of an output quantum state;
2) for a double-quantum-bit logic gate, the order reduction method is the same as that of a single-quantum-bit logic gate;
outputting quantum state | theta due to the grouping operation of the step (2)>out＝U*|θ>inRestated as: for q1q2...qi-1qi+1...qj-1qj+1...qN2 in total from 00 … 0 to 11 … 1N-2Cases, for each case, execution
Figure BDA0001531925060000041
Therefore will 2N*2NIs reduced to 2N-24-4 matrix multiplication is carried out, and each 4-4 matrix is completed in sequence to obtain a result of an output quantum state;
3) similarly, the method expands the operation of the qubit logic gate with more than three bits.
3. Advantageous effects
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention avoids the defect of excessive matrix element quantity in a system for explicitly representing a quantum logic gate matrix, omits redundant operation in matrix multiplication, obtains the rule of an operation matrix by rearranging the operation matrix and the quantum state number, directly calculates complex vectors representing the quantum state, replaces the technical scheme of matrix multiplication, and calculates the problem by a square magnitude relative matrix multiplication method;
(2) the invention adopts the technical scheme that the matrix multiplication is first-order vector operation, and provides a system for solving quantum circuit simulation, which has high calculation speed and low memory consumption. For the simulation of N-bit qubits, the conventional matrix algorithm requires storage of 2N*2NAnd 1 x 2NThe column vector of (2).The improved technology only needs to store 1 x 2NThe column vector of (a) can be realized;
(3) the invention has strong expandability. For the quantum logic gate with more than three quanta bits, the same arrangement and division method can be adopted to make an m-quanta bit logic gate for an N-bit quantum bit system, which can be simplified to 2N-m+1M by m matrix multiplication. The calculation amount of the system is far smaller than that of the traditional matrix algorithm, and the calculation complexity is not different from that of a single-quantum-bit logic gate.
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Fig. 1 is a flow chart of the circuit simulation of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The system of the present invention is further described based on a specific embodiment with reference to fig. 1. The invention relates to a low-complexity quantum line simulation system, which comprises an input module, a data processing module and an output module which are connected in sequence. The input module is used for inputting data. The data processing module is used for finishing the processing of the data from the input module. The output module is used for outputting the data processed by the data processing module. Specifically, the data processing module processes the data as follows:
the quantum input state is exemplified below by a qubit system with N ═ 4
Figure BDA0001531925060000051
The concrete expression is as follows:
Figure BDA0001531925060000052
note:
(1) in the examples below, the subscripts have the following meanings: | q1q3q3q4>in0The subscript in represents the input state, out represents the output state, 0 represents the order before the numbering rearrangement, and 1 represents the order after the numbering rearrangement.
(2) For convenience of description, each quantum state component coefficient in this embodiment is a real number, but is not limited to a real number, and the calculation methods are completely the same.
(3)|θ>in0And | θ>out0In (3), the quantum state component with a coefficient of zero is omitted from the expression of the total quantum state and is not represented.
Example 1: to q is2Hadamard gate operation is performed.
The method comprises the following steps: establishing a mathematical model with
Figure BDA0001531925060000053
Characterizing the operation on the quantum system, in which case the overall operation matrix U0And input quantum state | theta>in0Can be expressed as:
Figure BDA0001531925060000054
Figure BDA0001531925060000055
Figure BDA0001531925060000056
step two: grouping the qubits, rearranging the numbering of the qubits:
grouping the qubits according to whether the qubits are control bits or controlled bits as a decision condition, q1、q3、q4For cyclic bits, q2Is an operation bit.
The qubit numbers are rearranged according to the grouping result, and the vectors storing the quantum states and the overall operation matrix are rearranged according to the numbers. Rearranged quantum state | θ>in1And the rearranged total operation matrix U1The following were used:
Figure BDA0001531925060000061
Figure BDA0001531925060000062
step three: reducing the total operation matrix to calculate the output state
By means of the new numbering and the form of the operation matrix, a 16 x 16 matrix can be converted into 8 2 x 2 matrices.
Next, using the partitioned matrix, the output state is calculated:
Figure BDA0001531925060000063
wherein q is1q3q4The output results were calculated sequentially for 8 cases in total of 000 to 111.
The specific process is as follows:
q1q3q4when the content is 000, the content is,
Figure BDA0001531925060000064
q1q3q4when the alloy is set to be 001,
Figure BDA0001531925060000065
q1q3q4when the electric power is set to 010 ═ time,
Figure BDA0001531925060000066
q1q3q4when the power is set to 011, the power is turned on,
Figure BDA0001531925060000071
q1q3q4when the number is equal to 100, the number of the grooves,
Figure BDA0001531925060000072
Figure BDA0001531925060000073
q1q3q4when the number is 101, the number of the contact points,
Figure BDA0001531925060000074
q1q3q4when the number is equal to 110, the number is as follows,
Figure BDA0001531925060000075
q1q3q4when the number is 111,
Figure BDA0001531925060000076
finally, the output state can be obtained by combining the results
Figure BDA0001531925060000077
The data processing process is completed.
Example 1 Using a conventional matrix algorithm, it is necessary to store a total operation matrix of size 16 x 16, and 163The sub-floating-point multiply operation and the 16 x 15 floating-point add operation.
By adopting the method, only the operation matrix with the size of 2 x 2 needs to be stored, and 32 times of floating-point multiplication operation and 16 times of floating-point addition operation are needed.
Example 2: a CNOT gate for controlling q3 by q1 is marked as CNOT for q1q31，3
The method comprises the following steps: establishing a mathematical model with
Figure BDA0001531925060000081
A qubit logic gate is characterized.
Step two: dividing the quantum bit intoGroup, reordering numbering of qubits: grouping the qubits according to whether the qubits are control bits or controlled bits as a decision condition, q2、q4For cyclic bits, q1、q3Is an operation bit. The qubit numbers are rearranged according to the grouping result, and the vectors storing the quantum states and the overall operation matrix are rearranged according to the numbers. Rearranged quantum state | θ>in1And the rearranged total operation matrix U1The following were used:
Figure BDA0001531925060000082
Figure BDA0001531925060000083
wherein the content of the first and second substances,
Figure BDA0001531925060000084
step three: reducing the total operation matrix to calculate the output state
By means of the new numbering and the form of the operation matrix, a 16 x 16 matrix can be converted into 4 x 4 matrices.
Next, using the partitioned matrix, the output state is calculated:
Figure BDA0001531925060000085
wherein q is2q4The case of the full array is 00 to 11, and the total number is four.
The specific process is as follows:
q2q4when the value is 00:
Figure BDA0001531925060000086
Figure BDA0001531925060000091
q2q4when the value is 01:
Figure BDA0001531925060000092
q2q4when the value is 10:
Figure BDA0001531925060000093
q2q4when the value is 11:
Figure BDA0001531925060000094
Figure BDA0001531925060000101
finally, the output state can be obtained by combining the results
Figure BDA0001531925060000102
The data processing process is completed.
Example 2 Using a conventional matrix algorithm, it is necessary to store a total operation matrix of size 16 x 16, and 163The sub-floating-point multiply operation and the 16 x 15 floating-point add operation.
With the method of the present invention, only 4 × 4 operation matrices are required to be stored, and 64 floating-point multiplication operations and 48 floating-point addition operations are required.
Example 3: toffoli gate with q1q3 controlling q4 for q1q3q4, denoted as Toffoli1，3，4
The method comprises the following steps: establishing a mathematical model with
Figure BDA0001531925060000103
A qubit logic gate is characterized.
Step two: grouping the qubits, rearranging the numbering of the qubits: according toUsing whether the quantum bit is control bit or controlled bit as judging condition to group the quantum bit, q2For cyclic bits, q1、q3、q4Is an operation bit. The qubit numbers are rearranged according to the grouping result, and the vectors storing the quantum states and the overall operation matrix are rearranged according to the numbers. Rearranged quantum state | θ>in1And the rearranged total operation matrix U1The following were used:
Figure BDA0001531925060000104
Figure BDA0001531925060000105
wherein the content of the first and second substances,
Figure BDA0001531925060000106
step three: reducing the total operation matrix to calculate the output state
By means of the new numbering and the form of the operation matrix, a 16 x 16 matrix can be converted into 28 x 8 matrices.
Next, using the partitioned matrix, the output state is calculated:
Figure BDA0001531925060000111
wherein q is2The total arrangement of 0 to 1 is two cases.
The specific process is as follows:
q2when the value is 0:
Figure BDA0001531925060000112
Figure BDA0001531925060000121
q2when the value is 1:
Figure BDA0001531925060000122
finally, the output state can be obtained by combining the results
Figure BDA0001531925060000131
The data processing process is completed.
Example 3 Using a conventional matrix algorithm, it is necessary to store a total operation matrix of size 16 x 16, and 163The sub-floating-point multiply operation and the 16 x 15 floating-point add operation.
With the method of the present invention, only 8 × 8 operation matrices are required to be stored, and 128 floating-point multiply operations and 112 floating-point add operations.

Claims (3)

1. A low-complexity quantum wire simulation system comprises an input module, a data processing module and an output module, and is characterized in that the data processing module processes data as follows:
(1) establishing a mathematical model to characterize quantum states and quantum logic gate operations
For single-quantum bits, the mathematical model is a 1 x 2 complex vector; for N qubits, a direct product operation yields 1 x 2NA complex vector of (a); using two 1 x 2NDimensional vectors which respectively store the real part and the imaginary part of a quantum state and represent the corresponding quantum logic gate by any given quantum logic gate U and bit number of operation;
(2) grouping the qubits, rearranging the numbering of the qubits
And dividing the qubits into two groups according to whether the qubits are control bits or controlled bits as a judgment condition: the quantum bit which is not the control or controlled bit is marked as a cycle bit, and the control or controlled quantum bit is marked as an operation bit; arranging the serial number of all operation bits after the cyclic bit, and storing the vector of quantum state and the total operation matrix according to the serial numberU0Rearranging, said overall operation matrix U0The direct product of the matrix form of the quantum logic gate corresponding to each quantum bit is obtained, and the matrix form of the quantum logic gate corresponding to the cyclic bit is an identity matrix;
(3) to the total operation matrix U0Reducing order, calculating output state
Using rearranged total operation matrix U0Rule of middle matrix element arrangement, 2 of cyclic bit corresponding to the ruleN-mStep-by-step traversal of the quantum state components and corresponding quantum logic gate calculation of the operation bit corresponding to the law are carried out, and 2 is carried outN*2NBy a matrix multiplication of order 2N-m2 eachm*2mCompleting the data processing process by matrix multiplication;
where m is the dimension of a given qubit logic gate, m is 1 for a single qubit logic gate, m is 2 for a two qubit logic gate, and so on.
2. A low complexity quantum wire simulation system as claimed in claim 1, wherein in step (2), the qubits are grouped and their numbering is rearranged by:
for N-bit qubits, the overall operation matrix U0Is 2N*2NOutput quantum state | θ >outBy the total operation matrix U0And input quantum state | theta >inBy multiplication, i.e. | θ>out＝U0*|θ>in(ii) a Specifically, the method comprises the following steps:
1) for single quantum bit logic gate UiOverall operation matrix U0Can be expressed as:
Figure FDA0002432802010000011
wherein, I is a 2 x 2 unit matrix; after the ith quantum bit is shifted to the nth quantum bit, the positions of the rest quantum bits are unchanged and are arranged according to the sequence of the numbers from small to large, namely:
Figure FDA0002432802010000012
i is any integer between 1 and 2>inThe number of the code is correspondingly adjusted;
input quantum state | θ>inThe rewrite is: [ theta ]>in＝|q1q2...qi-1qi+1...qNqt>；q1、q2...qi-1、qi+1...qNFor cyclic bits, qiIs an operation bit;
the result of the direct product of the identity matrix is still the identity matrix, so the overall operation matrix U0The rewrite is:
Figure FDA0002432802010000021
2) for a two-qubit logic gate UijThe grouping principle is the same as that of a single-bit quantum logic gate, after the ijth quantum bit is shifted to the Nth quantum bit by the method, the positions of the rest quantum bits are unchanged and are arranged according to the sequence of the numbers from small to large, and the total operation matrix U0The rewrite is:
Figure FDA0002432802010000022
input quantum state | θ>inThe rewrite is: [ theta ]>in＝|q1q2...qi-1qt+1...qj-1qj+1...qNqiqj>；
q1、q2...qi-1、qi+1...qj-1qj+1...qNFor cyclic bits, qi、qjIs an operation bit;
3) similarly, the method extends to multi-bit qubit logic gate operations of more than three bits.
3. A low complexity quantum wire simulation system according to claim 1 or 2, wherein the step (3) is performed on the total operation matrix U0The order reduction method comprises the following steps:
1) for single quantum bit logic gates
Traversing the cyclic bits from 00.. 00 to 11.. 11 according to the number according to the arrangement result of the step (2), wherein the step length is 1; corresponding quantum logic gate calculation is carried out on the operation bits, specifically as follows:
Figure FDA0002432802010000023
wherein | q1q2...qi-1qi+1...qN0〉in，|q1q2...qi-1qi+1...qN1〉inRepresenting the input quantum state component as | q1q2...qi-1qf+1...qN0〉，|g1q2...qi-1qi+1...qN1 >;
|q1q2...qi-1qi+1...qN0〉out，|q1q2...qi-1qi+1...qN1〉outrepresenting the output quantum state component as | q1q2...qi-1qi+1...qN0>，|q1q2...qi-1qi+1...qN1 >;
therefore will 2N*2NIs reduced to 2N-12-2 matrix multiplication is carried out, and each 2-2 matrix is completed in sequence to obtain a result of an output quantum state;
2) for a double-quantum-bit logic gate, the order reduction method is the same as that of a single-quantum-bit logic gate;
outputting quantum state | theta > due to the grouping operation of step (2)out＝U*|θ〉inCan be used forRestated as: for q1q2...qi-1qi+1...qj-1qj+1...qN2. 0 to 11. 1 in totalN-2Cases, for each case, execution
Figure FDA0002432802010000031
Therefore will 2N*2NIs reduced to 2N-24-4 matrix multiplication is carried out, and each 4-4 matrix is completed in sequence to obtain a result of an output quantum state;
3) similarly, the method expands the operation of the qubit logic gate with more than three bits.
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