CN117519422A - Output stage circuit - Google Patents
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- CN117519422A CN117519422A CN202311569905.6A CN202311569905A CN117519422A CN 117519422 A CN117519422 A CN 117519422A CN 202311569905 A CN202311569905 A CN 202311569905A CN 117519422 A CN117519422 A CN 117519422A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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Abstract
The invention discloses an output stage circuit, which comprises: an output stage. The output stage includes: the device comprises a first following unit, a first output pipe, a sampling unit, a second following unit and a second output pipe. The first follower unit generates a first control voltage which follows the first input current variation; the control end of the first output pipe is used for receiving a first control voltage; the sampling unit generates a sampling current proportional to the current on the first output pipe; the second follower unit generates a second control voltage which follows the second input current and the sampling current; the control end of the second output pipe is used for receiving a second control voltage. According to the output stage circuit, when the power supply voltage is disturbed, the control end of the first output pipe is not easy to interfere, the high-frequency power supply rejection ratio performance can be optimized, and the rail-to-rail output swing is kept; the output stage circuit of the embodiment of the invention can support the use of a high-voltage environment, and compared with the traditional ClassAB, the output stage circuit has the advantages of no obvious cost increase, stronger structural conversion and no additional increase of power consumption.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an output stage circuit.
Background
The output structure of the ClassAB is widely applied to operational amplifier products because the output structure can realize the rail-to-rail output; with the improvement of chip integration, the requirement of transmission speed is improved, high-frequency disturbance on a power supply is more and more emphasized, and the high-frequency power supply rejection ratio (PSRR@high frequency) of the product is more and more required.
The power supply rejection ratio of the operational amplifier or the comparator with the traditional ClassAB output structure can be reduced from the position of the main pole of the operational amplifier or the comparator, and the main pole frequency is difficult to be high in design, so that the power supply rejection ratio of high frequency is not very high in general; selecting other output structures, and losing the output rail-to-rail advantage of ClassAB; it is valuable to design a ClassAB structure with excellent high frequency PSRR.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide an output stage circuit which achieves that the frequency point of which the power supply rejection ratio starts to drop is far higher than the frequency point of the main pole point of an operational amplifier or a comparator on the basis of the characteristic of retaining the ClassAB output, so as to obtain a high-frequency power supply rejection ratio.
To achieve the above object, an embodiment of the present invention provides an output stage circuit including: an output stage, the output stage comprising:
a first follower unit for generating a first control voltage that follows a change in the first input current based on the first input current;
the control end of the first output pipe is used for receiving a first control voltage;
the sampling unit is used for generating a sampling current proportional to the current on the first output tube based on the first control voltage;
a second follower unit for generating a second control voltage that follows a change in the second input current and the sampling current based on the second input current and the sampling current; and
the control end of the second output pipe is used for receiving second control voltage, the first end of the second output pipe is connected with the first end of the first output pipe to form an output end of the output stage circuit, and the second end of the first output pipe and the second end of the second output pipe are connected with power supply voltage and ground voltage respectively.
In one or more embodiments of the present invention, the first follower unit includes a first current source, a first transistor, and a second current source, the second terminal of the first transistor is configured to receive a first input current and simultaneously connected to the second current source, and the first terminal of the first transistor is connected to the first current source and configured to generate a first control voltage.
In one or more embodiments of the invention, the sampling unit comprises a second transistor, a control terminal of which is used for receiving the first control voltage to generate the sampling current on the second transistor.
In one or more embodiments of the present invention, the second follower unit includes a current mirror unit connected to the sampling unit to mirror the sampling current to generate the first current, and a current follower circuit to generate the second current varying with the second input current based on the second input current, the current mirror unit and the current follower circuit being simultaneously connected to the control terminal of the second output pipe to generate the second control voltage based on the first current and the second current.
In one or more embodiments of the present invention, the current mirror unit includes a first current mirror connected to the control terminals of the sampling unit, the current follower circuit, and the second output pipe to mirror the sampled current to generate a first current and generate a second control voltage in cooperation with the second current, or the first current mirror and the bias unit are connected to the first current mirror.
In one or more embodiments of the present invention, the first current mirror includes a third transistor and a fourth transistor, the bias unit includes a fifth transistor and a sixth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the third transistor is connected to the first terminal of the third transistor and to the control terminal of the current follower circuit and the second output pipe, the first terminal of the fourth transistor is connected to the sampling unit, the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor, the control terminal of the sixth transistor is connected to the first terminal of the fourth transistor or to the first terminal of the sixth transistor, the first terminal of the fifth transistor is connected to the second terminal of the third transistor, and the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor.
In one or more embodiments of the present invention, the first current mirror includes a third transistor and a fourth transistor, the bias unit includes a first resistor and a second resistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor and to the sampling unit, the first terminal of the third transistor is connected to the current follower circuit and the control terminal of the second output pipe, the second terminal of the third transistor is connected to the first resistor, and the second terminal of the fourth transistor is connected to the second resistor.
In one or more embodiments of the present invention, the current follower circuit includes a seventh transistor and a third current source, the second terminal of the seventh transistor is configured to receive the second input current and is connected to the third current source, and the first terminal of the seventh transistor is connected to the current mirror unit and the control terminal of the second output pipe.
In one or more embodiments of the present invention, the second follower unit further includes a second high voltage isolation unit disposed between the current mirror unit and the current follower circuit and between the current mirror unit and the sampling unit.
In one or more embodiments of the present invention, the first follower unit further includes a first high voltage isolation unit disposed between the first current source and the first transistor.
Compared with the prior art, according to the output stage circuit provided by the embodiment of the invention, the control end of the first output pipe and the control end of the second output pipe are respectively connected to two points, the two points are isolated by the high-resistance structure, when the power supply voltage is disturbed, the control end of the first output pipe is not easy to interfere, the high-frequency power supply rejection ratio performance can be optimized, and the rail-to-rail output swing amplitude is maintained; the output stage circuit of the embodiment of the invention can support the use of a high-voltage environment, and compared with the traditional ClassAB, the output stage circuit has the advantages of no obvious cost increase, stronger structural conversion and no additional increase of power consumption.
Drawings
Fig. 1 is a schematic circuit diagram of an output stage circuit according to an embodiment of the invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 1, an output stage circuit includes: the first follower unit 10, the sampling unit 20, the second follower unit, the first output pipe MN and the second output pipe MP. In one embodiment, the output stage circuit is an output stage circuit of an operational amplifier, and may also be an output stage circuit of a comparator.
The first follower unit 10 is configured to generate a first control voltage Va that follows a variation of the first input current Ia based on the first input current Ia; the control end of the first output tube MN is used for receiving a first control voltage Va; the sampling unit 20 is configured to generate a sampling current proportional to the current on the first output pipe MN based on the first control voltage Va. The second follower unit is used for generating a second control voltage Vb which follows the second input current Ib and the sampling current based on the second input current Ib and the sampling current; the control end of the second output tube MP is configured to receive the second control voltage Vb, the first end of the second output tube MP is connected to the first end of the first output tube MN to form an output end OUT of the output stage circuit, and the second end of the first output tube MN and the second end of the second output tube MP are respectively connected to the power supply voltage and the ground voltage.
The first output tube MN is an N-channel MOS tube, the control end of the first output tube MN is a grid electrode, the first end of the first output tube MN is a drain electrode, and the second end of the first output tube MN is a source electrode. The second output pipe MP is a P-channel MOS pipe, the control end of the second output pipe MP is a grid electrode, the first end of the second output pipe MP is a drain electrode, and the second end of the second output pipe MP is a source electrode.
In one embodiment, the operational amplifier with the output stage circuit further comprises an input stage, the input stage has two input stage positive terminals, the first input current Ia and the second input current Ib are respectively generated and changed simultaneously, the input stage further has an input stage negative terminal, and the current generated by the input stage negative terminal is equal to the sum of the first input current Ia and the second input current Ib. In other embodiments, the comparator with the output stage circuit also includes an input stage having two input stage positive terminals and one input stage negative terminal, the first input current Ia on the two input stage positive terminals is equal to the second input current Ib, and the sum of the current on the input stage negative terminal and the first input current Ia, the second input current Ib is a fixed value.
Specifically, the first follower cell 10 includes a first current source A1, a first high-voltage isolation cell, a first transistor M1, and a second current source A2. The first high voltage isolation unit includes a first high voltage tolerant pipe MV1. The second terminal of the first transistor M1 is configured to receive the first input current Ia and is simultaneously connected to a first terminal of the second current source A2, and the second terminal of the second current source A2 is connected to the ground voltage. The first end of the first transistor M1 is connected to the first end of the first high voltage tolerant tube MV1 and is used for generating the first control voltage Va, the second end of the first high voltage tolerant tube MV1 is connected to the first end of the first current source A1, and the second end of the first current source A1 is connected to the power supply voltage VDD.
In other embodiments, the first high-voltage isolation unit may not be provided if not applied in a high-voltage scenario.
The output stage further comprises a branch for receiving a current generated by the negative terminal of the input stage. The branch includes a fourth current source A4, a third high voltage isolation unit, an eighth transistor M8, and a fifth current source A5. The third high voltage isolation unit includes a second high voltage tolerant pipe MV2.
The first end of the fourth current source A4 is connected with the power supply voltage VDD, the second end of the fourth current source A4 is connected with the second end of the second high voltage resistant tube MV2, the first end of the second high voltage resistant tube MV2 is connected with the first end of the eighth transistor M8, the second end of the eighth transistor M8 is connected with the first end of the fifth current source A5 and receives current generated by the negative end of the input stage, and the second end of the fifth current source A5 is connected with the ground voltage.
In other embodiments, the third high-voltage isolation unit may not be provided if it is not applied in a high-voltage scenario.
It should be noted that each of the first current source A1, the fourth current source A4, and the additionally provided sixth current source A6 may be a current source composed of individual current mirrors; each current source may be formed by a single MOS transistor, so that the first current source A1 and the fourth current source A4 and a sixth current source A6 which is additionally arranged are connected in a common gate manner to form a current mirror, and the sixth current source A6 is simultaneously connected with the bias current Ibias provided by the previous stage, so that two mirror currents flowing to the first transistor M1 and the eighth transistor M8 respectively are mirrored on the first current source A1 and the fourth current source A4 based on the bias current Ibias. In this embodiment, it is preferable that the first current source A1, the fourth current source A4, and the sixth current source A6 are all composed of one MOS transistor.
As shown in fig. 1, the sampling unit 20 includes a second transistor M2, a control terminal of the second transistor M2 is connected to a first terminal of the first transistor M1, and the second transistor M2 is configured to receive the first control voltage Va to generate a sampling current on the second transistor M2. Since the control terminal of the first output tube MN also receives the first control voltage Va, and the second terminal of the first output tube MN and the second terminal of the second transistor M2 are both connected to the ground voltage, by adjusting the ratio of the width to length ratios of the first output tube MN and the second transistor M2, a sampling current proportional to the current on the first output tube MN can be generated on the second transistor M2.
As shown in fig. 1, the second follower unit includes a current mirror unit 31 and a current follower circuit 32. The current mirror unit 31 is connected to the sampling unit 20 to mirror the sampled current to generate a first current, and the current follower circuit 32 generates a second current that follows a change in the second input current Ib based on the second input current Ib. The current mirror unit 31 and the current follower circuit 32 are simultaneously connected to the control terminal of the second output pipe MP to generate the second control voltage Vb based on the first current and the second current.
Wherein the current mirror unit 31 comprises a first current mirror 311 and a biasing unit 312. The first current mirror 311 is connected to the sampling unit 20, the current follower circuit 32 and the control end of the second output tube MP to mirror the sampled current to generate a first current and cooperate with the second current to generate a second control voltage Vb, the bias unit 312 is connected to the first current mirror 311, and the bias unit 312 is used to make each MOS tube of the first current mirror 311 operate in a linear region. In other embodiments, the biasing unit 312 may not be provided in different application scenarios.
The first current mirror 311 includes a third transistor M3 and a fourth transistor M4, and the bias unit includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4, the control terminal of the third transistor M3 is connected to the first terminal of the third transistor M3 to generate the first current, the control terminal of the third transistor M3 is connected to the first terminal of the third transistor M3 and then connected to the current follower circuit 32 to generate the second control voltage Vb to the control terminal of the second output pipe MP, and the first terminal of the fourth transistor M4 is connected to the sampling unit 20. The control terminal of the fifth transistor M5 is connected to the control terminal of the sixth transistor M6 and to the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5 is connected to the second terminal of the third transistor M3, and the first terminal of the sixth transistor M6 is connected to the second terminal of the fourth transistor M4. In other embodiments, the control terminal of the fifth transistor M5 and the control terminal of the sixth transistor M6 may be connected to each other and then connected to the first terminal of the sixth transistor M6.
In other embodiments, the fifth transistor M5 may be replaced with a first resistor and the sixth transistor M6 may be replaced with a second resistor. At this time, the control terminal of the third transistor M3 is connected to the control terminal of the fourth transistor M4, the control terminal of the fourth transistor M4 is connected to the first terminal of the fourth transistor M4 and to the sampling unit 20, the first terminal of the third transistor M3 is connected to the current follower circuit 32 and the control terminal of the second output pipe MP, the second terminal of the third transistor M3 is connected to the first terminal of the first resistor, the second terminal of the fourth transistor M4 is connected to the first terminal of the second resistor, and the second terminals of the first resistor and the second resistor are connected to the power supply voltage VDD.
As shown in fig. 1, the current follower circuit 32 includes a seventh transistor M7 and a third current source A3. The second end of the seventh transistor M7 is configured to receive the second input current Ib and is connected to the first end of the third current source A3, the second end of the third current source A3 is connected to the ground voltage, and the first end of the seventh transistor M7 is connected to the current mirror unit 31 and the control end of the second output tube MP. The second current is generated on the seventh transistor M7.
In an embodiment, the second current source A2, the third current source A3 and the fifth current source A5 may be three separate current sources, or may be a current mirror formed by connecting three MOS transistors.
As shown in fig. 1, the second follower unit further includes a second high-voltage isolation unit 40 disposed between the current mirror unit 31 and the current follower circuit 32 and between the current mirror unit 31 and the sampling unit 20.
The second high voltage isolation unit 40 includes a third high voltage tolerant line MV3 and a fourth high voltage tolerant line MV4. The first end of the third high voltage resistant tube MV3 is connected with the first end of the third transistor M3 and the control end of the MP of the second output tube, and the first end of the fourth high voltage resistant tube MV4 is connected with the first end of the fourth transistor M4. The second terminal of the third high voltage tolerant transistor MV3 is connected to the first terminal of the seventh transistor M7, and the first terminal of the fourth high voltage tolerant transistor MV4 is connected to the first terminal of the second transistor M2. In other embodiments, the second high voltage isolation unit 40 may not be provided in a low voltage application scenario.
As shown in fig. 1, the output stage circuit further includes a first capacitor C1 and a second capacitor C2, where a first end of the first capacitor C1 is connected to the control end of the first output tube MN, a second end of the first capacitor C1 is connected to the first end of the first output tube MN, a first end of the second capacitor C2 is connected to the control end of the second output tube MP, and a second end of the second capacitor C2 is connected to the first end of the second output tube MP. The output of the output stage circuit can be stabilized by the first capacitor C1 and the second capacitor C2.
In an embodiment, the first transistor M1, the second transistor M2, the seventh transistor M7 and the second transistor M8 are N-channel MOS transistors, and the third high voltage tolerant transistor MV3 and the fourth high voltage tolerant transistor MV4 are N-channel high voltage tolerant MOS transistors.
The first end of the first transistor M1, the first end of the second transistor M2, the first end of the seventh transistor M7, and the first end of the second transistor M8 are drains, the second end of the first transistor M1, the second end of the second transistor M2, the second end of the seventh transistor M7, and the second end of the second transistor M8 are sources, and the control end of the first transistor M1, the control end of the second transistor M2, the control end of the seventh transistor M7, and the control end of the second transistor M8 are gates. The control terminal of the first transistor M1, the control terminal of the seventh transistor M7 and the control terminal of the second transistor M8 receive corresponding control voltages.
The first end of the third high-pressure resistant pipe MV3 and the first end of the fourth high-pressure resistant pipe MV4 are drain electrodes, the second end of the third high-pressure resistant pipe MV3 and the second end of the fourth high-pressure resistant pipe MV4 are source electrodes, and the control end of the third high-pressure resistant pipe MV3 and the control end of the fourth high-pressure resistant pipe MV4 are grid electrodes.
The third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are P-channel MOS transistors, and the first high voltage tolerant transistor MV1 and the second high voltage tolerant transistor MV2 are P-channel high voltage tolerant MOS transistors.
The first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, and the first terminal of the sixth transistor M6 are drains, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, and the second terminal of the sixth transistor M6 are sources, and the control terminal of the third transistor M3, the control terminal of the fourth transistor M4, the control terminal of the fifth transistor M5, and the control terminal of the sixth transistor M6 are gates.
The first end of the first high-pressure resistant pipe MV1 and the first end of the second high-pressure resistant pipe MV2 are drain electrodes, the second end of the first high-pressure resistant pipe MV1 and the second end of the second high-pressure resistant pipe MV2 are source electrodes, and the control end of the first high-pressure resistant pipe MV1 and the control end of the second high-pressure resistant pipe MV2 are grid electrodes.
The second current source A2, the fifth current source A5 and the third current source A3 are composed of N-channel MOS tubes, the first end of the second current source A2, the first end of the fifth current source A5 and the first end of the third current source A3 are drain electrodes, the second end of the second current source A2, the second end of the fifth current source A5 and the second end of the third current source A3 are source electrodes, and the control end of the second current source A2, the control end of the fifth current source A5 and the control end of the third current source A3 are grid electrodes.
The first current source A1, the fourth current source A4 and the sixth current source A6 are composed of MOS tubes with P channels. The first end of the first current source A1, the first end of the fourth current source A4 and the first end of the sixth current source A6 are drain electrodes, the second end of the first current source A1, the second end of the fourth current source A4 and the second end of the sixth current source A6 are source electrodes, and the control end of the first current source A1, the control end of the fourth current source A4 and the control end of the sixth current source A6 are gate electrodes.
In other embodiments, the N-channel MOS transistor may be replaced with a P-channel MOS transistor, and the P-channel MOS transistor may be replaced with an N-channel MOS transistor; or the MOS transistor is replaced by a corresponding triode.
As shown in fig. 1, a group of output pipes (a first output pipe MN and a second output pipe MP) at the output end OUT of the output stage circuit has the same output structure as the conventional ClassAB output structure, and the output still has a larger swing.
The magnitude of the current on the first output tube MN is determined by the first control voltage Va, and the magnitude of the first control voltage Va is mainly determined by the first input current Ia and the current on the first transistor M1.
The magnitude of the current on the second output pipe MP is determined by the second control voltage Vb, the magnitude of which is mainly determined by the current on the current mirror unit 31 and the current on the seventh transistor M7, the current on the seventh transistor M7 is mainly determined by the second input current Ib, and the current on the current mirror unit 31 is mainly determined by the current on the second transistor M2. The current on the second transistor M2 is determined by the first control voltage Va, and the ratio of the width to length of the second transistor M2 to the first output pipe MN is set so that a sampling current proportional to the current on the first output pipe MN and following the current variation on the first output pipe MN can be obtained on the second transistor M2.
In summary, the present invention maintains the large output swing while maintaining the large output swing in the optimized structure, fixes the quiescent current of the output stage, the control end of the first output tube MN is connected to the first end of the first transistor M1 of the first follower unit 10, the control end of the second output tube MP is connected to the first end of the third transistor M3 of the first current mirror 311, the control end of the first output tube MN and the control end of the second output tube MP are respectively connected to two points, and the two points are isolated by the high-resistance structure such as the current mirror unit 31, when the power supply voltage VDD is disturbed, the control end of the first output tube MN is not easily disturbed, so that the power supply rejection ratio of high frequency (such as 100 KHz) is optimized.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An output stage circuit, comprising:
a first follower unit for generating a first control voltage that follows a change in the first input current based on the first input current;
the control end of the first output pipe is used for receiving a first control voltage;
the sampling unit is used for generating a sampling current proportional to the current on the first output tube based on the first control voltage;
a second follower unit for generating a second control voltage that follows a change in the second input current and the sampling current based on the second input current and the sampling current; and
the control end of the second output pipe is used for receiving second control voltage, the first end of the second output pipe is connected with the first end of the first output pipe to form an output end of the output stage circuit, and the second end of the first output pipe and the second end of the second output pipe are connected with power supply voltage and ground voltage respectively.
2. The output stage circuit of claim 1 wherein the first follower element comprises a first current source, a first transistor and a second current source, the second terminal of the first transistor being for receiving a first input current and being coupled to the second current source at the same time, the first terminal of the first transistor being coupled to the first current source and for generating the first control voltage.
3. The output stage circuit of claim 1, wherein the sampling unit comprises a second transistor having a control terminal for receiving the first control voltage to generate the sampling current on the second transistor.
4. The output stage circuit of claim 1, wherein the second follower unit includes a current mirror unit coupled to the sampling unit to mirror the sampled current to generate the first current and a current follower circuit to generate a second current that follows a change in the second input current based on the second input current, the current mirror unit and the current follower circuit being coupled to the control terminal of the second output pipe simultaneously to generate the second control voltage based on the first current and the second current.
5. The output stage circuit of claim 4, wherein the current mirror unit comprises a first current mirror coupled to the control terminals of the sampling unit, the current follower circuit, and the second output tube to mirror the sampled current to generate the first current and to cooperate with the second current to generate the second control voltage, or a first current mirror coupled to the control terminals of the sampling unit, the current follower circuit, and the second output tube to generate the second control voltage.
6. The output stage circuit of claim 5, wherein the first current mirror comprises a third transistor and a fourth transistor, the bias unit comprises a fifth transistor and a sixth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the third transistor is connected to the first terminal of the third transistor and to the control terminal of the current follower circuit and the second output pipe, the first terminal of the fourth transistor is connected to the sampling unit, the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor, the control terminal of the sixth transistor is connected to the first terminal of the fourth transistor or to the first terminal of the sixth transistor, the first terminal of the fifth transistor is connected to the second terminal of the third transistor, and the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor.
7. The output stage circuit of claim 5, wherein the first current mirror comprises a third transistor and a fourth transistor, the bias unit comprises a first resistor and a second resistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, the control terminal of the fourth transistor is connected to the first terminal of the fourth transistor and to the sampling unit, the first terminal of the third transistor is connected to the current follower circuit and to the control terminal of the second output tube, the second terminal of the third transistor is connected to the first resistor, and the second terminal of the fourth transistor is connected to the second resistor.
8. The output stage circuit of claim 4 wherein the current follower circuit comprises a seventh transistor and a third current source, the second terminal of the seventh transistor being configured to receive the second input current and to be coupled to the third current source, the first terminal of the seventh transistor being coupled to the current mirror unit and to the control terminal of the second output pipe.
9. The output stage circuit of claim 4, wherein the second follower unit further comprises a second high voltage isolation unit disposed between the current mirror unit and the current follower circuit and between the current mirror unit and the sampling unit.
10. The output stage circuit of claim 2, wherein the first follower unit further comprises a first high voltage isolation unit disposed between the first current source and the first transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311569905.6A CN117519422A (en) | 2023-11-22 | 2023-11-22 | Output stage circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311569905.6A CN117519422A (en) | 2023-11-22 | 2023-11-22 | Output stage circuit |
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| CN117519422A true CN117519422A (en) | 2024-02-06 |
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| CN202311569905.6A Pending CN117519422A (en) | 2023-11-22 | 2023-11-22 | Output stage circuit |
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2023
- 2023-11-22 CN CN202311569905.6A patent/CN117519422A/en active Pending
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