CN117500270A

CN117500270A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN117500270A
Application number: CN202311840929.0A
Authority: CN
Inventors: 白王敏
Original assignee: Changxin Jidian Beijing Memory Technologies Co Ltd
Current assignee: Changxin Jidian Beijing Memory Technologies Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-02-02
Anticipated expiration: 2043-12-28
Also published as: CN117500270B

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor structure and a method for manufacturing the same. The manufacturing method of the semiconductor structure comprises the following steps: providing a base structure comprising a plurality of active regions; forming a plurality of bit line structures on the substrate structure; forming a first contact plug in contact with the active region between adjacent bit line structures; forming a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure; forming a plurality of isolation structures on the sacrificial layer, wherein gaps between adjacent isolation structures expose part of the top surface of the sacrificial layer; the sacrificial layer is removed and a conductive structure is formed at the location where the sacrificial layer is removed. The method and the device can avoid risks of damage to adjacent structures, poor appearance of the conductive structures, increased resistance of the conductive structures, serious electric leakage and the like caused by direct etching of the conductive materials, can effectively improve the appearance of the conductive structures, reduce the resistance and improve the electric leakage.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.

Background

A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in computers and is composed of a plurality of memory cells. With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. However, as the density of semiconductor devices increases, the size decreases, which makes the manufacturing process of the semiconductor devices more difficult, and thus results in a greatly reduced performance of the formed semiconductor devices.

Disclosure of Invention

Accordingly, a primary object of the present disclosure is to provide a semiconductor structure and a method for fabricating the same.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a base structure comprising a plurality of active regions; forming a plurality of bit line structures on the base structure; forming a first contact plug contacting the active region between adjacent bit line structures; forming a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure; forming a plurality of isolation structures on the sacrificial layer, wherein gaps between adjacent isolation structures expose part of the top surface of the sacrificial layer; and removing the sacrificial layer, and forming a conductive structure at the position where the sacrificial layer is removed.

In an alternative embodiment, forming a sacrificial layer on the first contact plug includes: forming a sacrificial material layer covering the first contact plug; flattening the sacrificial material layer to form the sacrificial layer; the top surface of the sacrificial layer is flush with the top surface of the bit line structure.

In an alternative embodiment, forming a plurality of isolation structures on the sacrificial layer includes: forming an isolation material layer on the sacrificial layer; forming a patterned mask layer on the isolation material layer; and removing part of the isolation material layer by using the patterned mask layer to form the isolation structure.

In an alternative embodiment, removing the sacrificial layer and forming a conductive structure at a location where the sacrificial layer is removed, includes: removing the sacrificial layer through gaps between adjacent isolation structures by utilizing a wet etching process to form a through hole exposing the top surface of the first contact plug; and filling conductive materials into the through holes and performing planarization treatment on the conductive materials to form the conductive structures.

In an alternative embodiment, the method for manufacturing the semiconductor structure further includes: depositing an insulating material into the via prior to filling the conductive material into the via;

And removing the insulating material at the bottom of the through hole to form an insulating layer positioned on the side wall of the through hole.

In an alternative embodiment, the material of the first contact plug comprises a semiconductor material; the manufacturing method of the semiconductor structure further comprises the following steps: before filling the conductive material into the through hole, a metallization process is performed on the top surface of the first contact plug.

In an alternative embodiment, forming a plurality of bit line structures on the base structure includes: forming a second contact plug, a bit line and a cover layer which are stacked on the substrate structure in sequence; sequentially forming a first dielectric layer, a second dielectric material layer and a third dielectric material layer which cover the side walls of the second contact plug, the bit line and the cover layer; removing part of the second dielectric material layer and part of the third dielectric material layer, and forming a second dielectric layer and a third dielectric layer by the rest of the second dielectric material layer and the rest of the third dielectric material layer; the top surfaces of the second dielectric layer and the third dielectric layer are higher than the top surfaces of the bit lines, and the top surfaces of the second dielectric layer and the third dielectric layer are inclined surfaces.

In an alternative embodiment, the etching selectivity of the material of the sacrificial layer to the material of the isolation structure is different.

The embodiment of the disclosure also provides a semiconductor structure, which comprises: a base structure including a plurality of active regions; a plurality of bit line structures on the base structure; a plurality of isolation structures, wherein the bottom surfaces of the isolation structures and the top surfaces of the bit line structures are positioned at the same height, and the isolation structures at least cover part of the top surfaces of the bit line structures; a plurality of first contact plugs located between the bit line structures and contacting the active region; and the conductive structures are positioned on the first contact plug and positioned between the adjacent bit line structures and between the adjacent isolation structures.

In an alternative embodiment, the conductive structure includes a first portion located between adjacent bit line structures and a second portion located between adjacent isolation structures, the first portion and the second portion having different widths at their junctions.

In an alternative embodiment, the first portion has a greater radial width at the interface than the second portion.

In an alternative embodiment, the semiconductor structure further includes: an insulating layer including a first insulating layer between the bit line structure and the first portion and a second insulating layer between the isolation structure and the second portion.

In an alternative embodiment, the bit line structure includes: the second contact plug, the bit line and the cover layer are stacked in sequence; a first dielectric layer, a second dielectric layer and a third dielectric layer covering the sidewalls of the second contact plug, the bit line and the cap layer; the top surfaces of the second dielectric layer and the third dielectric layer are higher than the top surface of the bit line, and the top surfaces of the second dielectric layer and the third dielectric layer are inclined surfaces; wherein, the density of the cover layer is greater than the density of the isolation structure, and the density of the first medium layer is greater than the density of the isolation structure.

In an alternative embodiment, the semiconductor structure further comprises a word line structure in the base structure; the word line structure passes through a portion of the active region; the bit line structure covers part of the active region; the projection of the bit line structure on the surface of the base structure is intersected with the projection of the word line structure on the surface of the base structure to form a grid; the projection of the first contact plug on the surface of the base structure is positioned in the grid holes surrounded by the grid bars.

In an alternative embodiment, the active region includes a first source/drain region in the middle and a second source/drain region at both ends; the projection of the word line structure on the surface of the substrate structure is positioned between the first source/drain region and the second source/drain region; the projection of the bit line structure on the surface of the substrate structure covers part of the first source/drain region and is electrically connected with the first source/drain region; the first contact plug is electrically connected with the second source/drain region.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a base structure comprising a plurality of active regions; forming a plurality of bit line structures on the substrate structure; forming a first contact plug in contact with the active region between adjacent bit line structures; forming a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure; forming a plurality of isolation structures on the sacrificial layer, wherein gaps between adjacent isolation structures expose part of the top surface of the sacrificial layer; the sacrificial layer is removed and a conductive structure is formed at the location where the sacrificial layer is removed. In the embodiment of the disclosure, the isolation structures are formed on the sacrificial layers, the sacrificial layers are removed through the gaps between the adjacent isolation structures, so that the forming positions of the conductive structures are reserved, and then the conductive structures are formed at the reserved positions. Further, by forming the sacrificial layer and the isolation structure in advance, the conductive structure is formed at the position where the sacrificial layer is removed, isolation between the conductive structures can be achieved without adopting an etching process, risks of damage to adjacent structures, poor appearance of the conductive structure, increased resistance of the conductive structure, serious electric leakage and the like caused by direct etching of the conductive material can be avoided, the appearance of the conductive structure can be effectively improved, the resistance is reduced, the electric leakage is improved, and therefore the performance of a semiconductor device where the semiconductor structure is located is improved.

Drawings

FIG. 1 is a schematic top view of a portion of a semiconductor structure formed in an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of the structure at bb' in FIG. 1 obtained in step S1 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of the structure at bb' in FIG. 1 obtained in step S2 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view of the structure at bb' in FIG. 1 obtained in step S3 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5 is an enlarged schematic view of area A of FIG. 4;

fig. 6 is a schematic implementation flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 7 is a schematic top view of a portion of a semiconductor structure formed in another embodiment of the present disclosure;

FIG. 8A is a schematic cross-sectional view of the structure aa' in FIG. 7, which is obtained in steps S10-S30 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 8B is a schematic cross-sectional view of the structure at bb' in fig. 7 obtained in steps S10 to S30 in the method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 8C is a schematic cross-sectional view of the structure at cc' in FIG. 7, obtained in steps S10-S30 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 8D is a schematic cross-sectional view of the structure dd' in fig. 7 obtained in steps S10 to S30 in the method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 8E is an enlarged schematic view of area B of FIG. 8B;

FIG. 9A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming a sacrificial material layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 9B is a schematic cross-sectional view of a structure obtained by forming a sacrificial material layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure at bb' in fig. 7;

FIG. 9C is a schematic cross-sectional view of the structure at cc' in FIG. 7, resulting from the formation of the sacrificial material layer in step S40 in a method of fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 9D is a schematic cross-sectional view of the structure dd' in fig. 7, which is obtained by forming a sacrificial material layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 10A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming a sacrificial layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

Fig. 10B is a schematic cross-sectional view of a structure obtained by forming a sacrificial layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure at bb' in fig. 7;

FIG. 10C is a schematic cross-sectional view of the structure at cc' in FIG. 7, obtained by forming a sacrificial layer in step S40 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 10D is a schematic cross-sectional view of the structure dd' in fig. 7, which is obtained by forming a sacrificial layer in step S40 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 11A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming an isolation material layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 11B is a schematic cross-sectional view of a structure obtained by forming an isolation material layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure at bb' in fig. 7;

FIG. 11C is a schematic cross-sectional view of the structure at cc' in FIG. 7, which is obtained by forming the isolation material layer in step S50 in the method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 11D is a schematic cross-sectional view of a structure obtained by forming an isolation material layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure, at dd' in fig. 7;

FIG. 12A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming a patterned mask layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 12B is a schematic cross-sectional view of a structure at bb' in fig. 7, which is obtained by forming a patterned mask layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 12C is a schematic cross-sectional view of the structure at cc' in FIG. 7, which is obtained by forming a patterned mask layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 12D is a schematic cross-sectional view of a structure dd' in fig. 7, which is obtained by forming a patterned mask layer in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 13A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming isolation structures in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 13B is a schematic cross-sectional view of a structure obtained by forming an isolation structure in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure at bb' in fig. 7;

FIG. 13C is a schematic cross-sectional view of the structure at cc' in FIG. 7, which is obtained by forming isolation structures in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

Fig. 13D is a schematic cross-sectional view of a structure dd' in fig. 7, which is obtained by forming an isolation structure in step S50 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 14A is a schematic cross-sectional view of a semiconductor structure at aa' in FIG. 7, which is obtained by forming a via hole in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 14B is a schematic cross-sectional view of a structure obtained by forming a via hole in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure, at bb' in fig. 7;

fig. 14C is a schematic cross-sectional view of a structure at cc' in fig. 7, which is obtained by forming a through hole in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 14D is a schematic cross-sectional view of a structure dd' in fig. 7, which is obtained by forming a through hole in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

FIG. 15A is a schematic cross-sectional view of a structure aa' in FIG. 7, which is obtained by forming a conductive structure in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 15B is a schematic cross-sectional view of a structure obtained by forming a conductive structure in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure, at bb' in fig. 7;

Fig. 15C is a schematic cross-sectional view of a structure obtained by forming a conductive structure in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure, at cc' in fig. 7;

fig. 15D is a schematic cross-sectional view of a structure dd' in fig. 7, which is obtained by forming a conductive structure in step S60 in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 16 is a schematic cross-sectional view of a process step for forming a conductive structure in a via according to another embodiment of the present disclosure;

fig. 17 is a schematic cross-sectional view of a second process step for forming a conductive structure in a via according to another embodiment of the present disclosure;

fig. 18 is a schematic cross-sectional view III of a process step for forming a conductive structure in a via according to another embodiment of the present disclosure;

fig. 19 is an enlarged schematic view of the region D in fig. 15B.

Detailed Description

The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the description that follows. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.

Fig. 1 is a schematic top view of a portion of a semiconductor structure according to an embodiment of the disclosure, fig. 2 to 5 are schematic cross-sectional views of main process steps in forming the semiconductor structure according to an embodiment of the disclosure, and fig. 5 is an enlarged schematic view of a region a in fig. 4. The method for manufacturing the semiconductor structure of the present embodiment is described below with reference to fig. 1 and fig. 2 to 5.

Here and below, the first direction may be a direction in which the word line extends, the second direction may be a direction in which the bit line extends, and the third direction may be a direction in which the active region extends. The first direction, the second direction, and the third direction are all parallel to the top surface of the substrate. In some embodiments, the first direction is perpendicular to the second direction. Illustratively, the first direction may be an extending direction of the D1 axis shown in the drawings, and the second direction may be an extending direction of the D2 axis shown in the drawings. The third direction D3 is inclined by a preset angle with respect to the first direction D1, and a specific value of the preset angle may be set according to actual needs, for example, the preset angle may be greater than or equal to 20 degrees and less than 90 degrees. The fourth direction is parallel to the thickness direction of the substrate. The first direction, the second direction and the third direction are all perpendicular to the fourth direction. The fourth direction may be, for example, an extending direction of the D4 axis shown in the drawings.

As shown in fig. 1, the semiconductor structure includes a substrate structure, wherein the substrate structure includes a plurality of active regions 111 arranged in an array, and a plurality of word line structures 120 extending along a first direction D1 and spaced apart along a second direction D2. The plurality of active regions 111 are isolated from each other by the first insulating structure 110. Illustratively, the material of the first insulating structure 110 may be silicon oxide, silicon oxynitride, or other suitable insulating material, and the first insulating structure 110 may be a shallow trench isolation (Shallow Trench Isolation, STI) structure.

In some embodiments, each active region 111 extends along the third direction D3. The preset angle of inclination of the third direction D3 with respect to the first direction D1 may be greater than or equal to 20 degrees and less than 90 degrees.

In some embodiments, the semiconductor structure further includes a plurality of bit line structures 130 located on the base structure and extending along the second direction D2. The second direction D2 is perpendicular to the first direction D1.

In some embodiments, the base structure further comprises a substrate (not shown in fig. 1) on which the plurality of active regions 111 are located.

It should be noted that, in order to more clearly show the positional relationship among the word line structure, the bit line structure and the active region, the word line structure and the bit line structure in fig. 1 are perspective effects.

Referring to fig. 1 and 2 to 5, the method of fabricating the semiconductor structure is as follows.

As shown in fig. 2, step S1 is performed to provide a substrate structure and form a plurality of bit line structures 130 on the substrate structure; forming a capacitance contact plug 150 in contact with the active region 111 between adjacent bit line structures 130; a conductive layer 140 is formed on the capacitive contact plug 150.

As shown in fig. 2, the base structure includes a substrate 101, and a plurality of active regions 111 are located on the substrate 101. The conductive layer 140 includes a metal nitride material layer 1401 and a metal material layer 1402. Illustratively, the material of the capacitive contact plug 150 is polysilicon, the material of the metal nitride material layer 1401 includes, but is not limited to, tungsten nitride, and the material of the metal material layer 1402 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), and the like.

As shown in fig. 3, step S2 is performed to form a patterned mask structure 160 on the conductive layer 140. The material of the mask structure 160 includes at least one of Photoresist (PR), spin On Hard mask (SOH), and silicon oxynitride (SiON). The mask structure 160 may be a single layer mask or a multi-layer composite mask, alternatively, the mask structure 160 is a multi-layer composite mask as shown in fig. 3.

Referring to fig. 3 to 4, step S3 is performed to remove a portion of the conductive layer 140 using the patterned mask structure 160, thereby forming a conductive plug 170, the conductive plug 170 including a metal nitride layer 1403 and a metal layer 1404. In some embodiments, a plasma etch process may be used to remove portions of conductive layer 140. Illustratively, a gas containing chlorine (Cl) or fluorine (F) is used as an etching source to remove a portion of the conductive layer 140.

Since the conductive layer 140 of fig. 2 covers the bit line structure 130, a plasma etch process is typically required to remove a portion of the conductive layer 140 of fig. 2 to avoid shorting in a subsequent process, and the resulting conductive plug 170 is typically formed by a high energy ion bombardment as shown in fig. 5, which may cause other structures (e.g., the isolation material 131 in the bit line structure 130) to change, compromising its performance. Further, the etching gas of the plasma etching process generally contains chemical substances such as fluoride or chloride, which react with the isolation material 131 in the bit line structure 130 in the reaction process, and generate unavoidable damage to the bit line structure 130, so as to cause electric leakage and seriously affect the stability of the semiconductor device formed later.

In addition, when the plasma etching process is used to remove a portion of the conductive layer 140, etching defects are easily formed, so that burrs, protrusions or roughness may exist on the sidewall surface of the formed conductive plug 170, and the poor sidewall surface morphology (profile) of the conductive plug 170 may increase resistance and cause leakage, which seriously affects the performance of the semiconductor device.

To this end, embodiments of the present disclosure provide a semiconductor structure and a method of fabricating the same. Fig. 6 is a schematic flowchart of a specific implementation of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 6, the method for manufacturing the semiconductor structure specifically includes the following steps:

step S10: a base structure is provided, the base structure including a plurality of active regions.

Step S20: a plurality of bit line structures are formed on the substrate structure.

Step S30: a first contact plug is formed between adjacent bit line structures to contact the active region.

Step S40: forming a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure.

Step S50: a plurality of isolation structures are formed on the sacrificial layer, and gaps between adjacent isolation structures expose a portion of the top surface of the sacrificial layer.

Step S60: the sacrificial layer is removed and a conductive structure is formed at the location where the sacrificial layer is removed.

Fig. 7 is a schematic top view of a portion of a semiconductor structure according to another embodiment of the present disclosure, and fig. 8A to 15D are schematic cross-sectional views of main process steps in forming the semiconductor structure according to another embodiment of the present disclosure, wherein fig. 8E is an enlarged schematic view of a region B in fig. 8B. The method of fabricating the semiconductor structure of the present embodiment is described below with reference to fig. 7 and fig. 8A to 15D.

Steps S10 to S30 are performed in conjunction with fig. 7 and 8A, 8B, 8C, and 8D.

Step S10 is performed to provide a substrate structure including a plurality of active regions.

In some embodiments, the substrate structure includes a plurality of active regions 211 arranged in an array, and a plurality of word line structures 220 extending in the first direction D1 and spaced apart in the second direction D2. The plurality of active regions 211 are isolated from each other by a second insulating structure 210. As shown in fig. 8A, the second insulating structure 210 includes a first sub-insulating structure 2101 and a second sub-insulating structure 2102.

Illustratively, the material of the second insulating structure 210 may be silicon oxide, silicon oxynitride, or other suitable insulating material, and the second insulating structure 210 may be an STI structure.

Optionally, the material of the first sub-insulating structure 2101 is silicon nitride, and the material of the second sub-insulating structure 2102 is silicon oxide.

Illustratively, the word line structure 220 includes a word line including a gate dielectric layer 2201 and a gate layer 2203, and an overlayer 2204 over the word line. Illustratively, the material of the capping layer 2204 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and the like. The material of gate dielectric layer 2201 includes, but is not limited to, silicon oxide. The material of the gate layer 2203 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), and the like.

In some embodiments, the word line also includes a liner 2202. Illustratively, a liner layer 2202 is optionally formed on the surface of the gate dielectric layer 2201 prior to forming the gate layer 2203. The material of the liner 2202 is, for example, titanium nitride, tungsten nitride, or tantalum nitride.

Here, the Word Line may be a Buried Word Line (BWL), and the integration level of the semiconductor device in which the semiconductor structure is located may be increased.

In some embodiments, each active region 211 extends along the third direction D3.

As shown in fig. 8A, 8B, 8C, and 8D, the base structure further includes a substrate 201, and a plurality of active regions 211 are located on the substrate 201. Illustratively, the substrate 201 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator (Silicon On Insulator, SOI) substrate, a germanium-on-insulator (Germanium On Insulator, GOI) substrate, or the like, may also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a group III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate, or the like), may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as silicon-on-insulator germanium (Silicon Germanium On Insulator, SGOI), or the like.

Step S20 is performed to form a plurality of bit line structures on the substrate structure.

Referring to fig. 8A, 8B, 8C, 8D, and 8E, in some embodiments, forming the plurality of bit line structures 230 on the base structure includes: forming a second contact plug 231, a bit line 235, and a cap layer 236 in sequence on the substrate structure; sequentially forming a first dielectric layer 239, a second dielectric material layer and a third dielectric material layer which cover the sidewalls of the second contact plug 231, the bit line 235 and the cap layer 236; removing a portion of the second dielectric material layer and a portion of the third dielectric material layer, the remaining second dielectric material layer and the remaining third dielectric material layer forming a second dielectric layer 238 and a third dielectric layer 237; the top surface of the second dielectric layer 238 and the top surface of the third dielectric layer 237 are higher than the top surface of the bit line 235, and the top surface of the second dielectric layer 238 and the top surface of the third dielectric layer 237 are sloped surfaces.

The first dielectric layer 239, the second dielectric layer 238 and the third dielectric layer 237 form isolation spacers, and the cap layer 236 and the isolation spacers form bit line isolation structures for isolating adjacent bit lines. Because the top surface of the second dielectric layer 238 and the top surface of the third dielectric layer 237 in the isolation sidewall are inclined surfaces, the gap between the adjacent cover layers 236 can be increased, conductive materials can be deposited to the gap between the adjacent cover layers 236 in the subsequent process, the formation of voids in the conductive materials can be prevented, and the reduction of the conductive performance is avoided.

In some embodiments, bit line 235 includes a first conductive layer 232, a connection layer 233, and a second conductive layer 234. In some embodiments, the material of the first conductive layer 232 includes, but is not limited to, polysilicon, the material of the connection layer 233 includes, but is not limited to, titanium nitride, and the material of the second conductive layer 234 includes, but is not limited to, tungsten, tantalum, and titanium.

In some embodiments, the material of the second contact plug 231 includes, but is not limited to, polysilicon.

In some embodiments, the material of cap layer 236 includes silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable materials.

In some embodiments, the material of first dielectric layer 239 and third dielectric layer 237 comprises silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and second dielectric layer 238 comprises silicon nitride, silicon oxynitride, or any combination thereof. First dielectric layer 239 and third dielectric layer 237 may be the same or different. Optionally, the material of the first dielectric layer 239 and the third dielectric layer 237 is silicon nitride, and the material of the second dielectric layer 238 is silicon oxide.

In some embodiments, the bit line structures 230 extend along the second direction D2 and are spaced apart along the first direction D1. The second direction D2 is perpendicular to the first direction D1.

The material of the first dielectric layer 239, the material of the second dielectric layer 238, the material of the third dielectric layer 237, and the material of the cap layer 236 may be the same or different, and in fig. 8E, the material of the first dielectric layer 239, the material of the second dielectric layer 238, the material of the third dielectric layer 237, and the material of the cap layer 236 are illustrated as examples in order to more clearly illustrate the positional relationship of the respective portions in the bit line structure. Fig. 8B illustrates an example in which the material of the first dielectric layer is the same as that of the capping layer.

In some embodiments, the top surface of first dielectric layer 239 is flush with the top surface of cap layer 236, which are the same material. After forming first dielectric layer 239 and cap layer 236, both may be ion doped to increase the density of first dielectric layer 239 and cap layer 236 and to increase the etch resistance of first dielectric layer 239 and cap layer 236.

Step S30 is performed to form a first contact plug in contact with the active region between adjacent bit line structures.

Referring to fig. 8A, 8B, 8C, and 8D, in some embodiments, forming a first contact plug 240 in contact with an active region between adjacent bit line structures, includes: a first conductive material layer is formed between adjacent bit line structures, and the first conductive material layer is etched back to a predetermined height to form a first contact plug 240. Illustratively, the first conductive material layer is etched back to be flush with the top of the second conductive layer 234 in the bit line structure, forming a first contact plug 240. The process of etching back the first conductive material layer includes, but is not limited to, a wet etching process.

Referring to fig. 9A to 10D, step S40 is performed to form a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure.

As shown in fig. 9A, 9B, 9C, and 9D, a sacrificial material layer 250 is formed to cover the first contact plug 240. Illustratively, the material of the sacrificial material layer 250 includes, but is not limited to, polysilicon.

In some embodiments, the process of forming the sacrificial material layer 250 may include any process known in the art, including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), sputtering (sputtering), atomic layer deposition (Atomic Layer Deposition, ALD).

As shown in fig. 10A, 10B, 10C, and 10D, the sacrificial material layer is planarized to form a sacrificial layer. Because the top surface of the sacrificial layer is not higher than the top surface of the bit line structure, the mutual connection between the sacrificial layers can be ensured not to occur, thereby avoiding damage to other structures (such as a cover layer in the bit line structure) when the sacrificial layers are separated by adopting an etching process (such as a plasma etching process).

In some embodiments, as shown in fig. 10B and 10D, the top surface of the sacrificial layer 260 is flush with the top surface of the bit line structure 230. Illustratively, the sacrificial layer 260 is formed by planarizing the sacrificial material layer by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process.

Note that, since the top surface of the sacrificial layer 260 shown in fig. 10B and 10D is flush with the top surface of the bit line structure 230, the sacrificial layer cannot be observed in the cross-sectional schematic diagrams of fig. 10A and 10C.

In other embodiments, after the planarization treatment is performed on the sacrificial material layer, the sacrificial material layer is etched back further, so that the top surface of the formed sacrificial layer is lower than the top surface of the bit line structure, and when the isolation material layer is deposited on the sacrificial layer in the subsequent process, the isolation material layer is also deposited between the adjacent bit line structures, so that the isolation effect on the adjacent bit lines can be further improved. Illustratively, after planarizing the sacrificial material layer, the sacrificial material layer is further etched back using a wet etch process such that a top surface of the sacrificial layer is formed below a top surface of the bit line structure. Since the etch source is highly selective to the material of the sacrificial material layer compared to silicon nitride, it does not damage other adjacent materials (e.g., bit line structures).

Referring to fig. 11A to 11D, step S50 is performed to form a plurality of isolation structures on the sacrificial layer.

Referring to fig. 11A, 11B, 11C, and 11D, an isolation material layer 270 is formed on the sacrificial layer. The isolation material layer 270 may be formed by a deposition process, such as CVD, PVD, ALD, or any combination thereof. The material of the isolation material layer 270 includes, but is not limited to, silicon nitride.

Referring to fig. 12A, 12B, 12C, and 12D, a patterned mask layer 280 is formed on the isolation material layer 270. Illustratively, the patterned mask layer 280 is a single layer mask or a multi-layer composite mask, and the material of the patterned mask layer 280 includes, but is not limited to, photoresist, spin-on hard mask, silicon oxynitride, and the like.

The patterned mask layer 280 may be formed using a Self-aligned double patterning (Self-Aligned Double Patterning, SADP) process, a Self-aligned reverse patterning (Self-Aligned Reverse Patterning, SARP) process, or a Self-aligned quad patterning (Self-Aligned Quadruple Patterning, SARP) process.

Referring to fig. 13A, 13B, 13C, and 13D, a portion of the isolation material layer is removed using the patterned mask layer 280 to form an isolation structure 300. The gaps 301 between adjacent isolation structures 300 expose portions of the top surface of the sacrificial layer 260.

As shown in fig. 8E and 13B, in some embodiments, portions of cap layer 236 and portions of first dielectric layer 239 are also exposed when isolation structure 300 is formed (without ion doping). Because the capping layer 236 and the first dielectric layer 239 are both ion doped, the ion doping concentration of the capping layer 236 and the first dielectric layer 239 is greater than that of the isolation structure 300, so that the density of the capping layer 236 and the density of the first dielectric layer 239 are both greater than that of the isolation structure 300, and when part of the isolation material layer is removed to form the isolation structure 300, the capping layer 236 and the first dielectric layer 239 have good etching resistance, and the capping layer 236 and the first dielectric layer 239 can be ensured to have complete shapes. The doping elements of cap layer 236 and first dielectric layer 239 are, for example, germanium or argon elements.

In some embodiments, cap layer 236 and first dielectric layer 239 may also be annealed to increase the density of both.

Referring to fig. 14A to 15D, step S50 is performed to remove the sacrificial layer and form a conductive structure at a location where the sacrificial layer is removed.

Referring to fig. 14A, 14B, 14C, and 14D, the sacrificial layer is removed by a wet etching process through the gaps between the adjacent isolation structures 300, forming a via hole 302 exposing the top surface of the first contact plug. In some embodiments, the etch selectivity of the material of the sacrificial layer to the material of the isolation structure is different.

Illustratively, the material of the sacrificial layer is polysilicon and the material of the isolation structure is silicon nitride. In the process of removing the sacrificial layer to form the through hole by utilizing the wet etching process, the etching source has high selectivity to the material of the sacrificial layer compared with silicon nitride, so that other adjacent materials (such as an isolation structure, a bit line structure and the like) are not damaged.

Referring to fig. 15A, 15B, 15C, and 15D, a conductive material is filled in the via hole and a planarization process is performed on the conductive material, forming a conductive structure 310. The conductive material is filled in the through holes and flattened, so that isolation among formed conductive structures is successfully realized, and risks of damage to adjacent structures, poor appearance of the conductive structures, increased resistance of the conductive structures, serious electric leakage and the like caused by directly etching the conductive material to form the conductive structures are avoided.

In some embodiments, the process by which the conductive material is formed may include, but is not limited to, pulse nucleation layers (Pulse nucleation layer, PNL), CVD, PVD, ALD, or any combination thereof. The conductive material includes, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni).

Illustratively, the ALD process is used to fill the titanium nitride layer 3102 into the via, the titanium nitride layer 3102 covers the inner wall of the via and the top surface of the first contact plug 240, and the PNL process in combination with the CVD process is continued to fill the deposited tungsten (W) layer 3101 into the via, with the tungsten (W) layer 3101 covering the surface of the titanium nitride layer 3102 and filling the via.

Illustratively, the conductive material is planarized by a CMP process to form conductive structures 310.

Fig. 16-18 are schematic cross-sectional views illustrating a process step of forming a conductive structure in a via according to another embodiment of the present disclosure. It should be noted that fig. 16 to fig. 18 are enlarged schematic views of the positions corresponding to the region C in fig. 14B in different process steps of forming the conductive structures in the through holes. This process step will be described below in connection with fig. 14B, 16-18.

In some embodiments, the method for fabricating a semiconductor structure further includes: depositing an insulating material into the via prior to filling the conductive material into the via; and removing the insulating material at the bottom of the through hole to form an insulating layer positioned on the side wall of the through hole. Illustratively, in conjunction with fig. 14B and 16, an insulating material 303 is deposited into the via 302. The insulating material 303 may be formed by a deposition process, such as CVD, PVD, ALD, or any combination thereof. Illustratively, the insulating material 303 includes, but is not limited to, silicon oxide.

Referring to fig. 14B, 16 and 17, the insulating material 303 at the bottom of the via 302 is removed, exposing a portion of the top surface of the first contact structure 240, to form an insulating layer 304 on the sidewall of the via 302. In this way, the resistance capacitance delay caused by parasitic capacitance can be further reduced.

Referring to fig. 18, a conductive material is filled into the via hole formed with the insulating layer and a planarization process is performed on the conductive material, forming a conductive structure 310. The conductive material includes a titanium nitride layer 3102 and a tungsten layer 3101, wherein the titanium nitride layer 3102 covers the inner wall of the insulating layer and the top surface of the first contact plug 240, and the tungsten layer 3101 covers the titanium nitride layer 3102 and fills the via hole.

Illustratively, the conductive structure 310 includes a first portion 310-1 located between adjacent bit line structures 230 and a second portion 310-2 located between adjacent isolation structures 300. The insulating layers include a first insulating layer 304-1 between the bit line structure 230 and the first portion 310-1 and a second insulating layer 304-2 between the isolation structure 300 and the second portion 310-2. In some embodiments, the material of the first contact plug comprises a semiconductor material; the manufacturing method of the semiconductor structure further comprises the following steps: before filling the conductive material into the via hole, a metallization process is performed on the top surface of the first contact plug. Illustratively, the material of the first contact plug is polysilicon, cobalt (Co) is deposited in the via, and a metallization process is performed on the top surface of the first contact plug using a rapid thermal process (Rapid Thermal Processing, RTP) to achieve a half-ohm contact, reducing the contact resistance of other structures formed in subsequent processes in contact with the first contact plug.

After the metallization process is performed on the top surface of the first contact plug, the remaining cobalt (Co) is removed by a wet etching process and then the conductive material is filled into the via hole.

According to the embodiment of the disclosure, the isolation structure is formed on the sacrificial layer, the sacrificial layer is removed through the gap of the isolation structure, so that the forming position of the conductive structure is reserved, and then the conductive structure is formed at the reserved position. Further, by forming the sacrificial layer and the isolation structure in advance, the conductive structure is formed at the position where the sacrificial layer is removed, isolation between the conductive structures can be achieved without adopting an etching process, risks of damage to adjacent structures, poor appearance of the conductive structure, increased resistance of the conductive structure, serious electric leakage and the like caused by direct etching of the conductive material can be avoided, the appearance of the conductive structure can be effectively improved, the resistance is reduced, the electric leakage is improved, and therefore the performance of a semiconductor device where the semiconductor structure is located is improved.

Furthermore, the conductive material is filled into the through hole in a mode of combining the PNL process and the CVD process, so that defects such as gaps in the filling process can be reduced, and the product yield is improved.

In addition, orthographic projections of the plurality of conductive structures on the substrate structure are arranged in a hexagonal close-packed mode, and the integration level of the semiconductor device where the semiconductor structure is located is improved.

The embodiment of the disclosure also provides a semiconductor structure. Fig. 19 is an enlarged schematic view of the region D in fig. 15B. Referring to fig. 7, 15A to 15D, and 19, the semiconductor structure includes: a base structure comprising a plurality of active regions 211; a plurality of bit line structures 230 on the substrate structure; a plurality of isolation structures 300, wherein the bottom surface of the isolation structures 300 and the top surface of the bit line structure 230 are located at the same height, and the isolation structures 300 at least cover part of the top surface of the bit line structure 230; a plurality of first contact plugs 240 located between the bit line structures 230 and contacting the active regions 211; the plurality of conductive structures 310, the conductive structures 310 are located on the first contact plugs 240, and are located between adjacent bit line structures 230 and between adjacent isolation structures 300.

Since the bottom surface of the isolation structure 300 is at the same level as the top surface of the bit line structure 230, the top surface of the portion of the conductive structure 310 between adjacent bit line structures 230 may be at the same level as the top surface of the bit line structure 230, and thus the top surface area of the portion of the conductive structure 310 between adjacent bit line structures 230 increases, which helps to reduce the overall resistance of the conductive structure 310. Furthermore, the isolation structure 300 at least covers part of the top surface of the bit line structure 230, so that adjacent bit line structures 230 and adjacent isolation structures 300 together form an isolation barrier of the conductive structures 310, and the conductive structures 310 are not connected with each other, so that effective isolation of the adjacent conductive structures 310 can be realized without performing an additional etching process, and the problem of short circuit of the adjacent conductive structures 310 is avoided, thereby improving the stability of the semiconductor device where the semiconductor structure is located.

In some embodiments, referring to fig. 15A-15D and 19, the conductive structure 310 includes a first portion 310-1 located between adjacent bit line structures 230 and a second portion 310-2 located between adjacent isolation structures 300, the first portion 310-1 and the second portion 310-2 having different widths at their interfaces. In some embodiments, the first portion 310-1 has a greater radial width at the interface than the second portion 310-2. As shown in fig. 19, W1 is the width of the first portion 310-1 at the junction therebetween, W2 is the width of the second portion 310-2 at the junction therebetween, and W1 is greater than W2. Because orthographic projection of the conductive structure 310 on the substrate structure is in hexagonal close-packed arrangement, the second portion is arranged on the first portion in an offset manner, and meanwhile, because the first portion has a larger diameter width, the contact area between the first portion and the second portion can be increased, and the contact resistance is reduced.

In some embodiments, the ratio between the width of the first portion 310-1 at the interface with the width of the second portion 310-2 at the interface is in the range of: 1.5 to 3. More specifically, the ratio between the radial width of the first portion 310-1 at the interface of the two and the radial width of the second portion 310-2 at the interface of the two may be 1.5, 2, 2.5, 3. In some embodiments, the shape of the first portion comprises a tetragonal frustum and the shape of the second portion comprises a square.

As shown in fig. 15A to 15D and 19, the first portion 310-1 is formed by a square body and a square frustum located above the square body, and the second portion 310-2 is formed by a square body.

In some embodiments, as shown in fig. 18, the semiconductor structure further comprises: an insulating layer comprising a first insulating layer 304-1 between the bit line structure 230 and the first portion 310-1 and a second insulating layer 304-2 between the isolation structure 300 and the second portion 310-2. The insulating layer may further reduce the resistance capacitance delay caused by parasitic capacitance.

In the disclosed embodiment, the dashed lines shown in fig. 18 and 19 are used only to distinguish the first portion 310-1 and the second portion 310-2 of the conductive structure 310, and it should be emphasized that in an actual semiconductor structure, the dashed lines are not present.

In some embodiments, referring to fig. 8E, the bit line structure 230 includes: a second contact plug 231, a bit line 235, and a cap layer 236 stacked in this order; a first dielectric layer 239, a second dielectric layer 238 and a third dielectric layer 237 covering sidewalls of the second contact plug 231, sidewalls of the bit line 235 and sidewalls of the cap layer 236; the top surface of the second dielectric layer 238 and the top surface of the third dielectric layer 237 are higher than the top surface of the bit line 235, and the top surface of the second dielectric layer 238 and the top surface of the third dielectric layer 237 are sloped surfaces.

The first dielectric layer 239, the second dielectric layer 238 and the third dielectric layer 237 form isolation spacers, and the cap layer 236 and the isolation spacers form bit line isolation structures for isolating adjacent bit lines.

In some embodiments, the material of the second contact plug 231 includes, but is not limited to, polysilicon. The material of cap layer 236 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable materials.

In some embodiments, the semiconductor structure further includes a word line structure 220 located in the base structure; the word line structure 220 passes through a portion of the active region 211; bit line structure 230 covers a portion of active region 211; the projection of the bit line structure 230 on the surface of the base structure intersects the projection of the word line structure 220 on the surface of the base structure and forms a grid; the projection of the first contact plug 240 on the surface of the base structure is located in the mesh holes surrounded by the mesh grid.

In some embodiments, active region 211 includes a first source/drain region in the middle and a second source/drain region at both ends; the projection of the word line structure 220 onto the substrate structure surface is located between the first source/drain region and the second source/drain region; the projection of the bit line structure 230 on the surface of the substrate structure covers part of the first source/drain region and is electrically connected with the first source/drain region; the first contact plug is electrically connected with the second source/drain region. Further, the conductive structure is connected to a memory storage structure, where the storage structure may comprise a capacitor. Thus, a memory may be formed, such as a DRAM, although other types of memories may be formed.

The disclosed embodiments also provide a memory comprising the semiconductor structure of any of the foregoing embodiments. The memory may be, for example, DRAM, static random access memory (Static Random Access Memory, SRAM), etc.

It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. The manufacturing method of the semiconductor structure is characterized by comprising the following steps of:

providing a base structure comprising a plurality of active regions;

forming a plurality of bit line structures on the base structure;

forming a first contact plug contacting the active region between adjacent bit line structures;

forming a sacrificial layer on the first contact plug; the top surface of the sacrificial layer is not higher than the top surface of the bit line structure;

forming a plurality of isolation structures on the sacrificial layer, wherein gaps between adjacent isolation structures expose part of the top surface of the sacrificial layer;

and removing the sacrificial layer, and forming a conductive structure at the position where the sacrificial layer is removed.

2. The method of fabricating a semiconductor structure of claim 1, wherein forming a sacrificial layer over the first contact plug comprises:

forming a sacrificial material layer covering the first contact plug;

flattening the sacrificial material layer to form the sacrificial layer; the top surface of the sacrificial layer is flush with the top surface of the bit line structure.

3. The method of fabricating a semiconductor structure according to claim 1 or 2, wherein forming a plurality of isolation structures on the sacrificial layer comprises:

Forming an isolation material layer on the sacrificial layer;

forming a patterned mask layer on the isolation material layer;

and removing part of the isolation material layer by using the patterned mask layer to form the isolation structure.

4. The method of fabricating a semiconductor structure according to claim 1, wherein removing the sacrificial layer and forming a conductive structure at a location where the sacrificial layer is removed, comprises:

removing the sacrificial layer through gaps between adjacent isolation structures by utilizing a wet etching process to form a through hole exposing the top surface of the first contact plug;

and filling conductive materials into the through holes and performing planarization treatment on the conductive materials to form the conductive structures.

5. The method of fabricating a semiconductor structure of claim 4, further comprising:

depositing an insulating material into the via prior to filling the conductive material into the via;

6. The method of claim 4, wherein the material of the first contact plug comprises a semiconductor material; the manufacturing method of the semiconductor structure further comprises the following steps:

Before filling the conductive material into the through hole, a metallization process is performed on the top surface of the first contact plug.

7. The method of fabricating a semiconductor structure of claim 1, wherein forming a plurality of bit line structures on the base structure comprises:

forming a second contact plug, a bit line and a cover layer which are stacked on the substrate structure in sequence;

sequentially forming a first dielectric layer, a second dielectric material layer and a third dielectric material layer which cover the side walls of the second contact plug, the bit line and the cover layer;

removing part of the second dielectric material layer and part of the third dielectric material layer, and forming a second dielectric layer and a third dielectric layer by the rest of the second dielectric material layer and the rest of the third dielectric material layer; the top surfaces of the second dielectric layer and the third dielectric layer are higher than the top surfaces of the bit lines, and the top surfaces of the second dielectric layer and the third dielectric layer are inclined surfaces.

8. The method of claim 1, wherein the material of the sacrificial layer and the material of the isolation structure have different etching selectivity.

9. A semiconductor structure, comprising:

A base structure including a plurality of active regions;

a plurality of bit line structures on the base structure;

a plurality of isolation structures, wherein the bottom surfaces of the isolation structures and the top surfaces of the bit line structures are positioned at the same height, and the isolation structures at least cover part of the top surfaces of the bit line structures;

a plurality of first contact plugs located between the bit line structures and contacting the active region;

and the conductive structures are positioned on the first contact plug and positioned between the adjacent bit line structures and between the adjacent isolation structures.

10. The semiconductor structure of claim 9, wherein the conductive structure comprises a first portion between adjacent bit line structures and a second portion between adjacent isolation structures, the first portion and the second portion having different widths at their interfaces.

11. The semiconductor structure of claim 10, wherein the first portion has a greater radial width at an interface than the second portion.

12. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises: an insulating layer including a first insulating layer between the bit line structure and the first portion and a second insulating layer between the isolation structure and the second portion.

13. The semiconductor structure of claim 9, wherein the bit line structure comprises: the second contact plug, the bit line and the cover layer are stacked in sequence;

a first dielectric layer, a second dielectric layer and a third dielectric layer covering the sidewalls of the second contact plug, the bit line and the cap layer; the top surfaces of the second dielectric layer and the third dielectric layer are higher than the top surface of the bit line, and the top surfaces of the second dielectric layer and the third dielectric layer are inclined surfaces;

wherein, the density of the cover layer is greater than the density of the isolation structure, and the density of the first medium layer is greater than the density of the isolation structure.

14. The semiconductor structure of claim 9, further comprising a word line structure in the base structure;

the word line structure passes through a portion of the active region;

the bit line structure covers part of the active region; the projection of the bit line structure on the surface of the base structure is intersected with the projection of the word line structure on the surface of the base structure to form a grid;

the projection of the first contact plug on the surface of the base structure is positioned in the grid holes surrounded by the grid bars.

15. The semiconductor structure of claim 14, wherein the active region comprises a first source/drain region in the middle and a second source/drain region at both ends;

the projection of the word line structure on the surface of the substrate structure is positioned between the first source/drain region and the second source/drain region;

the projection of the bit line structure on the surface of the substrate structure covers part of the first source/drain region and is electrically connected with the first source/drain region;

the first contact plug is electrically connected with the second source/drain region.