KR20230011204A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

In accordance with the present invention, provided are a semiconductor device capable of reducing parasitic capacitance between adjacent pattern structures, and a manufacturing method thereof. The semiconductor device includes: a plurality of bit line structures formed in an upper part of a semiconductor substrate, apart from each other; first spacers formed on both side walls of each of the bit line structures; a plurality of lower plugs formed between the plurality of bit line structures and coming in contact with the semiconductor substrate; an upper plug located in an upper part of the lower plugs, while having a larger line width than the lower plugs; an intermediate plug located between the lower plugs and the upper plug, while having a smaller line width than the lower plugs; and a second spacer located between the intermediate plug and the first spacers, while being thicker than the first spacers.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a dual contact plug and a manufacturing method thereof.

In the semiconductor device, an insulating material is formed between adjacent pattern structures. As semiconductor devices are highly integrated, distances between pattern structures are getting closer. Due to this, parasitic capacitance is increased. As the parasitic capacitance increases, the performance of the semiconductor device deteriorates.

Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between adjacent pattern structures and a manufacturing method thereof.

A semiconductor device according to an embodiment of the present invention includes a plurality of bit line structures spaced apart from each other formed on a semiconductor substrate, a first spacer formed on both side walls of each of the bit line structures, and formed between the plurality of bit line structures, and the semiconductor device A plurality of lower plugs in contact with a substrate, an upper plug positioned above the lower plug and having a larger line width than the lower plug, a middle plug positioned between the lower plug and the upper plug, but having a smaller line width than the lower plug, and A second spacer positioned between the middle plug and the first spacer may be included but thicker than the first spacer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a plurality of bit line structures on a semiconductor substrate, forming first spacers on sidewalls of the bit line structures, and forming the bit line structures on the first spacers. Forming plug isolation layers and initial contact openings positioned between line structures; trimming the plug isolation layers and initial contact openings to form contact openings wider than the initial contact openings; forming sacrificial spacers surrounding sidewalls of the openings; Forming a lower plug partially filling the contact openings; removing the sacrificial spacer to form an air gap surrounding the lower plug; and filling the air gap while surrounding the lower plug. It may include forming a spacer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a plurality of bit line structures on a semiconductor substrate, forming first spacers on both sidewalls of the bit line structures, and sacrificial spacers on the first spacers. forming plug isolation layers and initial contact openings positioned between the bit line structures on the sacrificial spacer, forming a lower plug partially filling the initial contact openings, the initial contact trimming the sacrificial spacer and the plug isolation layers to form contact openings wider than the openings; forming second spacers that surround sidewalls of the contact openings but are thicker than the first spacers; and and forming an upper plug having a larger line width than the lower plug on the lower plug.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a plurality of bit line structures on a semiconductor substrate, forming first spacers on both sidewalls of the bit line structures, and sacrificial spacers on the first spacers. However, forming plug separation layers and initial contact openings located between the bit line structures on the sacrificial spacer, in order to form contact openings wider than the initial contact openings, the sacrificial spacer and trimming plug separation layers, forming a lower plug partially filling the initial contact openings, removing the sacrificial spacer to form an air gap surrounding a sidewall of the lower plug, the air gap The method may include forming a second spacer filled with but thicker than the first spacer, and forming an upper plug having a larger line width than the lower plug on the second spacer and the lower plug.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a plurality of bit line structures on a semiconductor substrate, forming first spacers on sidewalls of the bit line structures, and forming a first spacer on the first spacer. Forming a sacrificial spacer, forming plug separation layers and initial contact openings located between the bit line structures on the first sacrificial spacer, forming contact openings wider than the initial contact openings, Trimming the plug isolation layers, forming a wide plug partially filling the initial contact openings, forming a second sacrificial spacer on the wide plug, and the wide plug exposed by the second sacrificial spacer. forming a narrow plug having a smaller line width than the wide plug, removing the first and second sacrificial spacers to form an air gap surrounding a sidewall of the narrow plug; The method may include forming a second spacer that is filled but thicker than the first spacer, and forming an upper plug having a larger line width than the narrow plug on the second spacer and the narrow plug.

Since the thickness of the silicon nitride occupied by the bit line spacer is reduced, the increase in parasitic capacitance can be suppressed.

This technology can reduce parasitic capacitance between the bit line and the storage node contact plug.

This technology can secure the open margin of the storage node contact hole by additionally securing the space of the storage node contact hole.

Since the size of the storage node contact plug facing the bit line is reduced and the bit line spacer is changed to a nitride-oxide (N-O) structure, parasitic capacitance between the bit line and the storage node contact plug can be reduced.

In this technology, since the upper plug of the storage node contact plug has a larger width than the lower plug, contact resistance can be improved by increasing the contact area with the subsequent landing pad.

In this technology, it is possible to secure the area of contact openings by using anisotropic etching using dry etching, regardless of the type of plug separation layer.

1 is a plan view illustrating a semiconductor device according to an exemplary embodiment.
FIG. 2A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 1 .
2B is a detailed enlarged view of a storage node contact plug.
3 to 26 are diagrams illustrating an embodiment of a method of manufacturing a semiconductor device.
27 to 32 are views for explaining a manufacturing method according to another embodiment.
33 to 42 are views for explaining a manufacturing method according to another embodiment.
43 to 48 are views for explaining a manufacturing method according to another embodiment.
49A to 49D are plan views illustrating a method of forming a storage node contact plug in detail.

The embodiments described herein will be described with reference to cross-sectional, plan and block diagrams, which are ideal schematic diagrams of the present invention. Accordingly, the shape of the illustrative drawings may be modified due to manufacturing techniques and/or tolerances. Therefore, embodiments of the present invention are not limited to the specific shapes shown, but also include changes in shapes generated according to manufacturing processes. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of a region of a device and are not intended to limit the scope of the invention.

1 is a plan view illustrating a semiconductor device according to an exemplary embodiment. FIG. 2A is a cross-sectional view taken along lines A-A' and B-B' of FIG. 1 . 2B is a detailed enlarged view of a storage node contact plug (SNC).

The semiconductor device 100 may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line 207 , a bit line 213 , and a memory element 230 .

The semiconductor device 200 will be examined in detail.

An isolation layer 202 and an active region 203 may be formed on the substrate 201 . A plurality of active regions 203 may be defined by the device isolation layer 202 . Substrate 201 may be a material suitable for semiconductor processing. The substrate 201 may include a semiconductor substrate. The substrate 201 may be made of a material containing silicon. Substrate 201 may include silicon, single crystal silicon, polysilicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multilayers thereof. Substrate 201 may also include other semiconductor materials such as germanium. The substrate 201 may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 201 may include a silicon on insulator (SOI) substrate. The device isolation layer 202 may be formed by a shallow trench isolation (STI) process.

A gate trench 205 may be formed in the substrate 201 . A gate insulating layer 206 may be formed on a surface of the gate trench 205 . A buried word line 207 partially filling the gate trench 205 may be formed on the gate insulating layer 206 . A gate capping layer 208 may be formed on the buried word line 207 . An upper surface of the buried word line 207 may be at a lower level than the surface of the substrate 201 . The buried word line 207 may be a low resistivity metal material. In the buried word line 207 , titanium nitride (TiN) and tungsten (W) may be sequentially stacked. In another embodiment, the buried word line 207 may be formed of titanium nitride only (TiN Only). The buried word line 206 may be referred to as a 'buried gate electrode'. The buried word line 207 may extend along the first direction D1. The gate trench 205, the gate insulating layer 206, the buried word line 208, and the gate capping layer 208 may be referred to as a buried word line structure (BWL).

First and second impurity regions 209 and 210 may be formed on the substrate 201 . The first and second impurity regions 209 and 210 may be spaced apart from each other by the gate trench 205 . The first and second impurity regions 209 and 210 may be referred to as source/drain regions. The first and second impurity regions 209 and 210 may include N-type impurities such as arsenic (As) or phosphorus (P). Thus, the buried word line 207 and the first and second impurity regions 209 and 210 may constitute a cell transistor. The cell transistor can improve a short channel effect by the buried word line 207 .

A bit line contact plug 212 may be formed on the substrate 201 . The bit line contact plug 212 may be connected to the first impurity region 209 . The bit line contact plug 212 may be located in the bit line contact hole 211 . The bit line contact hole 211 may pass through the hard mask layer 204 and extend to the substrate 201 . A hard mask layer 204 may be formed on the substrate 201 . The hard mask layer 204 may include an insulating material. The bit line contact hole 211 may expose the first impurity region 209 . A lower surface of the bit line contact plug 212 may be lower than upper surfaces of the isolation layer 202 and the active region 203 . The bit line contact plug 212 may be formed of polysilicon or a metal material. A part of the bit line contact plug 212 may have a smaller line width than the diameter of the bit line contact hole 211 . A bit line 213 may be formed on the bit line contact plug 212 . A bit line hard mask 214 may be formed on the bit line 213 . A stacked structure of the bit line contact plug 212 , the bit line 213 , and the bit line hard mask 214 may be referred to as a bit line structure BL. The bit line 213 may have a line shape extending along the second direction D2 intersecting the buried word line 207 . A portion of the bit line 213 may be connected to the bit line contact plug 212 . When viewed from the A-A' direction, the bit line 213 and the bit line contact plug 212 may have the same line width. Accordingly, the bit line 213 may extend along the second direction D2 while covering the bit line contact plug 212 . The bit line 213 may include a metal material such as tungsten. The bit line hard mask 214 may include an insulating material such as silicon nitride.

A bit line contact spacer BLCS may be formed on a sidewall of the bit line contact plug 212 . The bit line contact spacer BLCS may include a first spacer 215 and a gap fill spacer 215G. A bit line spacer BLS may be formed on a sidewall of the bit line 213 . The bit line spacer BLS may include a first spacer 215 and a second spacer 216 . The first spacer 215 may extend to be formed on both side walls of the bit line contact plug 212 . The first spacer 215 and the second spacer 216 may include silicon nitride. The first spacer 215 may have a thickness of about 10 Å or less. The first spacer 215 may include ultra thin silicon nitride of about 10 Å or less. The first spacer 215 may be thinner than the second spacer 216 . For example, the second spacer 216 may be twice as thick as the first spacer 215 .

The bit line contact hole 211 may be filled with a bit line contact plug 212 and a bit line contact spacer (BLCS).

A storage node contact plug (SNC) may be formed between adjacent bit line structures. The storage node contact plug SNC may be connected to the second impurity region 210 . The storage node contact plug (SNC) may include a lower plug 217 , an upper plug 218 , and a landing pad 220 . The lower plug 217 and the upper plug 218 may be referred to as a dual contact plug. The storage node contact plug SNC may further include an ohmic contact layer 219 between the upper plug 218 and the landing pad 220 . The ohmic contact layer 219 may include metal silicide. For example, the lower plug 217 and the upper plug 218 may include polysilicon, and the landing pad 220 may include a metal nitride, a metal material, or a combination thereof.

When viewed from a direction parallel to the bit line structure, a plug isolation layer 221 may be formed between neighboring storage node contact plugs SNC. The plug isolation layer 221 may be formed between adjacent bit line structures. Neighboring storage node contact plugs SNC may be separated by the plug separation layers 221 . A plurality of plug separation layers 221 and a plurality of storage node contact plugs SNC may be alternately positioned between adjacent bit line structures.

A memory element 230 may be formed on the landing pad 220 . The memory element 230 may include a capacitor including a storage node. The storage node may include a pillar type. Although not shown, a dielectric layer and a plate node may be further formed on the storage node. The storage node may have a cylinder shape in addition to a pillar shape.

Referring back to FIG. 2B , the lower plug 217 of the storage node contact plug (SNC) may include a wide plug 217L and a narrow plug 217U. The wide plug 217L and the narrow plug 217U may be made of the same material, but may have discontinuous interfaces. That is, the wide plug 217L and the narrow plug 217U may be formed by different processes. The line width L1 of the wide plug 217L may be larger than the line width L2 of the narrow plug 217U, and the line width L2 of the narrow plug 217U may be smaller than the line width L3 of the upper plug 218. there is. A line width L1 of the wide plug 217L and a line width L3 of the upper plug 218 may be equal to each other. In another embodiment, the line width L3 of the upper plug 218 may be greater than the line width L1 of the wide plug 217L.

Referring back to FIG. 2A , the lower plug 217 of the storage node contact plug (SNC) may extend horizontally into the gap fill spacer 215G. Also, the lower plug 217 may horizontally extend into the second impurity region 210 .

As described above, the first spacer 215 and the double spacer of the gap fill spacer 215G are positioned between the bit line contact plug 212 and the lower plug 217 of the storage node contact plug (SNC). can A double spacer of a first spacer 215 and a second spacer 216 may be positioned between the bit line 213 and the storage node contact plug SNC. The second spacer 216 may be thicker than the first spacer 215 .

The first spacer 215 and the gap-fill spacer 215G may include silicon nitride, and the second spacer 216 may include silicon oxide. Accordingly, a nitride-oxide (N-O) structure bit line spacer (BLS) may be provided between the bit line 213 and the lower plug 217 of the storage node contact plug (SNC), and the bit line contact plug 213 ) and the lower plug 217 of the storage node contact plug SNC, a bit line contact spacer BLCS having a nitride-nitride (N-N) structure may be provided.

The plug isolation layer 221 may include silicon nitride or a low dielectric constant material. When the plug isolation layer 221 includes a low-k material, parasitic capacitance between adjacent storage node contact plugs SNC with the plug isolation layer 221 interposed therebetween may be reduced.

In other embodiments, the second spacer 216 may be replaced with an air gap.

According to FIGS. 1 to 2B , since the thickness of silicon nitride, that is, the first spacer 215 occupied by the bit line spacer BLS is thinned, an increase in parasitic capacitance can be suppressed.

3 to 26 are diagrams illustrating an embodiment of a method of manufacturing a semiconductor device. 3 to 26 are cross-sectional views for explaining a manufacturing method taken along lines AA' and BB' of FIG. 1 .

As shown in FIG. 3 , a device isolation layer 12 may be formed on the substrate 11 . A plurality of active regions 13 are defined by the device isolation layer 12 . The device isolation layer 12 may be formed by a shallow trench isolation (STI) process. The STI process is as follows. The substrate 11 is etched to form an isolation trench (reference numeral omitted). The isolation trench is filled with an insulating material, and thus the device isolation layer 12 is formed. The device isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trench with an insulating material. A planarization process such as chemical-mechanical polishing (CMP) may additionally be used.

Next, a buried word line structure may be formed in the substrate 11 . The buried word line structure includes a gate trench 15, a gate insulating layer 16 covering the bottom surface and sidewalls of the gate trench 15, and a buried word line partially filling the gate trench 15 on the gate insulating layer 16. (17), and a gate capping layer 18 formed on the buried word line 17.

A method of forming the buried word line structure is as follows.

First, a gate trench 15 may be formed in the substrate 11 . The gate trench 15 may have a line shape crossing the active regions 13 and the device isolation layer 12 . The gate trench 15 may be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. To form the gate trench 15 , a hard mask layer 14 may be used as an etch barrier. The hard mask layer 14 may have a shape patterned by a mask pattern. The hard mask layer 14 may include silicon oxide. The hard mask layer 14 may include tetra ethyl ortho silicate (TEOS). A bottom surface of the gate trench 15 may be at a higher level than a bottom surface of the isolation layer 12 .

Although not shown, the active region 13 under the gate trench 15 may protrude by recessing a portion of the isolation layer 12 . For example, the device isolation layer 12 under the gate trench 15 may be selectively recessed along the second direction D2 of FIG. 1 . Accordingly, a fin region (reference numeral omitted) may be formed under the gate trench 15 . The pin area may be part of the channel area.

Next, a gate insulating layer 16 may be formed on the bottom surface and sidewalls of the gate trench 15 . Before forming the gate insulating layer 16 , etch damage on the surface of the gate trench 15 may be healed. For example, after forming the sacrificial oxide by thermal oxidation treatment, the sacrificial oxide may be removed.

The gate insulating layer 16 may be formed by a thermal oxidation process. For example, the gate insulating layer 16 may be formed by oxidizing the bottom and sidewalls of the gate trench 15 .

In another embodiment, the gate insulating layer 16 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate insulating layer 16 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In other embodiments, the high dielectric constant material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and combinations thereof.

In another embodiment, the gate insulating layer 16 may be formed by depositing a liner polysilicon layer and then radical oxidizing the liner polysilicon layer.

In another embodiment, the gate insulating layer 16 may be formed by radical oxidizing the liner silicon nitride layer after forming the liner silicon nitride layer.

Next, a buried word line 17 may be formed on the gate insulating layer 16 . To form the buried word line 17 , a recessing process may be performed after forming a conductive layer (not shown) to fill the gate trench 15 . The recessing process may be performed as an etchback process or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. The buried word line 17 may have a recessed shape partially filling the gate trench 15 . That is, the upper surface of the buried word line 17 may be at a lower level than the upper surface of the active region 13 . The buried word line 17 may include a metal, a metal nitride, or a combination thereof. For example, the buried word line 17 may be formed of a titanium nitride (TiN), tungsten (W), or titanium nitride/tungsten (TiN/W) stack. The titanium nitride/tungsten (TiN/W) stack may have a structure in which titanium nitride is conformally formed and then partially fills the gate trench 15 with tungsten. As the buried word line 17, titanium nitride may be used alone, and this may be referred to as a buried word line 17 having a “TiN Only” structure. As the buried word line 17, a double gate structure of a titanium nitride/tungsten (TiN/W) stack and a polysilicon layer may be used.

Next, a gate capping layer 18 may be formed on the buried word line 17 . The gate capping layer 18 includes an insulating material. The remaining portion of the gate trench 15 on the buried word line 17 is filled with the gate capping layer 18 . The gate capping layer 18 may include silicon nitride. In another embodiment, the gate capping layer 18 may include silicon oxide. In another embodiment, the gate capping layer 18 may have a Nitride-Oxide-Nitride (NON) structure. An upper surface of the gate capping layer 18 may be at the same level as an upper surface of the hard mask layer 14 . To this end, a CMP process may be performed when forming the gate capping layer 18 .

After forming the gate capping layer 18 , impurity regions 19 and 20 may be formed. The impurity regions 19 and 20 may be formed by a doping process such as implantation. The impurity regions 19 and 20 may include a first impurity region 19 and a second impurity region 20 . The first and second impurity regions 19 and 20 may be doped with impurities of the same conductivity type. The first and second impurity regions 19 and 20 may have the same depth. In another embodiment, the first impurity region 19 may be deeper than the second impurity region 20 . The first and second impurity regions 19 and 20 may be referred to as source/drain regions. The first impurity region 19 may be a region to which a bit line contact plug is connected, and the second impurity region 20 may be a region to which a storage node contact plug is connected. The first impurity region 19 and the second impurity region 20 may be located in different active regions 13 . In addition, the first impurity region 19 and the second impurity region 20 may be spaced apart from each other by gate trenches 15 and positioned in respective active regions 13 .

A cell transistor of a memory cell may be formed by the buried word line 17 and the first and second impurity regions 19 and 20 .

As shown in FIG. 4 , a bit line contact hole 21 may be formed. The hard mask layer 14 may be etched using a contact mask (not shown) to form the bit line contact hole 21 . The bit line contact hole 21 may have a circle shape or an elliptical shape when viewed from a plan view. A portion of the substrate 11 may be exposed through the bit line contact hole 21 . The bit line contact hole 21 may have a controlled diameter with a constant line width. The bit line contact hole 21 may have a shape exposing a portion of the active region 13 . For example, the first impurity region 19 is exposed through the bit line contact hole 21 . The bit line contact hole 21 has a larger diameter than the width of the minor axis of the active region 13 . Accordingly, in an etching process for forming the bit line contact hole 21 , portions of the first impurity region 19 , the isolation layer 12 , and the gate capping layer 18 may be etched. That is, the gate capping layer 18, the first impurity region 19, and the isolation layer 12 under the bit line contact hole 21 may be recessed to a predetermined depth. Accordingly, the bottom of the bit line contact hole 21 may be extended into the substrate 11 . As the bit line contact hole 21 expands, the surface of the first impurity region 19 may be recessed, and the surface of the first impurity region 19 may be at a lower level than the surface of the active region 13. can

As shown in FIG. 5, a pre-plug 22A is formed. The preliminary plug 22A may be formed by selectively epitaxial growth (SEG). For example, the preliminary plug 22A may include an epitaxial layer doped with phosphorus, for example SEG SiP. In this way, the preliminary plug 22A can be formed without voids by the selective epitaxial growth. In another embodiment, the preliminary plug 22A may be formed by polysilicon layer deposition and a CMP process. The preliminary plug 22A may fill the bit line contact hole 21 . An upper surface of the preliminary plug 22A may be at the same level as an upper surface of the hard mask layer 14 .

As shown in FIG. 6 , a bit line conductive layer 23A and a bit line hard mask layer 24A may be stacked. A bit line conductive layer 23A and a bit line hard mask layer 24A may be sequentially stacked on the preliminary plug 22A and the hard mask layer 14 . The bit line conductive layer 23A includes a metal-containing material. The bit line conductive layer 23A may include metal, metal nitride, metal silicide, or a combination thereof. In this embodiment, the bit line conductive layer 23A may include tungsten (W). In another embodiment, the bit line conductive layer 23A may include a stack of titanium nitride and tungsten (TiN/W). At this time, titanium nitride may serve as a barrier. The bit line hard mask layer 24A may be formed of an insulating material having an etch selectivity with respect to the bit line conductive layer 23A and the preliminary plug 22A. The bit line hard mask layer 24A may include silicon oxide or silicon nitride. In this embodiment, the bit line hard mask layer 24A may be formed of silicon nitride.

As shown in FIG. 7 , a bit line 23 and a bit line contact plug 22 may be formed. The bit line 23 and the bit line contact plug 22 may be formed by an etching process using a bit line mask layer (not shown).

The bit line hard mask layer 24A and the bit line conductive layer 23A are etched using the bit line mask layer as an etch barrier. Accordingly, the bit line 23 and the bit line hard mask 24 may be formed. The bit line 23 may be formed by etching the bit line conductive layer 23A. The bit line hard mask 24 may be formed by etching the bit line hard mask layer 24A.

Subsequently, the preliminary plug 22A may be etched with the same line width as the bit line 23 . Accordingly, the bit line contact plug 22 may be formed. The bit line contact plug 22 may be formed on the first impurity region 19 . The bit line contact plug 22 may interconnect the first impurity region 19 and the bit line 23 . The bit line contact plug 22 may be formed in the bit line contact hole 21 . The line width of the bit line contact plug 22 is smaller than the diameter of the bit line contact hole 21 . Accordingly, gaps 25 may be defined on both sides of the bit line contact plug 22 .

As described above, the gap 25 is formed in the bit line contact hole 21 by forming the bit line contact plug 22 . This is because the bit line contact plug 22 is etched and formed smaller than the diameter of the bit line contact hole 21 . The gap 25 does not have a surrounding shape surrounding the bit line contact plug 22 , but is formed independently on both side walls of the bit line contact plug 22 . As a result, one bit line contact plug 22 and a pair of gaps 25 are located in the bit line contact hole 21, and the pair of gaps 25 are separated by the bit line contact plug 22. do. A lower surface of the gap 25 may extend into the isolation layer 12 . The lower surface of the gap 25 may be at a level lower than the recessed upper surface of the first impurity region 19 .

A structure in which the bit line contact plug 22 , the bit line 23 , and the bit line hard mask 24 are sequentially stacked may be referred to as a bit line structure. When viewed from a top view, that is, as referred to in FIG. 1 , the bit line structure BL may be a line-shaped pattern structure elongated along any one direction D1.

As shown in FIG. 8 , a first spacer layer 26A may be formed. The first spacer layer 26A may include silicon nitride.

As shown in FIG. 9 , a buffer layer 27A and a gap fill material layer 28A may be sequentially formed on the first spacer layer 26A. The buffer layer 27A may cover the upper end and sidewalls of the upper end of the bit line hard mask 24 on the first spacer layer 26A. The buffer layer 27A may have an overhang shape and be formed non-conformally, and thus may not be located on both side walls of the bit line 23 . The buffer layer 27A may include silicon oxide.

The gap fill material layer 28A may fill the gap 25 . The gap fill material layer 28A and the first spacer layer 26A may be made of the same material, but the gap fill material layer 28A may be thicker than the first spacer layer 26A. The gap fill material layer 28A may include silicon nitride.

As shown in FIG. 10 , a gap fill spacer 28 filling the gap 25 may be formed. A trimming process of the gap fill material layer 28A may be performed to form the gap fill spacer 28 . The trimming process of the gap fill material layer 28A may be performed by an etch-back process, and the upper sidewall of the first spacer layer 26A may be protected by the buffer layer 27A.

After forming the gap fill spacers 28, the buffer layer 27A may be removed.

An upper surface of the gap fill spacer 28 may be positioned at a lower level than an upper surface of the bit line contact plug 22 . In another embodiment, the upper surface of the gap fill spacer 28 and the upper surface of the bit line contact plug 22 may be positioned at the same level.

The gap 25 may be filled with a double layer of a first spacer layer 26A and a gap fill spacer 28 . Gapfill spacer 28 may be referred to as an insulating plug or plugging spacer. In another embodiment, the gap fill spacer 28 may be formed of silicon oxide or a low-k material.

After the gap-fill spacers 28 are formed, line-shaped openings LO may be defined between adjacent bit lines 23 . A single layer of the first spacer layer 26A may remain on both side walls of the bit line 23 and the bit line hard mask 24 . A bi-layer of the first spacer layer 26A and the gap-fill spacer 28 may remain on both side walls of the bit line contact plug 22 .

As shown in FIG. 11 , a sacrificial spacer layer 29A may be formed on the gap fill spacer 28 and the first spacer layer 26A. The sacrificial spacer layer 29A and the first spacer layer 26A may include the same material. For example, the sacrificial spacer layer 29A may include silicon nitride.

As shown in FIG. 12 , a sacrificial layer 30A may be formed on the sacrificial spacer layer 29A. The sacrificial layer 30A may fill between the bit line structures and may include silicon oxide such as spin on dielectric (SOD).

Subsequently, the sacrificial layer 30A and the sacrificial spacer layer 29A may be planarized to expose the upper surface of the bit line hard mask 24 . After planarizing the sacrificial layer 30A, sacrificial spacers 29 may be placed between the bitline structures.

After the planarization process of the sacrificial layer 30A, a portion of the first spacer layer 26A may be planarized to form the first spacer 26 .

As shown in FIG. 13 , hole-shaped openings 31 may be formed in the sacrificial layer 30A. The hole-type openings 31 may be formed by etching the sacrificial layer 30A. The hole-type openings 31 and the sacrificial layers 30A may be alternately formed in the extending direction of the bit line 23, that is, between adjacent bit line structures. The hole-type openings 31 may have a square hole shape when viewed from a top view.

As shown in FIG. 14 , a plug isolation layer 32A filling the hole-type openings 31 may be formed. The plug separation layers 32A may include silicon nitride or a low dielectric constant material. In another embodiment, the plug isolation layers 32A may include silicon nitride containing boron.

As shown in FIG. 15 , the sacrificial layers 30A may be removed. Accordingly, a plurality of initial contact openings 33A may be formed between the plug isolation layers 32A. The initial contact openings 33A may be formed in the sacrificial spacer 29 between the bit line structures. The initial contact openings 33A may have a first line width W1. When viewed from a top view, the initial contact openings 33A may have a rectangular hole shape such as a square or a rectangle.

As shown in FIG. 16 , the sacrificial spacer 29 and the plug isolation layers 32A may be trimmed. Trimming of the sacrificial spacer 29 and the plug isolation layers 32A may be performed by an etch-back process. Through this trimming process, the contact opening 33 may be formed. The contact opening 33 may have a second line width W2 . The contact opening 33 may be obtained by expanding the initial contact opening 33A.

All of the sacrificial spacers 29 between the bit line structures may be removed, and the sacrificial spacers 29 under the contact openings 33 may be recessed. In another embodiment, all of the sacrificial spacers 29 under the contact openings 33 may be removed.

As shown in FIG. 17 , a metallic sacrificial material layer 34A may be formed on the contact openings 33 . The metallic sacrificial material layer 34A may be conformally formed. The metallic sacrificial material layer 34A may include titanium nitride.

As shown in FIG. 18 , a metallic sacrificial spacer 34 may be formed. To form the metallic sacrificial spacer 34 , the metallic sacrificial material layer 34A may be etched.

The metallic sacrificial spacer 34 may have a shape surrounding sidewalls of the contact opening 33 . An upper surface of the metallic sacrificial spacer 34 may be positioned at a lower level than an upper surface of the bit line hard mask 24 . The metallic sacrificial spacer 34 may be thicker than the first spacer 26 .

As shown in FIG. 19 , lower materials under the contact opening 33 may be etched. The underlying materials may be etched to self-align to the contact openings 33 . Accordingly, a plurality of recess regions 35 exposing a portion of the active region 13 may be formed between the bit line structures. Anisotropic etching or a combination of anisotropic etching and isotropic etching may be used to form the recessed regions 35 . For example, among the structures exposed through the contact openings 33 between the bit line structures, the first spacer 26, the hard mask layer 14, and the gap fill spacer 28 are sequentially anisotropically etched, and then A portion of the exposed active region 13 may be isotropically etched. Portions of the active region 13 and the gap fill spacer 28 may be exposed by the recess regions 32 .

The recessed regions 35 may extend into the substrate 11 . While forming the recess regions 35, the isolation layer 12 and the second impurity region 20 may be recessed to a predetermined depth. Bottom surfaces of the recess regions 35 may be at a lower level than an upper surface of the bit line contact plug 22 . Bottom surfaces of the recess regions 35 may be at a higher level than the bottom surface of the bit line contact plug 22 . The contact openings 33 and the recess regions 35 may be interconnected. A vertical structure of the contact openings 33 and the recess regions 35 may be referred to as a 'storage node contact hole'.

After forming the recess regions 35, a double layer of the first spacer 26 and the metallic sacrificial spacer 34 may remain on the sidewall of the bit line structure, and the metallic sacrificial spacer 34 may remain on the sidewall of the plug separation layers 32. A single layer of the sacrificial spacer 34 may remain.

As shown in FIG. 20 , lower plug layers 36A may be formed on the sacrificial metallic spacer 34 . The lower plug layers 36A may completely fill the recess regions 35 and partially fill the contact openings 33 . The lower plug layers 36A may contact the second impurity region 20 . The lower plug layers 36A may be adjacent to the bit line structure. When viewed from a top view, a plurality of lower plug layers 36A may be positioned between the plurality of bit line structures. In a direction parallel to the bit line 23 , a plurality of lower plug layers 36A and a plurality of plug isolation layers 32 may be alternately positioned between adjacent bit line structures.

The lower plug layers 36A may include a silicon-containing material. The lower plug layers 36A may include polysilicon, and the polysilicon may be doped with impurities. The lower plug layers 36A are connected to the second impurity region 20 . Upper surfaces of the lower plug layers 36A may be higher than upper surfaces of the bit lines 23 . After depositing polysilicon to fill the contact openings 33 and the recess regions 35 to form the lower plug layers 36A, planarization and etch-back processes may be sequentially performed.

As shown in FIG. 21 , the metallic sacrificial spacer 34 may be removed. Accordingly, the sacrificial metallic spacer 34 may be removed between the lower plug layer 36A and the bit line 35, and also, the sacrificial metallic spacer 34 may be disposed between the plug separation layers 32 and the lower plug layers 36A. Spacers 34 may be removed.

A space where the sacrificial metallic spacer 34 is removed may be referred to as an 'air gap 36G'.

As shown in FIG. 22 , a second spacer layer 37A filling the air gap 36G may be formed. The second spacer layer 37A may include silicon oxide. The second spacer layer 37A may be formed by selectively oxidizing portions of the lower plug layer 36A. The second spacer layer 27A may be formed by oxidizing portions of the first spacer layer 26A and the plug separation layers 32 .

An oxidation process for forming the second spacer layer 37A may include radical oxidation or/and dry oxidation. For example, after radical oxidation is first performed to form the second spacer layer 37A, dry oxidation may be subsequently performed. In another embodiment, in order to form the second spacer layer 37A, dry oxidation may be performed after thinly depositing an ultra low temperature oxide (ULTO).

During the formation of the second spacer layer 37A, portions 36B of the lower plug layers 36A may be lost and oxidized. The lower plug layers 36A may remain as indicated by reference numeral 36, and will be referred to as 'lower plugs 36' for short.

As shown in FIG. 23 , a second spacer 37 may be formed. The second spacer 37 may be formed by selectively etching the second spacer layer 37A. Upper surfaces of the second spacers 37 may be positioned at the same level as upper surfaces of the lower plugs 36 .

The second spacer 37 may be positioned between the lower plug 36 and the bit line 23 with the first spacer 26 interposed therebetween, and also between the plug separation layer 32 and the lower plug 36. can be located in

As shown in FIG. 24, an upper plug 38 may be formed. The lower plug 36 and the upper plug 38 may be of the same material. The upper plug 38 may include polysilicon. The line width of the upper plug 38 may be greater than that of the lower plug 36 . The upper plug 38 may be formed by a polysilicon deposition and etch-back process.

As shown in FIG. 25 , a contact spacer 39 may be formed on the upper plug 38 . The contact spacer 39 may include silicon oxide. A silicon oxide deposition and etch-back process may be performed to form the contact spacers 39 . Upper surfaces of the upper plug 38 may be partially exposed by the contact spacer 39 . The contact spacer 39 may be formed on a sidewall of the plug isolation layer 32 on the upper plug 38 . Also, the contact spacer 39 may be formed on the first spacer 26 on the upper plug 38 .

As shown in FIG. 26 , an ohmic contact layer 40 may be formed on the upper plug 38 . The ohmic contact layer 40 may include metal silicide. To form the ohmic contact layer 40, deposition and annealing of a silicidable metal layer is performed. Accordingly, silicidation occurs at the interface where the metal silicidation layer and the upper plug 38 come into contact, thereby forming a metal silicide layer. The ohmic contact layer 40 may include cobalt silicide. In this embodiment, the ohmic contact layer 40 may include 'CoSi ₂ phase' cobalt silicide.

When cobalt silicide of the CoSi ₂ phase is formed as the ohmic contact layer 40 , contact resistance can be improved and cobalt silicide with low resistance can be formed.

A landing pad 41 may be formed on the ohmic contact layer 40 . Deposition and etching of a metal-containing layer (not shown) may be performed to form the landing pad 41 . The landing pad 41 may include metal. The landing pad 41 may include a material containing tungsten. The landing pad 41 may include a tungsten layer or a tungsten compound. The landing pad 41 may also have a stacked structure of a titanium nitride liner layer and a tungsten layer. An upper end of the landing pad 41 may extend to overlap an upper surface of the bit line hard mask 24 .

The lower plug 36, the upper plug 38, the ohmic contact layer 39, and the landing pad 41 may form a storage node contact plug (SNC).

As described above, the first spacer 26 and the gap fill spacer 28 may be positioned between the bit line contact plug 22 and the lower plug 36 . A first spacer 26 and a second spacer 37 may be positioned between the bit line 23 and the lower plug 36 . Since the first spacer 26 includes silicon nitride and the second spacer 37 includes silicon oxide, a nitride-oxide (N-O) spacer structure is formed between the bit line 23 and the lower plug 36. can be formed The second spacer 37 may be thicker than the first spacer 26 .

A first spacer 26 may be positioned between the upper plug 38 and the bit line hard mask 24 .

27 to 32 are views for explaining a manufacturing method according to another embodiment. Hereinafter, FIGS. 27 to 32 may proceed similarly to the method shown in FIGS. 3 to 26 .

First, as illustrated in FIGS. 3 to 15 , a plurality of initial contact openings 33A may be formed between the plug isolation layers 32A. The initial contact opening 33A may be formed in the sacrificial spacer 29 between the bit line structures. When viewed from a top view, the initial contact openings 33A may have a square hole shape.

Next, as shown in FIG. 27 , lower materials under the initial contact opening 33A may be etched. Underlying materials may be etched to self-align to the initial contact openings 33A. Accordingly, a plurality of recess regions 35 exposing a portion of the active region 13 may be formed between the bit line structures. Anisotropic etching or a combination of anisotropic etching and isotropic etching may be used to form the recessed regions 35 . For example, the first spacer 26, the hard mask layer 14, the gap fill spacer 28, and the sacrificial spacer 29 among the structures exposed through the initial contact openings 33A between the bit line structures are formed. After anisotropic etching, a portion of the active region 13 exposed thereafter may be isotropically etched. Portions of the active region 13 and the gap fill spacer 28 may be exposed by the recess regions 35 .

The recessed regions 35 may extend into the substrate 11 . While forming the recess regions 35 , the isolation layer 12 and the second impurity region 20 may be recessed to a predetermined depth. Bottom surfaces of the recess regions 35 may be at a lower level than an upper surface of the bit line contact plug 22 . Bottom surfaces of the recess regions 35 may be at a higher level than the bottom surface of the bit line contact plug 22 . The contact openings 33A and the recess regions 35 may be interconnected. A vertical structure of the contact openings 33A and the recess regions 35 may be referred to as a 'storage node contact hole'.

As shown in FIG. 28 , a lower plug 51 may be formed. The lower plug 51 may completely fill the recessed regions 35 and may partially fill the contact opening 33A. The lower plug 51 may contact the second impurity region 20 . The lower plug 51 may be adjacent to the bit line structure. When viewed from a top view, a plurality of lower plugs 51 may be positioned between a plurality of bit line structures. In a direction parallel to the bit line 23 , a plurality of lower plugs 51 and a plurality of plug isolation layers 32A may be alternately positioned between adjacent bit line structures.

The lower plug 51 may include a silicon-containing material. The lower plug 51 may include polysilicon. Polysilicon may be doped with impurities. The lower plug 51 is connected to the second impurity region 20 . An upper surface of the lower plug 51 may be lower than an upper surface of the bit line 23 . After depositing polysilicon to fill the contact opening 33 and the recess region 35 to form the lower plug 51 , planarization and etch-back processes may be sequentially performed.

As shown in FIG. 29 , the sacrificial spacer 29 and the plug separation layers 32A may be trimmed. Trimming of the sacrificial spacer 29 and the plug isolation layers 32A may be performed by an etch-back process. Through this trimming process, the contact opening 33 may be formed. The contact opening 33 may be obtained by expanding the initial contact opening 33A.

In the A-A' direction, some of the sacrificial spacers 29 may remain on the upper sidewalls of the lower plugs 51 . In the B-B' direction, the plug separation layers may be trimmed as indicated by reference numeral '32'.

As shown in FIG. 30 , a second spacer layer 52A may be formed. The second spacer layer 52A may be formed by a silicon oxide deposition process and an etch-back process.

As shown in FIG. 31 , a middle plug 53 may be formed on the second spacer layer 52A and the lower plug 51 . The intermediate plug 53 may include a silicon-containing material. The intermediate plug 53 may include polysilicon, and the polysilicon may be doped with impurities. The middle plug 53 may be formed on the lower plug 51 . An upper surface of the intermediate plug 53 may be higher than an upper surface of the bit line 23 . After depositing polysilicon to fill the remaining portion of the contact opening 33 to form the intermediate plug 53, planarization and etch-back processes may be sequentially performed.

Next, a second spacer 52 may be formed. The second spacer 52 may be formed by selectively etching the second spacer layer 52A. An upper surface of the second spacer 52 may be positioned at the same level as an upper surface of the intermediate plug 53 .

The second spacer 52 may be positioned between the middle plug 53 and the bit line 23 with the first spacer 26 interposed therebetween, and also between the plug isolation layer 32 and the middle plug 53. can be located in

As shown in FIG. 32, an upper plug 54 may be formed. The upper plug 54 may include polysilicon. The line width of the upper plug 54 may be greater than the line widths of the lower plug 51 and the middle plug 53 .

Subsequently, as referred to in FIGS. 25 and 26 , contact spacers 40 and landing pads 41 may be formed.

33 to 42 are views for explaining a manufacturing method according to another embodiment. Hereinafter, FIGS. 33 to 42 may proceed similarly to the method shown in FIGS. 3 to 26 .

After FIG. 10 , as shown in FIG. 33 , a metallic material layer 61A may be formed on the first spacer layer 26A. The metallic material layer 61A may be conformally formed. The metallic material layer 61A may include titanium nitride.

As shown in FIG. 34 , a metallic spacer 61 may be formed. To form the metallic spacer 61, the metallic material layer 61A may be etched.

As shown in FIG. 35 , an insulating liner layer 62A may be formed on the metallic spacer 61 . The insulating liner layer 62A may include silicon nitride.

Subsequently, a series of processes as referred to in FIGS. 12 to 15 may be performed on the insulating liner layer 62A. Accordingly, as shown in FIG. 36 , a plurality of initial contact openings 33A may be formed between the plug isolation layers 32A. The initial contact opening 33A may be located between the bit line structures. The initial contact openings 33A may have a first line width W1. When viewed from a top view, the initial contact openings 33A may have a square hole shape.

As shown in FIG. 37 , the insulating liner layer 62A and the plug isolation layers 32A may be trimmed. Trimming of the insulating liner layer 62A and the plug isolation layers 32A may be performed by an etch-back process. Through this trimming process, the contact opening 33 may be formed. The contact opening 33 may have a second line width W2 . The contact opening 33 may be obtained by expanding the initial contact opening 33A.

All of the insulating liner layer 62A between the bit line structures may be removed, and the insulating liner layer 62A under the contact openings 33 may be recessed. After the insulating liner layer 62A is removed, metallic spacers 61 may remain on both sidewalls of the bit line 23 . An insulating liner pattern 62 may remain under the trimmed plug isolation layers 32 .

As shown in FIG. 38 , lower materials under the contact opening 33 may be etched. Subsequent materials may be etched to self-align to the metallic spacer 61 and the plug separation layer 32 . Accordingly, a plurality of recess regions 35 exposing a portion of the active region 13 may be formed between the bit line structures. Anisotropic etching or a combination of anisotropic etching and isotropic etching may be used to form the recessed regions 35 . For example, among structures exposed through contact openings 33 between bit line structures, the first spacer layer 26A, the hard mask layer 14, and the gap fill spacer 28 are sequentially anisotropically etched; Afterwards, a portion of the exposed active region 13 may be isotropically etched. Portions of the active region 13 and the gap fill spacer 28 may be exposed by the recess regions 32 .

The recessed regions 35 may extend into the substrate 11 . While forming the recess regions 35 , the isolation layer 12 and the second impurity region 20 may be recessed to a predetermined depth. Bottom surfaces of the recess regions 35 may be at a lower level than an upper surface of the bit line contact plug 22 . Bottom surfaces of the recess regions 35 may be at a higher level than the bottom surface of the bit line contact plug 22 . The contact openings 33 and the recess regions 35 may be interconnected. A vertical structure of the contact openings 33 and the recess regions 35 may be referred to as a 'storage node contact hole'.

After forming the recess regions 35 , a double layer of the first spacer 26 and the metallic spacer 61 may remain on the sidewall of the bit line structure. The metallic spacer 61 may not remain on the sidewall of the plug separation layer 32 . An insulating liner layer 62 and a first spacer 26 may be positioned under the plug separation layer 32 .

As shown in FIG. 39 , a lower plug layer 36A may be formed. The lower plug layer 36A may completely fill the recess regions 35 and may partially fill the contact opening 33 . The lower plug layer 36A may contact the second impurity region 20 . The lower plug layer 36A may be adjacent to the bit line structure. When viewed from a top view, a plurality of lower plug layers 36A may be positioned between the plurality of bit line structures. In a direction parallel to the bit line 23 , a plurality of lower plug layers 36A and a plurality of plug separation layers 32 may be alternately positioned between adjacent bit lines 23 .

The lower plug layer 36A may include a silicon-containing material. The lower plug 36A may include polysilicon, and the polysilicon may be doped with impurities. The lower plug layer 36A is connected to the second impurity region 20 . An upper surface of the lower plug layer 36A may be higher than an upper surface of the bit line 23 . After depositing polysilicon to fill the contact opening 33 and the recess region 35 to form the lower plug layer 36A, planarization and etch-back processes may be sequentially performed.

As shown in FIG. 40 , the metallic spacer 61 may be removed. Accordingly, the metallic spacer 61 may be removed between the lower plug layer 36A and the bit line 35 .

Next, a second spacer layer 37A filling the space from which the metallic spacer 61 is removed may be formed. The second spacer layer 37A may include silicon oxide. The second spacer layer 37A may be formed by selectively oxidizing portions of the lower plug 36A. The second spacer layer 27A may be formed by oxidizing portions of the first spacer layer 26A and the plug isolation layer 32 .

An oxidation process for forming the second spacer layer 37A may include radical oxidation or/and dry oxidation. For example, after radical oxidation is first performed to form the second spacer layer 37A, dry oxidation may be continuously performed. In another embodiment, in order to form the second spacer layer 37A, dry oxidation may be performed after thinly depositing the low-temperature oxide (ULTO).

During the formation of the second spacer layer 37A, portions 36B of the lower plug 36A may be lost and oxidized. Lower plugs between the bit line structures may be trimmed as shown in reference numeral 36 , and lower plugs between the plug separation layers 32 may not be trimmed.

As shown in FIG. 41 , a second spacer 37 may be formed. The second spacer 37 may be formed by selectively etching the second spacer layer 37A. An upper surface of the second spacer 37 may be positioned at the same level as an upper surface of the lower plug 36 .

The second spacer 37 may be positioned between the lower plug 36 and the bit line 23 with the first spacer 26 interposed therebetween.

As shown in FIG. 42, an upper plug 38 may be formed. The upper plug 38 may include polysilicon. The line width of the upper plug 38 may be greater than that of the lower plug 36 .

Subsequently, as referred to in FIGS. 25 and 26 , contact spacers 40 and landing pads 41 may be formed.

43 to 48 are views for explaining a manufacturing method according to another embodiment. Hereinafter, FIGS. 43 to 48 may proceed similarly to the methods shown in FIGS. 3 to 26 and 33 to 42 .

33 to 37 , a metallic spacer 61 may be formed on the first spacer layer 26A.

Next, as shown in FIG. 43 , a lower plug 36 may be formed. The lower plug 36 may completely fill the recessed regions 35 and may partially fill the contact opening 33 . The lower plug 36 may contact the second impurity region 20 . The lower plug 36 may be adjacent to the bit line structure. When viewed from a top view, a plurality of lower plugs 36 may be positioned between a plurality of bit line structures. In a direction parallel to the bit line 23 , a plurality of lower plugs 36 and a plurality of plug isolation layers 32 may be alternately positioned between adjacent bit lines 23 .

The lower plug 36 may include a silicon-containing material. The lower plug 36 may include polysilicon, and the polysilicon may be doped with impurities. The lower plug 36 is connected to the second impurity region 20 . An upper surface of the lower plug 36 may be lower than an upper surface of the bit line 23 . After depositing polysilicon to fill the contact opening 33 and the recess region 35 to form the lower plug 36 , planarization and etch-back processes may be sequentially performed.

As shown in FIG. 44, additional metallic spacers 63 may be formed. The additional metallic spacer 63 may have the same height as the metallic spacer 61 . The additional metallic spacer 63 may have a shape surrounding the sidewall of the plug separation layer 32 . A portion of the lower plug 36 may be exposed by the additional metallic spacer 63 .

A triple layer of a first spacer 26 , a metallic spacer 61 , and an additional metallic spacer 63 may be formed on both side walls of the bit line 23 . A single layer of an additional metallic spacer 63 may be formed on a sidewall of the plug separation layer 32 .

As shown in FIG. 45, an intermediate plug 64 may be formed. An intermediate plug 64 may be formed on the second metallic spacer 63 and the lower plug 36 . The intermediate plug 64 may include a silicon-containing material. The intermediate plug 64 may include polysilicon, and the polysilicon may be doped with impurities. A middle plug 64 may be formed on the lower plug 36 . The upper surface of the intermediate plug 64 may be higher than the upper surface of the bit line 23 . After depositing polysilicon to fill the remaining portion of the contact opening 33 to form the intermediate plug 64, planarization and etch-back processes may be sequentially performed.

The metallic spacer 61 and the additional metallic spacer 63 may be positioned between the middle plug 53 and the bit line 23 with the first spacer 26 interposed therebetween. An additional metallic spacer 63 may be positioned between the plug separation layer 32 and the intermediate plug 53 .

As shown in FIG. 46, metallic spacer 61 and additional metallic spacer 63 may be removed. Accordingly, the metallic spacer 61 and the additional metallic spacer 63 can be removed between the intermediate plug 64 and the bit line 35, and also between the plug separation layer 32 and the intermediate plug 64. Additional metallic spacers 63 may be eliminated. An air gap 64G may be formed by removing the metallic spacer 61 and the additional metallic spacer 63 .

As shown in FIG. 47 , a second spacer 65 may be formed to fill the air gap 64G from which the metallic spacers are removed. The second spacer 65 may include silicon oxide. The second spacer 65 may be formed by selectively oxidizing portions of the middle plug 64 .

An oxidation process for forming the second spacer 65 may include radical oxidation or/and dry oxidation. For example, after radical oxidation is first performed to form the second spacer 65 , dry oxidation may be continuously performed. In another embodiment, in order to form the second spacers 65, dry oxidation may be performed after thinly depositing low-temperature oxide (ULTO).

During formation of the second spacer 65, portions of the intermediate plug 64 may be lost and oxidized.

An upper surface of the second spacer 65 may be positioned at the same level as an upper surface of the intermediate plug 64 .

The second spacer 65 may be positioned between the intermediate plug 64 and the bit line 23 with the first spacer 26 interposed therebetween, and also between the plug separation layer 32 and the intermediate plug 64. can be located in

As shown in FIG. 48, an upper plug 38 may be formed. The upper plug 38 may include polysilicon. The line width of the upper plug 38 may be greater than that of the lower plug 36 .

Subsequently, as referred to in FIGS. 25 and 26 , contact spacers 40 and landing pads 41 may be formed.

49A to 49D are plan views illustrating a method of forming a storage node contact plug in detail.

As shown in FIGS. 15 and 49A , a plug isolation layer 32A and an initial contact opening 33A may be formed.

As shown in FIGS. 16 and 49B , a process of trimming the sacrificial spacer 29 and the plug isolation layer 32 may be performed.

As shown in FIGS. 20 and 49C , a metallic sacrificial spacer 34 and a lower plug 36A may be formed.

As shown in FIGS. 23 and 49D , after removal of the sacrificial metallic spacer 34 , a second spacer layer 37 and a trimmed lower plug 36 may be formed.

According to the above-described embodiments, it is possible to additionally secure the space of the contact openings 33 and thus secure the open margins of the contact openings 33 .

In addition, since the size of the storage node contact plug opposite to the bit line 23, that is, the lower plug 36 is reduced and the bit line spacer BLS is changed to an N-O structure, bit line parasitic capacitance can be reduced.

In addition, since the upper plug 38 of the storage node contact plug has a larger width than the lower plug 36, the contact resistance with the subsequent landing pad 40 can be increased by increasing the contact resistance.

In addition, it is possible to secure the area of the contact openings 33 by using anisotropic etching using dry etching, regardless of the type of the plug separation layer 32 .

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have knowledge of

201: substrate 202: device isolation layer
203: active region 204: hard mask layer
205: trench 206: gate insulating layer
207: buried word line 208: gate capping layer
209: first impurity region 210: second impurity region
212: bit line contact plug 213: bit line
214: bit line hard mask 215: first spacer
215G: gap fill spacer 216: second spacer
217: lower plug 218: upper plug
219: ohmic contact layer 220: landing pad

Claims (27)

a plurality of bit line structures formed spaced apart from each other on the semiconductor substrate;
first spacers formed on both side walls of each of the bit line structures;
a plurality of lower plugs formed between the plurality of bit line structures and contacting the semiconductor substrate;
an upper plug positioned above the lower plug and having a larger line width than the lower plug;
a middle plug positioned between the lower plug and the upper plug and having a smaller line width than the lower plug; and
A second spacer positioned between the intermediate plug and the first spacer but thicker than the first spacer
A semiconductor device comprising a.
According to claim 1,
The lower plug, the middle plug, and the upper plug include the same material.
According to claim 1,
The semiconductor device of claim 1 , wherein the lower plug, the middle plug, and the upper plug include polysilicon.
According to claim 1,
The first spacer includes silicon nitride, and the second spacer includes silicon oxide.
According to claim 1,
The first spacer has a line shape parallel to sidewalls of the bit line structure.
According to claim 1,
The second spacer has a shape surrounding a sidewall of the lower plug.
According to claim 1,
a landing pad above the upper plug;
an ohmic contact layer between the landing pad and the upper plug; and
Capacitor on top of the landing pad
A semiconductor device further comprising a.
According to claim 7,
The semiconductor device of claim 1 , wherein the landing pad has a shape extending to overlap an upper surface of the bit line structure.
According to claim 1,
The bit line structure,
a bit line contact plug connected to the semiconductor substrate;
a bit line over the bit line contact plug; and
Bit line hard mask on top of the bit line
A semiconductor device comprising a.
According to claim 1,
The semiconductor device further includes a gap-fill spacer in which a portion of the first spacer extends from sidewalls of the bit line contact plug and is positioned on the extended first spacer.
According to claim 1,
The lower plug,
a wide plug contacting the semiconductor substrate; and
and a narrow plug positioned on the wide plug and having a line width smaller than that of the wide plug.
forming a plurality of bit line structures on the semiconductor substrate;
forming first spacers on both side walls of the bit line structure;
forming plug separation layers and initial contact openings positioned between the bit line structures on the first spacer;
trimming the plug isolation layers and the initial contact openings to form contact openings wider than the initial contact openings;
forming sacrificial spacers surrounding sidewalls of the contact openings;
forming a lower plug partially filling the contact openings;
removing the sacrificial spacers to form air gaps surrounding the lower plugs; and
Forming a second spacer filling the air gaps while surrounding the lower plug
A semiconductor device manufacturing method comprising a.
According to claim 12,
Forming the second spacer,
and selectively oxidizing exposed surfaces of the lower plug.
According to claim 12,
Forming the second spacer,
forming a first oxide on exposed surfaces of the lower plug; and
Forming a second oxide filling the air gaps on the first oxide
A semiconductor device manufacturing method comprising a.
According to claim 12,
The second spacer is formed to be thicker than the first spacer.
According to claim 12,
The method of claim 1 , wherein the first spacer includes silicon nitride, and the second spacer includes silicon oxide.
According to claim 12,
After forming the second spacer,
and forming an upper plug having a larger line width than the lower plug on the lower plug.
According to claim 17,
The lower plug and the upper plug include polysilicon.
According to claim 12,
After forming the second spacer,
forming an upper plug having a larger line width than the lower plug on the lower plug;
forming a landing pad on top of the upper plug; and
Forming a capacitor on the landing pad
A semiconductor device manufacturing method further comprising a.
According to claim 19,
The method of claim 1 , wherein the lower plug and the upper plug include polysilicon, and the landing pad includes a metal material.
According to claim 12,
The sacrificial spacer includes titanium nitride.
forming a plurality of bit line structures on the semiconductor substrate;
forming first spacers on both side walls of the bit line structure;
forming a sacrificial spacer on the first spacer;
forming plug isolation layers and initial contact openings positioned between the bit line structures on the sacrificial spacer;
forming a lower plug partially filling the initial contact openings;
trimming the sacrificial spacer and the plug isolation layers to form contact openings wider than the initial contact openings;
forming second spacers that surround sidewalls of the contact openings but are thicker than the first spacers; and
Forming an upper plug having a larger line width than the lower plug on the second spacer and the lower plug;
A semiconductor device manufacturing method comprising a.
The method of claim 22,
The sacrificial spacer includes titanium nitride.
The method of claim 22,
The lower plug and the upper plug include polysilicon.
The method of claim 22,
The method of claim 1 , wherein the first spacer includes silicon nitride, and the second spacer includes silicon oxide.
forming a plurality of bit line structures on the semiconductor substrate;
forming first spacers on both side walls of the bit line structure;
forming a sacrificial spacer on the first spacer;
forming plug isolation layers and initial contact openings positioned between the bit line structures on the sacrificial spacer;
trimming the sacrificial spacer and plug separation layers to form contact openings wider than the initial contact openings;
forming a lower plug partially filling the initial contact openings;
removing the sacrificial spacer to form an air gap surrounding a sidewall of the lower plug;
forming a second spacer that fills the air gap and is thicker than the first spacer; and
Forming an upper plug having a larger line width than the lower plug on the second spacer and the lower plug;
A semiconductor device manufacturing method comprising a.
forming a plurality of bit line structures on the semiconductor substrate;
forming first spacers on both side walls of the bit line structure;
forming a first sacrificial spacer on the first spacer;
forming plug isolation layers and initial contact openings positioned between the bit line structures on the first sacrificial spacer;
trimming the plug isolation layers to form contact openings wider than the initial contact openings;
forming a wide plug partially filling the initial contact openings;
forming a second sacrificial spacer on the wide plug;
forming a narrow plug having a smaller line width than the wide plug on the wide plug exposed by the second sacrificial spacer;
removing the first and second sacrificial spacers to form an air gap surrounding a sidewall of the narrow plug;
forming a second spacer that fills the air gap and is thicker than the first spacer; and
forming an upper plug having a larger line width than the narrow plug on the second spacer and the narrow plug;
A semiconductor device manufacturing method comprising a.

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