CN117500269A - Semiconductor structure, manufacturing method thereof and storage device - Google Patents
Semiconductor structure, manufacturing method thereof and storage device Download PDFInfo
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- CN117500269A CN117500269A CN202311840859.9A CN202311840859A CN117500269A CN 117500269 A CN117500269 A CN 117500269A CN 202311840859 A CN202311840859 A CN 202311840859A CN 117500269 A CN117500269 A CN 117500269A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Abstract
The present disclosure provides a semiconductor structure, a method of manufacturing the same, and a memory device, the method of manufacturing including: forming an initial semiconductor structure including a plurality of initial bit line structures and a storage node contact window; forming a first conductive material layer on the surface of the structure formed by the initial bit line structure and the storage node contact window; etching the first conductive material layer and the initial bit line structure to reduce the height of the initial bit line structure, forming a target bit line structure by the residual initial bit line structure after etching, and forming a conductive contact layer by the residual first conductive material layer after etching; the surface of the conductive contact layer away from the substrate is flush with the surface of the target bit line structure away from the substrate; carrying out preset treatment on the conductive contact layer to form a first conductive layer and a second conductive layer positioned on one side of the first conductive layer away from the substrate; a third conductive layer is formed on a side of the second conductive layer remote from the substrate. The method can improve the structural defect of the device and greatly reduce the probability of short circuit in the device.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a manufacturing method thereof and a storage device.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in mobile devices such as mobile phones and tablet computers due to its small size, high integration level, and high transmission speed. The manufacturing process of the device affects the performance and yield, and the device formed by the existing semiconductor manufacturing process has structural defects, so that the short circuit phenomenon easily occurs in the device.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
In view of the above, a semiconductor structure, a manufacturing method thereof and a memory device are provided, and the manufacturing method of the semiconductor structure can improve the defect of the device structure, greatly reduce the probability of short circuit in the device structure, and further improve the yield of the device.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to one aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method comprising:
Forming an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and a plurality of initial bit line structures positioned on an array area of the substrate, and a storage node contact window is formed between adjacent initial bit line structures;
forming a first conductive material layer on the surface of a structure formed by the initial bit line structure and the storage node contact window, wherein the storage node contact window is filled with the first conductive material layer;
etching the first conductive material layer and the initial bit line structure to reduce the height of the initial bit line structure, wherein the initial bit line structure remained after etching forms a target bit line structure, and the first conductive material layer remained after etching forms a conductive contact layer; a surface of the conductive contact layer away from the substrate is flush with a surface of the target bit line structure away from the substrate;
performing preset treatment on the conductive contact layer to form a first conductive layer and a second conductive layer positioned on one side of the first conductive layer away from the substrate;
a third conductive layer is formed on a side of the second conductive layer remote from the substrate.
In an exemplary embodiment of the disclosure, the aspect ratio of the storage node contact window is 2:1 to 2.3:1.
In one exemplary embodiment of the present disclosure, the initial bit line structure has an etch height of less than or equal to 2nm when the first conductive material layer and the initial bit line structure are etched.
In an exemplary embodiment of the present disclosure, performing a preset process on the conductive contact layer to form a first conductive layer and a second conductive layer located on a side of the first conductive layer away from the substrate, includes:
forming a metal material layer on the surface of a structure formed by the conductive contact layer and the target bit line structure together;
forming an isolation barrier layer on the surface of the metal material layer;
and performing heat treatment on the metal material layer to form the second conductive layer at the interface of the conductive contact layer and the metal material layer, wherein the conductive contact layer which is not reacted with the metal material layer serves as the first conductive layer.
In an exemplary embodiment of the present disclosure, before forming the third conductive layer, the manufacturing method further includes:
and removing the isolation barrier layer and the rest of the metal material layer.
In one exemplary embodiment of the present disclosure, forming a third conductive layer on a side of the second conductive layer remote from the substrate includes:
Forming a second conductive material layer on the surface of the structure formed by the second conductive layer and the target bit line structure together;
etching the second conductive material layer to form conductive parts on different second conductive layers respectively, wherein gaps are reserved between the different conductive parts;
and etching the conductive part to reduce the thickness of a part of the region in the conductive part, wherein the rest of the conductive part is used as the third conductive layer.
In one exemplary embodiment of the present disclosure, the third conductive layer includes a first portion and a second portion connected to each other in a width direction parallel to the second conductive layer; in a direction perpendicular to the substrate, a distance between a surface of the first portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate is greater than a distance between a surface of the second portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate.
In an exemplary embodiment of the present disclosure, the manufacturing method further includes:
a passivation layer is formed overlying the third conductive layer and the target bit line structure.
In one exemplary embodiment of the present disclosure, the substrate further comprises a peripheral region provided with a peripheral transistor, source and drain regions of the peripheral transistor being covered with an insulating layer, wherein,
before forming the metal material layer on the surface of the structure formed by the conductive contact layer and the target bit line structure, the manufacturing method further comprises: etching the insulating layer to form a first contact hole exposing the source region and a second contact hole exposing the drain region;
forming a fourth conductive layer on the bottom surface of the first contact hole and forming a fifth conductive layer on the bottom surface of the second contact hole while forming the second conductive layer;
and forming a sixth conductive layer on the surface of the structure formed by the fourth conductive layer and the insulating layer positioned in the first preset area, and forming a seventh conductive layer on the surface of the structure formed by the fifth conductive layer and the insulating layer positioned in the second preset area, wherein the fourth conductive layer and the fifth conductive layer are made of the same material as the second conductive layer, and the sixth conductive layer and the seventh conductive layer are made of the same material as the third conductive layer.
According to another aspect of the present disclosure, there is provided a semiconductor structure comprising:
a substrate and a plurality of target bit line structures positioned on an array region of the substrate, wherein a storage node contact window is formed between adjacent target bit line structures;
a first conductive layer located within the storage node contact window;
a second conductive layer located on one side of the first conductive layer away from the substrate, and the surface of the second conductive layer away from the first conductive layer is flush with the surface of the target bit line structure away from the substrate;
and the third conductive layers are positioned on one side of the second conductive layers away from the substrate, and gaps are reserved between the third conductive layers.
In an exemplary embodiment of the disclosure, the aspect ratio of the storage node contact window is 2:1 to 2.3:1.
In one exemplary embodiment of the present disclosure, the third conductive layer includes a first portion and a second portion connected to each other in a width direction parallel to the second conductive layer; in a direction perpendicular to the substrate, a distance between a surface of the first portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate is greater than a distance between a surface of the second portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate.
In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:
and a passivation layer covering the third conductive layer and the target bit line structure.
In an exemplary embodiment of the disclosure, the substrate further includes a peripheral region, the peripheral region is provided with a peripheral transistor, a source region and a drain region of the peripheral transistor are covered with an insulating layer, and the semiconductor structure further includes:
a first contact plug passing through the insulating layer and disposed on a surface of the insulating layer located in a first preset region, the first contact plug including a fourth conductive layer in contact with the source region and a sixth conductive layer covering the fourth conductive layer and covering a surface of the insulating layer located in the first preset region, the fourth conductive layer being the same material as the second conductive layer, the sixth conductive layer being the same material as the third conductive layer;
the second contact plug passes through the insulating layer and is arranged on the surface of the insulating layer in a second preset area, the second contact plug comprises a fifth conductive layer and a seventh conductive layer, the fifth conductive layer is in contact with the drain region, the seventh conductive layer covers the fifth conductive layer and covers the surface of the insulating layer in the second preset area, the fifth conductive layer and the second conductive layer are made of the same material, and the seventh conductive layer and the third conductive layer are made of the same material.
According to another aspect of the present disclosure, there is provided a memory device including the above semiconductor structure.
According to the manufacturing method of the semiconductor structure, the first conductive material layer and the initial bit line structure are etched at the same time, so that the height of the initial bit line structure is reduced, the initial bit line structure left after etching forms a target bit line structure, and the first conductive material layer left after etching forms a conductive contact layer; and the surface of the conductive contact layer far away from the substrate is flush with the surface of the target bit line structure far away from the substrate, so that the appearance of the second conductive layer formed on the first conductive layer can be improved after the conductive contact layer is subjected to preset treatment, the probability of short circuit inside the device can be greatly reduced, and the yield of the device is improved.
The semiconductor structure provided by the disclosure is characterized in that the surface of the second conductive layer arranged in the storage node contact window is flush with the surface of the target bit line structure, so that the short circuit probability generated by the third conductive layer and the storage contact node is greatly reduced, the defect of the internal structure of the device is fewer, and the device performance is better.
The memory device provided by the disclosure comprises the semiconductor structure, and has good structure and performance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic structural view of a conventional semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 2 is a flow chart of a method of fabricating a semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic structural view of a semiconductor structure forming an initial bit line structure in an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural view of a semiconductor structure forming a target bit line structure in an exemplary embodiment of the present disclosure.
Fig. 5 is a schematic structural view of a semiconductor structure forming a metal material layer and an isolation barrier in an exemplary embodiment of the present disclosure.
Fig. 6 is a schematic structural view of a semiconductor structure forming a second conductive layer in an exemplary embodiment of the present disclosure.
Fig. 7 is a schematic structural view of a semiconductor structure during formation of a third conductive layer in an exemplary embodiment of the present disclosure.
Fig. 8 is a schematic structural view of a semiconductor structure during formation of a third conductive layer in another exemplary embodiment of the present disclosure.
Fig. 9 is a schematic structural view of a semiconductor structure during formation of a third conductive layer in another exemplary embodiment of the present disclosure.
Fig. 10 is a schematic structural view of a semiconductor structure forming a third conductive layer in an exemplary embodiment of the present disclosure.
Fig. 11 is a schematic structural view of a semiconductor structure forming a passivation layer in an exemplary embodiment of the present disclosure.
Wherein reference numerals are as follows:
1000. a bit line structure; 1001. a conductive structure; 1002. a first storage node contact window; 100. a substrate; 110. an initial bit line structure; 120. a target bit line structure; 200. storing node contact windows; 201. a first conductive material layer; 202. a second conductive material layer; 210. a conductive contact layer; 220. a conductive portion; 203. a metal material layer; 204. an isolation barrier; 313. a first sub-conductive layer; 3130. a first sub-conductive material layer; 323. a second sub-conductive layer; 3230. a second sub-conductive material layer; 301. a first conductive layer; 302. a second conductive layer; 303. a third conductive layer; 400. a passivation layer; 500. a mask layer; 600. a photoresist layer; 3031. a first portion; 3032. a second portion.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
In the related art, as shown in fig. 1, a first storage node contact window 1002 is formed between bit line structures 1000 in a memory, and is used to form a conductive structure 1001 to improve contact resistance inside the device. At present, due to the limitation of the manufacturing process, the bit line structure 1000 has a higher height, the formed storage node contact window 200 often has a larger aspect ratio, the range of the aspect ratio is 2.4:1 to 2.6:1, the larger aspect ratio can cause air gaps in the conductive structure 1001 film layer formed in the first storage node contact window 1002 later, and the formed film layer has a poor shape (as shown in the area a in fig. 1), so that the device short circuit problem occurs.
Based on this, the embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, as shown in fig. 2, including: step S100 to step S500.
Wherein, step S100: forming an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and a plurality of initial bit line structures positioned on an array area of the substrate, and a storage node contact window is formed between adjacent initial bit line structures;
step S200: forming a first conductive material layer on the surface of a structure formed by the initial bit line structure and the storage node contact window, wherein the storage node contact window is filled with the first conductive material layer;
step S300: etching the first conductive material layer and the initial bit line structure to reduce the height of the initial bit line structure, wherein the initial bit line structure remained after etching forms a target bit line structure, and the first conductive material layer remained after etching forms a conductive contact layer; a surface of the conductive contact layer away from the substrate is flush with a surface of the target bit line structure away from the substrate;
step S400: performing preset treatment on the conductive contact layer to form a first conductive layer and a second conductive layer positioned on one side of the first conductive layer away from the substrate;
Step S500: a third conductive layer is formed on a side of the second conductive layer remote from the substrate.
According to the manufacturing method of the semiconductor structure, the first conductive material layer and the initial bit line structure are etched at the same time, the initial bit line structure remained after etching forms a target bit line structure, and the first conductive material layer remained after etching forms a conductive contact layer; and the surface of the conductive contact layer far away from the substrate is flush with the surface of the target bit line structure far away from the substrate, so that after the conductive contact layer is subjected to preset treatment, the air gap phenomenon of the conductive contact layer formed in the storage node contact window can be improved, the appearance of a second conductive layer formed on the first conductive layer is improved, the probability of short circuit inside a device can be greatly reduced, and the yield of the device is improved.
The following describes in detail each step of the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure with reference to the accompanying drawings:
in step S100, as shown in fig. 3, an initial semiconductor structure is formed, where the initial semiconductor structure includes a substrate 100 and a plurality of initial bit line structures 110 located on an array region of the substrate 100, and a storage node contact window 200 is formed between adjacent initial bit line structures 110.
In embodiments provided by the present disclosure, the substrate 100 may be a semiconductor substrate, for example, may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Ge Si) substrate, SOI (silicon on insulator ) or GOI (germanium on insulator, germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs), or the like. The substrate 100 may be selected according to actual design requirements of the semiconductor structure, and the present disclosure is not particularly limited.
The substrate 100 includes an array region and a peripheral region, wherein a plurality of active regions and isolation structures between adjacent active regions are formed on the array region of the substrate 100. A plurality of initial bit line structures 110 are formed in the array region of the substrate 100, and a storage node contact window 200 is formed between adjacent initial bit line structures 110.
Each of the initial bit line structures 110 may include a metal conductive structure, which may include a metal layer, a diffusion barrier layer, and other film layers, and a dielectric layer structure, which may be NON (Nitride Oxide Nitride), although the initial bit line structures 110 may include other film layer structures not shown, it should be understood that the specific film layer structures of the initial bit line structures 110 are available in the art, and suitable modifications and combinations thereof, as well as are within the scope of the present disclosure.
In some embodiments, the storage node contact windows 200 are formed between adjacent initial bit line structures 110, in order to ensure the formation quality of the subsequent conductive layers, air gaps inside the conductive layers formed in the storage node contact windows 200 are eliminated, and after the initial bit line structures 110 are formed, the height of the initial bit line structures 110 may be reduced from the top surface to the bottom surface of the substrate 100 in a direction perpendicular to the substrate 100, so as to primarily reduce the aspect ratio of the storage node contact windows 200 formed between the adjacent initial bit line structures 110.
In step S200, as shown in fig. 3, a first conductive material layer 201 is formed on a surface of a structure formed by the initial bit line structure 110 and the storage node contact window 200, and the first conductive material layer 201 fills the storage node contact window 200.
The first conductive material layer 201 may be a semiconductor film layer such as a polysilicon (poly) layer. The first conductive material layer 201 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), low-pressure chemical vapor deposition (Low-Pressure Chemical Vapor Deposition, LPCVD), sputter deposition (Sputter Deposition), thermal decomposition (Thermal Decomposition), etc., and may be selected according to factors such as actual manufacturing process or manufacturing equipment of the device.
In step S300, as shown in fig. 4, the first conductive material layer 201 and the initial bit line structure 110 are etched to reduce the height of the initial bit line structure 110, the initial bit line structure 110 remaining after etching forms the target bit line structure 120, and the first conductive material layer 201 remaining after etching forms the conductive contact layer 210; the surface of the conductive contact layer 210 remote from the substrate 100 is flush with the surface of the target bit line structure 120 remote from the substrate 100.
The first conductive material layer 201 and the initial bit line structure 110 are etched using a Dry etch (Dry Etching), such as inductively coupled plasma etch (Inductively Coupled Plasma Etching, ICP), reactive ion beam etch (Reactive Ion Beam Etching, RIBE), electron beam etch (Electron Beam Etching); wet Etching (Wet Etching), such as acidic Wet Etching (Acidic Wet Etching), alkaline Wet Etching (Alkaline Wet Etching); laser Etching (Laser Etching); etching methods such as Ion Beam Etching (Ion Beam Etching) can be selected according to the specific film material of the structure, and the disclosure is not limited in detail.
In the embodiments provided by the present disclosure, the aspect ratio of the storage node contact window 200 between adjacent initial bit line structures 110 may be reduced by reducing the height of the formed initial bit line structures 110 or reducing the deposition height of silicon nitride of the formed initial bit line structures 110. In the present disclosure, the aspect ratio of the storage node contact window 200 is 2:1 to 2.3:1, for example, may be 2:1, a step of; 2.1:1;2.2:1;2.3:1, etc., compared with the existing aspect ratio of the storage node contact window 200 of 2.4:1-2.6:1, the aspect ratio of the storage node contact window 200 in the disclosure can be reduced by 10% -30%, the aspect ratio of the storage node contact window 200 is greatly reduced, the morphology of each conductive layer formed in the storage node contact window 200 is improved, the air gap phenomenon of the conductive contact layer formed in the storage node contact window is improved, the abnormal problem of the metal material layer formed in the storage node contact window is further improved, and therefore the metal material layer can better contact with the conductive contact layer and form a second conductive layer with excellent morphology at the junction, and the probability of internal short circuit of a device is greatly reduced. At the same time, the height of the formed initial bit line structure 110 is reduced or the deposition height of silicon nitride of the formed initial bit line structure 110 is reduced, so that the deposition temperature/time of silicon nitride is reduced, thereby avoiding adverse effects of high temperature on the device for a long time.
Further, by simultaneously etching the first conductive material layer 201 and the initial bit line structures 110 to reduce the height of the initial bit line structures 110, the aspect ratio of the storage node contact windows 200 between adjacent initial bit line structures 110 is further reduced. In the embodiment provided in the present disclosure, when the first conductive material layer 201 and the initial bit line structure 110 are etched, the etching height of the initial bit line structure 110 should not be too large, and the working film layer of the initial bit line structure 110 may be damaged when the etching height of the initial bit line structure 110 should not be too small, and if the etching height is too small, the effect of improving the aspect ratio of the storage node contact window 200 may not be achieved. In the present disclosure, the etch height of the initial bit line structure 110 needs to be less than or equal to 2nm, for example, the etch height of the initial bit line structure 110 may be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, which achieves the effect of improving the aspect ratio of the storage node contact window 200 while ensuring that the structural integrity of the bit line structure is not compromised.
In the embodiments provided in the present disclosure, the level positional relationship between the film layers may be non-strictly level, and due to the manufacturing process error and different process methods, different effects are generated on the film layers of different materials, for example, when etching the film layers of different materials simultaneously, due to different etching rates, the thickness of the different film layers etched at the etching stop time is different. Therefore, the level between the surfaces of the plurality of film layers may refer to zero height difference between the surfaces, or may refer to that the height difference between the two surfaces is within a certain error range, taking the level of the surfaces of the two film layers as an example, the height difference between the two surfaces may be in a range of 0-5 nm, and may all belong to a level setting, for example, the height difference between the two surfaces may be 1nm, 2nm, 3nm, 4nm or 5nm. The specific height difference range can be adaptively adjusted according to the actual process requirements of the device.
In step S400, the conductive contact layer 210 is subjected to a preset process to form a first conductive layer 301 and a second conductive layer 302 located on a side of the first conductive layer 301 away from the substrate 100.
In step S300, the first conductive material layer 201 is etched to form the conductive contact layer 210, and if the first conductive material layer 201 is a polysilicon layer, the conductive contact layer 210 is an etched polysilicon layer. Wherein forming the first conductive layer 301 and the second conductive layer 302 includes: step S401 to step S403.
Wherein, step S401: forming a metal material layer 203 on the surface of the structure formed by the conductive contact layer 210 and the target bit line structure 120;
step S402: forming an isolation barrier 204 on the surface of the metal material layer 203;
step S403: the metal material layer 203 is subjected to a heat treatment to form a second conductive layer 302 at the interface of the conductive contact layer 210 and the metal material layer 203, the conductive contact layer 210 that is not reacted with the metal material layer 203 serving as a first conductive layer 301.
In step S401, as shown in fig. 5, a metal material layer 203 is formed on the surface of the structure formed by the conductive contact layer 210 and the target bit line structure 120. The metal material layer 203 may be one or more of cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), or platinum (Pt). In this embodiment, the metal material layer 203 may be cobalt (Co), and may be formed by physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), nano-thickness metal evaporation or Hot-dip plating (Hot-dip plating), and the like.
In step S402, as shown in fig. 5, an isolation barrier 204 is formed on the surface of the metal material layer 203. The isolation barrier 204 may be a film layer with a barrier function such as titanium nitride (TiN), and in this embodiment, the isolation barrier 204 is used to isolate the metal material layer 203, prevent metal ions in the metal material layer 203 from reacting with a film layer outside the preset area, and also prevent metal ions in the metal material layer 203 from reacting with ions in the outside air such as oxidation, so as to change the properties of metal elements in the metal material layer 203.
The isolation barrier 204 may be formed by physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), ion Implantation (Ion Implantation), etc., and the specific forming method may be selected according to the specific material and actual requirement of the film.
In step S403, as shown in fig. 6, the metal material layer 203 is subjected to heat treatment to form a second conductive layer 302 at the interface of the conductive contact layer 210 and the metal material layer 203, the conductive contact layer 210 that does not react with the metal material layer 203 serving as the first conductive layer 301.
The metal material layer 203 and the conductive contact layer 210 react to form a metal compound by a heat treatment process, for example, the metal material layer 203 is cobalt metal, the conductive contact layer 210 is polysilicon layer, and cobalt silicide (CoSi) is formed by a rapid heat treatment process reaction 2 ). The heat treatment process may include a rapid thermal process (Rapid Thermal Processing, RTP) process, and the heat treatment process may include one or more treatments, for example, two RTP processes may be used according to different reaction times and reaction products, each time the temperature of the RTP process is different, the reaction rate or time and the reaction efficiency are improved, and specific heat treatment parameters may be selected according to specific process requirements.
Since the reaction of the metal material layer 203 (e.g., metal cobalt) with the conductive contact layer 210 (e.g., polysilicon) generally occurs at and near the contact surface of the metal material layer 203 and the conductive contact layer 210, a second conductive layer is formed at the interface of the conductive contact layer 210 and the metal material layer 203An electrical layer 302, the conductive contact layer 210 that is not reacted with the metal material layer 203 serves as a first conductive layer 301, wherein the first conductive layer 301 may be a polysilicon (poly) layer and the second conductive layer 302 may be cobalt silicide (CoSi) 2 ) Of course, depending on the kind of metal in the metal material layer 203, the second conductive layer 302 may be nickel silicide (NiSi 2 ) Molybdenum silicide (MoSi) 2 ) Titanium silicide (TiSi) 2 ) Tungsten silicide (WSi) 2 ) Tantalum silicide (TaSi) 2 ) Or one or more of platinum silicide (PtSi).
After step S403, the method further comprises: the isolation barrier 204 and the remaining metal material layer 203 are removed. The isolation barrier 204 and the remaining metal material layer 203 may be removed by chemical mechanical polishing (Chemical Mechanical Polishing, CMP), dry Etching (Dry Etching), wet Etching (Wet Etching), or the like. The isolation barrier 204 and the remaining metal material layer 203 may be removed simultaneously by the same or different etching methods, or the isolation barrier 204 and the remaining metal material layer 203 may be removed separately by the same or different etching methods.
After removing the isolation barrier 204 and the remaining metal material layer 203, the surface of the second conductive layer 302 and the surface of the target bit line structure 120 are exposed, as shown in fig. 6, where the surface of the second conductive layer 302 is substantially flush with the surface of the target bit line structure 120, and due to process limitations, the surface of the second conductive layer 302 may be slightly higher than the surface of the target bit line structure 120, and the difference in height between the two surfaces is within a predetermined range, which can be understood as being substantially flush. Preferably, the surface of the second conductive layer 302 is flush with the surface of the target bit line structure 120.
In the present disclosure, since the aspect ratio of the storage node contact window 200 is smaller, when the isolation barrier 204 and the remaining metal material layer 203 are removed, the residue of the metal material on the inner sidewall of the storage node contact window 200 can be reduced, and the occurrence probability of a short circuit due to the metal residue is reduced; in addition, since the aspect ratio of the storage node contact window 200 is smaller, the air gap phenomenon of the conductive contact layer formed in the storage node contact window can be improved, and the abnormal problem of the metal material layer is improved, so that the metal material layer can be better contacted with the conductive contact layer, and a second conductive layer with excellent morphology can be formed at the junction, further, the structural defect of the device is reduced, and the performance of the device is improved.
Wherein, in step S500, forming the third conductive layer 303 on the side of the second conductive layer 302 away from the substrate 100 includes: step S501 to step S503.
Wherein, step S501: forming a second conductive material layer 202 on the surface of the structure formed by the second conductive layer 302 and the target bit line structure 120;
step S502: etching the second conductive material layer 202 to form conductive portions 220 on different second conductive layers 302, respectively, with gaps between the different conductive portions 220;
Step S503: the conductive portion 220 is etched so that the thickness of a partial region in the conductive portion 220 is reduced, and the remaining conductive portion 220 serves as the third conductive layer 303.
In step S501, as shown in fig. 7, the second conductive material layer 202 is formed on the surface of the structure formed by the second conductive layer 302 and the target bit line structure 120, and the second conductive layer 302 may include the first sub-conductive material layer 3130 and the second sub-conductive material layer 3230, where the first sub-conductive material layer 3130 and the second sub-conductive material layer 3230 are sequentially formed on the surface of the structure formed by the second conductive layer 302 and the target bit line structure. The first sub-conductive material layer 3130 may be formed of a diffusion barrier material, such as a titanium nitride (TiN) layer or the like; the second sub-conductive material layer 3230 may be formed of a metal material, such as tungsten (W), copper (Cu), aluminum (Al), or the like. The first sub-conductive material layer 3130 and the second sub-conductive material layer 3230 may be formed by physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), ion Implantation (Ion Implantation), or the like, and the specific forming method may be selected according to the specific material and the actual requirement of the film layer.
In step S502, as shown in fig. 8, the second conductive material layer 202 is etched to form conductive portions 220 on different second conductive layers 302, and gaps are formed between the different conductive portions 220. The etching of the second conductive material layer 202 includes etching the first sub-conductive material layer 3130 and the second sub-conductive material layer 3230, so that the first sub-conductive material layer 3130 forms a first sub-conductive layer 313, the second sub-conductive material layer 3230 forms a second sub-conductive layer 323, the first sub-conductive layer 313 and the second sub-conductive layer 323 form conductive portions 220, and sidewalls of the etched first sub-conductive material layer 3130 and second sub-conductive material layer 3230 in each conductive portion 220 are flush in a direction perpendicular to the substrate 100.
Each of the second conductive layers 302 is correspondingly formed with one conductive portion 220, and the plurality of conductive portions 220 are spaced apart from each other, and gaps are formed between the different conductive portions 220. The width of the gap is not too large in a direction parallel to the substrate 100, and the too large gap width reduces the effective width of the conductive portion 220, reducing the conductivity of the conductive portion 220; the width of the gap is not too small, which may result in reduced insulation between adjacent conductive portions 220, with the risk of short circuits. For example, in a direction parallel to the substrate 100, the width of the gap may be 20nm to 60nm, so that the width of the conductive portion 220 is ensured, and good insulation between adjacent conductive portions 220 may be formed.
In an embodiment provided in the present disclosure, in step S503, as shown in fig. 8, 9 and 10, the conductive portion 220 is etched to reduce the thickness of a partial region in the conductive portion 220, and the remaining conductive portion 220 serves as the third conductive layer 303.
The conductive portion 220 may be etched by Dry Etching (Dry Etching), wet Etching (Wet Etching), laser Etching (Laser Etching), ion Beam Etching (Ion Beam Etching), or the like. Specifically, the method for etching the conductive portion 220 includes: forming a mask layer 500 covering the surface of each conductive portion 220 and the target bit line structure 120; forming a photoresist layer 600 on the mask layer 500; each of the conductive portions 220 is etched using the photoresist layer 600 and the mask layer 500 so that the thickness of a partial region in the conductive portion 220 is reduced. The mask layer 500 may be a Spin On hard mask (SOH), through which etched regions and locations On the conductive portions 220 may be defined and other portions of the device may be protected. After etching the conductive portion 220, the method further includes: the photoresist layer 600 and the mask layer 500 are removed to expose the etched conductive portions 220.
The third conductive layer 303 includes a first portion 3031 and a second portion 3032 connected to each other in a width direction parallel to the second conductive layer 302; the distance between the surface of the first portion 3031 remote from the second conductive layer 302 and the surface of the second conductive layer 302 remote from the substrate 100 in a direction perpendicular to the substrate 100 is greater than the distance between the surface of the second portion 3032 remote from the second conductive layer 302 and the surface of the second conductive layer 302 remote from the substrate 100, increasing the process window of the third conductive layer 303, facilitating the connection and layout of subsequent structures or wires.
In another embodiment provided in the present disclosure, the conductive portion 220 formed in step S502 may also be directly used as the third conductive layer 303, and the electrical connection between the target bit line structure 120 structure and other structures (such as a capacitor structure) in the device may be achieved through the third conductive layer 303.
In the above two embodiments, the maximum width of the third conductive layer 303 is slightly greater than or equal to the maximum width of the second conductive layer 302 in the direction parallel to the substrate 100, where the maximum width of the third conductive layer 303 may be slightly greater than the maximum width of the second conductive layer 302, so as to ensure that the third conductive layer 303 is in full contact with the surface of the second conductive layer 302, effectively reduce the contact resistance, and improve the device performance, and of course, the maximum width of the third conductive layer 303 may also be equal to the maximum width of the second conductive layer 302.
As shown in fig. 11, after forming the third conductive layer 303, the manufacturing method further includes: a passivation layer 400 is formed covering the third conductive layer 303 and the target bit line structure 120. The passivation layer 400 fills the gap between adjacent third conductive layers 303 and extends to the surface of the third conductive layers 303, and the surface of the passivation layer 400 may be parallel to the substrate 100. Wherein the passivation layer 400 may be silicon nitride (Si 3 N 4 ) Silicon oxide (SiO) 2 ) Or alumina (Al) 2 O 3 ) And the like; the passivation layer 400 may pass throughPhysical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), ion Implantation (Ion Implantation), etc., and the specific forming method may be selected according to the specific material and actual requirements of the film layer. The passivation layer 400 covers the surfaces of the third conductive layer 303 and the target bit line structure 120, and may protect the semiconductor device, repair surface defects, reduce contact resistance, and the like, and may improve device performance, stability, and reliability.
In addition, the substrate 100 further includes a peripheral region, the peripheral region is provided with a peripheral transistor, and source and drain regions of the peripheral transistor are covered with an insulating layer, wherein before the surface of the structure formed by the conductive contact layer 210 and the target bit line structure 120 forms the metal material layer 203, the manufacturing method further includes:
etching the insulating layer to form a first contact hole exposing the source region and a second contact hole exposing the drain region;
forming a fourth conductive layer on the bottom surface of the first contact hole and forming a fifth conductive layer on the bottom surface of the second contact hole while forming the second conductive layer 302;
While the third conductive layer 303 is formed on the side of the second conductive layer 302 away from the substrate 100, a sixth conductive layer is formed on the surface of the structure formed by the fourth conductive layer and the insulating layer located in the first preset region, and a seventh conductive layer is formed on the surface of the structure formed by the fifth conductive layer and the insulating layer located in the second preset region, the fourth conductive layer and the fifth conductive layer are both made of the same material as the second conductive layer 302, and the sixth conductive layer and the seventh conductive layer are both made of the same material as the third conductive layer 303.
The fourth conductive layer and the sixth conductive layer form a first contact plug in the first contact hole, and the fifth conductive layer and the seventh conductive layer form a second contact plug in the second contact hole.
The fourth and fifth conductive layers are each the same material as the second conductive layer 302, and may be, for example, a silicide layer, for example, cobalt silicide (CoSi 2 ) Nickel silicide (NiSi) 2 ) Molybdenum silicide (MoSi) 2 ) Titanium silicide (TiSi) 2 ) Tungsten silicide (WSi) 2 ) Tantalum silicide (TaSi) 2 ) Or platinum silicide (PtSi), in the present disclosure, preferably, the materials of the fourth and fifth conductive layers and the second conductive layer 302 may be cobalt silicide (CoSi) 2 ). The fourth conductive layer and the fifth conductive layer are both the same as the second conductive layer 302, and are not described here again.
The sixth conductive layer and the seventh conductive layer are both the same as the third conductive layer 303, for example, the sixth conductive layer and the seventh conductive layer may be formed of two different conductive material layers, for example, may be formed of a diffusion barrier layer and a metal layer together, for example, may be formed of a titanium nitride (TiN) layer and a tungsten (W) layer together. The sixth conductive layer and the seventh conductive layer are both formed by the same method as the third conductive layer 303, and will not be described here again.
After the passivation layer 400 is formed to cover the third conductive layer 303 and the target bit line structure 120, the passivation layer 400 covers the surfaces of the first contact plug and the second contact plug at the same time, and the passivation layer 400 can protect the first contact plug and the second contact plug, and can repair surface defects of the device and reduce contact resistance. The passivation layer 400 in the peripheral area and the passivation layer 400 in the array area may be formed simultaneously, so that the process steps are simplified, and the production efficiency is improved.
In the embodiments provided in the present disclosure, the peripheral transistors may be metal-oxide-semiconductor field effect transistors (MOSFETs), junction Field Effect Transistors (JFETs), or the like, and the plurality of peripheral transistors may be formed at intervals in an active region within a peripheral region of the substrate 100, and each peripheral transistor is electrically connected to other structures in the device through a source/drain electrode to perform a function of adjusting a signal of the device. The first contact plug is contacted with the source electrode area of the peripheral transistor, and the second contact plug is contacted with the drain electrode area of the peripheral transistor, so that the peripheral transistor is electrically connected with other structures in the device through the first contact plug and the second contact plug, the contact resistance can be reduced, and the device performance can be improved.
It should be noted that although the various steps of the method of fabricating a semiconductor structure in this disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
Embodiments of the present disclosure provide a semiconductor structure, as shown in fig. 11, including:
a substrate 100 and a plurality of target bit line structures 120 on an array region of the substrate 100, a storage node contact window 200 being formed between adjacent target bit line structures 120;
a first conductive layer 301 located within the storage node contact window 200;
a second conductive layer 302, which is located on one side of the first conductive layer 301 away from the substrate 100, and the surface of the second conductive layer 302 away from the first conductive layer 301 is flush with the surface of the target bit line structure 120 away from the substrate 100;
the third conductive layer 303 is located on a side of the second conductive layer 302 away from the substrate 100, and a gap is formed between the third conductive layers.
The semiconductor structure provided by the disclosure is characterized in that the surface of the second conductive layer arranged in the storage node contact window is flush with the surface of the target bit line structure, so that the occurrence probability of short circuit generated by the third conductive layer and the storage contact node is greatly reduced, the defect of the internal structure of the device is fewer, and the performance of the device is better.
Various portions of the semiconductor structure provided by embodiments of the present disclosure are described in detail below with reference to the attached drawing figures:
in the embodiment provided in the present disclosure, the aspect ratio of the storage node contact window 200 is 2:1 to 2.3:1, for example, may be 2:1, a step of; 2.1:1;2.2:1;2.3:1, etc., compared with the existing aspect ratio of the storage node contact window 200 of 2.4:1-2.6:1, the aspect ratio of the storage node contact window 200 in the disclosure can be reduced by 10% -30%, the aspect ratio of the storage node contact window 200 is greatly reduced, the morphology of each conductive layer formed in the storage node contact window 200 is improved, the air gap phenomenon of the conductive contact layer formed in the storage node contact window is improved, the abnormal problem of the metal material layer formed in the storage node contact window is further improved, and therefore the metal material layer can better contact with the conductive contact layer and form a second conductive layer with excellent morphology at the junction, the probability of internal short circuit of a device is greatly reduced, and the performance of the device is further improved.
In the embodiment provided in the present disclosure, as shown in fig. 10, the third conductive layer 303 includes a first portion 3031 and a second portion 3032 connected to each other in a width direction parallel to the second conductive layer 302; the distance between the surface of the first portion 3031 remote from the second conductive layer 302 and the surface of the second conductive layer 302 remote from the substrate 100 in a direction perpendicular to the substrate 100 is greater than the distance between the surface of the second portion 3032 remote from the second conductive layer 302 and the surface of the second conductive layer 302 remote from the substrate 100, increasing the process window of the third conductive layer 303, facilitating the connection and layout of subsequent structures or wires.
In the embodiment provided by the present disclosure, as shown in fig. 11, the semiconductor structure further includes a passivation layer 400 covering the third conductive layer 303 and the target bit line structure 120. Wherein the passivation layer 400 may be silicon nitride (Si 3 N 4 ) Silicon oxide (SiO) 2 ) Or alumina (Al) 2 O 3 ) Such materials, the particular materials may be selected based on the actual design requirements of the device. The passivation layer 400 covers the surfaces of the third conductive layer 303 and the target bit line structure 120, and can protect the semiconductor device from repairing surface defects and reducing contact resistance, and can improve device performance, stability and reliability. In addition, the passivation layer 400 also covers the surface of the peripheral region, that is, the passivation layer 400 can be formed at the same time in the peripheral region and the array region, so that the process steps are simplified, and the production efficiency is improved.
In the embodiment provided in the present disclosure, the substrate 100 further includes a peripheral region, the peripheral region is provided with a peripheral transistor, and an insulating layer is covered on a source region and a drain region of the peripheral transistor, and the semiconductor structure further includes: a first contact plug and a second contact plug.
The first contact plug passes through the insulating layer and is disposed on the surface of the insulating layer in the first preset area, the first contact plug includes a fourth conductive layer and a sixth conductive layer, the fourth conductive layer contacts the source region, the sixth conductive layer covers the fourth conductive layer and covers the surface of the insulating layer in the first preset area, the fourth conductive layer is the same as the second conductive layer 302, and the sixth conductive layer is the same as the third conductive layer 303.
The second contact plug passes through the insulating layer and is disposed on the surface of the insulating layer in the second preset region, the second contact plug includes a fifth conductive layer and a seventh conductive layer, the fifth conductive layer is in contact with the drain region, the seventh conductive layer covers the fifth conductive layer and covers the surface of the insulating layer in the second preset region, the fifth conductive layer is the same as the second conductive layer 302, and the seventh conductive layer is the same as the third conductive layer 303.
Specifically, the fourth conductive layer and the fifth conductive layer are both the same as the second conductive layer 302, and may be silicide layers, for example, cobalt silicide (CoSi 2 ) Nickel silicide (NiSi) 2 ) Molybdenum silicide (MoSi) 2 ) Titanium silicide (TiSi) 2 ) Tungsten silicide (WSi) 2 ) Tantalum silicide (TaSi) 2 ) Or platinum silicide (PtSi), in the present disclosure, preferably, the materials of the fourth and fifth conductive layers and the second conductive layer 302 may be cobalt silicide (CoSi) 2 ). The fourth conductive layer and the fifth conductive layer are both the same as the second conductive layer 302, and are not described here again.
The sixth conductive layer and the seventh conductive layer are both the same as the third conductive layer 303, for example, the sixth conductive layer and the seventh conductive layer may be formed of two different conductive material layers, for example, may be formed of a diffusion barrier layer and a metal layer together, for example, may be formed of a titanium nitride (TiN) layer and a tungsten (W) layer together. The sixth conductive layer and the seventh conductive layer are both formed by the same method as the third conductive layer 303, and will not be described here again.
The passivation layer 400 covers both the surface of the first contact plug and the surface of the second contact plug to protect the first contact plug and the second contact plug.
The semiconductor structure provided by the disclosure comprises a peripheral transistor, wherein the first contact plug is contacted with a source electrode area of the peripheral transistor, and the second contact plug is contacted with a drain electrode area of the peripheral transistor, so that the peripheral transistor is electrically connected with other structures in the device through the first contact plug and the second contact plug, the contact resistance can be reduced, the transmission efficiency of current and signals is improved, and the performance of the device is further improved.
Other specific structures in the semiconductor structure provided in the present disclosure are described in the above method for manufacturing a semiconductor structure, and are not described herein.
Embodiments of the present disclosure provide a memory device including the above semiconductor structure.
The Memory device of the present disclosure may be one of a static random access Memory (Static Random Access Memory, SRAM), a dynamic random access Memory (Dynamic Random Access Memory, DRAM), a Flash Memory (Flash Memory), a configuration Memory (Configuration Memory), a Flash Memory (NOR Flash Memory), a phase change Memory (Phase Change Memory, PCM), a magnesium punch register (Magnetoresistive Random Access Memory, MRAM), or a resistance change Memory (Resistive Random Access Memory, reRAM). The specific type of the storage device can be determined according to the actual application scene.
The storage device provided by the disclosure has the advantages of few structural defects, better performance and the like.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
forming an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate and a plurality of initial bit line structures positioned on an array area of the substrate, and a storage node contact window is formed between adjacent initial bit line structures;
forming a first conductive material layer on the surface of a structure formed by the initial bit line structure and the storage node contact window, wherein the storage node contact window is filled with the first conductive material layer;
Etching the first conductive material layer and the initial bit line structure to reduce the height of the initial bit line structure, wherein the initial bit line structure remained after etching forms a target bit line structure, and the first conductive material layer remained after etching forms a conductive contact layer; a surface of the conductive contact layer away from the substrate is flush with a surface of the target bit line structure away from the substrate;
performing preset treatment on the conductive contact layer to form a first conductive layer and a second conductive layer positioned on one side of the first conductive layer away from the substrate;
a third conductive layer is formed on a side of the second conductive layer remote from the substrate.
2. The method of claim 1, wherein the aspect ratio of the storage node contact is 2:1-2.3:1.
3. The method of manufacturing of claim 1, wherein an etch height of the initial bit line structure is less than or equal to 2nm when the first conductive material layer and the initial bit line structure are etched.
4. A method of manufacturing as claimed in any one of claims 1 to 3, wherein the pre-treating the conductive contact layer to form a first conductive layer and a second conductive layer on a side of the first conductive layer remote from the substrate comprises:
Forming a metal material layer on the surface of a structure formed by the conductive contact layer and the target bit line structure together;
forming an isolation barrier layer on the surface of the metal material layer;
and performing heat treatment on the metal material layer to form the second conductive layer at the interface of the conductive contact layer and the metal material layer, wherein the conductive contact layer which is not reacted with the metal material layer serves as the first conductive layer.
5. The manufacturing method according to claim 4, characterized in that before forming the third conductive layer, the manufacturing method further comprises:
and removing the isolation barrier layer and the rest of the metal material layer.
6. A method of manufacturing according to any one of claims 1 to 3, wherein forming a third conductive layer on a side of the second conductive layer remote from the substrate comprises:
forming a second conductive material layer on the surface of the structure formed by the second conductive layer and the target bit line structure together;
etching the second conductive material layer to form conductive parts on different second conductive layers respectively, wherein gaps are reserved between the different conductive parts;
and etching the conductive part to reduce the thickness of a part of the region in the conductive part, wherein the rest of the conductive part is used as the third conductive layer.
7. The manufacturing method according to claim 6, wherein the third conductive layer includes a first portion and a second portion connected to each other in a width direction parallel to the second conductive layer; in a direction perpendicular to the substrate, a distance between a surface of the first portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate is greater than a distance between a surface of the second portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate.
8. A method of manufacturing according to any one of claims 1 to 3, further comprising:
a passivation layer is formed overlying the third conductive layer and the target bit line structure.
9. The method of manufacturing as claimed in claim 4, wherein the substrate further comprises a peripheral region provided with a peripheral transistor, source and drain regions of the peripheral transistor are covered with an insulating layer, wherein,
before forming the metal material layer on the surface of the structure formed by the conductive contact layer and the target bit line structure, the manufacturing method further comprises: etching the insulating layer to form a first contact hole exposing the source region and a second contact hole exposing the drain region;
Forming a fourth conductive layer on the bottom surface of the first contact hole and forming a fifth conductive layer on the bottom surface of the second contact hole while forming the second conductive layer;
and forming a sixth conductive layer on the surface of the structure formed by the fourth conductive layer and the insulating layer positioned in the first preset area, and forming a seventh conductive layer on the surface of the structure formed by the fifth conductive layer and the insulating layer positioned in the second preset area, wherein the fourth conductive layer and the fifth conductive layer are made of the same material as the second conductive layer, and the sixth conductive layer and the seventh conductive layer are made of the same material as the third conductive layer.
10. A semiconductor structure, comprising:
a substrate and a plurality of target bit line structures positioned on an array region of the substrate, wherein a storage node contact window is formed between adjacent target bit line structures;
a first conductive layer located within the storage node contact window;
a second conductive layer located on one side of the first conductive layer away from the substrate, and the surface of the second conductive layer away from the first conductive layer is flush with the surface of the target bit line structure away from the substrate;
And the third conductive layers are positioned on one side of the second conductive layers away from the substrate, and gaps are reserved between the third conductive layers.
11. The semiconductor structure of claim 10, wherein the aspect ratio of the storage node contact window is 2:1-2.3:1.
12. The semiconductor structure of claim 10, wherein the third conductive layer comprises a first portion and a second portion connected to each other in a width direction parallel to the second conductive layer; in a direction perpendicular to the substrate, a distance between a surface of the first portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate is greater than a distance between a surface of the second portion remote from the second conductive layer and a surface of the second conductive layer remote from the substrate.
13. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises:
and a passivation layer covering the third conductive layer and the target bit line structure.
14. The semiconductor structure of any of claims 10-13, wherein the substrate further comprises a peripheral region, the peripheral region having peripheral transistors, source and drain regions of the peripheral transistors being covered with an insulating layer, the semiconductor structure further comprising:
A first contact plug passing through the insulating layer and disposed on a surface of the insulating layer located in a first preset region, the first contact plug including a fourth conductive layer in contact with the source region and a sixth conductive layer covering the fourth conductive layer and covering a surface of the insulating layer located in the first preset region, the fourth conductive layer being the same material as the second conductive layer, the sixth conductive layer being the same material as the third conductive layer;
the second contact plug passes through the insulating layer and is arranged on the surface of the insulating layer in a second preset area, the second contact plug comprises a fifth conductive layer and a seventh conductive layer, the fifth conductive layer is in contact with the drain region, the seventh conductive layer covers the fifth conductive layer and covers the surface of the insulating layer in the second preset area, the fifth conductive layer and the second conductive layer are made of the same material, and the seventh conductive layer and the third conductive layer are made of the same material.
15. A memory device comprising the semiconductor structure of any of claims 10-14.
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| CN107845633A (en) * | 2017-10-30 | 2018-03-27 | 睿力集成电路有限公司 | Memory and its manufacture method |
| CN111463208A (en) * | 2020-04-29 | 2020-07-28 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN111710679A (en) * | 2020-06-24 | 2020-09-25 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| US20220139922A1 (en) * | 2020-11-03 | 2022-05-05 | Fujian Jinhua Integrated Circuit Co., Ltd. | Memory device and fabrication method thereof |
| US20230079234A1 (en) * | 2021-09-13 | 2023-03-16 | Changxin Memory Technologies, Inc. | Method for forming semiconductor structure and semiconductor structure |
| CN116801618A (en) * | 2023-06-25 | 2023-09-22 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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| CN107845633A (en) * | 2017-10-30 | 2018-03-27 | 睿力集成电路有限公司 | Memory and its manufacture method |
| CN111463208A (en) * | 2020-04-29 | 2020-07-28 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN111710679A (en) * | 2020-06-24 | 2020-09-25 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| US20220139922A1 (en) * | 2020-11-03 | 2022-05-05 | Fujian Jinhua Integrated Circuit Co., Ltd. | Memory device and fabrication method thereof |
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