CN115312582A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN115312582A
CN115312582A CN202210951464.5A CN202210951464A CN115312582A CN 115312582 A CN115312582 A CN 115312582A CN 202210951464 A CN202210951464 A CN 202210951464A CN 115312582 A CN115312582 A CN 115312582A
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metal silicide
silicide layer
contact hole
metal
semiconductor structure
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陈海波
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The disclosure relates to the technical field of semiconductor manufacturing processes, and discloses a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: providing a substrate, and forming a source drain region on the substrate; forming a first metal silicide layer on the source drain region; etching the first metal silicide layer and the source drain region to form a contact hole extending to the interior of the source drain region; and forming a second metal silicide layer at the bottom of the contact hole, wherein the second metal silicide layer is connected with the first metal silicide layer. According to the embodiment of the disclosure, the performance of the semiconductor structure can be improved.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a manufacturing method thereof.
Background
In a semiconductor manufacturing process, source-drain contact resistance is often generated between a metal contact part of a semiconductor structure and a substrate due to a contact problem between a metal electrode and a silicon substrate, and the performance of the semiconductor structure is affected.
Therefore, how to reduce the source-drain contact resistance to improve the performance of the semiconductor structure becomes a technical problem to be solved.
Disclosure of Invention
The present disclosure discloses a semiconductor structure and a method for manufacturing the same, which can reduce source-drain contact resistance, thereby improving the performance of the semiconductor structure.
In order to achieve the above purpose, the present disclosure provides the following technical solutions:
according to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including:
providing a substrate, and forming a source drain region on the substrate;
forming a first metal silicide layer on the source drain region;
etching the first metal silicide layer and the source drain region to form a contact hole extending into the source drain region;
and forming a second metal silicide layer at the bottom of the contact hole, wherein the second metal silicide layer is connected with the first metal silicide layer.
In one embodiment, an orthographic projection of the first metal silicide layer on the substrate at least partially overlaps an orthographic projection of the contact hole on the substrate.
In one embodiment, an orthographic projection of the first metal silicide layer on the substrate covers an orthographic projection of the contact hole on the substrate.
In one embodiment, the bottom of the first metal silicide layer is higher than the bottom of the contact hole, or the bottom of the first metal silicide layer is flush with the bottom of the contact hole.
In one embodiment, forming a first metal silicide layer on the source drain regions includes: and depositing a first metal material on the surface of the source and drain region, and carrying out first heat treatment on the first metal material so that the first metal material reacts with silicon in the source and drain region to form a first metal silicide layer.
In one embodiment, the temperature of the first heat treatment is 460 ℃ to 520 ℃.
In one embodiment, forming a second metal silicide layer includes: depositing a second metal material on the bottom area of the contact hole; a second thermal treatment is performed on the second metal material to react the second metal material with the silicon in the bottom region to form a second metal silicide layer.
In one embodiment, after the second heat treatment is performed on the second metal material, the method further includes: and removing an unreacted portion of the second metal material, and performing a third heat treatment on the bottom region after the removal of the unreacted portion.
In one embodiment, the temperature of the second heat treatment is 460 ℃ to 500 ℃, and the temperature of the third heat treatment is 580 ℃ to 620 ℃.
According to another aspect of the present disclosure, there is provided a semiconductor structure comprising:
the substrate comprises a source drain region;
the first metal silicide layer is positioned on the surface of the source drain region;
at least one contact hole, the contact hole penetrates the first metal silicide layer, and extend to the inside of the source drain region;
the second metal silicide layer is positioned at the bottom of the contact hole; the second metal silicide layer is connected with the first metal silicide layer.
In one embodiment, the second metal silicide layer includes a horizontal portion and a convex portion connected to each other, the horizontal portion being located at a bottom surface of the contact hole, and the convex portion surrounding at least a portion of a bottom sidewall of the contact hole.
In one embodiment, the top surface of the raised portion is connected to the bottom surface of the first metal silicide layer.
In one embodiment, the semiconductor structure further comprises: the barrier layer covers the inner wall of the contact hole; the conductive layer covers the surface of the barrier layer and fills the contact hole.
In one embodiment, the constituent materials of the first metal silicide layer and the second metal silicide layer include at least one of: cobalt silicide, titanium silicide, nickel silicide, molybdenum silicide, tungsten silicide, or copper silicide.
In one embodiment, the constituent material of the first metal silicide layer and the constituent material of the second metal silicide layer are different.
According to the semiconductor structure and the manufacturing method thereof provided by the embodiment of the disclosure, by forming the first metal silicide layer and the second metal silicide layer which are connected at the interface of the contact hole and the substrate, the continuous metal silicide layer can be formed at the bottom and the side wall of the contact hole, so that the Schottky barrier height between the conductive layer in the contact hole and the substrate is fully reduced, the source-drain contact resistance of the semiconductor structure is further reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 shows a schematic diagram of the external resistance of a transistor;
FIG. 2 illustrates a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram illustrating a first metal silicide layer and a second metal silicide layer according to an embodiment of the disclosure;
fig. 4 illustrates a schematic structural diagram of an exemplary semiconductor structure provided by an embodiment of the present disclosure;
FIG. 5 is a flow chart illustrating a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 to 12 are schematic diagrams illustrating film preparation in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.
In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.
In a semiconductor manufacturing process, an external resistance of a semiconductor structure such as a transistor becomes one of factors that limit the integration and performance of the transistor. Fig. 1 shows a schematic diagram of the external resistance of a transistor. As shown in FIG. 1, the external resistance of the transistor may include a channel resistance R 1 Parasitic resistance R 2 Diffusion resistance R 3 And source-drain contact resistance R 4 And the like.
For example, in the development process of improving the integration level of an integrated circuit, the characteristics of a semiconductor process are continuously reduced, the sizes of a gate, a source, a drain, an active region and the like of a transistor are correspondingly reduced, and accordingly, the source-drain contact resistance is increased due to the reduction of the metal/semiconductor contact area, which affects the performance of a semiconductor structure.
Therefore, how to reduce the source-drain contact resistance of the semiconductor structure becomes one of the problems to be solved urgently.
It has been found that in order to improve the contact of the metal fill with the active region, such as the source and drain regions, it is often necessary to extend the contact hole into the source and drain regions. However, for the fabrication process of contact holes extending to the inside of the source and drain regions, at least one of the following process problems may exist:
(1) The contact resistance of the semiconductor structure is often affected by the discontinuity of the bottom or the sidewall of the contact hole due to the hole etching process and the like, and further, the subsequent formation of a continuous silicide layer is difficult.
(2) When the contact hole is formed by etching, the contact between metal and silicon may be obstructed due to the oxidation phenomenon of the bottom or the side wall of the contact hole, so that the metal layer deposited on part of the inner wall is removed in the subsequent process because the metal layer does not react with the silicon, and further, the subsequent continuous metal silicide layer is difficult to form, thereby influencing the contact resistance of the semiconductor structure.
In view of at least one of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, in which a continuous first metal silicide layer and a continuous second metal silicide layer may be formed between a contact hole and a substrate, so that a schottky barrier height between a conductive layer in the contact hole and the substrate may be reduced, and thus a source-drain contact resistance of the semiconductor structure may be reduced, thereby improving performance of the semiconductor structure. For example, compared with the scheme that the metal silicide layer is only formed at the bottom of the contact hole, the contact interface of the contact hole and the substrate can be completely coated, the source-drain contact resistance of the semiconductor structure is greatly reduced, and the performance of the semiconductor structure is improved.
And through the arrangement of the first metal silicide layer and the second metal silicide layer which are connected, even when the second metal silicide layer is formed after a contact hole (an opening) is formed, if the continuous second metal silicide layer cannot be formed due to problems such as process and the like, the substrate exposed part of the substrate on which the continuous second metal silicide layer is not formed can be coated through the first metal silicide layer, so that the influence of the actual process on the source-drain contact resistance of the semiconductor structure is avoided, and the product yield of the semiconductor structure is ensured.
To facilitate a general understanding of the technical solutions provided by the embodiments of the present disclosure, a semiconductor structure provided by the embodiments of the present disclosure will be described first.
Fig. 2 shows a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. As shown in fig. 2, the semiconductor structure may include a substrate 11, a first metal silicide layer 12, at least one contact hole 13, and a second metal silicide layer 14. Next, each constituent part of the structure will be explained in turn.
For substrate 11, it may include source and drain regions (not shown in fig. 1). Specifically, the substrate 11 may be a silicon substrate. The material forming the substrate may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic silicon, or a combination thereof, which is not limited thereto. The source and drain regions may be disposed in the substrate 11, and specifically, may be disposed on the surface of the substrate. The source and drain regions may be P-type ion doped regions or N-type ion doped regions on the surface of the substrate. Illustratively, with continued reference to fig. 2, source and drain regions may be located in substrate 11 on either side of gate structure 15.
For the first metal silicide layer 12, it is located on the surface of the source and drain regions, as shown in fig. 2, it may be disposed horizontally to the surface of the substrate. It should be noted that the bottom surface of the first metal silicide layer 12 may be horizontal to the substrate surface, have a certain angle or undulate, and this is not limited in particular.
The first metal silicide layer will be specifically described below in terms of a composition material, an area, a depth, and the like.
Among them, in some embodiments, the composition material of the first metal silicide layer 12 may include at least one of the following metal silicides: cobalt silicide (CoSi) x ) Titanium silicide (TiSi) x ) Nickel silicide (NiSi) x ) Molybdenum silicide (MoSi) x ) Tungsten silicide (WSi) x ) And copper silicide (CuSi) x ). It should be noted that the constituent material may also be silicide of other metals or metal compositions, such as nickel platinum silicide (NiPtSi) x ) And the like, and is not particularly limited thereto.
In this embodiment, the metal silicide may form a low-resistance ohmic contact between the conductive layer in the contact hole and the substrate, thereby reducing the contact resistance of the semiconductor structure and improving the performance of the semiconductor structure.
For the contact area between the first metal silicide layer 12 and the source and drain regions, the contact area between the first metal silicide layer 12 and the source and drain regions may be smaller than the area of the source and drain regions, that is, the first metal silicide layer 12 may partially cover the source and drain regions. Still alternatively, the contact area of the first metal silicide layer 12 and the source and drain regions may be the same as the area of the source and drain regions, that is, the first metal silicide layer 12 may completely cover the source and drain regions. It should be noted that specific values of the area of the first metal silicide layer 12 can be flexibly set according to actual manufacturing scenarios and specific manufacturing requirements, and are not limited in particular.
Wherein the depth of the first metal suicide layer 12. In some embodiments, with continued reference to fig. 2, the bottom of first metal silicide layer 12 is higher than the bottom of contact hole 13. In other embodiments, the bottom of first metal silicide layer 12 is flush with the bottom of contact hole 13. It should be noted that specific values of the depth of the first metal silicide layer 12 can be flexibly set according to actual manufacturing scenarios and specific manufacturing requirements, and are not limited in particular.
Through the arrangement, the first metal silicide layer 12 can cover the side wall of the contact hole 13, and even if a continuous second metal silicide layer 14 cannot be formed due to process problems during forming the contact hole (opening hole) in the subsequent process, the interface between the metal contact part and the substrate can be completely covered through the first metal silicide layer 12, so that the influence of actual process errors on the contact resistance of the semiconductor structure is avoided.
And, the influence on the conductive channel due to the first metal silicide layer 12 being too deep can be prevented. Therefore, the embodiment can reduce the contact resistance and the conductivity of the semiconductor structure, reduce the influence of actual process errors on the performance of the semiconductor structure, and improve the yield and the performance of the semiconductor structure.
As for the contact hole 13, it penetrates the first metal silicide layer 12 and extends to the inside of the source-drain region.
Here, the positional relationship between the contact hole 13 and the first metal silicide layer 12 is explained as follows.
In some embodiments, an orthographic projection of first metal silicide layer 12 on substrate 11 at least partially overlaps an orthographic projection of contact hole 13 on substrate 11. That is, an orthographic projection of first metal silicide layer 12 on substrate 11 may partially overlap an orthographic projection of contact hole 13 on substrate 11, or alternatively, an orthographic projection of first metal silicide layer 12 on substrate 11 may completely cover an orthographic projection of contact hole 13 on substrate 11.
Through the arrangement, at least part of the side wall of the contact hole 13 can be coated by the first metal silicide layer 12, for example, the position where the continuous second metal silicide layer 14 cannot be formed easily due to the process error of the actual manufacturing process can be covered, and the influence of the actual process error on the contact resistance of the semiconductor structure can be reduced at least to a certain extent, so that the contact resistance of the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved.
In one embodiment, an orthographic projection of first metal silicide layer 12 on substrate 11 covers an orthographic projection of contact hole 13 on the substrate. Accordingly, the sidewall of the contact hole 13 may be continuously formed with metal silicide in the circumferential direction. Alternatively, the metal silicide may be continuously formed on both the sidewall and the bottom of the contact hole 13 in the circumferential direction.
Through the setting, first metal silicide layer 12 can be at least to the complete cladding of the lateral wall of contact hole 13 to can realize the all-round cladding to the lateral wall and the bottom of contact hole 13 through first metal silicide layer 12 and the second metal silicide layer 14 that are connected, make each contact position department between the inside conducting layer of contact hole and the substrate all be formed with metal silicide, fully reduce the conducting layer in the contact hole and the schottky barrier height between the substrate, thereby fully reduced semiconductor structure's source leakage contact resistance.
And the second metal silicide layer 14 cannot form a continuous second metal silicide layer 14 on the sidewall or the bottom due to the manufacturing process and the like, and the continuous cladding of the metal-semiconductor contact interface can also be realized through the first metal silicide layer, so that the influence of the actual process on the source-drain contact resistance of the semiconductor structure is reduced.
For the second metal silicide layer 14, it may be located at the bottom of the contact hole 13, and it may cover at least the bottom region of the contact hole 13 leaking out of the source drain region. That is, the second metal silicide layer 14 may coat the bottom of the contact hole 13, or may coat the bottom and at least a portion of the sidewall of the contact hole 13. In one example, if the semiconductor structure includes a plurality of contact holes 13, a second metal silicide layer 14 may be formed at the bottom of each contact hole 13.
Next, the second metal silicide layer 14 will be specifically described by material composition and specific structure.
From the viewpoint of material composition, in some embodiments, the constituent material of the second metal silicide layer 14 may include at least one of the following metal silicides: cobalt silicide (CoSi) x ) Titanium silicide (TiSi) x ) Nickel silicide (NiSi) x ) Molybdenum silicide (MoSi) x ) Tungsten silicide (WSi) x ) And copper silicide (CuSi) x ). It should be noted that the constituent material may also be silicide of other metals or metal compositions, such as nickel platinum silicide (NiPtSi) x ) And the like, and is not particularly limited thereto.
In this embodiment, the metal silicide may form a low-resistance ohmic contact between the conductive layer in the contact hole and the substrate, thereby reducing the contact resistance of the semiconductor structure and improving the performance of the semiconductor structure.
In some embodiments, the constituent material of the second metal silicide layer 14 may be different from the constituent material of the first metal silicide layer 12.
Through the arrangement, the metal silicide layers with different work functions can be formed on the interface of the contact hole and the substrate, so that the reliability of the contact condition of the contact position is improved, and the reliability of reducing the contact resistance of the semiconductor structure is improved.
It should be noted that the composition materials of the second metal silicide layer 14 and the first metal silicide layer 12 may also be the same, and are not described in detail here.
In terms of specific structure, in some embodiments, fig. 3 illustrates a schematic structural diagram of a first metal silicide layer and a second metal silicide layer provided by the embodiments of the present disclosure. As shown in fig. 3, the second metal silicide layer 14 may include a horizontal portion 410 and a convex portion 420 connected to each other. Wherein the horizontal portion 410 may be located at a bottom surface of the contact hole 13, and the convex portion at least partially surrounds a bottom sidewall of the contact hole 13. Here, specific shapes of the horizontal portion and the convex portion may be set according to the shape of the contact hole, which is not particularly limited.
Through the arrangement, the bottom of the contact hole 13 can be coated by utilizing the horizontal part and the convex part, so that the contact resistance at the bottom of the contact hole 13 can be reduced, and the performance of the semiconductor structure is improved.
In one example, with continued reference to fig. 3, the top surface of the raised portion 420 of the second metal silicide layer 14 may be connected to the bottom surface of the first metal silicide layer 12.
Through the arrangement, the contact surface of the contact hole and the substrate can be completely covered by the first metal silicide layer 12 and the second metal silicide layer 14, meanwhile, the influence on a conductive channel and a source-drain region can be avoided as much as possible, and the conductivity of the semiconductor structure is ensured. And, the consumption of the first metal silicide 200 is saved, and the manufacturing cost can be reduced while the performance of the semiconductor structure is ensured.
And it should be further noted that the top surface of the convex portion of the second metal silicide layer 14 may also exceed the bottom surface of the first metal silicide layer 12, which is not particularly limited.
According to the semiconductor structure, the first metal silicide layer and the second metal silicide layer which are connected are formed at the interface of the contact hole and the substrate, the continuous metal silicide layers can be formed at the bottom and the side wall of the contact hole, the Schottky barrier height between the conducting layer in the contact hole and the substrate is fully reduced, the source-drain contact resistance of the semiconductor structure is further reduced, and therefore the performance of the semiconductor structure is improved.
And through the arrangement of the first metal silicide layer and the second metal silicide layer which are connected, even when the second metal silicide layer is formed after the contact hole (open hole) is formed, if the continuous second metal silicide layer cannot be formed due to problems of the process and the like, the exposed part of the substrate on which the continuous second metal silicide layer is not formed can be coated by the first metal silicide layer, so that the influence of the actual process on the source-drain contact resistance of the semiconductor structure is avoided, and the product yield of the semiconductor structure is ensured.
In some embodiments, to ensure device internal interconnection, the semiconductor structure may further include a conductive layer. The conductive layer is used to fill the contact hole 13. In particular, the conductive layer may fill or partially fill the contact hole 13. Exemplarily, fig. 4 shows a schematic structural diagram of an exemplary semiconductor structure provided by the embodiment of the present disclosure. As shown in fig. 4, the semiconductor structure may further include a conductive layer 16.
Illustratively, in order to ensure the conductive performance of the semiconductor structure, the contact hole 13 is used to fill a conductive layer, wherein the constituent material of the conductive layer may include one or more of tungsten (W), aluminum (Al), and aluminum titanium alloy (TiAl). It should be noted that the metal filler may also be selected from other metals or alloys according to actual manufacturing requirements or specific manufacturing requirements, and is not particularly limited in this regard.
Through setting up the conducting layer, can form the effective connecting channel between active area and the external circuit to the electric conductive property of semiconductor structure has been guaranteed.
In some embodiments, in order to ensure the performance of the semiconductor structure, the semiconductor structure may further include a barrier layer, and the barrier layer may cover the inner wall of the contact hole to block the diffusion of the metal. With continued reference to fig. 4, barrier layer 17 may cover the inner walls of the contact hole, and conductive layer 16 covers the surface of barrier layer 17. For example, the conductive layer 16 covers the surface of the barrier layer 17 on the side facing away from the inner wall of the contact hole.
Illustratively, the constituent material of the barrier layer may include titanium nitride (TiN). The composition material of the barrier layer may further include one or more of titanium (Ti), tantalum (Ta), tiN, titanium nitride (TaN), titanium aluminum alloy (TiAl), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), and titanium aluminum nitride (TiAlN), which is not particularly limited.
By providing the barrier layer, the metal (e.g., W) of the conductive layer can be prevented from diffusing into the substrate, thereby ensuring the performance of the semiconductor structure.
In some embodiments, a gate structure is also disposed on the substrate. In one example, with continued reference to fig. 4, gate structure 15 may include a gate insulating layer 151, a first conductive layer 152, a second conductive layer 153, sidewalls 154, and a barrier layer 155. The barrier layer 155 is disposed between the first conductive layer 152 and the second conductive layer 153.
The gate structure may be other structures, and is not particularly limited in this regard.
In some embodiments, the semiconductor structure may further include a dielectric layer, wherein each contact hole extends through the dielectric layer and the first metal silicide layer to the inside of the source drain region. In one example, with continued reference to fig. 4, the dielectric layer 18 may include a first dielectric layer 181 overlying the surface of the substrate 11 and a second dielectric layer 182 overlying the surface of the first dielectric layer 181.
It should be noted that the dielectric layer may also have other structures, which are not particularly limited.
In some embodiments, the semiconductor structure further comprises an insulating dielectric layer. Accordingly, each contact hole may extend through the insulating dielectric layer and the first metal silicide layer to the inside of the source drain region. In one example, with continued reference to fig. 4, an insulating dielectric layer 19 may be located on the surface of the substrate 11 and cover the gate structure and the first metal silicide layer.
Illustratively, the material of the insulating dielectric layer 19 may be, for example: silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or combinations thereof, without specific limitation.
In some embodiments, the semiconductor structure may further include a Shallow Trench Isolation (STI) structure. In one example, with continued reference to fig. 4, the shallow trench isolation structure 20 may include a first oxide layer 201, a nitride layer 202, and a second oxide layer 203.
By arranging the shallow trench isolation structure, effective isolation among a plurality of active regions can be realized, and the performance of the semiconductor structure is improved. It should be noted that the shallow trench isolation structure 20 may also be other structures, which is not particularly limited.
In some embodiments, the semiconductor structure may further include an air gap (Airgap). In one example, with continued reference to fig. 4, an air gap 21 may be disposed between the dielectric layer 18 and the shallow trench isolation structure 20.
By arranging the air gap, the parasitic capacitance between the conductive structures can be reduced, and the performance of the semiconductor structure is improved. It should be noted that the air gap may have other structures, which is not particularly limited.
It should be noted that the semiconductor structure may also be fabricated into other hierarchical structures according to actual situations and specific needs, which are not specifically limited.
Next, the following portions of the embodiments of the present disclosure will specifically explain a method of manufacturing a semiconductor structure with reference to fig. 5 to 12.
Fig. 5 is a schematic flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 5, the method of fabricating the semiconductor structure may include steps S510 to S540.
And S510, providing a substrate, and forming a source drain region on the substrate. Illustratively, as shown in fig. 6, P-type ions or N-type ions may be doped into the substrate on the substrate 11 by thermal diffusion, ion implantation, or the like to form source and drain regions.
In S510, the substrate may be formed in a manner including: one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), and Spin Coating (Spin Coating), but not limited thereto.
For the source and drain regions, the source and drain regions may be formed by Spacer Etch (Spacer Etch) and ion Implantation (IMP). For example, a mask pattern exposing the source and drain regions may be formed on the substrate 11, and then ion implantation may be performed using the mask pattern, and the mask pattern may be removed after the ion implantation is completed. Optionally, in order to improve the performance of the semiconductor structure, the source and drain regions after ion implantation may be subjected to heat treatment to perform lattice recovery on silicon ions in the substrate, which have lattice disorder caused by ion implantation.
And S520, forming a first metal silicide layer on the source drain region.
In S520, a first metal silicide layer may be formed from the reaction of the first metal and silicon.
In some embodiments, the first metal silicide layer constituent material includes at least one of: cobalt silicide, titanium silicide, nickel silicide, molybdenum silicide, tungsten silicide, or copper silicide.
For specific contents of the first metal silicide layer, reference may be made to the related description of the above-mentioned portions of the embodiments of the present disclosure, and details are not repeated herein.
After the description of the technical attributes of step S520, a specific embodiment of S520 will be described next.
In some embodiments, S520 may include step A1 and step A2 described below.
Step A1, depositing a first metal material on the surface of a source drain region. Illustratively, the deposition of the first metallic material may be achieved by a deposition process such as PVD and/or CVD.
For the first metal material, it may refer to a metal material required in forming the first metal silicide layer. For example, if the constituent material of the first metal silicide layer includes cobalt silicide, the first metal material may include cobalt. For another example, if the composition material of the first metal silicide layer includes nickel silicide, the first metal material may include nickel, which is not described in detail.
Illustratively, as shown in fig. 7, a layer of first metal material 22 covering the gate structure and the source and drain regions may be formed on the substrate 11, so that after the metal silicide layer corresponding to the formed first metal material 22 is formed, the remaining first metal silicide outside the source and drain regions is removed, and the first metal silicide layer 12 is obtained.
As still another example, the first metal material may be further patterned by a mask or the like to form the first metal silicide layer 12 only on the surface of the source/drain region.
It should be noted that, the embodiment of the present disclosure does not specifically limit the deposition manner of the first metal silicide layer.
It should be noted that, in the embodiments of the present disclosure, other processes besides the deposition process may be used to cover the first metal material, and no particular limitation is imposed on this.
In one embodiment, in order to improve the characteristics of the semiconductor structure, before depositing the first metal material, the oxide on the surface of the source/drain region may be removed, so that the first metal material and silicon can fully react, the thickness of the first metal silicide layer is more uniform, and the performance of the semiconductor structure is improved.
And A2, carrying out first heat treatment on the first metal material so as to enable the first metal material to react with silicon in the source and drain regions to form a first metal silicide layer. For example, as shown in fig. 8, a first metal silicide layer 12 covering the source and drain regions may be formed after the first heat treatment is performed.
For the first heat treatment, it is used to react the first metallic material with silicon in the substrate. Accordingly, the temperature of the first heat treatment may be a temperature that enables the first metal material and silicon in the substrate to react. Illustratively, the first Thermal treatment may be Rapid Thermal Processing (RTP). It should be noted that other heat treatment processes may be used, and are not particularly limited.
In one embodiment, taking cobalt as the first metal material as an example, the temperature of the first heat treatment may be 460 ℃ (degree centigrade) to 500 ℃. For example, it may be 480 ℃.
When the first metal material is subjected to heat treatment at the temperature of 460-500 ℃, the first metal material can fully react with silicon in the source-drain region to generate a first metal silicide, so that the performance of the semiconductor structure is improved.
For example, the temperature of the first heat treatment may be any one of the following values: 460 ℃, 462 ℃, 464 ℃, 466 ℃, 468 ℃, 470 ℃, 472 ℃, 474 ℃, 476 ℃, 478 ℃, 480 ℃, 482 ℃, 484 ℃, 486 ℃, 488 ℃, 490 ℃, 492 ℃, 494 ℃, 496 ℃, 498 ℃ and 500 ℃.
It should be noted that, when other materials except Co are selected as the first metal material, other suitable temperatures may be selected as the temperature of the first heat treatment according to actual situations and specific process requirements, which is not specifically limited in the embodiment of the present disclosure. For example, the temperature of the first heat treatment may be 200 ℃ to 300 ℃ in the case of NiPtSix.
In some embodiments, in order to improve the preparation precision of the first metal silicide layer, between step A1 and step A2, S520 may further include step A3.
And step A3, covering a barrier film on the surface of the first metal material. Illustratively, the barrier film may be a TiN film.
By providing the barrier film, the first metal material can be prevented from flowing at the time of the first heat treatment, improving the performance of the semiconductor structure.
Through the step A1 and the step A2, the first metal silicide layer can be generated on the surface of the source drain region in a deposition heating treatment mode, so that the preparation quality of the first metal silicide layer is improved, and the performance of the semiconductor structure is ensured.
And because the thickness of the first metal silicide layer is always thinner, the energy consumption can be reduced while the first metal material is ensured to be fully reacted with silicon in the source drain region through a heat treatment process, so that the preparation efficiency of the semiconductor structure is improved.
In some embodiments, step A4 may also be included after step A2.
And step A4, removing unreacted parts in the first metal material. I.e. the first metal material which has not reacted to form the first metal silicide after the first thermal treatment is removed.
Illustratively, a Wet etch (Wet Strip) may be used to remove the unreacted first metal material. It should be noted that, the first metal material may also be removed by dry etching or other methods, which is not particularly limited.
Optionally, in the case where step A3 is further included in S530, the barrier film such as TiN may also be removed when the unreacted first metal material is removed.
In this embodiment, the unreacted first metal material is removed, so that a short circuit caused by metal bridging can be prevented, and the electrical characteristics of the semiconductor structure are improved.
In some embodiments, step A5 may also be included after step A2.
Step A5, performing a fourth heat treatment on the first metal silicide layer.
For the fourth heat treatment, it is used to enable the metal silicide in the high resistance state to be converted into the metal silicide in the low resistance state. Illustratively, the fourth heat treatment may be RTP. It should be noted that other heat treatment processes may also be employed, and this is not particularly limited.
In one embodiment, taking cobalt as the first metal material as an example, the temperature of the fourth heat treatment may be 580 ℃ to 620 ℃. For example, it may be 600 ℃.
When the heat treatment is carried out at 580-620 ℃, the metal silicide in the high resistance state can be converted into the metal silicide in the low resistance state, thereby improving the performance of the semiconductor structure.
For example, the temperature of the fourth heat treatment may be any one of the following values: 580 deg.C, 582 deg.C, 584 deg.C, 586 deg.C, 588 deg.C, 590 deg.C, 592 deg.C, 594 deg.C, 596 deg.C, 598 deg.C, 600 deg.C, 602 deg.C, 604 deg.C, 606 deg.C, 608 deg.C, 610 deg.C, 612 deg.C, 614 deg.C, 616 deg.C, 618 deg.C, 620 deg.C.
It should be noted that, when other materials besides Co are selected as the first metal material, other suitable temperatures may be selected as the temperature of the fourth heat treatment according to actual situations and specific process requirements, and this is not particularly limited in the embodiments of the present disclosure. For example, the temperature of the fourth heat treatment may be 400 to 450 ℃, taking NiPtSix as an example.
S530, the first metal silicide layer and the source drain region are etched to form a contact hole extending to the interior of the source drain region. In the embodiment of the present disclosure, the contact hole may be formed by dry etching, wet etching, and the like, which is not specifically limited.
First, the contact hole is explained as follows.
In some embodiments, an orthographic projection of the first metal silicide layer on the substrate at least partially overlaps with an orthographic projection of the contact hole on the substrate.
It should be noted that, for specific contents of this embodiment, reference may be made to relevant descriptions of the foregoing parts of the embodiments of the present disclosure, and details are not described herein again.
In some embodiments, an orthographic projection of the first metal silicide layer on the substrate covers an orthographic projection of the contact hole on the substrate. It should be noted that, for specific contents of this embodiment, reference may be made to relevant descriptions of the above parts of the embodiment of the present disclosure, and details are not described herein again.
In some embodiments, the bottom of the first metal silicide layer is higher than the bottom of the contact hole, or the bottom of the first metal silicide layer is flush with the bottom of the contact hole. It should be noted that, for specific contents of this embodiment, reference may be made to relevant descriptions of the above parts of the embodiment of the present disclosure, and details are not described herein again.
It should be noted that other contents of the contact hole can refer to the related contents of the above parts of the embodiments of the present disclosure, and are not described herein again.
Next, an embodiment of S530 will be explained.
In one embodiment, a dielectric layer covering the source/drain region and the gate structure may be formed on the surface of the substrate, and then the dielectric layer, the first metal silicide layer, and the source/drain region may be etched to form the contact hole.
Illustratively, a dielectric layer may be deposited and then planarized. The dielectric layer may be formed in other ways, which is not particularly limited.
In another embodiment, for example, as shown in fig. 9, after forming the insulating dielectric layer 19 and the dielectric layer 18 on the substrate surface, the dielectric layer 18, the insulating dielectric layer 19, the first metal silicide layer 12, and the source/drain regions may be etched to form the contact holes 13 as shown in fig. 10.
In one embodiment, to improve the conductivity of the semiconductor structure, ion doping may be performed at the bottom of the contact hole after the contact hole is formed. The ion doping concentration is higher than that of the source and drain regions.
And S540, forming a second metal silicide layer at the bottom of the contact hole, wherein the second metal silicide layer is connected with the first metal silicide layer.
It should be noted that specific contents of the second metal silicide layer can be referred to in the related description of the above part of the embodiment of the disclosure, and are not described again.
In some embodiments, step S540 may include steps B1 and B2 described below.
And B1, depositing a second metal material in the bottom area of the contact hole. As shown in fig. 11, a second metal material may be underlying in the bottom region of the contact hole and then subjected to a heat treatment to form the semiconductor structure shown in fig. 12.
It should be noted that, step B1 is similar to step A1, and reference may be made to relevant contents of step A1, which is not described herein again.
As for the bottom region of the contact hole, it may be a region located at the bottom of the contact hole where the second metal silicide layer needs to be formed. Illustratively, the bottom region of the contact hole may include a bottom surface of the contact hole. Still alternatively, the bottom region of the contact hole may further include a bottom sidewall of the contact hole.
In one embodiment, to improve the uniformity of the second metal silicide layer, the oxide at the bottom of the contact hole may be removed before depositing the second metal material. And B2, carrying out second heat treatment on the second metal material so that the second metal material reacts with the silicon in the bottom area to form a second metal silicide layer.
In one embodiment, the temperature of the second heat treatment is 460 ℃ to 500 ℃. It should be noted that the second heat treatment is similar to the first heat treatment, and reference may be made to the description of the first heat treatment in the above part of the embodiments of the disclosure, and details thereof are not repeated.
In an embodiment, in order to prevent diffusion of the second metal material, before the second heat treatment is performed, a barrier film may be formed on a surface of the second metal material, where specific contents of the barrier film may be referred to in the description of step A3 in the above section of the embodiment of the present disclosure, and are not described herein again.
Through the step B1 and the step B2, the second metal silicide layer can be quickly formed at the bottom of the contact hole in a mode of depositing metal at the bottom of the contact hole for heating treatment, and the process preparation efficiency is improved.
In some embodiments, after step B2, step B3 may also be included.
And step B3, carrying out third heat treatment on the bottom area.
In one embodiment, the temperature of the third heat treatment is 580 ℃ to 620 ℃.
It should be noted that, the third heat treatment is similar to the fourth heat treatment, and reference may be made to the description of the fourth heat treatment in the above part of the embodiment of the present disclosure, and details are not repeated here.
Through the steps B1 to B3, the reaction of the second metal material and the silicon can be more thorough through the third heat treatment, and the performance of the semiconductor structure is improved. For example, in the second heat treatment (i.e., the first annealing process in preparing the second metal silicide), since the temperature of the second heat treatment is lower than that of the third heat treatment (i.e., the second annealing process in preparing the second metal silicide), the second metal material (such as Co) may diffuse toward the silicon substrate at a slower speed and react with silicon atoms to form a metal silicide in a high resistance state. Then, the high-resistance metal silicide can be converted into the low-resistance metal silicide through the third heat treatment, and the low-resistance metal silicide has good and stable thermal performance, and bridging short circuit caused by rapid diffusion of metal materials is reduced, so that the performance of the semiconductor structure is improved.
And through the third heat treatment, the crystal lattice of the silicon in the substrate can be recovered, so that the performance of the semiconductor structure is improved.
In some embodiments, after step A2, S540 may further include step B4.
And step B4, removing the unreacted part in the second metal material.
Illustratively, a Wet etch (Wet Strip) may be used to remove the unreacted second metallic material. It should be noted that, the second metal material may also be removed by dry etching or other methods, which is not particularly limited.
Alternatively, the barrier film such as TiN may also be removed when the unreacted first metal material is removed.
Alternatively, if step S540 further includes step B3, step B4 may be performed before step B3. That is, the unreacted portion of the second metal material may be removed first, and then the bottom region after the removal of the unreacted portion may be subjected to the third heat treatment.
In this embodiment, the removal of the unreacted second metal material can prevent a short circuit caused by metal bridging, thereby improving the electrical characteristics of the semiconductor structure.
In the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure through the above steps S510 to S540, by forming the first metal silicide layer and the second metal silicide layer connected to each other at the interface between the contact hole and the substrate, a continuous metal silicide layer can be formed at the bottom and the sidewall of the contact hole, so as to sufficiently reduce the schottky barrier height between the conductive layer in the contact hole and the substrate, and further reduce the source-drain contact resistance of the semiconductor structure, thereby improving the performance of the semiconductor structure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and example embodiments be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (15)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a source drain region on the substrate;
forming a first metal silicide layer on the source drain region;
etching the first metal silicide layer and the source drain region to form a contact hole extending into the source drain region;
and forming a second metal silicide layer at the bottom of the contact hole, wherein the second metal silicide layer is connected with the first metal silicide layer.
2. The method of claim 1, wherein an orthographic projection of the first metal silicide layer on the substrate at least partially overlaps an orthographic projection of the contact hole on the substrate.
3. The method of claim 2, wherein an orthographic projection of the first metal silicide layer on the substrate covers an orthographic projection of the contact hole on the substrate.
4. The method of claim 1, wherein the bottom of the first metal silicide layer is higher than the bottom of the contact hole, or the bottom of the first metal silicide layer is flush with the bottom of the contact hole.
5. The method of claim 1, wherein forming the first metal silicide layer on the source drain regions comprises: depositing a first metal material on the surface of the source drain region, and carrying out first heat treatment on the first metal material so as to enable the first metal material to react with silicon in the source drain region to form the first metal silicide layer.
6. The method according to claim 5, wherein the temperature of the first heat treatment is 460 ℃ to 500 ℃.
7. The method of claim 1, wherein forming the second metal silicide layer comprises: depositing a second metal material on the bottom area of the contact hole; performing a second thermal treatment on the second metal material to react the second metal material with the silicon in the bottom region to form the second metal silicide layer.
8. The method of claim 7, wherein after the second heat treating the second metallic material, the method further comprises: and removing an unreacted part in the second metal material, and carrying out third heat treatment on the bottom area after the unreacted part is removed.
9. The method according to claim 8, wherein the temperature of the second heat treatment is 460 to 500 ℃ and the temperature of the third heat treatment is 580 to 620 ℃.
10. A semiconductor structure, comprising:
the substrate comprises a source drain region;
the first metal silicide layer is positioned on the surface of the source drain region;
at least one contact hole, wherein the contact hole penetrates through the first metal silicide layer and extends to the inside of the source drain region;
the second metal silicide layer is positioned at the bottom of the contact hole; the second metal silicide layer is connected with the first metal silicide layer.
11. The semiconductor structure of claim 10, wherein the second metal silicide layer comprises a horizontal portion and a protruding portion connected to each other, the horizontal portion being located at a bottom surface of the contact hole, the protruding portion surrounding at least a portion of a bottom sidewall of the contact hole.
12. The semiconductor structure of claim 11, wherein a top surface of the raised portion connects to a bottom surface of the first metal silicide layer.
13. The semiconductor structure of claim 10, further comprising: the barrier layer covers the inner wall of the contact hole; the conducting layer covers the surface of the barrier layer and is filled in the contact hole.
14. The semiconductor structure of claim 10, wherein a constituent material of the first metal silicide layer and the second metal silicide layer comprises at least one of: cobalt silicide, titanium silicide, nickel silicide, molybdenum silicide, tungsten silicide, or copper silicide.
15. The semiconductor structure of claim 14, wherein a constituent material of the first metal silicide layer and a constituent material of the second metal silicide layer are different.
CN202210951464.5A 2022-08-09 2022-08-09 Semiconductor structure and manufacturing method thereof Pending CN115312582A (en)

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