CN117498867A - Digital-to-analog conversion circuit, control method, analog-to-digital converter and electronic equipment - Google Patents
Digital-to-analog conversion circuit, control method, analog-to-digital converter and electronic equipment Download PDFInfo
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Abstract
Description
技术领域Technical field
本发明设计数模转换电路领域,尤其涉及一种数模转换电路及控制方法、模数转换器及电子设备The present invention is in the field of designing digital-to-analog conversion circuits, and in particular relates to a digital-to-analog conversion circuit and a control method, an analog-to-digital converter and an electronic device.
背景技术Background technique
逐次逼近寄存器型模数转换器(又称SAR ADC)根据数模转换器(DAC)类型的不同分为电荷再分配型、电压等比例缩放型以及混合结构型;其中,若数模转换器由纯电阻阵列构成,则SAR ADC对应为电压等比例缩放型;若数模转换器由纯电容阵列构成,则SAR ADC对应为电荷再分配型;若数模转换器分别由电阻阵列和电容阵列构成,则SAR ADC对应为混合型。其中,混合型SAR ADC通常还分为C-R混合型和R-C混合型,其区别在于高Mbit是由电容阵列来实现,还是由电阻阵列来实现。Successive approximation register type analog-to-digital converters (also known as SAR ADCs) are divided into charge redistribution type, voltage scaling type and hybrid structure type according to the type of digital-to-analog converter (DAC); among them, if the digital-to-analog converter is composed of If the digital-to-analog converter is composed of a pure resistor array, the SAR ADC corresponds to the voltage scaling type; if the digital-to-analog converter is composed of a pure capacitor array, the SAR ADC corresponds to the charge redistribution type; if the digital-to-analog converter is composed of a resistor array and a capacitor array respectively , then the SAR ADC corresponds to the hybrid type. Among them, hybrid SAR ADC is usually divided into C-R hybrid type and R-C hybrid type. The difference lies in whether the high Mbit is achieved by a capacitor array or a resistor array.
但随着SAR ADC位数的增长即精度要求提高,对于电荷再分配型,电容阵列中电容容值会成呈指数型增长,增大了电容匹配的要求;对于电压等比例缩放型,电阻阵列中电阻的个数也会呈指数型增长,增大了电路面积。相较于电荷再分配型SAR ADC和电压等比例缩放型SAR ADC,混合型SAR ADC能大大减小因位数的增长而导致的电容匹配问题和电路面积问题,进而在一定程度上提高了SAR ADC的转换精度,以及降低了电路成本。However, as the number of SAR ADC bits increases, that is, the accuracy requirements increase, for the charge redistribution type, the capacitance value in the capacitor array will increase exponentially, increasing the requirements for capacitance matching; for the voltage scaling type, the resistor array The number of medium resistors will also increase exponentially, increasing the circuit area. Compared with charge redistribution SAR ADC and voltage scaling SAR ADC, hybrid SAR ADC can greatly reduce the capacitance matching problem and circuit area problem caused by the increase in number of bits, thereby improving SAR to a certain extent. ADC conversion accuracy and reduced circuit cost.
以电荷再分配型SAR ADC和C-R混合型SAR ADC为例进行说明如下:Taking charge redistribution SAR ADC and C-R hybrid SAR ADC as examples, the following explanation is given:
其原理为:对于N bit电荷再分配型SAR ADC,假设单位电容C服从均值为C0,标准差为σ的正态分布。那么,并联在一起的N个电容将服从均值为NC0,标准差为的正态分布。再定义由电容失配引起的误差小于1/2LSB,则对应的要求为公式(1):The principle is: for the N-bit charge redistribution SAR ADC, it is assumed that the unit capacitance C follows a normal distribution with a mean value of C0 and a standard deviation of σ. Then, N capacitors connected in parallel will have a mean value of NC0 and a standard deviation of normal distribution. It is further defined that the error caused by capacitor mismatch is less than 1/2LSB, then the corresponding requirement is formula (1):
其中,Cmsb代表最高位电容,Ctotal代表着总电容。 Among them, Cmsb represents the highest capacitance, and Ctotal represents the total capacitance.
将上述公式展开可得公式(2):Expanding the above formula, we can get formula (2):
考虑极端情况,最高位的电容偏差均为正值,其余为负值。可将上式整理为公式(3):Considering the extreme situation, the capacitance deviation of the highest bit is positive and the rest are negative. The above formula can be organized into formula (3):
其中,所述公式(3)用于表征数模转换器的匹配精度。 Among them, the formula (3) is used to characterize the matching accuracy of the digital-to-analog converter.
对于N bit的C-R混合型SAR ADC,设定高Mbit,剩余(N-M)bit由电阻阵列实现。按上述的推理方式可得电容阵列对应的匹配精度为公式(4):For the N-bit C-R hybrid SAR ADC, high Mbit is set, and the remaining (N-M) bits are implemented by the resistor array. According to the above reasoning method, the corresponding matching accuracy of the capacitor array can be obtained as formula (4):
对于电阻阵列只需要满足(N-M)bit的匹配精度,假设电阻R符合均值为R,标准差为σ的正态分布,可得到电阻阵列对应的匹配精度为公式(5):The resistor array only needs to meet the matching accuracy of (N-M) bits. Assuming that the resistor R conforms to the normal distribution with a mean value of R and a standard deviation of σ, the corresponding matching accuracy of the resistor array can be obtained as formula (5):
将公式(5)和公式(4)对比公式(3),可以明显看出C-R混合型SAR ADC对精度的要求要明显低于电荷再分配型SAR ADC。对于电压等比例缩放型SAR ADC的分析与电荷再分配型SAR ADC的分析类似,在此不再赘述。但C-R混合型SAR ADC或是R-C混合型SAR ADC存在的问题在于:随着SAR ADC精度要求的进一步提高,电容阵列的电容值与电阻阵列的电阻个数依然会成指数增加,依然会面临电容匹配问题和电路面积问题。Comparing formula (5) and formula (4) with formula (3), it can be clearly seen that the accuracy requirements of the C-R hybrid SAR ADC are significantly lower than those of the charge redistribution SAR ADC. The analysis of the voltage scaling SAR ADC is similar to the analysis of the charge redistribution SAR ADC and will not be repeated here. However, the problem with C-R hybrid SAR ADC or R-C hybrid SAR ADC is that as the accuracy requirements of SAR ADC further increase, the capacitance value of the capacitor array and the number of resistors in the resistor array will still increase exponentially, and the capacitance will still be faced. Matching problem and circuit area problem.
发明内容Contents of the invention
为解决上述问题,本发明提供了一种数模转换电路及控制方法、模数转换器及电子设备。In order to solve the above problems, the present invention provides a digital-to-analog conversion circuit and a control method, an analog-to-digital converter and electronic equipment.
根据本发明的第一方面,提供了一种数模转换电路,用于将N位的第一数字信号转换为对应的第一模拟电压;包括第一阻性阵列、第一电容阵列、第二阻性阵列;According to a first aspect of the present invention, a digital-to-analog conversion circuit is provided for converting an N-bit first digital signal into a corresponding first analog voltage; including a first resistive array, a first capacitor array, a second resistive array;
所述第一阻性阵列的第一端接地,其第二端接第一参考电压;所述第一阻性阵列被配置为响应于所述第一数字信号的高M位数字数据选择性地对所述第一参考电压进行分压,以使得所述第一阻性阵列的第一输出端和第二输出端分别输出第二参考电压与第三参考电压;其中,所述第二参考电压与所述第三参考电压均包括2M级电压,且所述第二参考电压小于所述第三参考电压;A first terminal of the first resistive array is connected to ground, and a second terminal thereof is connected to a first reference voltage; the first resistive array is configured to selectively respond to the high M-bit digital data of the first digital signal The first reference voltage is divided so that the first output terminal and the second output terminal of the first resistive array output a second reference voltage and a third reference voltage respectively; wherein, the second reference voltage and the third reference voltage both include 2 M level voltages, and the second reference voltage is smaller than the third reference voltage;
所述第二阻性阵列的第一端接第四参考电压,其第二端接第五参考电压;所述第二阻性阵列被配置为响应于所述第一数字信号的低J位数字数据选择性地对第一电压进行分压,以使得所述第二阻性阵列的输出端输出第六参考电压;其中,所述第六参考电压包括2J级电压;其中,所述第一电压为所述第二参考电压经缓冲获得的第四参考电压与所述第三参考电压经缓冲后获得的第五参考电压之差;The first terminal of the second resistive array is connected to the fourth reference voltage, and the second terminal thereof is connected to the fifth reference voltage; the second resistive array is configured to respond to the low J bits of the first digital signal. The data selectively divides the first voltage, so that the output end of the second resistive array outputs a sixth reference voltage; wherein the sixth reference voltage includes 2 J level voltage; wherein the first The voltage is the difference between the fourth reference voltage obtained by buffering the second reference voltage and the fifth reference voltage obtained by buffering the third reference voltage;
所述第一电容阵列包括第一电容器和第二电容子阵列,所述第二电容子阵列包括从低位到高位依次排列的N-M-J个第二电容器,且所述第二电容子阵列中的第i个第二电容器的电容值满足:Ci=2i-1C0;其中,C0为第一电容器的电容值;所述第一电容器的第一端接所述第六参考电压,所述第一电容器的第二端耦接至所述第二电容子阵列的输出端;其中,The first capacitor array includes a first capacitor and a second capacitor sub-array, the second capacitor sub-array includes NMJ second capacitors arranged sequentially from low to high, and the i-th capacitor in the second capacitor sub-array The capacitance value of the second capacitor satisfies: Ci=2 i-1 C0; where C0 is the capacitance value of the first capacitor; the first terminal of the first capacitor is connected to the sixth reference voltage, and the first capacitor The second terminal is coupled to the output terminal of the second capacitor sub-array; wherein,
所述第二电容子阵列的输入端用于对输入电压进行采样,且所述第二电容子阵列被配置为:The input end of the second capacitor subarray is used to sample the input voltage, and the second capacitor subarray is configured as:
响应于所述第一数字信号的中N-J位数字数据中的任意一位数字数据选择性地基于所述第二参考电压或所述第三参考电压输出匹配于所述第一数字信号中的N-J位数字数据的第二模拟电压;In response to any one bit of digital data among the N-J bits of digital data of the first digital signal, selectively output matching the N-J bits of the first digital signal based on the second reference voltage or the third reference voltage. a second analog voltage of bits of digital data;
其中,在所述第一电容器接收所述第六参考电压后,所述第一电容阵列输出匹配于所述第六参考电压的第三模拟电压;Wherein, after the first capacitor receives the sixth reference voltage, the first capacitor array outputs a third analog voltage that matches the sixth reference voltage;
其中,所述第一模拟电压为所述第二模拟电压和所述第三模拟电压的加权求和;其中,N、M、J、i均为正整数,且M、J≥1,M+J<N;1≤i≤N-M-J。Wherein, the first analog voltage is a weighted sum of the second analog voltage and the third analog voltage; where N, M, J, i are all positive integers, and M, J≥1, M+ J<N;1≤i≤N-M-J.
可选的,所述第一阻性阵列包括2M个串联连接的第一阻性单元、第一开关单元、第二开关单元;Optionally, the first resistive array includes 2M first resistive units, first switch units, and second switch units connected in series;
首个第一阻性单元的第一端作为所述第一阻性阵列的第一端,第二M个第一阻性单元的第二端作为所述第一阻性阵列的第二端;The first end of the first first resistive unit serves as the first end of the first resistive array, and the second end of the second M first resistive units serves as the second end of the first resistive array;
所述第一开关单元包括2M个第一开关子单元,所有第一开关子单元的第二端均耦接至所述第一阻性阵列的第一输出端;每个第一开关子单元均对应一第一阻性单元,且每个第一开关子单元的第一端均耦接至对应第一阻性单元的第一端;所述第一开关单元被配置为响应于所述第一数字信号的高M位数字数据,选择性地对所述第一参考电压进行分压,以输出所述第二参考电压;The first switch unit includes 2M first switch sub-units, the second ends of all first switch sub-units are coupled to the first output end of the first resistive array; each first switch sub-unit Corresponding to a first resistive unit, the first end of each first switch sub-unit is coupled to the first end of the corresponding first resistive unit; the first switch unit is configured to respond to the first The high M-bit digital data of the digital signal selectively divides the first reference voltage to output the second reference voltage;
所述第二开关单元包括2M个第二开关子单元,所有第二开关子单元的第二端均耦接至所述第一阻性阵列的第二输出端;每个第二开关子单元均对应一个第一阻性单元,且每个第二开关子单元的第一端均耦接至对应第一阻性单元的第二端;所述第二开关单元被配置为响应于所述第一数字信号的高M位数字数据,选择性地对所述第一参考电压进行分压,以输出所述第三参考电压。The second switch unit includes 2M second switch sub-units, the second terminals of all second switch sub-units are coupled to the second output terminal of the first resistive array; each second switch sub-unit Corresponding to a first resistive unit, the first end of each second switch sub-unit is coupled to the second end corresponding to the first resistive unit; the second switch unit is configured to respond to the first The high M-bit digital data of the digital signal selectively divides the first reference voltage to output the third reference voltage.
可选的,所述第二阻性阵列包括2J个串联连接的第二阻性单元和第三开关单元;Optionally, the second resistive array includes 2J second resistive units and a third switch unit connected in series;
首个第二阻性单元的第一端作为所述第一阻性阵列的第一端,第二J个第二阻性单元的第二端作为所述第二阻性阵列的第二端;The first end of the first second resistive unit serves as the first end of the first resistive array, and the second end of the second J second resistive units serves as the second end of the second resistive array;
所述第三开关单元包括2J个第三开关子单元,所有第三开关子单元的第二端均耦接至所述第二阻性阵列的输出端;每个第三开关子单元均对应一第二阻性单元,且每个第三开关子单元的第一端均耦接至对应第二阻性单元的第一端;所述第三开关单元被配置为响应于所述第一数字信号的低J位数字数据,选择性地对所述第一电压进行分压,以输出所述第六参考电压。The third switch unit includes 2J third switch sub-units, the second terminals of all third switch sub-units are coupled to the output terminals of the second resistive array; each third switch sub-unit corresponds to a a second resistive unit, and a first end of each third switch sub-unit is coupled to a first end of the corresponding second resistive unit; the third switch unit is configured to respond to the first digital signal The low J-bit digital data is used to selectively divide the first voltage to output the sixth reference voltage.
可选的,所述第一阻性单元和所述第二阻性单元均包括单个电阻。Optionally, both the first resistive unit and the second resistive unit include a single resistor.
可选的,所述第一阻性单元和所述第二阻性单元均包括电阻网络;其中,所述电阻网络由多个电阻串并联构成。Optionally, both the first resistive unit and the second resistive unit include a resistor network; wherein the resistor network is composed of a plurality of resistors connected in series and parallel.
可选的,所述第一开关子单元、所述第二开关子单元、所述第三开关子单元均包括单刀单掷开关。Optionally, the first switch subunit, the second switch subunit, and the third switch subunit all include single-pole single-throw switches.
可选的,所述第二电容子阵列还包括第四开关单元;Optionally, the second capacitor sub-array further includes a fourth switch unit;
所述第四开关单元包括N-M-J个第四开关子单元;每个所述第四开关子单元均对应一所述第二电容器;每个所述第四开关子单元的第一端均耦接至对应所述第二电容器的输入端;其中,所述第四开关单元被配置为:接入所述输入电压;The fourth switch unit includes N-M-J fourth switch sub-units; each fourth switch sub-unit corresponds to one of the second capacitors; the first end of each fourth switch sub-unit is coupled to Corresponding to the input end of the second capacitor; wherein the fourth switch unit is configured to: access the input voltage;
响应于所述第一数字信号的中N-J位数字数据,使每个所述第四开关子单元的第一端对应选择所述第一阻性阵列的第一输出端或所述第一阻性阵列的第二输出端。In response to the N-J bits of digital data of the first digital signal, the first end of each fourth switch subunit correspondingly selects the first output end of the first resistive array or the first resistive The second output of the array.
可选的,所述第四开关子单元包括单刀三掷开关。Optionally, the fourth switch subunit includes a single pole three throw switch.
根据本发明的第二方面,提供了一种数模转换电路的控制方法,用于对本发明第一方面及可选方案所提供的数模转换电路进行控制,该方法包括:According to the second aspect of the present invention, a method for controlling a digital-to-analog conversion circuit is provided, which is used to control the digital-to-analog conversion circuit provided by the first aspect and optional solutions of the present invention. The method includes:
根据所述第一数字信号的高M位数字数据,控制所述第一阻性阵列选择性地对所述第一参考电压进行分压,以使得所述第一阻性阵列分别输出第二参考电压与第三参考电压;其中,所述第二参考电压与所述第三参考电压均包括2M级电压,且所述第二参考电压小于所述第三参考电压;According to the high M-bit digital data of the first digital signal, the first resistive array is controlled to selectively divide the first reference voltage, so that the first resistive array outputs a second reference voltage respectively. voltage and a third reference voltage; wherein, the second reference voltage and the third reference voltage each include a 2M level voltage, and the second reference voltage is smaller than the third reference voltage;
根据所述第一数字信号的低J位数字数据,控制所述第二阻性阵列选择性地对第一电压进行分压,以使得所述第二阻性阵列输出第六参考电压;其中,所述第六参考电压包括2J级电压;其中,所述第一电压为所述第二参考电压经缓冲获得的第四参考电压与所述第三参考电压经缓冲后获得的第五参考电压之差;According to the low J-bit digital data of the first digital signal, the second resistive array is controlled to selectively divide the first voltage, so that the second resistive array outputs a sixth reference voltage; wherein, The sixth reference voltage includes 2J- level voltages; wherein the first voltage is a fourth reference voltage obtained by buffering the second reference voltage and a fifth reference voltage obtained by buffering the third reference voltage. Difference;
根据所述第一数字信号的中N-J位数字数据中的任意一位数字数据,控制所述第二电容子阵列选择性地基于所述第二参考电压或所述第三参考电压输出匹配于所述第一数字信号中的N-J位数字数据的第二模拟电压;According to any one of the N-J bits of digital data in the first digital signal, the second capacitor sub-array is controlled to selectively output a matching voltage based on the second reference voltage or the third reference voltage. a second analog voltage of N-J bits of digital data in the first digital signal;
根据接收发热所述第六参考电压,所述第一电容阵列输出匹配于所述第六参考电压的第三模拟电压;According to receiving and generating the sixth reference voltage, the first capacitor array outputs a third analog voltage that matches the sixth reference voltage;
其中,所述第一模拟电压等于所述第二模拟电压和所述第三模拟电压的加权求和;N、M、J、i均为正整数,且M、J≥1,M+J<N;1≤i≤N-M-J。Wherein, the first analog voltage is equal to the weighted sum of the second analog voltage and the third analog voltage; N, M, J, i are all positive integers, and M, J≥1, M+J< N;1≤i≤N-M-J.
根据本发明的第三方面,提供了一种模数转换器用于将所述输入电压转换为N位的第二数字信号,包括比较器、异步时钟发生器、逻辑控制模块、本发明第一方面及可选方案所提供的数模转换电路;According to the third aspect of the present invention, an analog-to-digital converter is provided for converting the input voltage into an N-bit second digital signal, including a comparator, an asynchronous clock generator, a logic control module, and the first aspect of the present invention. And the digital-to-analog conversion circuit provided by the optional solution;
所述第二电容子阵列的输入端接入所述输入电压,所述第一电容阵列的输出端耦接至所述比较器的第一输入端;所述比较器的第二输入端接地,所述比较器的输出端耦接至所述异步时钟发生器;所述异步时钟发生器的输出端耦接至所述逻辑控制模块;所述逻辑控制模块的输出端分别耦接至第一阻性阵列、第一电容阵列、第二阻性阵列;The input terminal of the second capacitor sub-array is connected to the input voltage, the output terminal of the first capacitor array is coupled to the first input terminal of the comparator; the second input terminal of the comparator is connected to ground, The output terminal of the comparator is coupled to the asynchronous clock generator; the output terminal of the asynchronous clock generator is coupled to the logic control module; the output terminals of the logic control module are respectively coupled to the first resistor. array, a first capacitor array, a second resistive array;
其中,所述第二电容子阵列用于根据第一使能信号,对接入的所述输入电压进行第一时间的采样;所述逻辑控制模块用于输出第i数字信号至所述第一阻性阵列、所述第二电容子阵列、所述第二阻性阵列,以得到第i模拟电压;所述比较器用于将所述第i模拟电压与所述第三模拟电压进行比较并输出第i比较信号;所异步时钟发生器用于根据所述第i比较信号和所述第一使能信号,输出第i时钟信号;所述逻辑控制模块还用于根据所述第i时钟信号和第二使能信号,输出第i+1数字信号、第i输出信号;其中,i为正整数,且1≤i≤N;所述第二使能信号为所述第一使能信号的反相信号;所述第i输出信号作为所述模数转换器最终输出的第i位数。Wherein, the second capacitor sub-array is used to sample the input voltage for a first time according to the first enable signal; the logic control module is used to output the i-th digital signal to the first a resistive array, the second capacitor sub-array, and the second resistive array to obtain the i-th analog voltage; the comparator is used to compare the i-th analog voltage with the third analog voltage and output The i-th comparison signal; the asynchronous clock generator is used to output the i-th clock signal according to the i-th comparison signal and the first enable signal; the logic control module is also used to output the i-th clock signal according to the i-th clock signal and the first enable signal. Two enable signals, output the i+1 digital signal and the i output signal; where i is a positive integer, and 1≤i≤N; the second enable signal is the inverse of the first enable signal signal; the i-th output signal is used as the i-th digit of the final output of the analog-to-digital converter.
根据本发明的第四方面,提供了一种电子设备,包括本发明第三方面所提供的模数转换器。According to a fourth aspect of the present invention, an electronic device is provided, including the analog-to-digital converter provided by the third aspect of the present invention.
本发明提供的数模转换电路由第一阻性阵列、第一电容阵列、第二阻性阵列组成,相对于现有技术的C-R混合型数模转换电路或R-C混合型数模转换电路,本发明对于高精度的SAR ADC具有更好的面积优化和更小的精度要求。The digital-to-analog conversion circuit provided by the present invention is composed of a first resistive array, a first capacitor array, and a second resistive array. Compared with the existing C-R hybrid digital-to-analog conversion circuit or the R-C hybrid digital-to-analog conversion circuit, this circuit has The invention has better area optimization and smaller accuracy requirements for high-precision SAR ADC.
附图说明Description of the drawings
下面结合附图和具体实施方式对本发明作进一步详细的说明。The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.
图1是本发明第一实施例提供的数模转换电路的电路结构图一;Figure 1 is a circuit structure diagram of a digital-to-analog conversion circuit provided by the first embodiment of the present invention;
图2是本发明第一实施例提供的数模转换电路的电路结构图二;Figure 2 is a second circuit structure diagram of a digital-to-analog conversion circuit provided by the first embodiment of the present invention;
图3是本发明第一实施例提供的数模转换电路的电路结构图三;Figure 3 is a circuit structure diagram of the digital-to-analog conversion circuit provided by the first embodiment of the present invention;
图4是本发明第三实施例提供的模数转换器的电路结构图;Figure 4 is a circuit structure diagram of an analog-to-digital converter provided by a third embodiment of the present invention;
图5是本发明第三实施例提供的模数转换器的微分非线性图;Figure 5 is a differential nonlinear diagram of the analog-to-digital converter provided by the third embodiment of the present invention;
图6是本发明第三实施例提供的模数转换器的积分非线性图;Figure 6 is an integral nonlinear diagram of the analog-to-digital converter provided by the third embodiment of the present invention;
图7是本发明第三实施例提供的模数转换器的FFT分析图。Figure 7 is an FFT analysis diagram of the analog-to-digital converter provided by the third embodiment of the present invention.
附图标记:Reference signs:
1-数模转换电路;1-Digital-to-analog conversion circuit;
2-比较器;2-Comparator;
3-异步时钟发生器;3-Asynchronous clock generator;
4-逻辑控制模块;4-Logic control module;
10-第一阻性阵列;10-First resistive array;
11-第一开关单元;11-First switch unit;
12-第二开关单元;12-Second switch unit;
20-第一电容阵列;20-The first capacitor array;
21-第二电容子阵列;21-The second capacitor subarray;
30-第二阻性阵列;30-Second resistive array;
31-第三开关单元;31-Third switch unit;
R1-第一阻性单元;R1-the first resistive unit;
R2-第二阻性单元;R2-the second resistive unit;
Vref-第一参考电压;Vref-first reference voltage;
Vref-H-第三参考电压;Vref-H-third reference voltage;
Vref-L-第二参考电压;Vref-L-second reference voltage;
Vref-h-第五参考电压;Vref-h-fifth reference voltage;
Vref-l-第四参考电压;Vref-l-the fourth reference voltage;
Vref-lsb-第六参考电压;Vref-lsb-sixth reference voltage;
Vin-输入电压;Vin - input voltage;
Vout-第二电容子阵列的输出端;Vout-the output terminal of the second capacitor sub-array;
C0-第一电容器;C0-first capacitor;
SWi-第一数字信号;SWi-first digital signal;
CLK1-第一使能信号;CLK1-the first enable signal;
CLK2-第二使能信号;CLK2-the second enable signal;
VPi-第i比较信号;VPi-ith comparison signal;
Di-输出信号;Di-output signal;
VALIDi-第i时钟信号。VALIDi-ith clock signal.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外,术语“包括”和“具有”以及他们的任何变形,意图在于覆盖不排他的包含,例如,包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if present) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects without necessarily using Used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the invention described herein are capable of being practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.
请参考图1,本发明第一实施例提供了一种数模转换电路,用于将N位的第一数字信号转换为对应的第一模拟电压,包括第一阻性阵列10、第一电容阵列20、第二阻性阵列30;Please refer to Figure 1. A first embodiment of the present invention provides a digital-to-analog conversion circuit for converting an N-bit first digital signal into a corresponding first analog voltage, including a first resistive array 10, a first capacitor Array 20, second resistive array 30;
所述第一阻性阵列10的第一端接地,其第二端接第一参考电压Vref;所述第一阻性阵列10被配置为响应于所述第一数字信号的高M位数字数据选择性地对所述第一参考电压Vref进行分压,以使得所述第一阻性阵列10的第一输出端和第二输出端分别输出第二参考电压Vref-L与第三参考电压Vref-H;其中,所述第二参考电压Vref-L与所述第三参考电压Vref-H均包括2M级电压,且所述第二参考电压Vref-L小于所述第三参考电压Vref-H;The first terminal of the first resistive array 10 is connected to ground, and the second terminal thereof is connected to the first reference voltage Vref; the first resistive array 10 is configured to respond to the high M-bit digital data of the first digital signal. Selectively divide the first reference voltage Vref, so that the first output terminal and the second output terminal of the first resistive array 10 output the second reference voltage Vref-L and the third reference voltage Vref respectively. -H; wherein, the second reference voltage Vref-L and the third reference voltage Vref-H both include 2M level voltages, and the second reference voltage Vref-L is smaller than the third reference voltage Vref- H;
所述第二阻性阵列30的第一端接第四参考电压Vref-l,其第二端接第五参考电压Vref-h;所述第二阻性阵列30被配置为响应于所述第一数字信号的低J位数字数据选择性地对选择性地对第一电压进行分压,以使得所述第二阻性阵列30的输出端输出第六参考电压Vref-lsb;其中,所述第六参考电压Vref-lsb包括2J级电压;其中,所述第一电压为所述第二参考电压Vref-L经缓冲获得的第四参考电压Vref-l与所述第三参考电压Vref-H经缓冲后获得的第五参考电压Vref-h之差;The first terminal of the second resistive array 30 is connected to the fourth reference voltage Vref-l, and the second terminal is connected to the fifth reference voltage Vref-h; the second resistive array 30 is configured to respond to the first The low J-bit digital data of a digital signal selectively divides the first voltage selectively, so that the output end of the second resistive array 30 outputs the sixth reference voltage Vref-lsb; wherein, the The sixth reference voltage Vref-lsb includes 2 J- level voltages; wherein the first voltage is the fourth reference voltage Vref-l obtained by buffering the second reference voltage Vref-L and the third reference voltage Vref- The difference between the fifth reference voltage Vref-h obtained after H is buffered;
所述第四参考电压Vref-l为所述第二参考电压Vref-L经缓冲后输出的电压,所述第五参考电压Vref-h为所述第三参考电压Vref-H经缓冲后输出的电压;The fourth reference voltage Vref-l is a buffered output voltage of the second reference voltage Vref-L, and the fifth reference voltage Vref-h is a buffered output voltage of the third reference voltage Vref-H. Voltage;
所述第一电容阵列20包括第一电容器C0和第二电容子阵列21,所述第二电容子阵列21包括从低位到高位依次排列的N-M-J个第二电容器,且所述第二电容子阵列21中的第i个第二电容器的电容值满足:The first capacitor array 20 includes a first capacitor C0 and a second capacitor sub-array 21. The second capacitor sub-array 21 includes N-M-J second capacitors arranged in sequence from low to high, and the second capacitor sub-array 20 The capacitance value of the i-th second capacitor in 21 satisfies:
Ci=2i-1C0;其中,C0为第一电容器C0的电容值;Ci=2 i-1 C0; where C0 is the capacitance value of the first capacitor C0;
所述第一电容器C0的第一端接所述第六参考电压Vref-lsb,所述第一电容器C0的第二端耦接至所述第二电容子阵列21的输出端Vout;其中,The first terminal of the first capacitor C0 is connected to the sixth reference voltage Vref-lsb, and the second terminal of the first capacitor C0 is coupled to the output terminal Vout of the second capacitor sub-array 21; wherein,
所述第二电容子阵列21的输入端用于对输入电压Vin进行采样,且所述第二电容子阵列21被配置为:The input end of the second capacitor sub-array 21 is used to sample the input voltage Vin, and the second capacitor sub-array 21 is configured as:
响应于所述第一数字信号的中N-J位数字数据中的任意一位数字数据选择性地基于所述第二参考电压Vref-L或所述第三参考电压Vref-H输出匹配于所述第一数字信号中的N-J位数字数据的第二模拟电压;In response to any one bit of digital data in the N-J bits of digital data of the first digital signal, the output is selectively matched to the third reference voltage Vref-L or the third reference voltage Vref-H based on the second reference voltage Vref-L or the third reference voltage Vref-H. a second analog voltage of N-J bits of digital data in a digital signal;
其中,在所述第一电容器接收所述第六参考电压Vref-lsb后,所述第一电容阵列20输出匹配于所述第六参考电压Vref-lsb的第三模拟电压;Wherein, after the first capacitor receives the sixth reference voltage Vref-lsb, the first capacitor array 20 outputs a third analog voltage matching the sixth reference voltage Vref-lsb;
其中,所述第一模拟电压为所述第二模拟电压和所述第三模拟电压的加权求和;其中,N、M、J、i均为正整数,且M、J≥1,M+J<N;1≤i≤N-M-J。Wherein, the first analog voltage is a weighted sum of the second analog voltage and the third analog voltage; where N, M, J, i are all positive integers, and M, J≥1, M+ J<N;1≤i≤N-M-J.
本发明第一实施例通过上述技术方案,以实现相较于现有技术的C-R混合型数模转换电路或R-C混合型数模转换电路,具有更好的面积优化和更小的精度要求。其原理为:设定N bit的SAR ADC的高M位均通过本发明第一实施例提供的所述第一阻性阵列10实现,中N-M-J位均通过本发明第一实施例提供的所述第一电容阵列20实现,剩余的J位均通过本发明第一实施例提供的所述第二阻性阵列30实现,根据背景技术提到的极端分析可以得到:对所述第一阻性单元R1的精度要求、所述第一电容单元的精度要求、所述第二阻性单元R2的精度要求分别是公式(6)、公式(7)、公式(8):The first embodiment of the present invention uses the above technical solution to achieve better area optimization and smaller accuracy requirements compared to the C-R hybrid digital-to-analog conversion circuit or the R-C hybrid digital-to-analog conversion circuit in the prior art. The principle is: the high M bits of the N-bit SAR ADC are all realized by the first resistive array 10 provided by the first embodiment of the present invention, and the middle N-M-J bits are all realized by the first resistive array 10 provided by the first embodiment of the present invention. The first capacitor array 20 is implemented, and the remaining J bits are implemented through the second resistive array 30 provided in the first embodiment of the present invention. According to the extreme analysis mentioned in the background art, it can be obtained that: for the first resistive unit The accuracy requirements of R1, the accuracy requirements of the first capacitive unit, and the accuracy requirements of the second resistive unit R2 are formula (6), formula (7), and formula (8) respectively:
将公式(6)至公式(8)与背景技术提到的公式(4)和公式(5)进行比较可以看出,本发明第一实施例提供的数模转换电路相较于现有C-R混合型数模转换电路具有更小的精度要求。对于R-C混合型数模转换电路与本发明第一实施例的的比较与上述比较的方法、结果类似,在此不再赘述。Comparing Formula (6) to Formula (8) with Formula (4) and Formula (5) mentioned in the background art, it can be seen that the digital-to-analog conversion circuit provided by the first embodiment of the present invention is better than the existing C-R hybrid The digital-to-analog conversion circuit has smaller accuracy requirements. The comparison between the R-C hybrid digital-to-analog conversion circuit and the first embodiment of the present invention is similar to the above comparison method and results, and will not be described again here.
对于面积优化,其原理为:以8bit的数模转换电路进行举例,对于C-R混合型数模转换电路,选择高4bit均通过电容阵列实现,低4bit均通过电阻阵列实现,因此需要电容阵列需要4个电容,电阻阵列需要24个电阻。对于本发明第一实施例提供的数模转换电路,选择高2bit均通过第一阻性阵列10实现,中4bit均通过第一电容阵列20实现,低2bit均通过第二阻性阵列30实现,因此第一电容阵列20需要4个电容,而第一阻性阵列10和所述第二阻性阵列30一共只需要8个电阻。在相同精度要求下,本发明第一实施例提供的数模转换电路相较于C-R混合型数模转换电路,具有更小的电路面积,达到更好的面积优化,而且随着精度要求的不断提高,面积优化的效果就越显著。当然,所述第一阻性阵列10、所述第一电容阵列20、所述第二阻性阵列30各自设置的位数会结合电路中电容和电阻的实际工艺,及电路的实际面积进行折衷设置,在此不做限定。For area optimization, the principle is: taking an 8-bit digital-to-analog conversion circuit as an example. For the C-R hybrid digital-to-analog conversion circuit, the high 4 bits are all realized through the capacitor array, and the low 4 bits are all realized through the resistor array. Therefore, the capacitor array requires 4 capacitor, the resistor array requires 24 resistors. For the digital-to-analog conversion circuit provided by the first embodiment of the present invention, the high 2 bits are all realized through the first resistive array 10, the middle 4 bits are all realized through the first capacitor array 20, and the low 2 bits are all realized through the second resistive array 30. Therefore, the first capacitor array 20 requires 4 capacitors, while the first resistive array 10 and the second resistive array 30 only require 8 resistors in total. Under the same accuracy requirements, the digital-to-analog conversion circuit provided by the first embodiment of the present invention has a smaller circuit area than the C-R hybrid digital-to-analog conversion circuit, achieving better area optimization, and as accuracy requirements continue to increase The higher the value, the more significant the effect of area optimization will be. Of course, the number of bits provided in each of the first resistive array 10 , the first capacitor array 20 , and the second resistive array 30 will be compromised based on the actual process of the capacitors and resistors in the circuit and the actual area of the circuit. Settings are not limited here.
请参考图1,需要补充的是,本发明第一实施例提供的第二电容子阵列21是通过电容的底极板对输入电压Vin进行采样,相较于现有技术通常通过电容的顶极板进行采样,能避免在采样过程中因电荷注入带来的问题。Please refer to Figure 1. It should be added that the second capacitor sub-array 21 provided by the first embodiment of the present invention samples the input voltage Vin through the bottom plate of the capacitor. Compared with the prior art, which usually samples the input voltage Vin through the top plate of the capacitor, Sampling with a plate can avoid problems caused by charge injection during the sampling process.
以下对所述数模转换电路的内部电路结构进行说明:The following describes the internal circuit structure of the digital-to-analog conversion circuit:
请参考图2,作为一种具体实施方式,所述第一阻性阵列10包括2M个串联连接的第一阻性单元R1、第一开关单元11、第二开关单元12;Please refer to Figure 2. As a specific implementation, the first resistive array 10 includes 2M first resistive units R1, first switch units 11, and second switch units 12 connected in series;
首个第一阻性单元R1的第一端作为所述第一阻性阵列10的第一端,第二M个第一阻性单元R1的第二端作为所述第一阻性阵列10的第二端;The first end of the first first resistive unit R1 serves as the first end of the first resistive array 10 , and the second end of the second M first resistive units R1 serves as the first end of the first resistive array 10 second end;
所述第一开关单元11包括2M个第一开关子单元,所有第一开关子单元的第二端均耦接至所述第一阻性阵列10的第一输出端;每个第一开关子单元均对应一第一阻性单元R1,且每个第一开关子单元的第一端均耦接至对应第一阻性单元R1的第一端;所述第一开关单元11被配置为响应于所述第一数字信号的高M位数字数据,选择性地对所述第一参考电压Vref进行分压,以输出所述第二参考电压Vref-L;The first switch unit 11 includes 2M first switch sub-units, and the second terminals of all first switch sub-units are coupled to the first output terminal of the first resistive array 10; each first switch sub-unit Each unit corresponds to a first resistive unit R1, and the first end of each first switch sub-unit is coupled to the first end corresponding to the first resistive unit R1; the first switch unit 11 is configured to respond Selectively divide the first reference voltage Vref on the high M-bit digital data of the first digital signal to output the second reference voltage Vref-L;
所述第二开关单元12包括2M个第二开关子单元,所有第二开关子单元的第二端均耦接至所述第一阻性阵列10的第二输出端;每个第二开关子单元均对应一个第一阻性单元R1,且每个第二开关子单元的第一端均耦接至对应第一阻性单元R1的第二端;所述第二开关单元12被配置为响应于所述第一数字信号的高M位数字数据,选择性地对所述第一参考电压Vref进行分压,以输出所述第三参考电压Vref-H。The second switch unit 12 includes 2M second switch sub-units, and the second terminals of all second switch sub-units are coupled to the second output terminal of the first resistive array 10; each second switch sub-unit Each unit corresponds to a first resistive unit R1, and the first end of each second switch sub-unit is coupled to the second end corresponding to the first resistive unit R1; the second switch unit 12 is configured to respond The first reference voltage Vref is selectively divided on the high M-bit digital data of the first digital signal to output the third reference voltage Vref-H.
请参考图3,作为一种具体实施方式,所述第二阻性阵列30包括2J个串联连接的第二阻性单元R2和第三开关单元31;Please refer to Figure 3. As a specific implementation, the second resistive array 30 includes 2J second resistive units R2 and third switch units 31 connected in series;
首个第二阻性单元R2的第一端作为所述第一阻性阵列10的第一端,第二J个第二阻性单元R2的第二端作为所述第二阻性阵列30的第二端;The first end of the first second resistive unit R2 serves as the first end of the first resistive array 10 , and the second end of the second J second resistive units R2 serves as the second end of the second resistive array 30 second end;
所述第三开关单元31包括2J个第三开关子单元,所有第三开关子单元的第二端均耦接至所述第二阻性阵列30的输出端;每个第三开关子单元均对应一第二阻性单元R2,且每个第三开关子单元的第一端均耦接至对应第二阻性单元R2的第一端;所述第三开关单元31被配置为响应于所述第一数字信号的低J位数字数据,选择性地对所述第一电压进行分压,以输出所述第六参考电压Vref-lsb。The third switch unit 31 includes 2J third switch sub-units, and the second terminals of all third switch sub-units are coupled to the output terminals of the second resistive array 30; each third switch sub-unit is Corresponds to a second resistive unit R2, and the first end of each third switch sub-unit is coupled to the first end corresponding to the second resistive unit R2; the third switch unit 31 is configured to respond to the The low J-bit digital data of the first digital signal is used to selectively divide the first voltage to output the sixth reference voltage Vref-lsb.
作为一种具体实施方式,所述第一阻性单元R1和所述第二阻性单元R2均包括单个电阻。当然,所述第一阻性单元R1和所述第二阻性单元R2均包括电阻网络;其中,所述电阻网络由多个电阻串并联构成。具体电路结构可根据实际需求进行选择,在此不做限定。As a specific implementation manner, the first resistive unit R1 and the second resistive unit R2 each include a single resistor. Of course, both the first resistive unit R1 and the second resistive unit R2 include a resistor network; wherein the resistor network is composed of a plurality of resistors connected in series and parallel. The specific circuit structure can be selected according to actual needs and is not limited here.
作为一种具体实施方式,所述第一开关子单元、所述第二开关子单元、所述第三开关子单元均包括单刀单掷开关。As a specific implementation manner, the first switch subunit, the second switch subunit, and the third switch subunit all include single-pole single-throw switches.
请参考图3,作为一种具体实施方式,所述第二电容子阵列21还包括第四开关单元;Please refer to Figure 3, as a specific implementation manner, the second capacitor sub-array 21 also includes a fourth switch unit;
所述第四开关单元包括N-M-J个第四开关子单元;每个所述第四开关子单元均对应一所述第二电容器;每个所述第四开关子单元的第一端均耦接至对应所述第二电容器的输入端;所述第四开关单元被配置为:接入所述输入电压Vin;The fourth switch unit includes N-M-J fourth switch sub-units; each fourth switch sub-unit corresponds to one of the second capacitors; the first end of each fourth switch sub-unit is coupled to Corresponding to the input end of the second capacitor; the fourth switch unit is configured to: connect to the input voltage Vin;
响应于所述第一数字信号的中N-J位数字数据,使每个所述第四开关子单元的第一端对应选择所述第一阻性阵列10的第一输出端或所述第一阻性阵列20的第二输出端。In response to the N-J bits of digital data of the first digital signal, the first end of each fourth switch subunit correspondingly selects the first output end of the first resistive array 10 or the first resistor. The second output terminal of the array 20.
作为一种具体实施方式,所述第四开关子单元包括单刀三掷开关。As a specific implementation manner, the fourth switch subunit includes a single-pole three-throw switch.
本发明第二实施例提供了一种数模转换电路的控制方法用于对本发明第一实施例提供的所述数模转换电路进行控制,该方法包括:The second embodiment of the present invention provides a control method for a digital-to-analog conversion circuit for controlling the digital-to-analog conversion circuit provided by the first embodiment of the present invention. The method includes:
根据所述第一数字信号的高M位数字数据,控制所述第一阻性阵列选择性地对所述第一参考电压进行分压,以使得所述第一阻性阵列分别输出第二参考电压与第三参考电压;其中,所述第二参考电压与所述第三参考电压均包括2M级电压,且所述第二参考电压小于所述第三参考电压;According to the high M-bit digital data of the first digital signal, the first resistive array is controlled to selectively divide the first reference voltage, so that the first resistive array outputs a second reference voltage respectively. voltage and a third reference voltage; wherein, the second reference voltage and the third reference voltage each include a 2M level voltage, and the second reference voltage is smaller than the third reference voltage;
根据所述第一数字信号的低J位数字数据,控制所述第二阻性阵列选择性地对第一电压进行分压,以使得所述第二阻性阵列输出第六参考电压;其中,所述第六参考电压包括2J级电压;其中,所述第一电压为所述第二参考电压经缓冲获得的第四参考电压与所述第三参考电压经缓冲后获得的第五参考电压之差;According to the low J-bit digital data of the first digital signal, the second resistive array is controlled to selectively divide the first voltage, so that the second resistive array outputs a sixth reference voltage; wherein, The sixth reference voltage includes 2J- level voltages; wherein the first voltage is a fourth reference voltage obtained by buffering the second reference voltage and a fifth reference voltage obtained by buffering the third reference voltage. Difference;
根据所述第一数字信号的中N-J位数字数据中的任意一位数字数据,控制所述第二电容子阵列选择性地基于所述第二参考电压或所述第三参考电压输出匹配于所述第一数字信号中的N-J位数字数据的第二模拟电压;According to any one of the N-J bits of digital data in the first digital signal, the second capacitor sub-array is controlled to selectively output a matching voltage based on the second reference voltage or the third reference voltage. a second analog voltage of N-J bits of digital data in the first digital signal;
根据接收发热所述第六参考电压,所述第一电容阵列输出匹配于所述第六参考电压的第三模拟电压;其中,所述第一模拟电压等于所述第二模拟电压和所述第三模拟电压的加权求和;N、M、J、i均为正整数,且M、J≥1,M+J<N;1≤i≤N-M-J。According to receiving and generating the sixth reference voltage, the first capacitor array outputs a third analog voltage matching the sixth reference voltage; wherein the first analog voltage is equal to the second analog voltage and the third analog voltage. Weighted sum of three analog voltages; N, M, J, i are all positive integers, and M, J≥1, M+J<N; 1≤i≤N-M-J.
请参考图4,本发明第三实施例提供了一种模数转换器,用于将所述输入电压转换为N位的第二数字信号,包括比较器2、异步时钟发生器3、逻辑控制模块4、本发明第一实施例提供的所述数模转换电路1;Please refer to Figure 4. The third embodiment of the present invention provides an analog-to-digital converter for converting the input voltage into an N-bit second digital signal, including a comparator 2, an asynchronous clock generator 3, and a logic control Module 4. The digital-to-analog conversion circuit 1 provided by the first embodiment of the present invention;
所述第二电容子阵列21的输入端接入所述输入电压,所述第一电容阵列20的输出端耦接至所述比较器2的第一输入端;所述比较器2的第二输入端接地,所述比较器2的输出端耦接至所述异步时钟发生器3;所述异步时钟发生器3的输出端耦接至所述逻辑控制模块4;所述逻辑控制模块4的输出端分别耦接至第一阻性阵列10、第一电容阵列20、第二阻性阵列30;The input terminal of the second capacitor sub-array 21 is connected to the input voltage, and the output terminal of the first capacitor array 20 is coupled to the first input terminal of the comparator 2; The input terminal is grounded, and the output terminal of the comparator 2 is coupled to the asynchronous clock generator 3; the output terminal of the asynchronous clock generator 3 is coupled to the logic control module 4; the logic control module 4 The output terminals are respectively coupled to the first resistive array 10, the first capacitor array 20, and the second resistive array 30;
其中,所述第二电容子阵列21用于根据第一使能信号CLK1,对接入的所述输入电压进行第一时间的采样;所述逻辑控制模块4用于输出第i数字信号SWi至所述第一阻性阵列10、所述第二电容子阵列21、所述第二阻性阵列30,以得到第i模拟电压;所述比较器2用于将所述第i模拟电压与所述第三模拟电压进行比较并输出第i比较信号VP;所异步时钟发生器3用于根据所述第i比较信号VP和所述第一使能信号CLK1,输出第i时钟信号VALID;所述逻辑控制模块4还用于根据所述第i时钟信号VALID和第二使能信号CLK2,输出第i+1数字信号SWi、第i输出信号Di;其中,i为正整数,且1≤i≤N;所述第二使能信号CLK2为所述第一使能信号CLK1的反相信号;所述第i输出信号DiDI作为所述模数转换器最终输出的第i位数。Wherein, the second capacitor sub-array 21 is used to sample the input voltage for a first time according to the first enable signal CLK1; the logic control module 4 is used to output the i-th digital signal SWi to The first resistive array 10, the second capacitor sub-array 21, and the second resistive array 30 are used to obtain the i-th analog voltage; the comparator 2 is used to compare the i-th analog voltage with the i-th analog voltage. The third analog voltage is compared and outputs the i-th comparison signal VP; the asynchronous clock generator 3 is used to output the i-th clock signal VALID according to the i-th comparison signal VP and the first enable signal CLK1; the The logic control module 4 is also used to output the i+1 digital signal SWi and the i output signal Di according to the i clock signal VALID and the second enable signal CLK2; where i is a positive integer, and 1≤i≤ N; the second enable signal CLK2 is the inverse signal of the first enable signal CLK1; the i-th output signal DiDI is the i-th digit finally output by the analog-to-digital converter.
请参考图5、图6、图7,图5为本发明第三实施例提供的模数转换器的微分非线性图(DNL-Differential Non-linearity),图6为本发明第三实施例提供的模数转换器的积分非线性图(INL-Integral Non-linearity),通过图5和图6可知本发明第三实施例提供的模数转换器的微分非线性值为0.034LSB,积分非线性值为0.073LSB。需要说明是,对于模数转换器来说,微分非线性值和积分非线性值越小越好。图7为本发明第三实施例提供的模数转换器的FFT分析图;其中,模数转换器的输入信号为100k,采样点数为4096,模拟精度为12bit;通过图7可知本发明第三实施例提供的模数转换器的无杂散动态范围(SFDR)、信噪比(SNR)、有效位数(ENOB)分别为79.56、73.32dB、11.7bit。需要说明的是,对于模数转换器来说,有效位数越接近模拟精度越好。当然,以上只是发明人的实验数据,具体参数受实验环境、电路器件的工艺误差等影响,在此不做限定。Please refer to Figure 5, Figure 6, and Figure 7. Figure 5 is a differential nonlinearity diagram (DNL-Differential Non-linearity) of the analog-to-digital converter provided by the third embodiment of the present invention. Figure 6 is provided by the third embodiment of the present invention. The integral nonlinearity diagram (INL-Integral Non-linearity) of the analog-to-digital converter. From Figure 5 and Figure 6, it can be seen that the differential nonlinearity value of the analog-to-digital converter provided by the third embodiment of the present invention is 0.034LSB, and the integral nonlinearity The value is 0.073LSB. It should be noted that for analog-to-digital converters, the smaller the differential nonlinearity value and the integral nonlinearity value, the better. Figure 7 is an FFT analysis diagram of the analog-to-digital converter provided by the third embodiment of the present invention; wherein, the input signal of the analog-to-digital converter is 100k, the number of sampling points is 4096, and the simulation accuracy is 12 bits; it can be seen from Figure 7 that the third embodiment of the present invention The spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), and effective number of bits (ENOB) of the analog-to-digital converter provided by the embodiment are 79.56, 73.32dB, and 11.7bit respectively. It should be noted that for analog-to-digital converters, the closer the effective number of bits is to analog accuracy, the better. Of course, the above is only the inventor's experimental data. The specific parameters are affected by the experimental environment, process errors of circuit devices, etc., and are not limited here.
以下对本发明第三实施例提供的模数转换器的工作流程进行说明;其中,设置模数转换器精度为8位,所述第一阻性阵列10用于对输出数据的前3位进行转换;所述第一电容阵列20用于对输出数据的第四、5位进行转换;所述第二阻性阵列30用于对输出数据的后3位进行转换。当然,这只是一种具体实施例,也可以根据需求调整各个阵列的所占位数,并不以此为限:The following describes the workflow of the analog-to-digital converter provided by the third embodiment of the present invention; wherein, the precision of the analog-to-digital converter is set to 8 bits, and the first resistive array 10 is used to convert the first 3 bits of the output data. ; The first capacitive array 20 is used to convert the fourth and fifth bits of the output data; the second resistive array 30 is used to convert the last 3 bits of the output data. Of course, this is just a specific embodiment, and the number of digits occupied by each array can also be adjusted according to needs, and is not limited to this:
采样阶段:所述异步时钟发生器3输出第一使能信号CLK1至所述第一电容子阵列的第四开关单元,使所有第四开关子单元的第一端均选择接入所述输入电压Vin,以对所述输入电压Vin进行采样。Sampling stage: the asynchronous clock generator 3 outputs the first enable signal CLK1 to the fourth switch unit of the first capacitor sub-array, so that the first ends of all fourth switch sub-units are selectively connected to the input voltage Vin to sample the input voltage Vin.
量化阶段:首先完成对输出数据的前3位进行转换,接着完成对输出数据的第四位和第五位进行转换,然后完成对输出数据的后3位进行转换。各转换具体如下:Quantization stage: first complete the conversion of the first 3 bits of the output data, then complete the conversion of the fourth and fifth bits of the output data, and then complete the conversion of the last 3 bits of the output data. The details of each conversion are as follows:
对于对输出数据的前3位进行转换,其具体包括以下步骤:For converting the first 3 bits of output data, it specifically includes the following steps:
S1:所述逻辑控制模块4输出第一数字信号SW1至所述第一阻性阵列10、所述第二电容子阵列21、所述第二阻性阵列30,以使所述第一阻性阵列10对所述第一参考电压Vref进行分压,得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于1/2*所述第一参考电压Vref;还使所有第四开关子单元的第一端均选择所述第一阻性阵列10的第一输出端。S1: The logic control module 4 outputs the first digital signal SW1 to the first resistive array 10, the second capacitor sub-array 21, and the second resistive array 30, so that the first resistive The array 10 divides the first reference voltage Vref to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 1/2*the first reference voltage Vref; and all The first terminals of the fourth switch sub-units all select the first output terminal of the first resistive array 10 .
S2:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第一比较信号VP1是低电平还是高电平;若是低电平,则跳转至S31;若是高电平,则跳转至S41。S2: The comparator 2 compares according to the input voltage, and determines whether the first comparison signal VP1 output by the comparator 2 is low level or high level; if it is low level, jump to S31; if it is high level level, jump to S41.
S31:所述异步时钟发生器3根据低电平的所述第一比较信号VP1,输出第i时钟信号VALID1;所述第一逻辑控制模块4用于根据所述第i时钟信号VALID1和所述第二使能信号CLK2,输出第二数字信号SW2、第一输出信号D1;其中,此时所述第一输出信号D1为0,即所述第二数字信号的最高位为0。所述第一阻性阵列10根据第二数字信号SW2,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于1/4*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S31: The asynchronous clock generator 3 outputs the i-th clock signal VALID1 according to the low-level first comparison signal VP1; the first logic control module 4 is used to output the i-th clock signal VALID1 according to the i-th clock signal VALID1 and the The second enable signal CLK2 outputs a second digital signal SW2 and a first output signal D1; wherein, at this time, the first output signal D1 is 0, that is, the highest bit of the second digital signal is 0. The first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the second digital signal SW2 to obtain the second reference voltage Vref-L; wherein, the first The second reference voltage Vref-L is equal to 1/4*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S32:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第二比较信号VP2是低电平还是高电平;若是低电平,则跳转至S331;若是高电平,则跳转至S341。S32: The comparator 2 compares according to the input voltage, and determines whether the second comparison signal VP2 output by the comparator 2 is low level or high level; if it is low level, jump to S331; if it is high level level, jump to S341.
S331:所述异步时钟发生器3根据低电平的所述第二比较信号VP2,输出第二时钟信号VALID2;所述第一逻辑控制模块4用于根据所述第二时钟信号VALID2和所述第二使能信号CLK2,输出第三数字信号SW3、第二输出信号D2;其中,此时所述第二输出信号D2为0,即所述第二数字信号的第二位也为0。接着,所述第一阻性阵列10根据第三数字信号SW3,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于1/8*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S331: The asynchronous clock generator 3 outputs the second clock signal VALID2 according to the low-level second comparison signal VP2; the first logic control module 4 is used to output the second clock signal VALID2 according to the second clock signal VALID2 and the The second enable signal CLK2 outputs a third digital signal SW3 and a second output signal D2; wherein, at this time, the second output signal D2 is 0, that is, the second bit of the second digital signal is also 0. Next, the first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain the second reference voltage Vref-L; where, The second reference voltage Vref-L is equal to 1/8*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S332:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第三比较信号VP3是低电平还是高电平;若是低电平,则跳转至S3331;若是高电平,则跳转至S3341。S332: The comparator 2 compares according to the input voltage, and determines whether the third comparison signal VP3 output by the comparator 2 is low level or high level; if it is low level, jump to S3331; if it is high level level, jump to S3341.
S3331:所述异步时钟发生器3根据低电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为0,即所述第二数字信号的第三位仍为0。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于1/4*所述第一参考电压Vref。此时,所述第二数字信号的前三位为000。S3331: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the low-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is still 0. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 1/4*the The first reference voltage Vref. At this time, the first three digits of the second digital signal are 000.
S3341:所述异步时钟发生器3根据高电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为1,即所述第二数字信号的第三位为1。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于1/4*所述第一参考电压Vref。此时,所述第二数字信号的前三位为001。S3341: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the high-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 1/4*the The first reference voltage Vref. At this time, the first three digits of the second digital signal are 001.
S341:所述异步时钟发生器3根据高电平的所述第二比较信号VP2,输出第二时钟信号VALID2;所述第一逻辑控制模块4用于根据所述第二时钟信号VALID2和所述第二使能信号CLK2,输出第三数字信号SW3、第二输出信号D2;其中,此时所述第一输出信号D1为1,即所述第二数字信号的第二位为1。接着,所述第一阻性阵列10根据第三数字信号SW3,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于3/8*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S341: The asynchronous clock generator 3 outputs the second clock signal VALID2 according to the high-level second comparison signal VP2; the first logic control module 4 is used to output the second clock signal VALID2 according to the second clock signal VALID2 and the The second enable signal CLK2 outputs a third digital signal SW3 and a second output signal D2; where, at this time, the first output signal D1 is 1, that is, the second bit of the second digital signal is 1. Next, the first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain the second reference voltage Vref-L; where, The second reference voltage Vref-L is equal to 3/8*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S342:所述比较器2根据输入的电压进行比较,并通过所述比较器2判断所述第二参考电压Vref-L是否大于所述第三模拟电压;若是低电平,则跳转至S3431;若是高电平,则跳转至S3441。S342: The comparator 2 compares according to the input voltage, and determines whether the second reference voltage Vref-L is greater than the third analog voltage through the comparator 2; if it is low level, jump to S3431 ; If it is high level, jump to S3441.
S3431:所述异步时钟发生器3根据低电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为0,即所述第二数字信号的第三位为0。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于1/2*所述第一参考电压Vref此时,所述第二数字信号的前三位为010。S3431: The asynchronous clock generator 3 outputs the third clock signal VALID3 according to the low-level third comparison signal VP3; the first logic control module 4 is used to output the third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is 0. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 1/2*the At this time, the first three digits of the first reference voltage Vref of the second digital signal are 010.
S3441:所述异步时钟发生器3根据高电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为1,即所述第二数字信号的第三位为1。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于1/2*所述第一参考电压Vref此时,所述第二数字信号的前三位为011。S3441: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the high-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 1/2*the At this time, the first three digits of the first reference voltage Vref of the second digital signal are 011.
S41:所述异步时钟发生器3根据高电平的所述第一比较信号VP1,输出第i时钟信号VALID1;所述第一逻辑控制模块4用于根据所述第i时钟信号VALID1和所述第二使能信号CLK2,输出第二数字信号SW2、第一输出信号D1;其中,此时所述第一输出信号D1为1,即所述第二数字信号的最高位为1。所述第一阻性阵列10根据第二数字信号SW2,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于3/4*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S41: The asynchronous clock generator 3 outputs the i-th clock signal VALID1 according to the high-level first comparison signal VP1; the first logic control module 4 is used to output the i-th clock signal VALID1 according to the i-th clock signal VALID1 and the The second enable signal CLK2 outputs a second digital signal SW2 and a first output signal D1; wherein, at this time, the first output signal D1 is 1, that is, the highest bit of the second digital signal is 1. The first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the second digital signal SW2 to obtain the second reference voltage Vref-L; wherein, the first The second reference voltage Vref-L is equal to 3/4*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S42:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第二比较信号VP2是低电平还是高电平;若是低电平,则跳转至S431;若高电平,则跳转至S441。S42: The comparator 2 performs comparison according to the input voltage, and determines whether the second comparison signal VP2 output by the comparator 2 is low level or high level; if it is low level, jump to S431; if it is high level level, jump to S441.
S431:所述异步时钟发生器3根据低电平的所述第二比较信号VP2,输出第二时钟信号VALID2;所述第一逻辑控制模块4用于根据所述第二时钟信号VALID2和所述第二使能信号CLK2,输出第三数字信号SW3、第二输出信号D2;其中,此时所述第二输出信号D2为0,即所述第二数字信号的第二位为0。接着,所述第一阻性阵列10根据第三数字信号SW3,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于5/8*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S431: The asynchronous clock generator 3 outputs the second clock signal VALID2 according to the low-level second comparison signal VP2; the first logic control module 4 is used to output the second clock signal VALID2 according to the second clock signal VALID2 and the The second enable signal CLK2 outputs a third digital signal SW3 and a second output signal D2; wherein, at this time, the second output signal D2 is 0, that is, the second bit of the second digital signal is 0. Next, the first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain the second reference voltage Vref-L; where, The second reference voltage Vref-L is equal to 5/8*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S432:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第三比较信号VP3是低电平还是高电平;若是低电平,则跳转至S4331;若是高电平,则跳转至S4341。S432: The comparator 2 compares according to the input voltage, and determines whether the third comparison signal VP3 output by the comparator 2 is low level or high level; if it is low level, jump to S4331; if it is high level level, jump to S4341.
S4331:所述异步时钟发生器3根据低电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为0,即所述第二数字信号的第三位仍为0。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于3/4*所述第一参考电压Vref。此时,所述第二数字信号的前三位为100。S4331: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the low-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is still 0. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 3/4*the The first reference voltage Vref. At this time, the first three digits of the second digital signal are 100.
S4341:所述异步时钟发生器3根据高电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为1,即所述第二数字信号的第三位为1。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于3/4*所述第一参考电压Vref。此时,所述第二数字信号的前三位为101。S4341: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the high-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to 3/4*the The first reference voltage Vref. At this time, the first three digits of the second digital signal are 101.
S441:所述异步时钟发生器3根据高电平的所述第二比较信号VP2,输出第二时钟信号VALID2;所述第一逻辑控制模块4用于根据所述第二时钟信号VALID2和所述第二使能信号CLK2,输出第三数字信号SW3、第二输出信号D2;其中,此时所述第一输出信号D1为1,即所述第二数字信号的第二位为1。接着,所述第一阻性阵列10根据第三数字信号SW3,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第二参考电压Vref-L;其中,所述第二参考电压Vref-L等于7/8*所述第一参考电压Vref;所有第四开关子单元的第一端均仍选择所述第一阻性阵列10的第一输出端。S441: The asynchronous clock generator 3 outputs the second clock signal VALID2 according to the high-level second comparison signal VP2; the first logic control module 4 is used to output the second clock signal VALID2 according to the second clock signal VALID2 and the The second enable signal CLK2 outputs a third digital signal SW3 and a second output signal D2; where, at this time, the first output signal D1 is 1, that is, the second bit of the second digital signal is 1. Next, the first resistive array 10 adjusts the closing and opening of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain the second reference voltage Vref-L; where, The second reference voltage Vref-L is equal to 7/8*the first reference voltage Vref; the first terminals of all fourth switch subunits still select the first output terminal of the first resistive array 10 .
S442:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第三比较信号VP3是低电平还是高电平;若是低电平,则跳转至S4431;若是高电平,则跳转至S4441。S442: The comparator 2 compares according to the input voltage, and determines whether the third comparison signal VP3 output by the comparator 2 is low level or high level; if it is low level, jump to S4431; if it is high level level, jump to S4441.
S4431:所述异步时钟发生器3根据低电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为0,即所述第二数字信号的第三位为0。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于所述第一参考电压Vref。此时,所述第二数字信号的前三位为110。S4431: The asynchronous clock generator 3 outputs the third clock signal VALID3 according to the low-level third comparison signal VP3; the first logic control module 4 is used to output the third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is 0. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to the first reference voltage Vref. At this time, the first three digits of the second digital signal are 110.
S4441:所述异步时钟发生器3根据高电平的所述第三比较信号VP3,输出第三时钟信号VALID3;所述第一逻辑控制模块4用于根据所述第三时钟信号VALID3和所述第二使能信号CLK2,输出第四数字信号SW4、第三输出信号D3;其中,此时所述第三输出信号D3为1,即所述第二数字信号的第三位为1。其中,所述第三参考电压Vref-H等于1/8*所述第一参考电压Vref+所述第二参考电压Vref-L,即所述第三参考电压Vref-H等于所述第一参考电压Vref。此时,所述第二数字信号的前三位为111。S4441: The asynchronous clock generator 3 outputs a third clock signal VALID3 according to the high-level third comparison signal VP3; the first logic control module 4 is configured to output a third clock signal VALID3 according to the third clock signal VALID3 and the The second enable signal CLK2 outputs a fourth digital signal SW4 and a third output signal D3; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. Wherein, the third reference voltage Vref-H is equal to 1/8*the first reference voltage Vref+the second reference voltage Vref-L, that is, the third reference voltage Vref-H is equal to the first reference voltage Vref. At this time, the first three digits of the second digital signal are 111.
对于对输出数据的第四位和第五位进行转换,其具体包括以下步骤:For converting the fourth and fifth bits of the output data, it specifically includes the following steps:
S5:所述第二电容子阵列21中的第四开关单元根据所述第四数字信号SW4,调整对应所述第四开关子单元的第一端的选择。S5: The fourth switch unit in the second capacitor sub-array 21 adjusts the selection corresponding to the first end of the fourth switch sub-unit according to the fourth digital signal SW4.
S6:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第四比较信号VP4是低电平还是高电平;若是低电平,则跳转至S71;若是高电平,则跳转至S81。S6: The comparator 2 compares according to the input voltage, and determines whether the fourth comparison signal VP4 output by the comparator 2 is low level or high level; if it is low level, jump to S71; if it is high level level, jump to S81.
S71:所述异步时钟发生器3根据低电平的所述第四比较信号VP4,输出第四时钟信号VALID4;所述第一逻辑控制模块4用于根据所述第四时钟信号VALID4和所述第二使能信号CLK2,输出第五数字信号SW5、第四输出信号D4;其中,此时所述第四输出信号D4为0,即所述第二数字信号的第四位为0。所述第四开关单元根据第五数字信号SW5,调整对应所述第四开关子单元的第一端的选择。S71: The asynchronous clock generator 3 outputs a fourth clock signal VALID4 according to the low-level fourth comparison signal VP4; the first logic control module 4 is configured to output a fourth clock signal VALID4 according to the fourth clock signal VALID4 and the The second enable signal CLK2 outputs a fifth digital signal SW5 and a fourth output signal D4; wherein, at this time, the fourth output signal D4 is 0, that is, the fourth bit of the second digital signal is 0. The fourth switch unit adjusts the selection corresponding to the first end of the fourth switch subunit according to the fifth digital signal SW5.
S72:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第五比较信号VP5是低电平还是高电平;若是低电平,则跳转至S731;若是高电平,则跳转至S741。S72: The comparator 2 compares according to the input voltage, and determines whether the fifth comparison signal VP5 output by the comparator 2 is low level or high level; if it is low level, jump to S731; if it is high level level, jump to S741.
S731:所述异步时钟发生器3根据低电平的所述第五比较信号VP5,输出第五时钟信号VALID5;所述第一逻辑控制模块4用于根据所述第五时钟信号VALID5和所述第二使能信号CLK2,输出第六数字信号SW6、第五输出信号D5;其中,此时所述第五输出信号D5仍为0,即所述第二数字信号的第五位为0。此时,所述第二数字信号的第四,五位为00。S731: The asynchronous clock generator 3 outputs the fifth clock signal VALID5 according to the low-level fifth comparison signal VP5; the first logic control module 4 is used to output the fifth clock signal VALID5 according to the fifth clock signal VALID5 and the The second enable signal CLK2 outputs a sixth digital signal SW6 and a fifth output signal D5; wherein, at this time, the fifth output signal D5 is still 0, that is, the fifth bit of the second digital signal is 0. At this time, the fourth and fifth bits of the second digital signal are 00.
S741:所述异步时钟发生器3根据高电平的所述第五比较信号VP5,输出第五时钟信号VALID5;所述第一逻辑控制模块4用于根据所述第五时钟信号VALID5和所述第二使能信号CLK2,输出第六数字信号SW6、第五输出信号D5;其中,此时所述第五输出信号D5为1,即所述第二数字信号的第五位为1。此时,所述第二数字信号的第四,五位为01。S741: The asynchronous clock generator 3 outputs the fifth clock signal VALID5 according to the high-level fifth comparison signal VP5; the first logic control module 4 is used to output the fifth clock signal VALID5 according to the fifth clock signal VALID5 and the The second enable signal CLK2 outputs a sixth digital signal SW6 and a fifth output signal D5; wherein, at this time, the fifth output signal D5 is 1, that is, the fifth bit of the second digital signal is 1. At this time, the fourth and fifth bits of the second digital signal are 01.
S81:所述异步时钟发生器3根据高电平的所述第四比较信号VP4,输出第四时钟信号VALID4;所述第一逻辑控制模块4用于根据所述第四时钟信号VALID4和所述第二使能信号CLK2,输出第五数字信号SW5、第四输出信号D4;其中,此时所述第四输出信号D4为1,即所述第二数字信号的第四位为1。所述第四开关单元根据第五数字信号SW5,调整对应所述第四开关子单元的第一端的选择。S81: The asynchronous clock generator 3 outputs a fourth clock signal VALID4 according to the high-level fourth comparison signal VP4; the first logic control module 4 is configured to output a fourth clock signal VALID4 according to the fourth clock signal VALID4 and the The second enable signal CLK2 outputs a fifth digital signal SW5 and a fourth output signal D4; wherein, at this time, the fourth output signal D4 is 1, that is, the fourth bit of the second digital signal is 1. The fourth switch unit adjusts the selection corresponding to the first end of the fourth switch subunit according to the fifth digital signal SW5.
S82:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第五比较信号VP5是低电平还是高电平;若是低电平,则跳转至S831;若否,则跳转至S841。S82: The comparator 2 performs comparison according to the input voltage, and determines whether the fifth comparison signal VP5 output by the comparator 2 is low level or high level; if it is low level, jump to S831; if not , jump to S841.
S831:所述异步时钟发生器3根据低电平的所述第五比较信号VP5,输出第五时钟信号VALID5;所述第一逻辑控制模块4用于根据所述第五时钟信号VALID5和所述第二使能信号CLK2,输出第六数字信号SW6、第五输出信号D5;其中,此时所述第五输出信号D5为0,即所述第二数字信号的第五位为0。此时,所述第二数字信号的第四,五位为10。S831: The asynchronous clock generator 3 outputs the fifth clock signal VALID5 according to the low-level fifth comparison signal VP5; the first logic control module 4 is used to output the fifth clock signal VALID5 according to the fifth clock signal VALID5 and the The second enable signal CLK2 outputs a sixth digital signal SW6 and a fifth output signal D5; wherein, at this time, the fifth output signal D5 is 0, that is, the fifth bit of the second digital signal is 0. At this time, the fourth and fifth bits of the second digital signal are 10.
S841:所述异步时钟发生器3根据高电平的所述第五比较信号VP5,输出第五时钟信号VALID5;所述第一逻辑控制模块4用于根据所述第五时钟信号VALID5和所述第二使能信号CLK2,输出第六数字信号SW6、第五输出信号D5;其中,此时所述第五输出信号D5为1,即所述第二数字信号的第五位为1。此时,所述第二数字信号的第四,五位为11。S841: The asynchronous clock generator 3 outputs the fifth clock signal VALID5 according to the high-level fifth comparison signal VP5; the first logic control module 4 is used to output the fifth clock signal VALID5 according to the fifth clock signal VALID5 and the The second enable signal CLK2 outputs a sixth digital signal SW6 and a fifth output signal D5; wherein, at this time, the fifth output signal D5 is 1, that is, the fifth bit of the second digital signal is 1. At this time, the fourth and fifth bits of the second digital signal are 11.
对于对输出数据的后3位进行转换,其具体包括以下步骤:For converting the last 3 bits of the output data, it specifically includes the following steps:
S9:所述第二阻性阵列30根据第六数字信号SW6,调整所述第一开关单元11内第一开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S9: The second resistive array 30 adjusts the closing and opening of the first switch sub-unit in the first switch unit 11 according to the sixth digital signal SW6 to obtain the sixth reference voltage Vref-lsb, and outputs it to The first terminal of the first capacitor C0.
S10:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第六比较信号VP6是低电平还是高电平;若是低电平,则跳转至S111;若是高电平,则跳转至S121。S10: The comparator 2 compares according to the input voltage, and determines whether the sixth comparison signal VP6 output by the comparator 2 is low level or high level; if it is low level, jump to S111; if it is high level level, jump to S121.
S111:所述异步时钟发生器3根据低电平的所述第六比较信号VP6,输出第六时钟信号VALID6;所述第一逻辑控制模块4用于根据所述第六时钟信号VALID6和所述第二使能信号CLK2,输出第七数字信号SW7、第六输出信号D6;其中,此时所述第六输出信号D6为0,即所述第二数字信号的第六位为0。所述第二阻性阵列30根据第七数字信号SW7,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S111: The asynchronous clock generator 3 outputs the sixth clock signal VALID6 according to the low-level sixth comparison signal VP6; the first logic control module 4 is used to output the sixth clock signal VALID6 according to the sixth clock signal VALID6 and the The second enable signal CLK2 outputs a seventh digital signal SW7 and a sixth output signal D6; wherein, at this time, the sixth output signal D6 is 0, that is, the sixth bit of the second digital signal is 0. The second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the seventh digital signal SW7 to obtain the sixth reference voltage Vref-lsb, and outputs it to the the first terminal of the first capacitor C0.
S112:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第七比较信号VP7是低电平还是高电平;若是低电平,则跳转至S1131;若是高电平,则跳转至S1141。S112: The comparator 2 compares according to the input voltage, and determines whether the seventh comparison signal VP7 output by the comparator 2 is low level or high level; if it is low level, jump to S1131; if it is high level level, jump to S1141.
S1131:所述异步时钟发生器3根据低电平的所述第七比较信号VP7,输出第七时钟信号VALID7;所述第一逻辑控制模块4用于根据所述第七时钟信号VALID7和所述第二使能信号CLK2,输出第八数字信号SW8、第七输出信号D7;其中,此时所述第七输出信号D7为0,即所述第二数字信号的第七位也为0。接着,所述第二阻性阵列30根据第八数字信号SW8,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S1131: The asynchronous clock generator 3 outputs the seventh clock signal VALID7 according to the low-level seventh comparison signal VP7; the first logic control module 4 is used to output the seventh clock signal VALID7 according to the seventh clock signal VALID7 and the The second enable signal CLK2 outputs an eighth digital signal SW8 and a seventh output signal D7; wherein, at this time, the seventh output signal D7 is 0, that is, the seventh bit of the second digital signal is also 0. Next, the second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the eighth digital signal SW8 to obtain the sixth reference voltage Vref-lsb, and outputs it to The first terminal of the first capacitor C0.
S1132:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第八比较信号VP8是低电平还是高电平;若是低电平,则跳转至S11331;若是高电平,则跳转至S11341。S1132: The comparator 2 compares according to the input voltage, and determines whether the eighth comparison signal VP8 output by the comparator 2 is low level or high level; if it is low level, jump to S11331; if it is high level level, jump to S11341.
S11331:所述异步时钟发生器3根据低电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为0,即所述第二数字信号的第八位仍为0。此时,所述第二数字信号的后三位为000。S11331: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the low-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is still 0. At this time, the last three digits of the second digital signal are 000.
S11341:所述异步时钟发生器3根据高电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为1,即所述第二数字信号的第八位为1。此时,所述第二数字信号的后三位为001。S11341: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the high-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 1, that is, the eighth bit of the second digital signal is 1. At this time, the last three digits of the second digital signal are 001.
S1141:所述异步时钟发生器3根据高电平的所述第七比较信号VP7,输出第七时钟信号VALID7;所述第一逻辑控制模块4用于根据所述第七时钟信号VALID7和所述第二使能信号CLK2,输出第八数字信号SW8、第七输出信号D7;其中,此时所述第七输出信号D7为1,即所述第二数字信号的第七位也为1。接着,所述第二阻性阵列30根据第八数字信号SW8,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S1141: The asynchronous clock generator 3 outputs the seventh clock signal VALID7 according to the high-level seventh comparison signal VP7; the first logic control module 4 is used to output the seventh clock signal VALID7 according to the seventh clock signal VALID7 and the The second enable signal CLK2 outputs an eighth digital signal SW8 and a seventh output signal D7. At this time, the seventh output signal D7 is 1, that is, the seventh bit of the second digital signal is also 1. Next, the second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the eighth digital signal SW8 to obtain the sixth reference voltage Vref-lsb, and outputs it to The first terminal of the first capacitor C0.
S1142:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第八比较信号VP8是低电平还是高电平;若是低电平,则跳转至S11431;若是高电平,则跳转至S11441。S1142: The comparator 2 compares according to the input voltage, and determines whether the eighth comparison signal VP8 output by the comparator 2 is low level or high level; if it is low level, jump to S11431; if it is high level level, jump to S11441.
S11431:所述异步时钟发生器3根据低电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为0,即所述第二数字信号的第八位为0。此时,所述第二数字信号的后三位为010。S11431: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the low-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is 0. At this time, the last three digits of the second digital signal are 010.
S11441:所述异步时钟发生器3根据高电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为1,即所述第二数字信号的第八位为1。此时,所述第二数字信号的后三位为011。S11441: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the high-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 1, that is, the eighth bit of the second digital signal is 1. At this time, the last three digits of the second digital signal are 011.
S121:所述异步时钟发生器3根据高电平的所述第六比较信号VP6,输出第六时钟信号VALID6;所述第一逻辑控制模块4用于根据所述第六时钟信号VALID6和所述第二使能信号CLK2,输出第七数字信号SW7、第六输出信号D6;其中,此时所述第六输出信号D6为1,即所述第二数字信号的第六位为1。所述第二阻性阵列30根据第七数字信号SW7,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S121: The asynchronous clock generator 3 outputs the sixth clock signal VALID6 according to the high-level sixth comparison signal VP6; the first logic control module 4 is used to output the sixth clock signal VALID6 according to the sixth clock signal VALID6 and the The second enable signal CLK2 outputs a seventh digital signal SW7 and a sixth output signal D6; wherein, at this time, the sixth output signal D6 is 1, that is, the sixth bit of the second digital signal is 1. The second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the seventh digital signal SW7 to obtain the sixth reference voltage Vref-lsb, and outputs it to the the first terminal of the first capacitor C0.
S122:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第七比较信号VP7是低电平还是高电平;若是低电平,则跳转至S1231;若是高电平,则跳转至S1241。S122: The comparator 2 compares according to the input voltage, and determines whether the seventh comparison signal VP7 output by the comparator 2 is low level or high level; if it is low level, jump to S1231; if it is high level level, jump to S1241.
S1231:所述异步时钟发生器3根据低电平的所述第七比较信号VP7,输出第七时钟信号VALID7;所述第一逻辑控制模块4用于根据所述第七时钟信号VALID7和所述第二使能信号CLK2,输出第八数字信号SW8、第七输出信号D7;其中,此时所述第七输出信号D7为0,即所述第二数字信号的第七位也为0。接着,所述第二阻性阵列30根据第八数字信号SW8,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S1231: The asynchronous clock generator 3 outputs the seventh clock signal VALID7 according to the low-level seventh comparison signal VP7; the first logic control module 4 is used to output the seventh clock signal VALID7 according to the seventh clock signal VALID7 and the The second enable signal CLK2 outputs an eighth digital signal SW8 and a seventh output signal D7; wherein, at this time, the seventh output signal D7 is 0, that is, the seventh bit of the second digital signal is also 0. Next, the second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the eighth digital signal SW8 to obtain the sixth reference voltage Vref-lsb, and outputs it to The first terminal of the first capacitor C0.
S1232:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第八比较信号VP8是低电平还是高电平;若是低电平,则跳转至S12331;若是高电平,则跳转至S12341。S1232: The comparator 2 compares according to the input voltage, and determines whether the eighth comparison signal VP8 output by the comparator 2 is low level or high level; if it is low level, jump to S12331; if it is high level level, jump to S12341.
S12331:所述异步时钟发生器3根据低电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为0,即所述第二数字信号的第八位仍为0。此时,所述第二数字信号的后三位为100。S12331: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the low-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is still 0. At this time, the last three digits of the second digital signal are 100.
S12341:所述异步时钟发生器3根据高电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为1,即所述第二数字信号的第八位为1。此时,所述第二数字信号的后三位为101。S12341: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the high-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 1, that is, the eighth bit of the second digital signal is 1. At this time, the last three digits of the second digital signal are 101.
S1241:所述异步时钟发生器3根据高电平的所述第七比较信号VP7,输出第七时钟信号VALID7;所述第一逻辑控制模块4用于根据所述第七时钟信号VALID7和所述第二使能信号CLK2,输出第八数字信号SW8、第七输出信号D7;其中,此时所述第七输出信号D7为1,即所述第二数字信号的第七位也为1。接着,所述第二阻性阵列30根据第八数字信号SW8,调整所述第三开关单元31内第三开关子单元的闭合和断开,以得到第六参考电压Vref-lsb,并输出至所述第一电容器C0的第一端。S1241: The asynchronous clock generator 3 outputs the seventh clock signal VALID7 according to the high-level seventh comparison signal VP7; the first logic control module 4 is used to output the seventh clock signal VALID7 according to the seventh clock signal VALID7 and the The second enable signal CLK2 outputs an eighth digital signal SW8 and a seventh output signal D7. At this time, the seventh output signal D7 is 1, that is, the seventh bit of the second digital signal is also 1. Next, the second resistive array 30 adjusts the closing and opening of the third switch sub-unit in the third switch unit 31 according to the eighth digital signal SW8 to obtain the sixth reference voltage Vref-lsb, and outputs it to The first terminal of the first capacitor C0.
S1242:所述比较器2根据输入的电压进行比较,并判断所述比较器2输出的第八比较信号VP8是低电平还是高电平;若是低电平,则跳转至S12431;若是高电平,则跳转至S11441。S1242: The comparator 2 compares according to the input voltage, and determines whether the eighth comparison signal VP8 output by the comparator 2 is low level or high level; if it is low level, jump to S12431; if it is high level level, jump to S11441.
S12431:所述异步时钟发生器3根据低电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为0,即所述第二数字信号的第八位为0。此时,所述第二数字信号的后三位为110。S12431: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the low-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is 0. At this time, the last three digits of the second digital signal are 110.
S12441:所述异步时钟发生器3根据高电平的所述第八比较信号VP8,输出第八时钟信号VALID8;所述第一逻辑控制模块4用于根据所述第八时钟信号VALID8和所述第二使能信号CLK2,第八输出信号D8;其中,此时所述第八输出信号D8为1,即所述第二数字信号的第八位为1。此时,所述第二数字信号的后三位为111。S12441: The asynchronous clock generator 3 outputs the eighth clock signal VALID8 according to the high-level eighth comparison signal VP8; the first logic control module 4 is used to output the eighth clock signal VALID8 according to the eighth clock signal VALID8 and the The second enable signal CLK2 and the eighth output signal D8; at this time, the eighth output signal D8 is 1, that is, the eighth bit of the second digital signal is 1. At this time, the last three digits of the second digital signal are 111.
需要说明的是,在上述所述模数转换器的比较过程中,为了说明的方便对不同时间的比较信号、时钟信号、数字信号进行了区分,其中,第一比较信号VP1至第八比较信号VP8体现的只是比较信号的数值在不同时间发生了变化;第一时钟信号VALID1至第八时钟信号VALID8体现的只是时钟信号的数值在不同时间发生了变化;第一数字信号SW1至第八数字信号SW8体现的只是数字信号的数值在不同时间发生了变化。It should be noted that in the above comparison process of the analog-to-digital converter, comparison signals, clock signals, and digital signals at different times are distinguished for the convenience of explanation. Among them, the first comparison signal VP1 to the eighth comparison signal VP8 only reflects that the value of the comparison signal changes at different times; the first clock signal VALID1 to the eighth clock signal VALID8 only reflects that the value of the clock signal changes at different times; the first digital signal SW1 to the eighth digital signal SW8 only reflects that the value of the digital signal changes at different times.
以下对本发明第三实施例提供的模数转换器的其他结构进行说明:Other structures of the analog-to-digital converter provided by the third embodiment of the present invention are described below:
作为一种具体实施方式,所述比较器2、所述异步时钟发生器3、所述逻辑控制模块4均为本领域的惯用技术手段,在此不再对所述比较器2、所述异步时钟发生器3、所述逻辑控制模块4的内部结构进行赘述。As a specific implementation manner, the comparator 2, the asynchronous clock generator 3, and the logic control module 4 are all conventional technical means in this field, and the comparator 2, the asynchronous clock generator 3, and the asynchronous clock generator 3 are no longer discussed here. The internal structures of the clock generator 3 and the logic control module 4 will be described in detail below.
作为一种具体实施方式,所述第四参考电压Vref-l具体为所述第二参考电压Vref-L输入缓冲器后的输出电压。所述第五参考电压Vref-h具体为所述第三参考电压Vref-H输入缓冲器后的输出电压。其具有的有益效果为:防止因2M个串联连接的第一阻性单元R1和2J个串联连接的第二阻性单元R2形成电阻分压,而影响所述第一阻性阵列10和所述第二阻性阵列30产生所述第二参考电压Vref-L、第三参考电压Vref-H、第六参考电压Vref-lsb的精确度。其中,所述缓冲器具体为电压缓冲器。As a specific implementation manner, the fourth reference voltage Vref-l is specifically the output voltage after the second reference voltage Vref-L is input into the buffer. The fifth reference voltage Vref-h is specifically the output voltage after the third reference voltage Vref-H is input into the buffer. It has the beneficial effect of preventing the first resistive array 10 and the first resistive array 10 from being affected by the resistive voltage division caused by the 2M series-connected first resistive units R1 and the 2J series-connected second resistive units R2. The second resistive array 30 generates the second reference voltage Vref-L, the third reference voltage Vref-H, and the sixth reference voltage Vref-lsb with the accuracy. Wherein, the buffer is specifically a voltage buffer.
本发明第四实施例提供了一种电子设备,包括本发明第三实施例提供的模数转换器。The fourth embodiment of the present invention provides an electronic device, including the analog-to-digital converter provided by the third embodiment of the present invention.
最后应说明的是:以上各实施例仅用以说明本发明的技术方案而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present invention. .
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