CN117498867A

CN117498867A - Digital-to-analog conversion circuit, control method, analog-to-digital converter and electronic equipment

Info

Publication number: CN117498867A
Application number: CN202311514936.1A
Authority: CN
Inventors: 王旭茂
Original assignee: Shanghai Qinqian Semiconductor Technology Co ltd
Current assignee: Shanghai Qinqian Semiconductor Technology Co ltd
Priority date: 2023-11-14
Filing date: 2023-11-14
Publication date: 2024-02-02

Abstract

The invention provides a digital-to-analog conversion circuit, a control method, an analog-to-digital converter and electronic equipment, wherein the digital-to-analog conversion circuit comprises a first resistive array, a second reference voltage and a third reference voltage, wherein the first resistive array is configured to selectively divide a first reference voltage in response to high M-bit digital data of a first digital signal so as to output the second reference voltage and the third reference voltage; a second resistive array configured to selectively divide a difference between the fifth reference voltage and the fourth reference voltage in response to low J-bit digital data of the first digital signal to output a sixth reference voltage; a first capacitive array comprising a first capacitor and a second capacitive sub-array configured to selectively output a second analog voltage based on the second reference voltage or the third reference voltage in response to medium N-J-bit digital data of a first digital signal; compared with a C-R mixed digital-to-analog conversion circuit or an R-C mixed digital-to-analog conversion circuit, the digital-to-analog conversion circuit has better area optimization and smaller precision requirement.

Description

Digital-to-analog conversion circuit, control method, analog-to-digital converter and electronic equipment

Technical Field

The invention relates to the field of digital-to-analog conversion circuits, in particular to a digital-to-analog conversion circuit, a control method, an analog-to-digital converter and electronic equipment

Background

Successive approximation register analog-to-digital converters (also known as SAR ADCs) are divided into charge redistribution, voltage scaling and mixed structure types according to different types of digital-to-analog converters (DACs); if the digital-to-analog converter is composed of a pure resistor array, the SAR ADC corresponds to voltage equal-scale scaling; if the digital-to-analog converter is formed by a pure capacitor array, the SAR ADC is correspondingly provided with charge redistribution; if the digital-to-analog converter is composed of a resistor array and a capacitor array, respectively, the SAR ADC is correspondingly hybrid. Among them, the hybrid SAR ADC is also generally classified into a C-R hybrid type and an R-C hybrid type, which is different in that a high Mbit is implemented by a capacitor array or by a resistor array.

However, as the number of bits of the SAR ADC increases, namely the precision requirement is improved, for the charge redistribution type, the capacitance value of the capacitor in the capacitor array increases exponentially, and the requirement for capacitor matching is increased; for the voltage scaling type, the number of resistors in the resistor array is also exponentially increased, so that the circuit area is increased. Compared with the charge redistribution SAR ADC and the voltage equal-proportion scaling SAR ADC, the hybrid SAR ADC can greatly reduce the capacitance matching problem and the circuit area problem caused by the increase of the number of bits, thereby improving the conversion precision of the SAR ADC to a certain extent and reducing the circuit cost.

Taking charge redistribution type SAR ADC and C-R mixed SAR ADC as examples, the following description is given:

the principle is as follows: for an N-bit charge redistribution SAR ADC, it is assumed that the unit capacitance C obeys a normal distribution with a mean value of C0 and a standard deviation of σ. Then the N capacitors connected in parallel will obey a mean value of NC0 and a standard deviation of NC0Is a normal distribution of (c). And defining that the error caused by the mismatch of the capacitor is smaller than 1/2LSB, and the corresponding requirement is as shown in formula (1):

where Cmsb represents the highest capacitance and Ctotal represents the total capacitance.

Expanding the above formula to obtain formula (2):

considering the extreme case, the capacitance deviation of the highest order is positive, and the rest is negative. The above can be put into the formula (3):

wherein, the formula (3) is used for representing the matching precision of the digital-to-analog converter.

For an N-bit C-R hybrid SAR ADC, a high Mbit is set, and the remaining (N-M) bits are implemented by a resistor array. The matching precision corresponding to the capacitor array can be obtained according to the reasoning mode as formula (4):

for the resistor array, only the matching precision of (N-M) bit is required to be met, and the matching precision corresponding to the resistor array can be obtained as formula (5) assuming that the resistor R accords with normal distribution with the mean value of R and the standard deviation of sigma:

by comparing equation (5) with equation (4) to equation (3), it can be seen that the accuracy requirements of the C-R hybrid SAR ADC are significantly lower than those of the charge redistribution SAR ADC. The analysis of the voltage-scaling SAR ADC is similar to that of the charge redistribution SAR ADC and will not be described in detail herein. However, the problems of the C-R or R-C hybrid SAR ADC are: with further improvement of the SAR ADC precision requirement, the capacitance value of the capacitor array and the number of resistors of the resistor array still increase exponentially, and the capacitor matching problem and the circuit area problem still face.

Disclosure of Invention

In order to solve the above problems, the present invention provides a digital-to-analog conversion circuit, a control method, an analog-to-digital converter and an electronic device.

According to a first aspect of the present invention, there is provided a digital-to-analog conversion circuit for converting a first digital signal of N bits into a corresponding first analog voltage; the capacitive array comprises a first resistive array, a first capacitor array and a second resistive array;

the first end of the first resistive array is grounded, and the second end of the first resistive array is connected with a first reference voltage; the first resistive array is configured to selectively divide the first reference voltage in response to high M-bit digital data of the first digital signal such that a first output terminal and a second output terminal of the first resistive array output a second reference voltage and a third reference voltage, respectively; wherein the second reference voltage and the third reference voltage each comprise 2 ^M A stage voltage, and the second reference voltage is less than the third reference voltage;

the first end of the second resistive array is connected with a fourth reference voltage, and the second end of the second resistive array is connected with a fifth reference voltage; the second resistive array is configured to selectively divide a first voltage in response to low J-bit digital data of the first digital signal such that an output of the second resistive array outputs a sixth reference voltage; wherein the sixth reference voltage comprises 2 ^J A stage voltage; the first voltage is the difference between a fourth reference voltage obtained by buffering the second reference voltage and a fifth reference voltage obtained by buffering the third reference voltage;

the first capacitor array comprises a first capacitor and a second capacitor sub-array, the second capacitor sub-array comprises N-M-J second capacitors which are sequentially arranged from low order to high order, and the capacitance value of an ith second capacitor in the second capacitor sub-array meets the following conditions: ci=2 ^i-1 C0; wherein, C0 is the capacitance value of the first capacitor; a first end of the first capacitor is connected with the sixth reference voltage, and a second end of the first capacitor is coupled to an output end of the second capacitor subarray; wherein,

the input of the second capacitor subarray is used for sampling input voltage, and the second capacitor subarray is configured to:

selectively outputting a second analog voltage matching the N-J-bit digital data in the first digital signal based on the second reference voltage or the third reference voltage in response to any one of the N-J-bit digital data in the first digital signal;

wherein after the first capacitor receives the sixth reference voltage, the first capacitor array outputs a third analog voltage that matches the sixth reference voltage;

Wherein the first analog voltage is a weighted sum of the second analog voltage and the third analog voltage; wherein N, M, J, i is a positive integer, M, J is more than or equal to 1, and M+J is less than N; i is more than or equal to 1 and less than or equal to N-M-J.

Optionally, the first resistive array includes 2M first resistive units, a first switching unit, and a second switching unit connected in series;

a first end of a first resistive element is used as a first end of the first resistive array, and a second end of a second M first resistive elements is used as a second end of the first resistive array;

the first switch unit comprises 2M first switch subunits, and second ends of all the first switch subunits are coupled to first output ends of the first resistive array; each first switch subunit corresponds to a first resistive unit, and a first end of each first switch subunit is coupled to a first end of the corresponding first resistive unit; the first switching unit is configured to selectively divide the first reference voltage in response to high M-bit digital data of the first digital signal to output the second reference voltage;

the second switch unit comprises 2M second switch subunits, and second ends of all the second switch subunits are coupled to second output ends of the first resistive array; each second switch subunit corresponds to one first resistive unit, and the first end of each second switch subunit is coupled to the second end of the corresponding first resistive unit; the second switching unit is configured to selectively divide the first reference voltage to output the third reference voltage in response to high M-bit digital data of the first digital signal.

Optionally, the second resistive array includes 2J second resistive units and third switching units connected in series;

a first end of a first second resistive element is used as a first end of the first resistive array, and a second end of a second J second resistive elements is used as a second end of the second resistive array;

the third switch unit comprises 2J third switch subunits, and second ends of all the third switch subunits are coupled to the output ends of the second resistive array; each third switch subunit corresponds to a second resistive unit, and the first end of each third switch subunit is coupled to the first end of the corresponding second resistive unit; the third switching unit is configured to selectively divide the first voltage to output the sixth reference voltage in response to low J-bit digital data of the first digital signal.

Optionally, the first resistive element and the second resistive element each comprise a single resistor.

Optionally, the first resistive element and the second resistive element each comprise a resistive network; the resistor network is formed by connecting a plurality of resistors in series and parallel.

Optionally, the first switch subunit, the second switch subunit, and the third switch subunit each include a single pole single throw switch.

Optionally, the second capacitor subarray further includes a fourth switch unit;

the fourth switch unit comprises N-M-J fourth switch subunits; each fourth switch subunit corresponds to one second capacitor; a first end of each fourth switch subunit is coupled to an input end of a corresponding second capacitor; wherein the fourth switching unit is configured to: accessing the input voltage;

and responding to the N-J bit digital data in the first digital signal, so that the first end of each fourth switch subunit correspondingly selects the first output end of the first resistive array or the second output end of the first resistive array.

Optionally, the fourth switch subunit includes a single pole, triple throw switch.

According to a second aspect of the present invention, there is provided a method of controlling a digital to analog conversion circuit, for controlling the digital to analog conversion circuit provided in the first aspect and the optional aspects of the present invention, the method comprising:

according to the high M-bit digital data of the first digital signal, controlling the first resistive array to selectively divide the first reference voltage so that the first resistive array outputs a second reference voltage and a third reference voltage respectively; wherein the second reference voltage and the third reference voltage each comprise 2 ^M A stage voltage, and the second reference voltage is less than the third reference voltage;

controlling the second resistive array to selectively divide a first voltage according to low J-bit digital data of the first digital signal, so that the second resistive array outputs a sixth reference voltage; wherein the sixth reference voltage comprises 2 ^J A stage voltage; the first voltage is the difference between a fourth reference voltage obtained by buffering the second reference voltage and a fifth reference voltage obtained by buffering the third reference voltage;

controlling the second capacitor subarray to selectively output a second analog voltage matched with the N-J-bit digital data in the first digital signal based on the second reference voltage or the third reference voltage according to any one bit of the N-J-bit digital data in the first digital signal;

according to the received heating of the sixth reference voltage, the first capacitor array outputs a third analog voltage matched with the sixth reference voltage;

wherein the first analog voltage is equal to a weighted sum of the second analog voltage and the third analog voltage; n, M, J, i are positive integers, M, J is more than or equal to 1, and M+J is less than N; i is more than or equal to 1 and less than or equal to N-M-J.

According to a third aspect of the present invention, there is provided an analog-to-digital converter for converting the input voltage into a second digital signal of N bits, comprising a comparator, an asynchronous clock generator, a logic control module, a digital-to-analog conversion circuit provided by the first aspect and alternatives of the present invention;

the input end of the second capacitor subarray is connected with the input voltage, and the output end of the first capacitor array is coupled to the first input end of the comparator; the second input end of the comparator is grounded, and the output end of the comparator is coupled to the asynchronous clock generator; the output end of the asynchronous clock generator is coupled to the logic control module; the output end of the logic control module is respectively coupled to the first resistive array, the first capacitor array and the second resistive array;

the second capacitor subarray is used for sampling the input voltage which is accessed in a first time according to a first enabling signal; the logic control module is used for outputting an ith digital signal to the first resistive array, the second capacitor subarray and the second resistive array so as to obtain an ith analog voltage; the comparator is used for comparing the ith analog voltage with the third analog voltage and outputting an ith comparison signal; the asynchronous clock generator is used for outputting an ith clock signal according to the ith comparison signal and the first enabling signal; the logic control module is also used for outputting an (i+1) th digital signal and an (i) th output signal according to the (i) th clock signal and the second enabling signal; wherein i is a positive integer, and i is more than or equal to 1 and less than or equal to N; the second enable signal is an inverted signal of the first enable signal; the ith output signal is used as the ith bit number finally output by the analog-to-digital converter.

According to a fourth aspect of the present invention there is provided an electronic device comprising the analogue to digital converter provided by the third aspect of the present invention.

The digital-to-analog conversion circuit provided by the invention consists of the first resistive array, the first capacitor array and the second resistive array, and compared with the C-R mixed digital-to-analog conversion circuit or the R-C mixed digital-to-analog conversion circuit in the prior art, the digital-to-analog conversion circuit has better area optimization and smaller precision requirements for the high-precision SAR ADC.

Drawings

The invention will be described in further detail with reference to the drawings and the detailed description.

Fig. 1 is a circuit configuration diagram of a digital-to-analog conversion circuit according to a first embodiment of the present invention;

fig. 2 is a second circuit configuration diagram of a digital-to-analog conversion circuit according to the first embodiment of the present invention;

fig. 3 is a circuit configuration diagram III of a digital-to-analog conversion circuit according to a first embodiment of the present invention;

fig. 4 is a circuit configuration diagram of an analog-to-digital converter according to a third embodiment of the present invention;

FIG. 5 is a differential non-linear diagram of an analog-to-digital converter according to a third embodiment of the present invention;

FIG. 6 is an integrated nonlinear diagram of an analog-to-digital converter according to a third embodiment of the present invention;

fig. 7 is an FFT analysis chart of an analog-to-digital converter according to a third embodiment of the present invention.

Reference numerals:

1-a digital-to-analog conversion circuit;

a 2-comparator;

a 3-asynchronous clock generator;

4-logic control module;

10-a first resistive array;

11-a first switching unit;

12-a second switching unit;

20-a first capacitor array;

21-a second capacitor subarray;

30-a second resistive array;

31-a third switching unit;

r1-a first resistive element;

r2-a second resistive element;

vref—a first reference voltage;

Vref-H-the third reference voltage;

Vref-L-a second reference voltage;

vref-h-the fifth reference voltage;

vref-l-fourth reference voltage;

vref-lsb-sixth reference voltage;

vin-input voltage;

output of Vout-second capacitor subarray;

c0-a first capacitor;

SWi-first digital signal;

CLK 1-a first enable signal;

CLK 2-a second enable signal;

VPi-ith comparison signal;

di-output signal;

valid-i clock signal.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1, a digital-to-analog conversion circuit is provided in a first embodiment of the present invention, which is configured to convert a first digital signal with N bits into a corresponding first analog voltage, and includes a first resistive array 10, a first capacitor array 20, and a second resistive array 30;

the first end of the first resistive array 10 is grounded, and the second end of the first resistive array is connected with a first reference voltage Vref; the first resistive array 10 is configured to respond to high M bits of digital data of the first digital signalSelectively dividing the first reference voltage Vref so that a first output terminal and a second output terminal of the first resistive array 10 output a second reference voltage Vref-L and a third reference voltage Vref-H, respectively; wherein the second reference voltage Vref-L and the third reference voltage Vref-H each comprise 2 ^M A stage voltage, and the second reference voltage Vref-L is less than the third reference voltage Vref-H;

the first end of the second resistive array 30 is connected with a fourth reference voltage Vref-l, and the second end is connected with a fifth reference voltage Vref-h; the second resistive array 30 is configured to selectively divide a first voltage in response to low J-bit digital data of the first digital signal such that an output of the second resistive array 30 outputs a sixth reference voltage Vref-lsb; wherein the sixth reference voltage Vref-lsb comprises 2 ^J A stage voltage; the first voltage is the difference between a fourth reference voltage Vref-L obtained by buffering the second reference voltage Vref-L and a fifth reference voltage Vref-H obtained by buffering the third reference voltage Vref-H;

the fourth reference voltage Vref-L is the voltage outputted after the second reference voltage Vref-L is buffered, and the fifth reference voltage Vref-H is the voltage outputted after the third reference voltage Vref-H is buffered;

the first capacitor array 20 includes a first capacitor C0 and a second capacitor sub-array 21, the second capacitor sub-array 21 includes N-M-J second capacitors sequentially arranged from a lower position to a higher position, and a capacitance value of an ith second capacitor in the second capacitor sub-array 21 satisfies:

Ci＝2 ^i-1 c0; wherein C0 is the capacitance value of the first capacitor C0;

a first end of the first capacitor C0 is connected to the sixth reference voltage Vref-lsb, and a second end of the first capacitor C0 is coupled to the output terminal Vout of the second capacitor sub-array 21; wherein,

the input terminal of the second capacitor subarray 21 is used for sampling the input voltage Vin, and the second capacitor subarray 21 is configured to:

selectively outputting a second analog voltage matched to the N-J-bit digital data in the first digital signal based on the second reference voltage Vref-L or the third reference voltage Vref-H in response to any one of the N-J-bit digital data in the first digital signal;

Wherein, after the first capacitor receives the sixth reference voltage Vref-lsb, the first capacitor array 20 outputs a third analog voltage matching the sixth reference voltage Vref-lsb;

According to the first embodiment of the invention, compared with the C-R mixed digital-to-analog conversion circuit or the R-C mixed digital-to-analog conversion circuit in the prior art, the method has better area optimization and smaller precision requirements. The principle is as follows: the high M bits of the SAR ADC with N bits are all realized by the first resistive array 10 provided by the first embodiment of the present invention, the middle N-M-J bits are all realized by the first capacitive array 20 provided by the first embodiment of the present invention, and the remaining J bits are all realized by the second resistive array 30 provided by the first embodiment of the present invention, which can be obtained according to the extreme analysis mentioned in the background: the precision requirement for the first resistive unit R1, the precision requirement for the first capacitive unit, and the precision requirement for the second resistive unit R2 are respectively formula (6), formula (7), and formula (8):

As can be seen from comparing the formulas (6) to (8) with the formulas (4) and (5) mentioned in the background art, the digital-to-analog conversion circuit provided in the first embodiment of the present invention has smaller accuracy requirements than the existing C-R hybrid digital-to-analog conversion circuit. The comparison of the R-C hybrid digital-to-analog conversion circuit and the first embodiment of the present invention is similar to the comparison method and result described above, and will not be described herein.

For area optimization, the principle is as follows: for the C-R hybrid digital-to-analog conversion circuit, the high 4bit is realized by a capacitor array, and the low 4bit is realized by a resistor array, so that 4 capacitors are needed by the capacitor array, and 24 resistors are needed by the resistor array. For the digital-to-analog conversion circuit provided in the first embodiment of the present invention, the selection of the high 2bit is realized by the first resistive array 10, the middle 4bit is realized by the first capacitive array 20, and the low 2bit is realized by the second resistive array 30, so that the first capacitive array 20 needs 4 capacitors, and the total of the first resistive array 10 and the second resistive array 30 needs only 8 resistors. Compared with a C-R hybrid digital-to-analog conversion circuit, the digital-to-analog conversion circuit provided by the first embodiment of the invention has smaller circuit area under the same precision requirement, achieves better area optimization, and has more remarkable area optimization effect along with the continuous improvement of the precision requirement. Of course, the number of bits of each of the first resistive array 10, the first capacitor array 20, and the second resistive array 30 may be compromised by the actual process of capacitance and resistance in the circuit, and the actual area of the circuit, which is not limited herein.

Referring to fig. 1, it should be added that the second capacitor sub-array 21 according to the first embodiment of the present invention samples the input voltage Vin through the bottom plate of the capacitor, and can avoid the problem caused by the charge injection during the sampling process compared to the prior art that the input voltage Vin is typically sampled through the top plate of the capacitor.

The internal circuit structure of the digital-to-analog conversion circuit is described below:

referring to fig. 2, as a specific embodiment, the first resistive array 10 includes 2M first resistive units R1, first switch units 11, and second switch units 12 connected in series;

a first end of the first resistive unit R1 is used as a first end of the first resistive array 10, and a second end of the second M first resistive units R1 is used as a second end of the first resistive array 10;

the first switch unit 11 includes 2M first switch sub-units, and second ends of all the first switch sub-units are coupled to a first output end of the first resistive array 10; each first switch subunit corresponds to a first resistive unit R1, and a first end of each first switch subunit is coupled to a first end of the corresponding first resistive unit R1; the first switching unit 11 is configured to selectively divide the first reference voltage Vref in response to high M-bit digital data of the first digital signal to output the second reference voltage Vref-L;

The second switch unit 12 includes 2M second switch sub-units, and second ends of all the second switch sub-units are coupled to the second output end of the first resistive array 10; each second switch subunit corresponds to one first resistive unit R1, and a first end of each second switch subunit is coupled to a second end of the corresponding first resistive unit R1; the second switching unit 12 is configured to selectively divide the first reference voltage Vref in response to high M-bit digital data of the first digital signal to output the third reference voltage Vref-H.

Referring to fig. 3, as a specific embodiment, the second resistive array 30 includes 2J second resistive units R2 and third switching units 31 connected in series;

a first end of the first second resistive unit R2 is used as a first end of the first resistive array 10, and a second end of the second J second resistive units R2 is used as a second end of the second resistive array 30;

the third switch unit 31 comprises 2J third switch sub-units, and second ends of all third switch sub-units are coupled to the output end of the second resistive array 30; each third switch subunit corresponds to a second resistive unit R2, and a first end of each third switch subunit is coupled to a first end of the corresponding second resistive unit R2; the third switching unit 31 is configured to selectively divide the first voltage in response to low J-bit digital data of the first digital signal to output the sixth reference voltage Vref-lsb.

As a specific embodiment, the first resistive unit R1 and the second resistive unit R2 each include a single resistor. Of course, the first resistive unit R1 and the second resistive unit R2 each comprise a resistive network; the resistor network is formed by connecting a plurality of resistors in series and parallel. The specific circuit structure may be selected according to actual requirements, and is not limited herein.

As a specific embodiment, the first switch subunit, the second switch subunit, and the third switch subunit each include a single pole single throw switch.

Referring to fig. 3, as a specific embodiment, the second capacitor sub-array 21 further includes a fourth switch unit;

the fourth switch unit comprises N-M-J fourth switch subunits; each fourth switch subunit corresponds to one second capacitor; a first end of each fourth switch subunit is coupled to an input end of a corresponding second capacitor; the fourth switching unit is configured to: accessing the input voltage Vin;

in response to the N-J bit digital data in the first digital signal, a first terminal of each of the fourth switch sub-units is correspondingly selected to either the first output terminal of the first resistive array 10 or the second output terminal of the first resistive array 20.

As a specific embodiment, the fourth switch subunit comprises a single pole, triple throw switch.

A second embodiment of the present invention provides a control method for a digital-to-analog conversion circuit, for controlling the digital-to-analog conversion circuit provided in the first embodiment of the present invention, including:

controlling the first resistive array to selectively divide the first reference voltage according to the high M-bit digital data of the first digital signal so thatThe first resistive array outputs a second reference voltage and a third reference voltage respectively; wherein the second reference voltage and the third reference voltage each comprise 2 ^M A stage voltage, and the second reference voltage is less than the third reference voltage;

according to the received heating of the sixth reference voltage, the first capacitor array outputs a third analog voltage matched with the sixth reference voltage; wherein the first analog voltage is equal to a weighted sum of the second analog voltage and the third analog voltage; n, M, J, i are positive integers, M, J is more than or equal to 1, and M+J is less than N; i is more than or equal to 1 and less than or equal to N-M-J.

Referring to fig. 4, a third embodiment of the present invention provides an analog-to-digital converter for converting the input voltage into a second digital signal with N bits, which includes a comparator 2, an asynchronous clock generator 3, a logic control module 4, and the digital-to-analog conversion circuit 1 provided by the first embodiment of the present invention;

the input end of the second capacitor sub-array 21 is connected to the input voltage, and the output end of the first capacitor array 20 is coupled to the first input end of the comparator 2; a second input terminal of the comparator 2 is grounded, and an output terminal of the comparator 2 is coupled to the asynchronous clock generator 3; the output end of the asynchronous clock generator 3 is coupled to the logic control module 4; the output end of the logic control module 4 is coupled to the first resistive array 10, the first capacitor array 20 and the second resistive array 30 respectively;

Wherein the second capacitor sub-array 21 is configured to sample the input voltage according to a first enable signal CLK1 at a first time; the logic control module 4 is configured to output an ith digital signal SWi to the first resistive array 10, the second capacitor sub-array 21, and the second resistive array 30 to obtain an ith analog voltage; the comparator 2 is configured to compare the ith analog voltage with the third analog voltage and output an ith comparison signal VP; the asynchronous clock generator 3 is configured to output an ith clock signal VALID according to the ith comparison signal VP and the first enable signal CLK 1; the logic control module 4 is further configured to output an i+1th digital signal SWi and an i output signal Di according to the i clock signal VALID and the second enable signal CLK 2; wherein i is a positive integer, and i is more than or equal to 1 and less than or equal to N; the second enable signal CLK2 is an inverted signal of the first enable signal CLK 1; the ith output signal DiDI is used as the ith bit number finally output by the analog-to-digital converter.

Referring to fig. 5, 6 and 7, fig. 5 is a Differential Non-linear diagram (DNL-Differential Non-linear) of an analog-to-digital converter according to a third embodiment of the present invention, fig. 6 is an Integral Non-linear diagram (INL-Integral Non-linear) of an analog-to-digital converter according to a third embodiment of the present invention, and fig. 5 and 6 show that the Differential Non-linear value of the analog-to-digital converter according to the third embodiment of the present invention is 0.034LSB and the Integral Non-linear value is 0.073LSB. It should be noted that, in the analog-to-digital converter, the smaller the differential nonlinear value and the integral nonlinear value are, the better. FIG. 7 is a diagram showing an FFT analysis of an analog-to-digital converter according to a third embodiment of the present invention; the input signal of the analog-to-digital converter is 100k, the sampling point number is 4096, and the analog precision is 12 bits; as can be seen from fig. 7, the Spurious Free Dynamic Range (SFDR), the signal-to-noise ratio (SNR), and the effective bit number (ENOB) of the analog-to-digital converter according to the third embodiment of the present invention are 79.56, 73.32dB, and 11.7bit, respectively. The analog-to-digital converter has a better analog accuracy as the effective bit number is closer to the analog accuracy. Of course, the above is only experimental data of the inventors, and specific parameters are affected by experimental environments, process errors of circuit devices, and the like, and are not limited herein.

The following describes the operation flow of the analog-to-digital converter according to the third embodiment of the present invention; setting the precision of the analog-to-digital converter to 8 bits, wherein the first resistive array 10 is used for converting the first 3 bits of output data; the first capacitor array 20 is used for converting fourth and 5 bits of output data; the second resistive array 30 is used to convert the last 3 bits of the output data. Of course, this is only a specific embodiment, and the number of bits occupied by each array may be adjusted according to the requirement, which is not limited to this.

Sampling: the asynchronous clock generator 3 outputs a first enable signal CLK1 to the fourth switch units of the first capacitor sub-array, so that the first ends of all the fourth switch sub-units are selectively connected to the input voltage Vin to sample the input voltage Vin.

Quantization stage: the conversion of the first 3 bits of the output data is completed first, then the conversion of the fourth bit and the fifth bit of the output data is completed, and then the conversion of the last 3 bits of the output data is completed. Each conversion is specifically as follows:

for converting the first 3 bits of output data, the method specifically comprises the following steps:

s1: the logic control module 4 outputs a first digital signal SW1 to the first resistive array 10, the second capacitive sub-array 21, and the second resistive array 30, so that the first resistive array 10 divides the first reference voltage Vref to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 1/2 of the first reference voltage Vref; the first terminals of all fourth switching subunits are also enabled to select the first output terminal of said first resistive array 10.

S2: the comparator 2 compares according to the input voltage and judges whether the first comparison signal VP1 output by the comparator 2 is at a low level or at a high level; if the level is low, jumping to S31; if the level is high, the process goes to S41.

S31: the asynchronous clock generator 3 outputs an i-th clock signal VALID1 according to the first comparison signal VP1 of a low level; the first logic control module 4 is configured to output a second digital signal SW2 and a first output signal D1 according to the i-th clock signal VALID1 and the second enable signal CLK 2; wherein, at this time, the first output signal D1 is 0, i.e. the most significant bit of the second digital signal is 0. The first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the second digital signal SW2 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 1/4 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S32: the comparator 2 compares according to the input voltage and judges whether the second comparison signal VP2 output by the comparator 2 is at a low level or at a high level; if yes, jumping to S331; if so, the process goes to S341.

S331: the asynchronous clock generator 3 outputs a second clock signal VALID2 according to the second comparison signal VP2 of a low level; the first logic control module 4 is configured to output a third digital signal SW3 and a second output signal D2 according to the second clock signal VALID2 and the second enable signal CLK 2; wherein, at this time, the second output signal D2 is 0, that is, the second bit of the second digital signal is also 0. Then, the first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 1/8 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S332: the comparator 2 compares the input voltage and judges whether the third comparison signal VP3 output by the comparator 2 is in a low level or in a high level; if yes, jump to S3331; if the level is high, the process goes to S3341.

S3331: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a low level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 0, i.e. the third bit of the second digital signal is still 0. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage vref+the second reference voltage Vref-L, i.e., the third reference voltage Vref-H is equal to 1/4 of the first reference voltage Vref. At this time, the first three bits of the second digital signal are 000.

S3341: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a high level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage vref+the second reference voltage Vref-L, i.e., the third reference voltage Vref-H is equal to 1/4 of the first reference voltage Vref. At this time, the first three bits of the second digital signal are 001.

S341: the asynchronous clock generator 3 outputs a second clock signal VALID2 according to the second comparison signal VP2 of a high level; the first logic control module 4 is configured to output a third digital signal SW3 and a second output signal D2 according to the second clock signal VALID2 and the second enable signal CLK 2; wherein, at this time, the first output signal D1 is 1, that is, the second bit of the second digital signal is 1. Then, the first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 3/8 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S342: the comparator 2 compares according to the input voltage and judges whether the second reference voltage Vref-L is larger than the third analog voltage or not through the comparator 2; if yes, jump to S3431; if the level is high, the process goes to S3441.

S3431: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a low level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is 0. The third reference voltage Vref-H is equal to 1/8 x the first reference voltage vref+the second reference voltage Vref-L, i.e. the third reference voltage Vref-H is equal to 1/2 x the first reference voltage Vref, and the first three bits of the second digital signal are 010.

S3441: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a high level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. The third reference voltage Vref-H is equal to 1/8 x the first reference voltage vref+the second reference voltage Vref-L, i.e. the third reference voltage Vref-H is equal to 1/2 x the first reference voltage Vref, and at this time, the first three bits of the second digital signal are 011.

S41: the asynchronous clock generator 3 outputs an i-th clock signal VALID1 according to the first comparison signal VP1 of a high level; the first logic control module 4 is configured to output a second digital signal SW2 and a first output signal D1 according to the i-th clock signal VALID1 and the second enable signal CLK 2; wherein, at this time, the first output signal D1 is 1, that is, the most significant bit of the second digital signal is 1. The first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the second digital signal SW2 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 3/4 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S42: the comparator 2 compares according to the input voltage and judges whether the second comparison signal VP2 output by the comparator 2 is at a low level or at a high level; if yes, jump to S431; if high, the process goes to S441.

S431: the asynchronous clock generator 3 outputs a second clock signal VALID2 according to the second comparison signal VP2 of a low level; the first logic control module 4 is configured to output a third digital signal SW3 and a second output signal D2 according to the second clock signal VALID2 and the second enable signal CLK 2; wherein, at this time, the second output signal D2 is 0, that is, the second bit of the second digital signal is 0. Then, the first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 5/8 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S432: the comparator 2 compares the input voltage and judges whether the third comparison signal VP3 output by the comparator 2 is in a low level or in a high level; if yes, jump to S4331; if the voltage is high, the process goes to S4341.

S4331: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a low level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 0, i.e. the third bit of the second digital signal is still 0. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage vref+the second reference voltage Vref-L, i.e., the third reference voltage Vref-H is equal to 3/4 of the first reference voltage Vref. At this time, the first three bits of the second digital signal are 100.

S4341: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a high level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage vref+the second reference voltage Vref-L, i.e., the third reference voltage Vref-H is equal to 3/4 of the first reference voltage Vref. At this time, the first three bits of the second digital signal are 101.

S441: the asynchronous clock generator 3 outputs a second clock signal VALID2 according to the second comparison signal VP2 of a high level; the first logic control module 4 is configured to output a third digital signal SW3 and a second output signal D2 according to the second clock signal VALID2 and the second enable signal CLK 2; wherein, at this time, the first output signal D1 is 1, that is, the second bit of the second digital signal is 1. Then, the first resistive array 10 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the third digital signal SW3 to obtain a second reference voltage Vref-L; wherein the second reference voltage Vref-L is equal to 7/8 of the first reference voltage Vref; the first ends of all fourth switch subunits still select the first output of the first resistive array 10.

S442: the comparator 2 compares the input voltage and judges whether the third comparison signal VP3 output by the comparator 2 is in a low level or in a high level; if yes, jump to S4431; if the level is high, the process goes to S4441.

S4431: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a low level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 0, that is, the third bit of the second digital signal is 0. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage Vref+the second reference voltage Vref-L, i.e. the third reference voltage Vref-H is equal to the first reference voltage Vref. At this time, the first three bits of the second digital signal are 110.

S4441: the asynchronous clock generator 3 outputs a third clock signal VALID3 according to the third comparison signal VP3 of a high level; the first logic control module 4 is configured to output a fourth digital signal SW4 and a third output signal D3 according to the third clock signal VALID3 and the second enable signal CLK 2; wherein, at this time, the third output signal D3 is 1, that is, the third bit of the second digital signal is 1. The third reference voltage Vref-H is equal to 1/8 of the first reference voltage Vref+the second reference voltage Vref-L, i.e. the third reference voltage Vref-H is equal to the first reference voltage Vref. At this time, the first three bits of the second digital signal are 111.

The conversion of the fourth bit and the fifth bit of the output data specifically comprises the following steps:

s5: the fourth switch unit in the second capacitor sub-array 21 adjusts the selection of the first terminal corresponding to the fourth switch sub-unit according to the fourth digital signal SW 4.

S6: the comparator 2 compares the input voltage and judges whether the fourth comparison signal VP4 output by the comparator 2 is in a low level or in a high level; if yes, jumping to S71; if the level is high, the process goes to S81.

S71: the asynchronous clock generator 3 outputs a fourth clock signal VALID4 according to the fourth comparison signal VP4 of a low level; the first logic control module 4 is configured to output a fifth digital signal SW5 and a fourth output signal D4 according to the fourth clock signal VALID4 and the second enable signal CLK 2; wherein, at this time, the fourth output signal D4 is 0, i.e. the fourth bit of the second digital signal is 0. The fourth switch unit adjusts the selection of the first end corresponding to the fourth switch subunit according to the fifth digital signal SW 5.

S72: the comparator 2 compares the input voltage and judges whether the fifth comparison signal VP5 output by the comparator 2 is at a low level or at a high level; if so, jumping to S731; if the signal is at the high level, the process goes to S741.

S731: the asynchronous clock generator 3 outputs a fifth clock signal VALID5 according to the fifth comparison signal VP5 of a low level; the first logic control module 4 is configured to output a sixth digital signal SW6 and a fifth output signal D5 according to the fifth clock signal VALID5 and the second enable signal CLK 2; wherein the fifth output signal D5 is still 0 at this time, i.e. the fifth bit of the second digital signal is 0. At this time, the fourth, fifth bit of the second digital signal is 00.

S741: the asynchronous clock generator 3 outputs a fifth clock signal VALID5 according to the fifth comparison signal VP5 of a high level; the first logic control module 4 is configured to output a sixth digital signal SW6 and a fifth output signal D5 according to the fifth clock signal VALID5 and the second enable signal CLK 2; wherein, at this time, the fifth output signal D5 is 1, i.e. the fifth bit of the second digital signal is 1. At this time, the fourth, fifth bit of the second digital signal is 01.

S81: the asynchronous clock generator 3 outputs a fourth clock signal VALID4 according to the fourth comparison signal VP4 of a high level; the first logic control module 4 is configured to output a fifth digital signal SW5 and a fourth output signal D4 according to the fourth clock signal VALID4 and the second enable signal CLK 2; wherein, at this time, the fourth output signal D4 is 1, that is, the fourth bit of the second digital signal is 1. The fourth switch unit adjusts the selection of the first end corresponding to the fourth switch subunit according to the fifth digital signal SW 5.

S82: the comparator 2 compares the input voltage and judges whether the fifth comparison signal VP5 output by the comparator 2 is at a low level or at a high level; if yes, jumping to S831; if not, go to S841.

S831: the asynchronous clock generator 3 outputs a fifth clock signal VALID5 according to the fifth comparison signal VP5 of a low level; the first logic control module 4 is configured to output a sixth digital signal SW6 and a fifth output signal D5 according to the fifth clock signal VALID5 and the second enable signal CLK 2; wherein, at this time, the fifth output signal D5 is 0, i.e. the fifth bit of the second digital signal is 0. At this time, the fourth, fifth bit of the second digital signal is 10.

S841: the asynchronous clock generator 3 outputs a fifth clock signal VALID5 according to the fifth comparison signal VP5 of a high level; the first logic control module 4 is configured to output a sixth digital signal SW6 and a fifth output signal D5 according to the fifth clock signal VALID5 and the second enable signal CLK 2; wherein, at this time, the fifth output signal D5 is 1, i.e. the fifth bit of the second digital signal is 1. At this time, the fourth, fifth bit of the second digital signal is 11.

For converting the last 3 bits of output data, the method specifically comprises the following steps:

s9: the second resistive array 30 adjusts the on/off of the first switch subunit in the first switch unit 11 according to the sixth digital signal SW6 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S10: the comparator 2 compares the input voltage and judges whether the sixth comparison signal VP6 output by the comparator 2 is at a low level or at a high level; if yes, jumping to S111; if the level is high, the process goes to S121.

S111: the asynchronous clock generator 3 outputs a sixth clock signal VALID6 according to the sixth comparison signal VP6 of a low level; the first logic control module 4 is configured to output a seventh digital signal SW7 and a sixth output signal D6 according to the sixth clock signal VALID6 and the second enable signal CLK 2; wherein, at this time, the sixth output signal D6 is 0, that is, the sixth bit of the second digital signal is 0. The second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the seventh digital signal SW7 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S112: the comparator 2 compares the input voltage and judges whether the seventh comparison signal VP7 output by the comparator 2 is in a low level or in a high level; if yes, jump to S1131; if high, the process goes to S1141.

S1131: the asynchronous clock generator 3 outputs a seventh clock signal VALID7 according to the seventh comparison signal VP7 of a low level; the first logic control module 4 is configured to output an eighth digital signal SW8 and a seventh output signal D7 according to the seventh clock signal VALID7 and the second enable signal CLK 2; wherein, at this time, the seventh output signal D7 is 0, that is, the seventh bit of the second digital signal is also 0. Next, the second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the eighth digital signal SW8 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S1132: the comparator 2 compares the voltages according to the input voltages and judges whether the eighth comparison signal VP8 output by the comparator 2 is at a low level or at a high level; if yes, jump to S11331; if high, the process goes to S11341.

S11331: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a low level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is still 0. At this time, the last three bits of the second digital signal are 000.

S11341: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a high level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 1 at this time, that is, the eighth bit of the second digital signal is 1. At this time, the last three bits of the second digital signal are 001.

S1141: the asynchronous clock generator 3 outputs a seventh clock signal VALID7 according to the seventh comparison signal VP7 of a high level; the first logic control module 4 is configured to output an eighth digital signal SW8 and a seventh output signal D7 according to the seventh clock signal VALID7 and the second enable signal CLK 2; wherein, at this time, the seventh output signal D7 is 1, that is, the seventh bit of the second digital signal is also 1. Next, the second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the eighth digital signal SW8 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S1142: the comparator 2 compares the voltages according to the input voltages and judges whether the eighth comparison signal VP8 output by the comparator 2 is at a low level or at a high level; if yes, jump to S11431; if high, the process goes to S11441.

S11431: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a low level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 0 at this time, that is, the eighth bit of the second digital signal is 0. At this time, the last three bits of the second digital signal are 010.

S11441: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a high level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 1 at this time, that is, the eighth bit of the second digital signal is 1. At this time, the last three bits of the second digital signal are 011.

S121: the asynchronous clock generator 3 outputs a sixth clock signal VALID6 according to the sixth comparison signal VP6 of a high level; the first logic control module 4 is configured to output a seventh digital signal SW7 and a sixth output signal D6 according to the sixth clock signal VALID6 and the second enable signal CLK 2; wherein, the sixth output signal D6 is 1 at this time, that is, the sixth bit of the second digital signal is 1. The second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the seventh digital signal SW7 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S122: the comparator 2 compares the input voltage and judges whether the seventh comparison signal VP7 output by the comparator 2 is in a low level or in a high level; if yes, jump to S1231; if so, the process goes to S1241.

S1231: the asynchronous clock generator 3 outputs a seventh clock signal VALID7 according to the seventh comparison signal VP7 of a low level; the first logic control module 4 is configured to output an eighth digital signal SW8 and a seventh output signal D7 according to the seventh clock signal VALID7 and the second enable signal CLK 2; wherein, at this time, the seventh output signal D7 is 0, that is, the seventh bit of the second digital signal is also 0. Next, the second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the eighth digital signal SW8 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S1232: the comparator 2 compares the voltages according to the input voltages and judges whether the eighth comparison signal VP8 output by the comparator 2 is at a low level or at a high level; if yes, jump to S12331; if the level is high, the process goes to S12341.

S12331: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a low level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, at this time, the eighth output signal D8 is 0, that is, the eighth bit of the second digital signal is still 0. At this time, the last three bits of the second digital signal are 100.

S12341: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a high level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 1 at this time, that is, the eighth bit of the second digital signal is 1. At this time, the last three bits of the second digital signal are 101.

S1241: the asynchronous clock generator 3 outputs a seventh clock signal VALID7 according to the seventh comparison signal VP7 of a high level; the first logic control module 4 is configured to output an eighth digital signal SW8 and a seventh output signal D7 according to the seventh clock signal VALID7 and the second enable signal CLK 2; wherein, at this time, the seventh output signal D7 is 1, that is, the seventh bit of the second digital signal is also 1. Next, the second resistive array 30 adjusts the on/off state of the third switch subunit in the third switch unit 31 according to the eighth digital signal SW8 to obtain a sixth reference voltage Vref-lsb, and outputs the sixth reference voltage Vref-lsb to the first end of the first capacitor C0.

S1242: the comparator 2 compares the voltages according to the input voltages and judges whether the eighth comparison signal VP8 output by the comparator 2 is at a low level or at a high level; if yes, jump to S12431; if high, the process goes to S11441.

S12431: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a low level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 0 at this time, that is, the eighth bit of the second digital signal is 0. At this time, the last three bits of the second digital signal are 110.

S12441: the asynchronous clock generator 3 outputs an eighth clock signal VALID8 according to the eighth comparison signal VP8 of a high level; the first logic control module 4 is configured to output an eighth output signal D8 according to the eighth clock signal VALID8 and the second enable signal CLK 2; wherein, the eighth output signal D8 is 1 at this time, that is, the eighth bit of the second digital signal is 1. At this time, the last three bits of the second digital signal are 111.

In the comparison process of the analog-to-digital converter, the comparison signals, the clock signals and the digital signals at different times are distinguished for convenience of description, wherein the first comparison signal VP1 to the eighth comparison signal VP8 only show that the values of the comparison signals change at different times; the first clock signal VALID1 to the eighth clock signal VALID8 represent only that the values of the clock signals change at different times; the first to eighth digital signals SW1 to SW8 embody only digital signals whose values change at different times.

Other structures of the analog-to-digital converter provided by the third embodiment of the present invention are described below:

as a specific implementation manner, the comparator 2, the asynchronous clock generator 3 and the logic control module 4 are conventional technical means in the art, and the internal structures of the comparator 2, the asynchronous clock generator 3 and the logic control module 4 are not described herein.

As a specific embodiment, the fourth reference voltage Vref-L is specifically an output voltage after the second reference voltage Vref-L is input into the buffer. The fifth reference voltage Vref-H is specifically the output voltage of the third reference voltage Vref-H after being input into the buffer. The beneficial effects that it has are: the accuracy of the second reference voltage Vref-L, the third reference voltage Vref-H, and the sixth reference voltage Vref-lsb generated by the first resistive array 10 and the second resistive array 30 is prevented from being affected by the formation of a resistance voltage divider by the 2M series-connected first resistive cells R1 and the 2J series-connected second resistive cells R2. The buffer is specifically a voltage buffer.

A fourth embodiment of the present invention provides an electronic device including the analog-to-digital converter provided by the third embodiment of the present invention.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A digital-to-analog conversion circuit for converting a first digital signal of N bits into a corresponding first analog voltage; the capacitive touch screen is characterized by comprising a first resistive array, a first capacitor array and a second resistive array;

the first capacitor array comprises a first capacitor and a second capacitor sub-array, the second capacitor sub-array comprises N-M-J second capacitors which are sequentially arranged from low order to high order, and the capacitance value of an ith second capacitor in the second capacitor sub-array meets the following conditions: ci=2i—1C0; wherein, C0 is the capacitance value of the first capacitor; a first end of the first capacitor is connected with the sixth reference voltage, and a second end of the first capacitor is coupled to an output end of the second capacitor subarray; wherein,

wherein the first analog voltage is a weighted sum of the second analog voltage and the third analog voltage; n, M, J, i are positive integers, M, J is more than or equal to 1, and M+J is less than N; i is more than or equal to 1 and less than or equal to N-M-J.

2. The digital to analog conversion circuit of claim 1, wherein said first resistive array comprises 2M first resistive cells, first switch cells, second switch cells connected in series;

a first end of a first resistive element is used as a first end of the first resistive array, and a second end of a 2M first resistive element is used as a second end of the first resistive array;

3. The digital to analog conversion circuit of claim 2, wherein said second resistive array comprises 2J second resistive cells and a third switching cell connected in series;

A first end of a first second resistive element is used as a first end of the first resistive array, and a second end of a 2J second resistive element is used as a second end of the second resistive array;

4. The digital to analog conversion circuit of claim 3, wherein said first resistive element and said second resistive element each comprise a single resistor.

5. A digital to analog conversion circuit according to claim 3, wherein said first resistive element and said second resistive element each comprise a resistive network; the resistor network is formed by connecting a plurality of resistors in series and parallel.

6. The digital to analog conversion circuit of claim 3, wherein said first switch subunit, said second switch subunit, and said third switch subunit each comprise single pole single throw switches.

7. The digital to analog conversion circuit of claim 3, wherein said second capacitor sub-array further comprises a fourth switching element;

8. The digital to analog conversion circuit of claim 7, wherein said fourth switch subunit comprises a single pole, triple throw switch.

9. A control method of a digital-to-analog conversion circuit for controlling the digital-to-analog conversion circuit according to any one of claims 1 to 8, comprising:

controlling the second resistive array to selectively divide a first voltage according to low J-bit digital data of the first digital signal, so that the second resistive array outputs a sixth reference voltage; wherein the sixth reference voltage comprises 2 ^J A stage voltage; wherein the first voltage is the second referenceA difference between a fourth reference voltage obtained by buffering the reference voltage and a fifth reference voltage obtained by buffering the third reference voltage;

10. An analog-to-digital converter for converting said input voltage to a second digital signal of N bits, comprising a comparator, an asynchronous clock generator, a logic control module and the digital-to-analog conversion circuit of any one of claims 1 to 8;

11. An electronic device comprising the analog-to-digital converter of claim 10.