CN117497539A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench, and a gettering site. The semiconductor layer and the insulating layer are sequentially arranged on the insulating base layer, and the isolation trench is arranged in the semiconductor layer and penetrates through the insulating layer. The isolation trench comprises a first section, a second section and a third section from top to bottom, wherein the first section is higher than the bottom surface of the insulating layer, and the second section and the third section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and contacts the isolation trench, and an apex of the gettering site is lower than the second cross-section.

Description

Semiconductor device and method for manufacturing the same

[ field of technology ]

The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor device with gettering sites and a method for fabricating the same.

[ background Art ]

Semiconductor devices, such as transistors, in integrated circuits are typically fabricated in semiconductor substrates, and the fabrication of semiconductor devices typically involves performing multiple semiconductor processes such as doping, thin film deposition, and epitaxial growth. For the semiconductor substrate, it is unavoidable that impurity (impurity) atoms, such as copper, iron, gold, and the like, may be further generated in the semiconductor substrate in the semiconductor process. When impurity atoms exist in the semiconductor substrate, not only the leakage current of the semiconductor device, such as junction leakage current, is increased, but also the breakdown voltage of the semiconductor device is reduced, and the electrical performance of the semiconductor device is further deteriorated.

In order to eliminate impurity atoms in the semiconductor substrate, a gettering site (gettering site) is generally provided in the semiconductor substrate for trapping the impurity atoms in the semiconductor substrate. However, the gettering portion is typically fabricated in a semiconductor bulk (bulk semiconductor) rather than in a semiconductor-on-insulator (SOI) substrate. Accordingly, there is still a need for further improvements in gettering portions and methods of fabricating semiconductor devices fabricated on semiconductor-on-insulator substrates.

[ invention ]

In view of the foregoing, there is a need for an improved semiconductor device that ameliorates the shortcomings of conventional semiconductor devices.

A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench, and a gettering site. The semiconductor layer is disposed on the insulation base layer, and the insulation layer is disposed on the semiconductor layer. The isolation trench is disposed in the semiconductor layer and penetrates through the insulating layer. The isolation trench comprises a first section, a second section and a third section from top to bottom, wherein the first section is higher than the bottom surface of the insulating layer, and the second section and the third section are lower than the bottom surface of the insulating layer. The gettering sites are disposed in the semiconductor layer and respectively contact the isolation trenches, and an apex of the gettering sites is lower than the second cross section.

A method for manufacturing a semiconductor device includes the following steps. A substrate is provided, on which an insulation base layer and a semiconductor layer are sequentially disposed. An insulating layer is formed over the semiconductor layer, wherein the insulating layer includes a bottom surface. Forming isolation trenches in the semiconductor layer and the insulating layer to expose the insulating base layer, the step of forming the isolation trenches comprising: etching the insulating layer to form an upper through hole in the insulating layer; and etching the semiconductor layer after etching the insulating layer to form a lower through hole in the semiconductor layer, wherein the lower part of the lower through hole comprises a tapered part, and in the process of etching the semiconductor layer, an etching inhibition layer is formed at the same time, and covers the inner side wall of the upper through hole. After the isolation trench is formed, the insulating layer is used as an ion implantation shielding to form a gettering site, wherein the gettering site contacts the isolation trench, and the vertex of the gettering site is lower than the bottom surface of the insulating layer. An insulating material is formed in the isolation trench.

According to the embodiments of the present disclosure, since the top of the gettering site is lower than the bottom surface of the insulating layer, the gettering site is further away from the upper portion of the semiconductor layer, so that the lattice defect of the gettering site can be prevented from negatively affecting the electric field distribution of the upper portion of the semiconductor layer, or the impurity atoms in the gettering site can be prevented from being attracted by the electric field to diffuse outwards to the upper portion of the semiconductor layer, thereby improving the electrical performance of the semiconductor device.

In addition, since each isolation trench includes the first cross section, the second cross section, and the third cross section from top to bottom, when the width of the first cross section and the third cross section is smaller than the width of the second cross section, the gettering site can be more advantageously formed only at the lower periphery of the isolation trench, but not at the upper periphery of the isolation trench during the process of forming the gettering site.

[ description of the drawings ]

For easier understanding, reference is made to the drawings and their detailed description when read in this disclosure. Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the various features of the disclosure. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.

Fig. 1 is a schematic top view of a chip structure according to an embodiment of the disclosure.

FIG. 2 is a schematic cross-sectional view of an embodiment of the present disclosure along the line A-A' of FIG. 1.

Fig. 3 is an enlarged schematic view of a partial region of the semiconductor device of fig. 1.

Fig. 4-10 are schematic cross-sectional views of various stages of a process for fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

[ detailed description ] of the invention

The present disclosure provides several different embodiments that may be used to implement different features of the present disclosure. For simplicity of explanation, the present disclosure also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments in the present disclosure may use repeated reference characters and/or text labels. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for spatially related narrative terms mentioned in this disclosure, for example: when "under", "low", "lower", "upper", "top", "bottom" and the like, for ease of description, the description is used to describe one component or feature's relative to another component (or feature) in the drawings. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.

Although the present disclosure uses first, second, third, etc. terms to describe various elements, components, regions, layers, and/or blocks, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself connote or imply any preceding ordinal number or order of arrangement of elements or methods of manufacture. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present disclosure.

The terms "about" or "substantially" as referred to in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.

Although the invention of the present disclosure is described below by way of specific embodiments, the inventive principles of the present disclosure may also be applied to other embodiments. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of persons of ordinary skill in the art.

Fig. 1 is a schematic top view of a chip structure according to an embodiment of the disclosure. As shown in fig. 1, the chip structure 1 may be disposed in a chip area a of a wafer, and the periphery of the chip area a may be surrounded by a scribe line area B. In a subsequent process, dicing may be performed along the dicing street regions B so that adjacent chip regions a are separated from each other. The chip area a may include an integrated circuit therein, and the integrated circuit includes a plurality of semiconductor device areas, such as the semiconductor device areas 20, 30, 40 for accommodating power transistors, logic operation components, or memory devices, respectively, but is not limited thereto. For the semiconductor device 100 in the chip region a, it includes a semiconductor device region 20 and an isolation region 22. The isolation region 22, for example, comprises a deep trench isolation structure that may surround the periphery of the semiconductor device region 20 to electrically isolate the semiconductor device region 20 from the other semiconductor device regions 30, 40 or from other regions in the chip region a.

FIG. 2 is a schematic cross-sectional view of an embodiment of the present disclosure along the line A-A' of FIG. 1. As shown in fig. 2, the semiconductor device 100 at least comprises a substrate 101, an insulation base layer 103, a semiconductor layer 105, at least two insulation layers 117, at least two isolation trenches 151, and at least two gettering sites 153. The substrate 101 may be a semiconductor substrate, an insulating substrate, or other suitable carrier substrate (handle substrate). According to one embodiment of the present disclosure, the substrate 101 may be removed such that the bottom surface of the insulation base layer 103 is exposed. An insulation base layer 103, such as a buried insulation layer buried insulating layer, is disposed over the substrate 101 and comprises, for example, silicon oxide or other silicon-containing oxide, or other suitable insulation material. By providing the insulating base layer 103, leakage current can be prevented from flowing from the substrate 101 to a layer provided over the insulating base layer 103. A semiconductor layer 105 is provided over the insulating base layer 103, and its composition includes, for example, a silicon semiconductor such as single crystal silicon, or a compound semiconductor such as gallium nitride or silicon carbide. An insulating layer 117, such as a shallow trench isolation structure, is disposed over the semiconductor layer 105, and the insulating layer 117 includes a bottom surface buried in the semiconductor layer 105. Isolation trenches 151 are disposed in semiconductor layer 105 and extend through insulating layers 117. The isolation trench 151 may be filled with an insulating material such that the isolation trench 151 and the insulating layer 117 that is penetrated may be formed as part of the deep trench isolation structure 200. By providing the insulation base layer 103 and the deep trench isolation structure 200, the semiconductor device region 20 can be electrically insulated from the outer region.

The gettering site 153 is disposed in the semiconductor layer 105 and contacts the isolation trench 151. The gettering sites 153 are located between the isolation trenches 151 and laterally (e.g., in the X-direction) apart from each other. The gettering site 153 is, for example, a doped region, such as an arsenic doped region or other suitable doped region, which may be used to trap impurity atoms in the semiconductor layer 105, such as conductive atoms of copper, iron, and gold, to avoid the impurity atoms from adversely affecting the electrical performance of the semiconductor device 100. According to an embodiment of the present disclosure, the gettering site 153 itself has conductivity, and the gettering site 153 is formed by ion implantation, and thus has more lattice defects than the adjacent semiconductor layer 105. Further, since the gettering site 153 serves to trap impurity atoms in the semiconductor layer 105, when the impurity atoms are trapped to the gettering site 153, the gettering site 153 may have a high concentration of impurity atoms. According to an embodiment of the present disclosure, the gettering site 153 is disposed only at the lower periphery of the isolation trench 151, but not at the upper periphery of the isolation trench 151, so that the gettering site 153 is separated from each doped region, such as a source doped region, a drain doped region, a well region, a body region, a drift region, etc., located at the upper portion of the semiconductor layer 105 in a vertical direction (e.g., Z direction). Thus, current flowing through the gettering site 15 can be prevented, or lattice defects in the gettering site 153 can be prevented from adversely affecting the electric field distribution in each doped region, or impurity atoms trapped in the gettering site 153 are prevented from being attracted by the electric field to be diffused out into each doped region, thereby improving the electrical performance of the semiconductor device.

In addition to the components described above, the semiconductor device 100 may further include other components, such as doped regions, insulating structures, and electrode structures, according to an embodiment of the present disclosure. As also shown in fig. 2, the semiconductor device 100 includes a well region 171 of a first conductivity type (e.g., p-type) disposed on the upper portion of the semiconductor layer 105 and on one side of the semiconductor device region 20. A source doped region 173 and a heavily doped region 175, each having a second conductivity type (e.g., n-type) and a first conductivity type, are disposed in the well region 171. The body doped region 177, having the first conductivity type, is disposed in the well region 171 and is disposed adjacent to the source doped region 173 and the heavily doped region 175. The drift region 181, having the second conductivity type, is disposed on the upper portion of the semiconductor layer 105 and on the other side of the semiconductor device region 20. The drain doped region 183, having the second conductivity type, is disposed in the drift region 181. An insulating structure 185 is provided in drift region 181 for increasing the path of current transfer in drift region 181. A gate structure 191 is disposed over the semiconductor layer 105 and spans the junction between the well 171 and drift region 181. The upper portion of the partial well 171 is adjacent to and overlaps the bottom surface of the gate structure 191 to serve as a channel region of the semiconductor device 100. A dielectric layer 193 and a field plate 195 are sequentially disposed over drift region 181, partially overlapping gate structure 191. In operation of semiconductor device 100, the electric field distribution within drift region 181 may be modulated by applying a bias voltage to field plate 195.

Fig. 3 is an enlarged schematic view of a partial region of the semiconductor device of fig. 1. As shown in fig. 3, a deep trench isolation structure 200 is disposed over the insulation base layer 103 and includes an isolation trench 151. Isolation trenches 151 include upper trenches 125 and lower trenches 135. The upper trench 125 is disposed in the upper through hole 127, wherein the upper through hole 127 is a hole penetrating the insulating layer 117. The lower trench 135 coincides with the lower through hole 147, wherein the lower through hole 147 is a hole penetrating the semiconductor layer 105, and the lower through hole 147 exposes the top surface of the insulation base layer 103.

The etch stop layer (inhibitor) 141 covers the inner sidewall of the upper via 127 such that the inner sidewall 143 of the etch stop layer 141 overlaps the inner sidewall 132 of the upper trench 125. The etch-stop layer 141 comprises, for example, a polymer (e.g., a fluoropolymer) or an oxide (e.g., a silicon-containing oxide), which may be a solid product formed during a plasma etch process performed to form the isolation trench 151. According to an embodiment of the present disclosure, the etching-stopper layer 141 is not limited to cover only the inner sidewall of the upper through hole 127, but may further cover a partial inner sidewall of the lower through hole 147, so that a portion of the inner sidewall of the etching-stopper layer 141 may further overlap with a portion of the inner sidewall of the lower trench 135. According to one embodiment of the present disclosure, the etching-inhibiting layer 141 has an inclined surface, and the width of the opening defined by the inclined surface increases from top to bottom. However, according to other embodiments, the cross-sectional profile of the etch-stop layer 141 in the vertical direction (e.g., Z-direction) may also include a vertical plane or a curved plane, and the narrowest point of its opening width is not limited to the top end thereof, but may be the middle or bottom end thereof.

For the isolation trench 151, the isolation trench 151 may include a plurality of trench cross sections, for example, from top to bottom including a first cross section P1, a second cross section P2, and a third cross section P3. The first section P1 is higher than the bottom surface 119 of the insulating layer 117, and is defined between two opposite etching stopper layers 141 to have a width Wp1. The second section P2 is lower than the bottom 119 of the insulating layer 117 and is located in the lower trench 135 of the isolation trench 151, for example in the flared portion 133 of the lower trench 135, and has a width Wp2. The third section P3 is lower than the bottom 119 of the insulating layer 117 and is located in the lower trench 135 of the isolation trench 151, for example in the tapered portion 137 of the lower trench 135, and has a width Wp3. The relationship among the widths Wp1, wp2, wp3 satisfies the following expression (1) and expression (2):

Wp1＜Wp2 (1)

Wp3＜Wp2 (2)

in addition, the upper through hole 127 in the insulating layer 117 may have a width Wt1, and a width relationship between the upper through hole 127 and the third section P3 of the isolation trench 151 satisfies the following formula (3):

Wt1＞Wp3 (3)

for the flared portion 133 of the lower trench 135, the partial inner sidewall 134 is widened outwardly so that the partial width thereof is wider than the width Wt1 of the upper through hole 127, and the cross-sectional profile of the flared portion 133 in the vertical direction (e.g., Z direction) may include an inclined surface or a curved surface. In addition, for the topmost end of the flared portion 133, the topmost end is adjacent to the bottom corner 117c of the insulating layer 117 and the top corner 105c of the semiconductor layer 105, and since the inner sidewall 134 of the flared portion 133 is flared outwardly, the bottom corner 117c of the insulating layer 117 and the top corner 105c of the semiconductor layer 105 are laterally (e.g., in the X-direction) separated from each other.

For the tapered portion 137 of the lower trench 135, the tapered portion 137 is located below the flared portion 133, but is not limited to the immediate vicinity of the flared portion 133, and the inner sidewall 136 of the tapered portion 137 tapers from top to bottom to have an inclined surface or curved surface.

According to one embodiment of the present disclosure, the width of any cross section of the flared portion 133 is greater than the width Wt1 of the upper through hole 127, and the width of some cross sections of the tapered portion 137 is less than the width Wt1 of the upper through hole 127. In addition, the lower trench 135 may include other portions, such as a vertical portion or a curved portion, in addition to the flared portion 133 and the tapered portion 137.

The gettering site 153 contacts a portion of the isolation trench and is disposed along the inner sidewall 136 of the tapered portion 137 of the lower trench 135 and directly contacts the insulation base layer 103. The apex 155 of the gettering site 153 is lower than the second cross section P2, so that the gettering site 153 is separated vertically (e.g., in the Z direction) from the flared portion 133 of the lower trench 135.

An insulating material may be disposed in the isolation trench 151 of the deep trench isolation structure 200 to increase the electrical isolation capability of the deep trench isolation structure 200. According to an embodiment of the present disclosure, the isolation trench 151 may include an insulating material 161 and a filling material 163, wherein the insulating material 161 may cover the inner sidewalls 132, 134, 136 of the isolation trench 151 in a forward direction, and the filling material 163 may fill the isolation trench 151. The composition of the filler material 163 may be an insulating material or a conductive material, depending on the actual requirements. In accordance with an embodiment of the present disclosure, the isolation trench 151 may not have the conformal insulating material 161 present therein, such that the fill material 163 directly contacts the inner sidewalls 132, 134, 136 of the isolation trench 151, where the fill material 163 may be composed of an insulating material.

In order to protect the surface of the semiconductor layer 105, according to an embodiment of the present disclosure, a pad layer 111, such as an oxide pad layer 107 and a nitride pad layer 109, may be additionally provided between the semiconductor layer 105 and the insulating layer 117, but is not limited thereto.

In order to enable a person having ordinary skill in the art to implement the semiconductor device of the present disclosure, a method for fabricating the semiconductor device of the present disclosure is further described below.

Fig. 4 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. As shown in the cross section 400 of fig. 4, a substrate 101 is provided on which an insulation base layer 103 and a semiconductor layer 105 are sequentially disposed. The insulation base layer 103 may be a bonding layer, and thus a bonding manner may be utilized to bond the semiconductor layer 105 to the substrate 101. The surface of the semiconductor layer 105 is provided with a pad layer 111, for example, including an oxide pad layer 107 and a nitride pad layer 109. When the composition of the semiconductor layer 105 is single crystal silicon, the composition of the oxide pad layer 107 may include silicon oxide, and the composition of the nitride pad layer 109 may include silicon nitride. An opening may be formed in the pad layer 111, and at least two recess regions 113 may be formed on the surface of the semiconductor layer 105 using the pad layer 111 as an etching mask, and the bottom surfaces of the recess regions 113 may be vertically separated from the insulation base layer 103. Thereafter, an insulating layer 117 is deposited such that the insulating layer 117 covers the pad layer 111 and fills the recess 113. In order to fill the recess 113 with the insulating layer 117, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process (high density plasma chemical vapor deposition) or other suitable plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD) process may be performed to form the insulating layer 117. At this stage of the process, the insulating layer 117 filled in the recess 113 has a bottom 119 separated from the insulating base layer 103 in a vertical direction (e.g., Z direction).

In a subsequent process, at least one isolation trench may be further formed in the insulating layer 117 and the semiconductor layer 105 to expose the insulating base layer 103. The process of forming isolation trenches is shown in FIGS. 5-7.

Fig. 5 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. As shown in section 402 of fig. 5, an etch mask 121, such as a photoresist, is formed, and the etch mask 121 has an opening 123 therein. Next, the insulating layer 117 exposing the opening 123 is etched to form an upper through hole 127 in the insulating layer 117. The bottom surface of the upper through hole 127 includes a width Wt1, and the width Wt1 is smaller than the width of the bottom surface of the recess 113. At this stage, the upper through hole 127 coincides with the upper trench 125, and the upper trench 125 constitutes an upper portion of the isolation trench in a subsequent process.

Fig. 6 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. After etching the insulating layer 117 to form the upper via 127, the semiconductor layer 105 is etched, for example, by performing a plasma etching process or other suitable etching process, with the insulating layer 117 as an etching mask, as shown in a cross section 404 of fig. 6, to form a flash trench 131 in the semiconductor layer 105. During the etching of the conductor layer 105, an etching stopper layer 141 is simultaneously formed, and the etching stopper layer 141 covers the inner sidewall of the upper through hole 127. In addition, the thickness of the etching stopper layer 141 is not constant, but continuously changes, for example, gradually increases, as the etching of the conductor layer 105 proceeds. In accordance with one embodiment of the present disclosure, the transient trench 131 is etched using a deep reactive ion etching (deep reactive ion etching, DRIE) process. Since the solid product generated by the deep reactive ion etching process, such as a fluoropolymer or other polymer, or a silicon-containing oxide or other oxide, is deposited on the inner sidewall of the upper via 127, the two opposite etching-inhibiting layers 141 define a width Wp1 on the first cross-section P1 of the upper trench 125, and the width Wp1 is smaller than the width Wt1 of the upper via 127. According to the embodiment of the disclosure, the etching-inhibiting layer 141 has an inclined surface at this stage, and the width of the opening defined therein increases from top to bottom. However, according to other embodiments, the cross-sectional profile of the etch-stop layer 141 in the vertical direction (e.g., Z-direction) may also include a vertical plane or a curved plane, and the narrowest point of the opening width thereof is not limited to the top end thereof, but may be the middle or bottom end thereof.

For the instant trench 131, it includes the flared portion 133, and the width Wp2 of the flared portion 133 at the second section P2 is wider than the width Wt1 of the upper through hole 127 and also wider than the width Wp1 of the first section P1 of the upper trench 125.

Fig. 7 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. As shown in section 406 of fig. 7, the semiconductor layer 105 continues to be etched, such as by performing a deep reactive ion etch (deep reactive ion etching, DRIE) or other suitable etching process, to form a lower through-hole 147 (otherwise referred to as a lower trench 135) in the semiconductor layer 105 and expose the insulation base layer 103. The lower through hole 147 includes the flared portion 133 and the tapered portion 137, and the tapered portion 137 is located below the flared portion 133. The inner sidewall 136 of the tapered portion 137 tapers from top to bottom to have an inclined or curved surface. The bottom surface of the tapered portion 137 includes a width Wp3, and the width Wp3 is smaller than the width Wp2 of the flared portion 133. The upper trench 125 and the lower trench 135 may form a part of the isolation trench 151, and the isolation trench 151 includes, from top to bottom, an inner sidewall 132, an inner sidewall 134, and an inner sidewall 136, and the inner sidewall 143 of the etch-stopper 141 overlaps the inner sidewall 132 of the upper trench 125.

Fig. 8 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. After the isolation trench 151 is formed, an ion implantation process is performed using the insulating layer 117 as an ion implantation mask or simultaneously using the etch stop layer 141 as an ion implantation mask, as shown in a cross section 408 of fig. 8, to form a gettering site 153 contacting the isolation trench 151. Since the widths Wp1, wp2, wp3 between the first, second, and third cross-sections P1, P2, and P3 of the isolation trench 151 satisfy the above-described equations (1) and (2), the gettering site 153 is formed only on the side of the tapered portion 137, but not on the side of the flared portion 133, so that the vertex 155 of the gettering site 153 is lower than the bottom surface 119 of the insulating layer 117 when the ion implantation process is performed.

Fig. 9 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. After the gettering site 153 is formed, as shown in a cross section 410 of fig. 9, an insulating material 161 and a filling material 163 are sequentially formed in the isolation trench 151, wherein the insulating material 161 may cover the inner sidewalls 132, 134, 136 of the isolation trench 151 in a forward direction, and the filling material 163 may fill the isolation trench 151. The composition of the filler material 163 may be an insulating material or a conductive material, depending on the actual requirements.

Fig. 10 is a schematic cross-sectional view of a stage in the fabrication of a semiconductor device according to an embodiment of the present disclosure. As shown in the cross section 412 of fig. 10, an etching process is performed to remove the filling material 163, the insulating material 161 and the insulating layer 117 not covered by the etching mask 197 until the pad layer 111 is exposed, thereby forming the deep trench isolation structure 200 in the isolation region 22. In a subsequent process, a suitable semiconductor process may be performed, for example, a doped region, an insulating structure, an electrode structure, or a field plate may be further formed in the semiconductor device region 20 to form a semiconductor device similar to that shown in fig. 2, and the substrate 101 may be further removed to expose the bottom surface of the insulating base layer 103 according to an embodiment of the present disclosure, but is not limited thereto.

According to the above embodiment, since the gettering site 153 in the semiconductor device 100 is provided only at the lower periphery of the isolation trench 151, not at the upper periphery of the isolation trench 151, the gettering site 153 can be separated from each doped region or each component located at the upper portion of the semiconductor layer 105 in the vertical direction (for example, Z direction). Thus, the current flowing through the gettering site 153 can be prevented, or lattice defects in the gettering site 153 can be prevented from negatively affecting the electric field distribution in each doped region, or the impurity atoms trapped in the gettering site 153 can be prevented from being attracted by the electric field to diffuse out into each doped region, thereby improving the electrical performance of the semiconductor device 100. In addition, since each isolation trench 151 includes the first cross section P1, the second cross section P2, and the third cross section P3 from top to bottom, when the widths Wp1 and Wp3 of the first cross section P1 and the third cross section P3 are smaller than the width Wp2 of the second cross section P2, the gettering site 153 is more advantageously formed only at the lower periphery of the isolation trench 151, but not at the upper periphery of the isolation trench 151 during the ion implantation process.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

[ symbolic description ]

1 chip structure

20 semiconductor device region

22 isolation region

30 semiconductor device region

40 semiconductor device region

100 semiconductor device

101. Substrate

103 insulating base layer

105 semiconductor layer

105c · apex angle

107. Oxide underlayer

109 nitride pad layer

111- & cushion layer

113. Recessed region

117 insulating layer

117c base angle

119. Bottom surface

121 etching mask

123 opening

125 upper trench

127 upper through hole

131 & gttransient trench

132 inner side wall

133 outer part

134 inner sidewall

135 lower trench

136 inner sidewall

137 taper

141 etching-inhibiting layer

143 inner sidewall

147 lower through hole

151 isolation trench

153 suction site

155. Vertex

161 insulating material

163 filler

171 well region

173 source doped region

175 heavily doped region

181 drift zone

183 drain doped region

185 & ltinsulation structure & gt

191 gate structure

193 dielectric layer

195 & ltfield plate

197 etching mask

200 DEG deep trench isolation structure

400. Cross section

402 section

404. Cross section

406. Cross section

408 cross section

410. Cross section

412. Cross section

A & ltchip area & gt

B & gtcutting lane region

P1.first section

P2.second section

P3.third section

Wp1.cndot.cndot.Width

Wp2.Width

Wp3.cndot.cndot.Width

Wt1. Width

Claims (20)

1. A semiconductor device, comprising:

an insulating base layer;

a semiconductor layer disposed on the insulation base layer;

at least two insulating layers disposed on the semiconductor layer, each insulating layer including a bottom surface;

at least two isolation trenches, each isolation trench is disposed in the semiconductor layer and penetrates through each insulating layer, wherein each isolation trench comprises a first section, a second section and a third section from top to bottom, the first section is higher than the bottom surface of each insulating layer, and the second section and the third section are lower than the bottom surface of each insulating layer; and

at least two gettering sites disposed in the semiconductor layer and contacting the isolation trenches, respectively, wherein an apex of each of the gettering sites is lower than the second cross-section.

2. The semiconductor device of claim 1, wherein each of said insulating layers comprises a bottom corner laterally separated from a top corner of said semiconductor layer.

3. The semiconductor device of claim 1, wherein each of said isolation trenches extends through said semiconductor layer to expose said insulating base layer.

4. The semiconductor device of claim 1, wherein each of said gettering sites is disposed along an inner sidewall of a lower portion of each of said isolation trenches.

5. The semiconductor device of claim 1, wherein the gettering sites between the isolation trenches are laterally separated from each other.

6. The semiconductor device according to claim 1, wherein a width relationship among the first cross section, the second cross section, and the third cross section satisfies the following formulas (1) and (2):

Wp1＜Wp2 (1)

Wp3＜Wp2 (2)

wherein Wp1 is the width of the first section, wp2 is the width of the second section, and Wp3 is the width of the third section.

7. The semiconductor device of claim 1, further comprising:

at least two upper through holes respectively arranged in the insulating layers; and

an etching-inhibiting layer covers the inner sidewall of each upper through hole.

8. The semiconductor device of claim 7, wherein a width relationship between each of said upper through holes and said third section of each of said isolation trenches satisfies the following formula (3):

Wt1＞Wp3 (3)

wherein Wt1 is the width of each upper through hole.

9. The semiconductor device of claim 7, wherein a composition of said etch-stop layer comprises a polymer or silicon-containing oxide.

10. The semiconductor device of claim 7, wherein an inner sidewall of said etch-stop layer coincides with an inner sidewall of an upper portion of each of said isolation trenches.

11. The semiconductor device of claim 7, wherein said etch-stop layer comprises an inclined surface.

12. The semiconductor device of claim 7, further comprising at least two lower through holes disposed in said semiconductor layer, wherein said etch-stop layer further covers inner sidewalls of each of said lower through holes.

13. The semiconductor device according to claim 1, wherein a surface of the semiconductor layer comprises at least two recessed regions, and the insulating layers are filled in the recessed regions, respectively.

14. The semiconductor device of claim 1, further comprising an active device region disposed between said isolation trenches, said active device region comprising a doped region vertically separated from said gettering sites.

15. A method of fabricating a semiconductor device, comprising:

providing a substrate, on which an insulating base layer and a semiconductor layer are sequentially arranged;

forming an insulating layer on the semiconductor layer, wherein the insulating layer comprises a bottom surface;

forming at least one isolation trench in the semiconductor layer and the insulating layer to expose the insulating base layer, the forming at least one isolation trench comprising:

etching the insulating layer to form an upper through hole in the insulating layer; and

etching the semiconductor layer after etching the insulating layer to form a lower through hole in the semiconductor layer, wherein the lower part of the lower through hole comprises a tapered part, and an etching inhibition layer is formed simultaneously in the process of etching the semiconductor layer, and covers the inner side wall of the upper through hole;

after forming the at least one isolation trench, forming a gettering site by using the insulating layer as an ion implantation mask, wherein the gettering site contacts the at least one isolation trench, and a vertex of the gettering site is lower than the bottom surface of the insulating layer; and

an insulating material is formed in the at least one isolation trench.

16. The method of claim 15, wherein the at least one isolation trench comprises, from top to bottom, a first cross section, a second cross section, and a third cross section, the first cross section being higher than the bottom surface of each insulating layer, the second cross section and the third cross section being lower than the bottom surface of each insulating layer, the width relationship among the first cross section, the second cross section, and the third cross section satisfying the following formulas (1) and (2):

Wp1＜Wp2 (1)

Wp3＜Wp2 (2)

wherein Wp1 is the width of the first section, wp2 is the width of the second section, and Wp3 is the width of the third section.

17. The method of claim 15, wherein the composition of the etch-stop layer comprises a polymer or a silicon-containing oxide.

18. The method of claim 15, wherein said etch-stop layer is gradually thickened during etching of said semiconductor layer.

19. The method of claim 15, wherein said forming said gettering site further comprises using said etch-stop layer as an ion implantation mask.

20. The method of claim 15, wherein said gettering site directly contacts said insulating base layer.