CN117497506A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
CN117497506A
CN117497506A CN202310896462.5A CN202310896462A CN117497506A CN 117497506 A CN117497506 A CN 117497506A CN 202310896462 A CN202310896462 A CN 202310896462A CN 117497506 A CN117497506 A CN 117497506A
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CN
China
Prior art keywords
substrate
die
integrated circuit
semiconductor package
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CN202310896462.5A
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Chinese (zh)
Inventor
陈威智
陈晞白
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
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MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/215,830 external-priority patent/US20240038647A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN117497506A publication Critical patent/CN117497506A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a semiconductor package, comprising: a divided package substrate composed of a plurality of substrate parts arranged side by side; at least one integrated circuit die mounted on the first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface. The plurality of substrate components form the divided packaging substrate with larger size, and the integrated circuit die is arranged on the divided packaging substrate and can help the plurality of substrate components to be more stably adjacent together, so that the integrated circuit die and the divided packaging substrate are mutually matched, thereby not only improving the yield of substrate manufacture, but also remarkably improving the integral mechanical strength and mechanical stability of the semiconductor packaging structure.

Description

Semiconductor package
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor package.
Background
With more and more consumers hugging intelligent devices, the demands for network data centers, internet of things, intelligent sensors and the like are increasing. To meet these demands, semiconductor design companies have encountered challenges in terms of chip design complexity and PPA (power, performance, area) factors in lower geometries (e.g., 7nm, 5nm, and 3 nm).
Advanced packaging plays an increasing role throughout the semiconductor industry. Advanced encapsulation is adopted for applications such as network devices, servers, smartphones and the like. To advance the design, IC suppliers developed ASICs (Application Specific Integrated Circuit, application specific integrated circuits). The vendor then shrinks and encapsulates the different functions of each node onto an ASIC. But this approach becomes more and more complex and expensive at each node.
For example, an ASIC for a switch router or data center may include a large die (die) and the size of the package may typically exceed 4500mm 2 This leads to an increase in cost of the ASIC package due to a lower production yield of the package substrate (package substrate) of this size. Large die ASIC packages also experience warpage problems.
Disclosure of Invention
In view of this, the present invention provides an improved large die semiconductor package using substrate block integration (substrate block integration, SBI) to address the above-described problems.
According to a first aspect of the present invention, a semiconductor package is disclosed, comprising:
a divided package substrate composed of a plurality of substrate parts arranged side by side;
at least one integrated circuit die mounted on the first surface of the partitioned package substrate; and
and a solder ball mounted on a second surface of the divided packaging substrate opposite to the first surface.
Further, the at least one integrated circuit die is electrically connected to the partitioned package substrate by conductive elements. Thereby electrically connecting the at least one integrated circuit die with the partitioned package substrate and electrically connecting the at least one integrated circuit die with the plurality of substrate members, the number of the at least one integrated circuit die mechanically and electrically connected substrate members may be equal to or greater than two.
Further, the conductive element includes a microbump, a copper bump, or a copper pillar. To more stably mechanically and electrically connect the integrated circuit die with the plurality of substrate members.
Further, the plurality of substrate members are physically separated from each other. Thus, a plurality of substrate components with smaller sizes are mutually spliced to form a separated packaging substrate with larger sizes.
Further, the plurality of substrate members are rearranged and abutted together with a gap therebetween. Thus, a plurality of substrate components with smaller sizes are mutually spliced to form a separated packaging substrate with larger sizes.
Further, the plurality of substrate members are abutted together by using an adhesive filled into the gap. The separated substrate components are spliced and integrated in this way, so that a larger separated packaging substrate is formed.
Further, the width of the gap is in the range of 1-3mm. The proper gap width between the substrate members not only ensures the stability and mechanical stability of the adhesion between the substrate members, but also prevents accidental detachment between the substrate members, etc.
Further, the plurality of substrate components are homogenous substrates or heterogeneous substrates. Thereby facilitating the manufacture of the substrate components and improving the flexibility of splicing and assembly.
Further, the plurality of substrate members may have the same thickness or different thicknesses. Thereby facilitating the manufacture of the substrate components and improving the flexibility of splicing and assembly.
Further, the method further comprises the following steps:
at least one die is flip-chip mounted on the first surface of the divided packaging substrate. Thereby improving flexibility of design.
Further, the at least one die is a dummy die or a memory die. Thereby improving flexibility of design.
Further, the method further comprises the following steps:
a second integrated circuit die; and
and an electronic device mounted on the first surface of the divided packaging substrate. Thereby improving flexibility of design.
Further, the electronic device includes a decoupling capacitor. Thereby improving flexibility of design.
Further, the second integrated circuit die and the electronic device do not overlap the gap. Thereby ensuring the mounting stability of the second integrated circuit die and the electronic device.
Further, the method further comprises the following steps:
an annular frame mounted on the first surface of the divided packaging substrate. The frame can improve the connection stability between the plurality of substrate components, and simultaneously improve the overall mechanical strength of the package structure.
Further, the frame is a metal frame. To provide a more stable support structure for the plurality of substrate components.
Further, the frame is attached to the first surface of the divided packaging substrate by using bonding bumps or an adhesive. The use of the bonding bump connection can improve the heat dissipation capability of the substrate to the frame, and facilitate manufacturing and shaping, and the connection is more reliable and stable. The use of adhesive attachment may be more convenient to manufacture.
Further, the frame includes an opening for receiving the at least one integrated circuit die. To protect the integrated circuit die and to increase the strength of the overall structure.
Further, the method further comprises the following steps:
and a cover mounted on the first surface of the partitioned package substrate, wherein the at least one integrated circuit die is received by the cover and encapsulated by the molded cap. Thereby improving the heat dissipation and mechanical strength of the package structure.
Further, the method further comprises the following steps:
and a redistribution layer structure on the first surface of the partitioned package substrate, wherein the at least one integrated circuit die is mounted on the redistribution layer structure. To increase flexibility in layout design and die mounting.
The semiconductor package of the present invention includes: a divided package substrate composed of a plurality of substrate parts arranged side by side; at least one integrated circuit die mounted on the first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface. The plurality of substrate components form the divided packaging substrate with larger size, and the integrated circuit die is arranged on the divided packaging substrate and can help the plurality of substrate components to be more stably adjacent together, so that the integrated circuit die and the divided packaging substrate are mutually matched, thereby not only improving the yield of substrate manufacture, but also remarkably improving the integral mechanical strength and mechanical stability of the semiconductor packaging structure.
Drawings
Fig. 1A is a schematic diagram illustrating an exemplary semiconductor package according to an embodiment of the present invention;
FIG. 1B is a cross-sectional view taken along line I-I' in FIG. 1A;
fig. 2A is a schematic diagram illustrating an exemplary semiconductor package according to another embodiment of the present invention;
FIG. 2B is a cross-sectional view taken along line II-II' in FIG. 2A;
fig. 3A is a schematic diagram illustrating an exemplary semiconductor package according to yet another embodiment of the present invention;
FIG. 3B is a cross-sectional view taken along line III-III' in FIG. 3A; and
fig. 4 is a schematic cross-sectional view showing another embodiment of the present invention.
Detailed Description
In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for manufacturing a semiconductor device. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.
It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary component, region, layer or section discussed below could be termed a second or secondary component, region, layer or section without departing from the teachings of the present inventive concept.
Further, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to describe one component or feature's relationship thereto. Another component or feature as shown. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terms "about", "approximately" and "approximately" generally mean within a range of ±20% of a specified value, or ±10% of the specified value, or ±5% of the specified value, or ±3% of the specified value, or ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The prescribed value of the present invention is an approximation. When not specifically described, the stated values include the meaning of "about," approximately, "and" about. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Note that: (i) The same features will be denoted by the same reference numerals throughout the figures and not necessarily described in detail in each of the figures in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear in the entire sequence or may appear only in selected figures of the sequence.
Please refer to fig. 1A and fig. 1B. Fig. 1A is a schematic diagram illustrating an exemplary semiconductor package according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line I-I' in FIG. 1A. As shown in fig. 1A and 1B, the semiconductor package 1 includes a divided (divided) package substrate 10 and at least one integrated circuit die 20 mounted on a first surface S1 of the divided package substrate 10. According to one embodiment, the first surface S1 of the divided (or partitioned, zoned) package substrate 10 is a planar surface. According to one embodiment, for example, at least one integrated circuit die 20 may be flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to one embodiment, at least one integrated circuit die 20 is electrically connected to the partitioned package substrate 10 through a plurality of conductive elements 201, such as micro-bumps, copper bumps, or copper pillars, but is not limited thereto. The underfill 210 may be filled into a space between the at least one integrated circuit die 20 and the first surface S1 of the divided packaging substrate 10. According to one embodiment, the divided packaging substrate 10 may have dimensions of, for example, 60 mm by 60 mm and 70 mm by 70 mm.
According to an embodiment of the present invention, the divided packaging substrate 10 is composed of at least two smaller substrates (hereinafter referred to as substrate members (or substrate partitions, substrate portions)) arranged in a side-by-side manner. For example, four substrate members 10a to 10d coplanar with each other are illustrated in fig. 1A. It should be understood that the number and shape of the base members 10a-10d are for illustration purposes only. The larger size divided package substrate is formed by combining or stitching smaller size substrate components 10a-10d in embodiments of the present invention.
According to an embodiment of the invention, the four substrate parts 10a-10d are physically separated from each other. According to one embodiment, each of the four substrate parts 10a-10d may have dimensions, for example, between 30mm x 30mm and 40mm x 40 mm. By employing a substrate member (or substrate partition, substrate portion) of smaller size, the reliability and design flexibility of the semiconductor package structure can be improved and the production cost can be reduced. The partitioned package substrate 10 also improves package warpage issues. In one embodiment, the size of the integrated circuit die 20 is large, which requires a large-sized substrate to mount the large-sized integrated circuit die 20. However, the yield of the large-size substrate is extremely low, and warpage is likely to occur. In the embodiment of the invention, at least two substrate components with smaller sizes are adjacently arranged to form the separated packaging substrate with larger sizes. The yield rate of the manufacturing process is greatly improved, and the stress concentration can be reduced in the mode, so that the warping is effectively improved. Wherein at least two of the substrate components may be package substrates.
According to an embodiment of the invention, the four base plate parts 10a-10d are rearranged and adjoined together with a gap G therebetween. According to an embodiment of the invention, the four substrate parts 10a-10d may be abutted side by side or glued together, for example, by using an adhesive or a molding compound filled into the gap G. For example, in embodiments of the present invention, the gap G may have a width of between 1-3mm. In one embodiment of the invention, the integrated circuit die 20 is disposed across at least two substrate components; alternatively, the integrated circuit die 20 spans (or spans) at least one gap G. In this way, the integrated circuit die 20 can be utilized to electrically and mechanically connect the substrate components, so that the divided packaging substrate is more stable and is less prone to cracking or falling off. In one embodiment, the integrated circuit die 20 overlaps at least two substrate components in a top view. In the embodiment of the present invention, at least two substrate components form a larger-sized divided package substrate, and the integrated circuit die 20 is mounted on the divided package substrate and can help the at least two substrate components to be more stably adjacent to each other, so that the integrated circuit die 20 and the divided package substrate are mutually matched in the embodiment of the present invention, thereby not only improving the yield of substrate manufacturing, but also remarkably improving the overall mechanical strength and mechanical stability of the semiconductor package structure. The mode of the embodiment of the invention is particularly suitable for large-size integrated circuit crystal grains, and the large-size integrated circuit crystal grains have higher strength and are easier to stably fix a plurality of substrate components. In one embodiment, the integrated circuit die 20 may overlap three substrate components in a top view, thereby enabling more balanced forces between the substrate components, maintaining the force balance and stability of the semiconductor package structure. In one embodiment, the integrated circuit die 20 may overlap four substrate components in a top view, thereby enabling more balanced forces between the substrate components and maintaining the force balance and stability of the semiconductor package structure. In one embodiment, the center position of the integrated circuit die 20 may be substantially the same as the center position of the singulated package substrate, thereby ensuring the overall mechanical strength and robustness of the semiconductor package structure. In addition, in the embodiment of the present invention, the width of the gap G is designed to be between 1 and 3mm to achieve a balance of adhesive strength between the substrate portions, bonding stability between each other, and overall stability. If the gap G is too small, the adhesion between the substrate members may be unstable, and if the gap G is too large, the mechanical strength of the entire divided package substrate may be insufficient. The inventors have thus devised that the width of the gap G is between 1-3mm to achieve adequate bonding strength of the substrate components and that the mechanical strength of the whole package substrate after bonding is satisfactory. Therefore, the above-mentioned mode of the embodiment of the invention optimizes the mechanical performance, electrical connection, structural stability and the like of the semiconductor packaging structure from various aspects, and improves the overall performance of the semiconductor packaging structure under the condition of improving the production yield.
According to an embodiment of the invention, the four substrate parts 10a-10d may be homogeneous (homogeneous) bases. For example, the four substrate members 10a-10d may be composed of substantially the same substrate material (e.g., BT (Bismaleimide Triazine, bismaleimide triazine) substrate or ABF (Aromatic Benzocyclobutene Film, aromatic benzocyclobutane film) substrate). According to another embodiment of the invention, the four substrate components 10a-10d may be heterogeneous substrates. For example, the four substrate members 10a to 10d may be composed of different substrate materials, such as a glass substrate, a ceramic substrate, a BT substrate, an ABF substrate, or the like. According to an embodiment of the invention, the four substrate parts 10a-10d may have substantially the same thickness. According to an embodiment of the invention, the four substrate parts 10a-10d may have different thicknesses.
According to an embodiment of the present invention, each of the four substrate components 10a-10d may include an interconnect structure 101, the interconnect structure 101 being used to electrically connect the integrated circuit die 20 to a corresponding solder ball SB mounted on the second surface S2 of the divided packaging substrate 10. According to an embodiment of the invention, the interconnect structures 101 of the four substrate members 10a-10d may be identical or similar to each other. The interconnect structures 101 of the four substrate components 10a-10d may be different from each other according to embodiments of the invention.
According to an embodiment of the present invention, the semiconductor package 1 may further include at least one die 30 flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to an embodiment of the present invention, the die 30 may overlap at least two of the four substrate members 10a-10 d. For example, in fig. 1A, the die 30a is disposed between the substrate members 10a and 10b, and the die 30b is disposed between the substrate members 10c and 10 d. Die 30 may be a dummy die (dummy die) that does not contain active integrated circuit elements, according to embodiments of the invention. The dummy die is used to bridge or interconnect two adjacent substrate components. Thereby improving signal transmission efficiency between the substrate parts. According to another embodiment of the invention, die 30 may include a memory die such as a high bandwidth memory (high bandwidth memory, HBM) die.
According to some embodiments, the semiconductor package 1 may further include an integrated circuit die 40 and an electronic device 50, such as a decoupling capacitor mounted on the first surface S1 of the divided package substrate 10. The integrated circuit die 40 and the electronic device 50 may not overlap the gap G. Thereby improving the stability of the integrated circuit die 40 and the electronic device 50 after being mounted and ensuring the stability of the overall structure.
Please refer to fig. 2A and fig. 2B. Fig. 2A is a schematic diagram illustrating an exemplary semiconductor package according to another embodiment of the present invention, wherein like regions, layers or elements are designated by like numerals or labels. Fig. 2B is a cross-sectional view taken along line II-II' in fig. 2A. As shown in fig. 2A and 2B, as such, the semiconductor package 2 includes a divided package substrate 10 and at least one integrated circuit die 20 mounted on a first surface S1 of the divided package substrate 10. The first surface S1 of the divided packaging substrate 10 is a flat surface. According to one embodiment, for example, at least one integrated circuit die 20 may be flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to one embodiment, at least one integrated circuit die 20 is electrically connected to the partitioned package substrate 10 through a plurality of conductive elements 201, such as micro-bumps, copper bumps, or copper pillars, but is not limited thereto. The underfill 210 may be filled into a space between the at least one integrated circuit die 20 and the first surface S1 of the divided packaging substrate 10. According to one embodiment, the divided packaging substrate 10 may have a thickness of, for example, 60 mm x 60 mm and 70 mm x 70 mm.
According to an embodiment of the present invention, the divided packaging substrate 10 is composed of at least two substrate parts arranged in a side-by-side manner. For example, four substrate members 10a to 10d coplanar with each other are illustrated in fig. 2A. It should be understood that the number and shape of the substrates 10a-10d are for illustration purposes only.
According to an embodiment of the invention, the four substrate parts 10a-10d are physically separated from each other. According to one embodiment, each of the four substrate parts 10a-10d may have dimensions, for example, between 30mm x 30mm and 40mm x 40 mm. According to an embodiment of the invention, the four base plate parts 10a-10d are rearranged and adjoined together with a gap G therebetween. According to an embodiment of the invention, the four substrate parts 10a-10d may be abutted side by side or glued together, for example, by using an adhesive or a molding compound filled into the gap G. For example, in embodiments of the present invention, the gap G may have a width of between 1-3mm.
According to an embodiment of the invention, the four substrate parts 10a-10d may be homogenous (or homogeneous) substrates. For example, the four substrate members 10a-10d may be composed of substantially the same substrate material (e.g., a BT substrate or an ABF substrate). According to another embodiment of the invention, the four substrate parts 10a-10d may be heterogeneous substrates. For example, the four substrate members 10a to 10d may be composed of different substrate materials, such as a glass substrate, a ceramic substrate, a BT substrate, an ABF substrate, or the like. According to an embodiment of the invention, the four substrate parts 10a-10d may have substantially the same thickness. According to an embodiment of the invention, the four substrate parts 10a-10d may have different thicknesses.
According to an embodiment of the invention, each of the four substrate components 10a_10d may comprise an interconnect structure 101 for electrically connecting the integrated circuit die 20 to a respective solder ball SB mounted on the second surface S2 of the partitioned package substrate 10. According to an embodiment of the invention, the interconnect structures 101 of the four substrate members 10a-10d may be identical or similar to each other. The interconnect structures 101 of the four substrate components 10a-10d may be different from each other according to embodiments of the invention.
According to an embodiment of the present invention, the semiconductor package 2 may further include at least one die 30 flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to an embodiment of the present invention, the die 30 may overlap at least two of the four substrate members 10a-10 d. For example, in fig. 1A, the die 30a is disposed between the substrate members 10a and 10b, and the die 30b is disposed between the substrate members 10c and 10 d. Die 30 may be a dummy die that does not contain active integrated circuit elements, according to an embodiment of the invention. The dummy die is used to bridge or interconnect two adjacent substrate components. According to another embodiment of the invention, die 30 may comprise a memory die such as a High Bandwidth Memory (HBM) chip. In one embodiment, die 30a spans at least two substrate components (e.g., substrate components 10a and 10 b), and die 30a spans gap G between substrate components 10a and 10 b. This makes it possible to use not only the die 30a as a functional die or a bridging die, but also the die 30a as a mechanical connection member between the substrate members 10c and 10d, increasing connection reliability and stability between the substrate members. In one embodiment, die 30b spans at least two substrate components (e.g., substrate components 10c and 10 d) and die 30a spans gap G between substrate components 10c and 10 d. This makes it possible to use not only the die 30a as a functional die or a bridging die, but also the die 30a as a mechanical connection member between the substrate members 10c and 10d, increasing connection reliability and stability between the substrate members. In one embodiment, other dies may also be provided, such as dies that span the gap G between the substrate members 10a and 10d, dies that span the gap G between the substrate members 10b and 10c, and so on. The use of die 30 will thereby further increase the robustness and mechanical strength of the partitioned package substrate.
According to an embodiment of the present invention, the semiconductor package 2 may further include a ring-shaped frame 60 mounted on the first surface Sl of the divided package substrate 10. According to an embodiment of the present invention, the frame 60 may be a metal frame, but is not limited thereto, and for example, the frame 60 may be a non-metal material such as a resin. According to an embodiment of the present invention, the frame 60 may be attached to the first surface S1 of the divided packaging substrate 10 by using the bonding bump 601. According to some embodiments, the frame 60 may be attached to the first surface S1 of the divided packaging substrate 10 by using an adhesive. Frame 60 may include an opening 60a for receiving integrated circuit die 20, die 30a, and die 30 b. Integrated circuit die 20, die 30a, and die 30b may be surrounded by a frame 60. The frame 60 may be connected with the divided packaging substrate 10 by using bonding bumps 601, wherein the bonding bumps 601 may be provided on each substrate part, and one or more bonding bumps 601 may be provided on each substrate part, respectively. This not only facilitates manufacturing and bonding, but also further improves the stability of the abutment between the substrate components and the overall mechanical strength of the package after the frame 60 is installed, greatly improving the overall stability of the package. The provision of the bonding bumps 601 further enhances design flexibility, for example, other dies or electronic devices (e.g., capacitors, resistors, etc.) may be provided on the singulated package substrate 10 for electrical and mechanical connection through the bonding bumps 601. The bonding bump 601 is easy to manufacture, and the convenience of connection and stability of connection are better, and by matching the above-mentioned manner of overlapping the integrated circuit die 20 with at least two substrate components according to the embodiment of the present invention, the mechanical strength of the adjacent and encapsulated structure between the substrate components can be greatly improved, and the warpage can be further improved.
Please refer to fig. 3A and 3B. Fig. 3A is a schematic diagram illustrating an exemplary semiconductor package according to yet another embodiment of the present invention, wherein like regions, layers or elements are designated by like numerals or labels. Fig. 3B is a cross-sectional view taken along line III-III' in fig. 3A. As shown in fig. 3A and 3B, as such, the semiconductor package 3 includes a divided package substrate 10 and at least one integrated circuit die 20 mounted on a first surface S1 of the divided package substrate 10. S1 of the divided packaging substrate 10 is a flat surface. According to one embodiment, for example, at least one integrated circuit die 20 may be flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to one embodiment, at least one integrated circuit die 20 is electrically connected to the partitioned package substrate 10 through a plurality of conductive elements 201, such as micro-bumps, copper bumps, or copper pillars, but is not limited thereto. The underfill 210 may be filled into a space between the at least one integrated circuit die 20 and the first surface S1 of the divided packaging substrate 10. According to one embodiment, the divided packaging substrate 10 may have a thickness of, for example, 60 mm x 60 mm and 70 mm x 70 mm.
According to an embodiment of the present invention, the divided packaging substrate 10 is composed of at least two substrate parts arranged in a side-by-side manner. For example, four substrate members 10a to 10d coplanar with each other are illustrated in fig. 3A. It should be understood that the number and shape of the substrates 10a-10d are for illustration purposes only.
According to an embodiment of the invention, the four substrate parts 10a-10d are physically separated from each other. According to one embodiment, each of the four substrate parts 10a-10d may have dimensions, for example, between 30mm x 30mm and 40mm x 40 mm. According to an embodiment of the invention, the four base plate parts 10a-10d are rearranged and adjoined together with a gap G therebetween. According to an embodiment of the invention, the four substrate parts 10a-10d may be abutted side by side or glued together, for example, by using an adhesive or a molding compound filled into the gap G. For example, in the present invention, the width of the gap G may be between 1-3mm.
According to an embodiment of the invention, the four substrate parts 10a-10d may be homogeneous bases. For example, the four substrate members 10a-10d may be composed of substantially the same substrate material (e.g., a BT substrate or an ABF substrate). According to another embodiment of the invention, the four substrate parts 10a-10d may be heterogeneous substrates. For example, the four substrate members 10a to 10d may be composed of different substrate materials, such as a glass substrate, a ceramic substrate, a BT substrate, an ABF substrate, or the like. According to an embodiment of the invention, the four substrate parts 10a-10d may have substantially the same thickness. According to an embodiment of the invention, the four substrate parts 10a-10d may have different thicknesses.
According to an embodiment of the present invention, each of the four substrate components 10a-10d may include an interconnect structure 101 for electrically connecting the integrated circuit die 20 to a corresponding solder ball SB mounted on the second surface S2 of the singulated package substrate 10. According to an embodiment of the invention, the interconnect structures 101 of the four substrate members 10a-10d may be identical or similar to each other. The interconnect structures 101 of the four substrate components 10a-10d may be different from each other according to embodiments of the invention.
According to an embodiment of the present invention, the semiconductor package 3 may further include at least one die 30 flip-chip mounted on the first surface S1 of the divided packaging substrate 10. According to an embodiment of the present invention, the die 30 may overlap at least two of the four substrate members 10a-10 d. For example, in fig. 1A, the die 30a is disposed between the substrate members 10a and 10b, and the die 30b is disposed between the substrate members 10c and 10 d. Die 30 may be a dummy die that does not contain active integrated circuit elements, according to an embodiment of the invention. The dummy die is used to bridge or interconnect two adjacent substrate components. According to another embodiment of the invention, die 30 may comprise a memory die such as a High Bandwidth Memory (HBM) die.
According to some embodiments, the semiconductor package 3 may further include an integrated circuit die 40 and an electronic device 50, such as a decoupling capacitor mounted on the first surface Sl of the divided package substrate 10. The integrated circuit die 40 and the electronic device 50 may not overlap the gap G. Thus, the mounting stability of the integrated circuit die 40 and the electronic device 50 is better, and the integrated circuit die 40 and the electronic device 50 are more stable.
According to an embodiment of the present invention, the semiconductor package 3 may further include a cover (lid) 70 mounted on the first surface S1 of the divided package substrate 10. According to an embodiment of the invention, integrated circuit die 20, die 30a, die 30b, integrated circuit die 40, and electronic device 50 may be housed by a lid 70 and may be encapsulated by a molded cap (mold cap) 80.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of another embodiment of the present invention. As shown in fig. 4, a redistribution layer (re-distribution layer, RDL) structure 90 may be disposed on the first surface S1 of the singulated package substrate 10. Integrated circuit die 20 is mounted on RDL structure 90. The integrated circuit die 20 is electrically connected to the respective solder balls SB mounted on the second surface S2 of the divided package substrate 10 through the RDL structure 90 and the divided package substrate 10.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). The scope of the appended claims is therefore to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (11)

1. A semiconductor package, comprising:
a divided package substrate composed of a plurality of substrate parts arranged side by side;
at least one integrated circuit die mounted on the first surface of the partitioned package substrate; and
and a solder ball mounted on a second surface of the divided packaging substrate opposite to the first surface.
2. The semiconductor package of claim 1, wherein the at least one integrated circuit die is electrically connected to the partitioned package substrate by conductive elements.
3. The semiconductor package of claim 1, wherein the plurality of substrate components are physically separated from one another, the plurality of substrate components are rearranged and abutted together with a gap therebetween, the plurality of substrate components being abutted together using an adhesive filled into the gap.
4. A semiconductor package according to claim 3, wherein the gap has a width in the range of 1-3mm.
5. The semiconductor package of claim 1, wherein the plurality of substrate components are homogenous substrates or heterogeneous substrates, the plurality of substrate components having the same thickness or different thicknesses.
6. The semiconductor package of claim 1, further comprising:
at least one die flip-chip mounted on the first surface of the divided packaging substrate;
wherein the at least one die spans at least two substrate members.
7. The semiconductor package of claim 6, wherein the at least one die is a dummy die or a memory die.
8. The semiconductor package of claim 3, further comprising:
a second integrated circuit die; and
and an electronic device mounted on the first surface of the divided packaging substrate.
9. The semiconductor package of claim 8, wherein the second integrated circuit die and the electronic device do not overlap the gap.
10. The semiconductor package of claim 1, further comprising:
and a frame mounted on the first surface of the divided packaging substrate.
11. The semiconductor package of claim 10, wherein the frame is attached to the first surface of the divided package substrate using bonding bumps or an adhesive.
CN202310896462.5A 2022-08-01 2023-07-20 Semiconductor package Pending CN117497506A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/369,980 2022-08-01
US18/215,830 US20240038647A1 (en) 2022-08-01 2023-06-29 Semiconductor package using substrate block integration
US18/215,830 2023-06-29

Publications (1)

Publication Number Publication Date
CN117497506A true CN117497506A (en) 2024-02-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310896462.5A Pending CN117497506A (en) 2022-08-01 2023-07-20 Semiconductor package

Country Status (1)

Country Link
CN (1) CN117497506A (en)

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