CN117497506A - Semiconductor packaging - Google Patents

Abstract

The invention discloses a semiconductor package, comprising: a divided package substrate composed of a plurality of substrate parts arranged side by side; at least one integrated circuit die mounted on the first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface. The plurality of substrate components form the divided packaging substrate with larger size, and the integrated circuit die is arranged on the divided packaging substrate and can help the plurality of substrate components to be more stably adjacent together, so that the integrated circuit die and the divided packaging substrate are mutually matched, thereby not only improving the yield of substrate manufacture, but also remarkably improving the integral mechanical strength and mechanical stability of the semiconductor packaging structure.

Description

Semiconductor packaging

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor package.

Background technique

As more consumers embrace smart devices, demand for network data centers, IoT, smart sensors, and more continues to grow. To meet these demands, semiconductor design companies are encountering challenges with chip design complexity and PPA (power, performance, area) factors in lower geometries such as 7nm, 5nm and 3nm.

Advanced packaging plays an increasing role throughout the semiconductor industry. Applications such as network equipment, servers and smartphones use advanced packaging. In order to advance the design, IC suppliers developed ASIC (ApplicationSpecific Integrated Circuit, Application Specific Integrated Circuit). Vendors then shrink and package the different functions of each node onto an ASIC. But this approach becomes increasingly complex and expensive at each node.

For example, ASICs used in switching routers or data centers may include large dies and package sizes may typically exceed 4500 mm ² , which results in lower production yields for package substrates of this size. The cost of packaging increases. Large-die ASIC packages also encounter warpage issues.

Contents of the invention

In view of this, the present invention provides an improved large-die semiconductor package using substrate block integration (SBI) to solve the above problems.

According to a first aspect of the present invention, a semiconductor package is disclosed, including:

A divided packaging substrate consists of multiple substrate components arranged side by side;

At least one integrated circuit die mounted on the first surface of the separated packaging substrate; and

Solder balls are mounted on a second surface of the separated packaging substrate opposite to the first surface.

Further, the at least one integrated circuit die is electrically connected to the separated packaging substrate through a conductive element. Thereby, at least one integrated circuit die is electrically connected to the separated packaging substrate, and at least one integrated circuit die is electrically connected to a plurality of substrate components, and the at least one integrated circuit die is mechanically and electrically connected to the number of substrate components. Can be greater than or equal to two.

Further, the conductive elements include micro-bumps, copper bumps or copper pillars. Provides more stable mechanical and electrical connections between integrated circuit dies and multiple substrate components.

Further, the plurality of substrate components are physically separated from each other. As a result, a plurality of smaller substrate components are spliced together to form a larger separated packaging substrate.

Further, the plurality of substrate components are rearranged and adjacent to each other with gaps between the plurality of substrate components. As a result, a plurality of smaller substrate components are spliced together to form a larger separated packaging substrate.

Further, the plurality of substrate components are adjacent together by using an adhesive filled in the gap. In this way, multiple separated substrate components are spliced and integrated to form a larger separated packaging substrate.

Further, the width of the gap ranges from 1 to 3 mm. The appropriate gap width between the substrate components not only ensures the firmness and mechanical stability of the bonding between the substrate components, but also prevents accidental detachment between the substrate components.

Further, the plurality of substrate components are homogeneous substrates or heterogeneous substrates. This facilitates the manufacturing of substrate components and improves the flexibility of splicing and combination.

Further, the plurality of substrate components have the same thickness or different thicknesses. This facilitates the manufacturing of substrate components and improves the flexibility of splicing and combination.

Furthermore, it also includes:

At least one die is mounted on the first surface of the separated packaging substrate in a flip-chip manner. This increases design flexibility.

Further, the at least one die is a dummy die or a memory die. This increases design flexibility.

Furthermore, it also includes:

the second integrated circuit die; and

An electronic device is mounted on the first surface of the separated packaging substrate. This increases design flexibility.

Further, the electronic device includes a decoupling capacitor. This increases design flexibility.

Further, the second integrated circuit die and the electronic device do not overlap the gap. This ensures the installation stability of the second integrated circuit die and the electronic device.

Furthermore, it also includes:

An annular frame is installed on the first surface of the separated packaging substrate. The frame improves connection stability between multiple substrate components while increasing the overall mechanical strength of the package structure.

Further, the frame is a metal frame. To provide a more stable support structure for multiple substrate components.

Further, the frame is attached to the first surface of the separated packaging substrate using bonding bumps or adhesive. The use of bonding bump connections can improve the heat dissipation capacity from the substrate to the frame, facilitate manufacturing and forming, and make the connection more reliable and stable. Using adhesive connections will make manufacturing easier.

Further, the frame includes an opening for accommodating the at least one integrated circuit die. To protect the integrated circuit die and improve the strength of the overall structure.

Furthermore, it also includes:

A cover is mounted on the first surface of the divided packaging substrate, wherein the at least one integrated circuit die is received by the cover and encapsulated by the mold cap. Thereby improving the heat dissipation and mechanical strength of the packaging structure.

Furthermore, it also includes:

A redistribution layer structure is located on the first surface of the separated packaging substrate, wherein the at least one integrated circuit die is mounted on the redistribution layer structure. To improve layout design and die installation flexibility.

The semiconductor package of the present invention includes: a separated packaging substrate, which is composed of a plurality of substrate components arranged side by side; at least one integrated circuit die installed on the first surface of the divided packaging substrate; and a solder ball installed on on a second surface of the separated packaging substrate opposite to the first surface. In the present invention, multiple substrate components form a larger-sized separated packaging substrate, and the integrated circuit die is installed on the separated packaging substrate and can help the multiple substrate components to be more stably adjacent together. Therefore, the integrated circuit die in the present invention The cooperation between the particles and the separated packaging substrate not only improves the yield of substrate manufacturing, but also significantly improves the overall mechanical strength and mechanical stability of the semiconductor packaging structure.

Description of drawings

1A is a schematic diagram illustrating an exemplary semiconductor package according to an embodiment of the present invention;

Figure 1B is a cross-sectional view taken along line I-I' in Figure 1A;

2A is a schematic diagram illustrating an exemplary semiconductor package according to another embodiment of the present invention;

Figure 2B is a cross-sectional view taken along line II-II' in Figure 2A;

3A is a schematic diagram illustrating an exemplary semiconductor package according to yet another embodiment of the present invention;

Figure 3B is a cross-sectional view taken along line III-III' in Figure 3A; and

4 is a schematic cross-sectional view showing another embodiment of the present invention.

Detailed ways

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof and which illustrate by way of illustration certain preferred embodiments in which the invention may be practiced. . These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and structural changes may be made without departing from the spirit and scope of the invention. and procedural changes. this invention. Accordingly, the following detailed description is not to be construed as limiting, and the scope of embodiments of the invention is defined only by the appended claims. The drawings described are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.

It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, layers and/or portions shall not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a secondary or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.

In addition, for convenience of description, terms such as “below”, “under”, “below”, “above”, “between” may be used herein. Spatially relative terms such as "on" to describe the relationship of a component or feature to it. Another component or feature as shown in a figure. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean ±20% of the stated value, or ±10% of the stated value, or ±5% of the stated value, or ±3% of the stated value , or within the range of ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The values specified in this invention are approximate. When not specifically described, stated values include the meanings of "about," "approximately," and "approximately." The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a", "an" and "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when a "component" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent" another component or layer, it can be directly on the other component or layer Intermediate components or layers may be present on, connected to, coupled to, or adjacent thereto. In contrast, when a component is referred to as being "directly on," "directly connected to," "directly coupled to" or "immediately adjacent" another component or layer, there are no intervening components or layers present.

Note: (i) like features will be designated by the same reference numerals throughout the Figures and will not necessarily be described in detail in every Figure in which they appear, and (ii) a series of Figures may show a single item Each aspect is associated with various reference labels that may appear throughout the sequence, or may appear only in selected plots of the sequence.

Please refer to Figure 1A and Figure 1B. 1A is a schematic diagram illustrating an exemplary semiconductor package according to an embodiment of the present invention. Fig. 1B is a cross-sectional view taken along line I-I' in Fig. 1A. As shown in FIGS. 1A and 1B , the semiconductor package 1 includes a partitioned packaging substrate 10 and at least one integrated circuit die 20 mounted on a first surface S1 of the partitioned packaging substrate 10 . According to one embodiment, the first surface S1 of the separated (or separated, partitioned, partitioned) packaging substrate 10 is a flat surface. According to one embodiment, for example, at least one integrated circuit die 20 may be mounted on the first surface S1 of the separated packaging substrate 10 in a flip-chip manner. According to one embodiment, at least one integrated circuit die 20 is electrically connected to the separated packaging substrate 10 through a plurality of conductive elements 201 such as micro-bumps, copper bumps or copper pillars, but is not limited thereto. The underfill 210 may be filled into the space between the at least one integrated circuit die 20 and the first surface S1 of the separated package substrate 10 . According to one embodiment, the divided packaging substrate 10 may have dimensions of, for example, 60 mm x 60 mm and 70 mm x 70 mm.

According to an embodiment of the present invention, the divided packaging substrate 10 consists of at least two smaller substrates (hereinafter referred to as substrate parts (or substrate partitions, substrate parts)) arranged side by side. For example, FIG. 1A illustrates four coplanar substrate members 10a to 10d. It should be understood that the number and shape of substrate components 10a-10d are for illustrative purposes only. In the embodiment of the present invention, smaller-sized substrate components 10a-10d are combined or spliced to form a larger-sized separated packaging substrate.

According to an embodiment of the present invention, the four substrate components 10a-10d are physically separated from each other. According to one embodiment, each of the four base plate components 10a-10d may have dimensions, for example, between 30 mm x 30 mm and 40 mm x 40 mm. By using smaller substrate components (or substrate partitions, substrate sections), the reliability and design flexibility of the semiconductor packaging structure can be improved, and production costs can be reduced. The separated package substrate 10 also improves package warpage issues. In one embodiment, the size of the integrated circuit die 20 is relatively large, which requires a large-size substrate to mount the large-size integrated circuit die 20 . However, the yield rate of manufacturing large-size substrates is extremely low, and problems such as warpage are prone to occur. In the embodiment of the present invention, at least two substrate components with smaller sizes are arranged adjacently to form a separated packaging substrate with larger sizes. The yield of manufacturing in this way will be greatly improved, and this method can reduce stress concentration and effectively improve warpage. At least two of the substrate components may be package substrates.

According to an embodiment of the present invention, the four substrate components 10a-10d are rearranged and abutted together with a gap G therebetween. According to an embodiment of the present invention, the four substrate members 10a - 10d may be adjacent or glued together side by side by using an adhesive or molding compound filled into the gap G, for example. For example, in the embodiment of the present invention, the width of the gap G may be between 1-3 mm. In one embodiment of the present invention, the integrated circuit die 20 is disposed across at least two substrate components; or, the integrated circuit die 20 spans (or spans) at least one gap G. In this way, the integrated circuit die 20 can be used to provide electrical and mechanical connections between substrate components, thereby making the separated packaging substrate more stable and less prone to problems such as cracking or falling off. In one embodiment, integrated circuit die 20 overlaps at least two substrate components in a top view. In the embodiment of the present invention, at least two substrate components form a larger-sized separated packaging substrate, and the integrated circuit die 20 is installed on the separated packaging substrate and can help the at least two substrate components to be more stably adjacent together, thereby In the embodiment of the present invention, the integrated circuit die 20 and the separated packaging substrate cooperate with each other, thereby not only improving the yield rate of substrate manufacturing, but also significantly improving the overall mechanical strength and mechanical stability of the semiconductor packaging structure. The above methods of the embodiments of the present invention are particularly suitable for large-sized integrated circuit chips. Larger-sized integrated circuit chips have higher strength and are easier to stably fix multiple substrate components. In one embodiment, in a top view, the integrated circuit die 20 can overlap with three substrate components, thereby making the forces between the substrate components more balanced and maintaining the force balance and stability of the semiconductor packaging structure. In one embodiment, in a top view, the integrated circuit die 20 can overlap four substrate components, thereby making the forces between the substrate components more balanced and maintaining the force balance and stability of the semiconductor packaging structure. In one embodiment, the center position of the integrated circuit die 20 may be approximately the same as the center position of the separated packaging substrate, thereby ensuring the overall mechanical strength and stability of the semiconductor packaging structure. In addition, in the embodiment of the present invention, the width of the designed gap G is between 1 and 3 mm to achieve a balance between the bonding strength between the substrate parts, the stability of the mutual combination, and the overall stability. If the gap G is too small, the bonding between substrate components may be unstable. If the gap G is too large, the overall mechanical strength of the separated packaging substrate may be insufficient. Therefore, the inventor designed the width of the gap G to be between 1 and 3 mm, so as to achieve sufficient bonding strength of the substrate components and to meet the requirements for the overall mechanical strength of the separated packaging substrate after bonding. Therefore, the above-mentioned methods of the embodiments of the present invention optimize the mechanical properties, electrical connections, structural stability, etc. of the semiconductor packaging structure from all aspects, and improve the overall performance of the semiconductor packaging structure while improving the production yield.

According to embodiments of the present invention, the four substrate components 10a-10d may be homogeneous substrates. For example, the four substrate components 10a - 10d may be made of substantially the same substrate material (such as a BT (Bismaleimide Triazine) substrate or an ABF (Aromatic Benzocyclobutene Film) substrate). )composition. According to another embodiment of the present invention, the four substrate components 10a-10d may be heterogeneous substrates. For example, the four substrate components 10a-10d may be composed of different substrate materials, such as glass substrate, ceramic substrate, BT substrate, ABF substrate, etc. According to embodiments of the present invention, the four substrate members 10a-10d may have substantially the same thickness. According to embodiments of the present invention, the four substrate components 10a-10d may have different thicknesses.

According to embodiments of the present invention, each of the four substrate components 10a - 10d may include an interconnect structure 101 for electrically connecting the integrated circuit die 20 to a second die mounted on the divided package substrate 10 The corresponding solder ball SB on surface S2. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be the same or similar to each other. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be different from each other.

According to an embodiment of the present invention, the semiconductor package 1 may further include at least one die 30 mounted in a flip-chip manner on the first surface S1 of the divided package substrate 10 . According to embodiments of the present invention, die 30 may overlap at least two of the four substrate components 10a-10d. For example, in FIG. 1A , die 30 a is disposed between substrate members 10 a and 10 b, and die 30 b is disposed between substrate members 10 c and 10 d. According to embodiments of the present invention, die 30 may be a dummy die that does not contain active integrated circuit components. Dummy dies are used to bridge or interconnect two adjacent substrate components. This improves signal transmission efficiency between substrate components. According to another embodiment of the present invention, die 30 may include a memory die such as a high bandwidth memory (HBM) die.

According to some embodiments, the semiconductor package 1 may further include an integrated circuit die 40 and an electronic device 50 such as a decoupling capacitor mounted on the first surface S1 of the separated package substrate 10 . Integrated circuit die 40 and electronic devices 50 may not overlap gap G. This improves the stability of the integrated circuit die 40 and the electronic device 50 after installation, ensuring the stability of the overall structure.

Please refer to Figure 2A and Figure 2B. 2A is a schematic diagram illustrating an exemplary semiconductor package according to another embodiment of the present invention, in which similar regions, layers or elements are designated by similar numbers or labels. Fig. 2B is a cross-sectional view taken along line II-II' in Fig. 2A. As shown in FIGS. 2A and 2B , similarly, the semiconductor package 2 includes a separated packaging substrate 10 and at least one integrated circuit die 20 mounted on the first surface S1 of the separated packaging substrate 10 . The first surface S1 of the separated packaging substrate 10 is a flat surface. According to one embodiment, for example, at least one integrated circuit die 20 may be flip-chip mounted on the first surface S1 of the separated packaging substrate 10 . According to one embodiment, at least one integrated circuit die 20 is electrically connected to the separated packaging substrate 10 through a plurality of conductive elements 201 such as micro-bumps, copper bumps or copper pillars, but is not limited thereto. The underfill 210 may be filled into the space between the at least one integrated circuit die 20 and the first surface S1 of the separated package substrate 10 . According to one embodiment, the divided packaging substrate 10 may have dimensions of, for example, 60 mm x 60 mm and 70 mm x 70 mm.

According to an embodiment of the present invention, the divided packaging substrate 10 consists of at least two substrate components arranged side by side. For example, FIG. 2A illustrates four coplanar substrate members 10a to 10d. It should be understood that the number and shape of substrates 10a-10d are for illustrative purposes only.

According to an embodiment of the present invention, the four substrate components 10a-10d are physically separated from each other. According to one embodiment, each of the four base plate components 10a-10d may have dimensions, for example, between 30 mm x 30 mm and 40 mm x 40 mm. According to an embodiment of the invention, the four substrate components 10a-10d are rearranged and abutted together with a gap G therebetween. According to an embodiment of the present invention, the four substrate members 10a - 10d may be adjacent or glued together side by side by using an adhesive or molding compound filled into the gap G, for example. For example, in the embodiment of the present invention, the width of the gap G may be between 1-3 mm.

According to embodiments of the present invention, the four substrate components 10a-10d may be homogeneous (or homogeneous) substrates. For example, the four substrate components 10a-10d may be composed of substantially the same substrate material (eg, a BT substrate or an ABF substrate). According to another embodiment of the invention, the four substrate components 10a-10d may be heterogeneous substrates. For example, the four substrate components 10a-10d may be composed of different substrate materials, such as glass substrate, ceramic substrate, BT substrate, ABF substrate, etc. According to embodiments of the present invention, the four substrate members 10a-10d may have substantially the same thickness. According to embodiments of the present invention, the four substrate components 10a-10d may have different thicknesses.

According to embodiments of the present invention, each of the four substrate components 10a-10d may include an interconnect structure 101 for electrically connecting the integrated circuit die 20 to a corresponding solder mount mounted on the second surface S2 of the compartmentalized package substrate 10. Ball SB. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be the same or similar to each other. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be different from each other.

According to an embodiment of the present invention, the semiconductor package 2 may further include at least one die 30 mounted in a flip-chip manner on the first surface S1 of the separated package substrate 10 . According to embodiments of the present invention, die 30 may overlap at least two of the four substrate components 10a-10d. For example, in FIG. 1A , die 30 a is disposed between substrate members 10 a and 10 b, and die 30 b is disposed between substrate members 10 c and 10 d. According to embodiments of the present invention, die 30 may be a dummy die that does not contain active integrated circuit elements. Dummy dies are used to bridge or interconnect two adjacent substrate components. According to another embodiment of the invention, die 30 may include a memory die such as a high bandwidth memory (HBM) chip. In one embodiment, die 30a spans at least two substrate components (eg, substrate components 10a and 10b), with die 30a spanning the gap G between substrate components 10a and 10b. In this way, not only can the die 30a be used as a functional die or a bridge die, but the die 30a can also be used as a mechanical connection component between the substrate components 10c and 10d, thereby increasing the connection reliability and stability between the substrate components. In one embodiment, die 30b spans at least two substrate components (eg, substrate components 10c and 10d) and die 30a spans the gap G between substrate components 10c and 10d. In this way, not only can the die 30a be used as a functional die or a bridge die, but the die 30a can also be used as a mechanical connection component between the substrate components 10c and 10d, thereby increasing the connection reliability and stability between the substrate components. In one embodiment, other dies may also be provided, such as dies across the gap G between the substrate components 10a and 10d, dies across the gap G between the substrate components 10b and 10c, and so on. Therefore, using the die 30 will further improve the stability and mechanical strength of the separated packaging substrate.

According to an embodiment of the present invention, the semiconductor package 2 may further include an annular frame 60 mounted on the first surface S1 of the divided package substrate 10 . According to the embodiment of the present invention, the frame 60 may be a metal frame, but is not limited thereto. For example, the frame 60 may be made of non-metallic materials such as resin. According to an embodiment of the present invention, the frame 60 may be attached to the first surface S1 of the separated package substrate 10 by using bonding bumps 601 . According to some embodiments, the frame 60 may be attached to the first surface S1 of the separated packaging substrate 10 using an adhesive. Frame 60 may include opening 60a for receiving integrated circuit die 20, die 30a, and die 30b. Integrated circuit die 20 , die 30 a and die 30 b may be surrounded by frame 60 . The frame 60 may be connected to the divided package substrate 10 by using bonding bumps 601 , wherein the bonding bumps 601 may be provided on each substrate part, and one or more bonding bumps 601 may be respectively provided on each substrate part. This method not only facilitates manufacturing and joining, but also can further improve the adjacency stability between substrate components and the overall mechanical strength of the packaging structure after the frame 60 is installed, greatly improving the overall stability of the packaging structure. The arrangement of the bonding bumps 601 further improves the design flexibility. For example, other dies or electronic devices (such as capacitors, resistors, etc.) can be provided on the separated packaging substrate 10 to perform electrical and mechanical connections through the bonding bumps 601 . The bonding bump 601 is easy to manufacture, and the connection convenience and connection stability are better. With the above-mentioned method of overlapping the integrated circuit die 20 and at least two substrate components in the embodiment of the present invention, the connection between the substrate components can be greatly improved. The adjacency stabilizes and mechanically strengthens the package structure and further improves warpage.

Please refer to Figure 3A and Figure 3B. 3A is a schematic diagram illustrating an exemplary semiconductor package according to yet another embodiment of the present invention, in which similar regions, layers or elements are designated by similar numbers or labels. Fig. 3B is a cross-sectional view taken along line III-III' in Fig. 3A. As shown in FIGS. 3A and 3B , similarly, the semiconductor package 3 includes a separated packaging substrate 10 and at least one integrated circuit die 20 mounted on the first surface S1 of the separated packaging substrate 10 . S1 of the divided package substrate 10 is a flat surface. According to one embodiment, for example, at least one integrated circuit die 20 may be flip-chip mounted on the first surface S1 of the separated packaging substrate 10 . According to one embodiment, at least one integrated circuit die 20 is electrically connected to the separated packaging substrate 10 through a plurality of conductive elements 201 such as micro-bumps, copper bumps or copper pillars, but is not limited thereto. The underfill 210 may be filled into the space between the at least one integrated circuit die 20 and the first surface S1 of the separated package substrate 10 . According to one embodiment, the divided packaging substrate 10 may have dimensions of, for example, 60 mm x 60 mm and 70 mm x 70 mm.

According to an embodiment of the present invention, the divided packaging substrate 10 consists of at least two substrate components arranged side by side. For example, FIG. 3A illustrates four coplanar substrate members 10a to 10d. It should be understood that the number and shape of substrates 10a-10d are for illustrative purposes only.

According to an embodiment of the present invention, the four substrate components 10a-10d are physically separated from each other. According to one embodiment, each of the four base plate components 10a-10d may have dimensions, for example, between 30 mm x 30 mm and 40 mm x 40 mm. According to an embodiment of the invention, the four substrate components 10a-10d are rearranged and abutted together with a gap G therebetween. According to an embodiment of the present invention, the four substrate members 10a - 10d may be adjacent or glued together side by side by using an adhesive or molding compound filled into the gap G, for example. For example, in the present invention, the width of the gap G may be between 1-3 mm.

According to embodiments of the present invention, the four substrate components 10a-10d may be homogeneous substrates. For example, the four substrate components 10a-10d may be composed of substantially the same substrate material (eg, a BT substrate or an ABF substrate). According to another embodiment of the invention, the four substrate components 10a-10d may be heterogeneous substrates. For example, the four substrate components 10a-10d may be composed of different substrate materials, such as glass substrate, ceramic substrate, BT substrate, ABF substrate, etc. According to embodiments of the present invention, the four substrate members 10a-10d may have substantially the same thickness. According to embodiments of the present invention, the four substrate components 10a-10d may have different thicknesses.

According to an embodiment of the present invention, each of the four substrate components 10a - 10d may include an interconnect structure 101 for electrically connecting the integrated circuit die 20 to the second surface S2 mounted on the divided package substrate 10 Corresponding solder ball SB. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be the same or similar to each other. According to embodiments of the present invention, the interconnection structures 101 of the four substrate components 10a - 10d may be different from each other.

According to an embodiment of the present invention, the semiconductor package 3 may further include at least one die 30 mounted in a flip-chip manner on the first surface S1 of the divided package substrate 10 . According to embodiments of the present invention, die 30 may overlap at least two of the four substrate components 10a-10d. For example, in FIG. 1A , die 30 a is disposed between substrate members 10 a and 10 b, and die 30 b is disposed between substrate members 10 c and 10 d. According to embodiments of the present invention, die 30 may be a dummy die that does not contain active integrated circuit elements. Dummy dies are used to bridge or interconnect two adjacent substrate components. According to another embodiment of the present invention, die 30 may include a memory die such as a high bandwidth memory (HBM) die.

According to some embodiments, the semiconductor package 3 may also include an integrated circuit die 40 and an electronic device 50 such as a decoupling capacitor mounted on the first surface S1 of the separated package substrate 10 . Integrated circuit die 40 and electronic devices 50 may not overlap gap G. Therefore, the installation stability of the integrated circuit die 40 and the electronic device 50 is better, and the devices such as the integrated circuit die 40 and the electronic device 50 are more stable.

According to an embodiment of the present invention, the semiconductor package 3 may further include a lid 70 mounted on the first surface S1 of the divided package substrate 10 . In accordance with embodiments of the invention, integrated circuit die 20 , die 30 a , die 30 b , integrated circuit die 40 and electronic device 50 may be received by cover 70 and may be encapsulated by mold cap 80 .

Please refer to FIG. 4 , which is a schematic cross-sectional view of another embodiment of the present invention. As shown in FIG. 4 , a re-distribution layer (RDL) structure 90 may be disposed on the first surface S1 of the separated packaging substrate 10 . Integrated circuit die 20 is mounted on RDL structure 90 . The integrated circuit die 20 is electrically connected to each solder ball SB mounted on the second surface S2 of the separated package substrate 10 through the RDL structure 90 and the separated package substrate 10 .

While the invention has been described by way of example and in accordance with preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as will be apparent to those skilled in the art. Therefore, the scope of the appended claims is to be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims (11)

1. A semiconductor package, characterized in that it includes: A divided packaging substrate consists of multiple substrate components arranged side by side; At least one integrated circuit die mounted on the first surface of the separated packaging substrate; and Solder balls are mounted on a second surface of the separated packaging substrate opposite to the first surface. 2. The semiconductor package of claim 1, wherein the at least one integrated circuit die is electrically connected to the separated package substrate through a conductive element. 3. The semiconductor package of claim 1, wherein the plurality of substrate components are physically separated from each other, the plurality of substrate components are rearranged and adjacent to each other, and there is a gap between the plurality of substrate components. Gaps, the plurality of substrate components are abutted together using an adhesive filled in the gaps. 4. The semiconductor package according to claim 3, wherein the width of the gap ranges from 1 to 3 mm. 5. The semiconductor package according to claim 1, wherein the plurality of substrate components are homogeneous substrates or heterogeneous substrates, and the plurality of substrate components have the same thickness or different thicknesses. 6. The semiconductor package of claim 1, further comprising: At least one die is mounted on the first surface of the separated packaging substrate in a flip-chip manner; Wherein, the at least one die spans at least two substrate components. 7. The semiconductor package of claim 6, wherein the at least one die is a dummy die or a memory die. 8. The semiconductor package of claim 3, further comprising: the second integrated circuit die; and An electronic device is mounted on the first surface of the separated packaging substrate. 9. The semiconductor package of claim 8, wherein the second integrated circuit die and the electronic device do not overlap the gap. 10. The semiconductor package of claim 1, further comprising: A frame is mounted on the first surface of the separated packaging substrate. 11. The semiconductor package of claim 10, wherein the frame is attached to the first surface of the separated package substrate using bonding bumps or adhesive.