CN117492287A - Display panel - Google Patents

Abstract

The invention discloses a display panel which comprises sub-pixels, a first metal layer, a second metal layer, a transparent conductive layer and a third metal layer. The sub-pixel includes a switching element. The first metal layer includes a scan line electrically connected to the switching element. The second metal layer is disposed on the first metal layer and includes a pixel electrode and a data line electrically connected to the switching element, and a portion of the data line includes a darkening layer. The transparent conductive layer includes a transparent electrode disposed on and electrically connected to the pixel electrode. The third metal layer includes a reflective electrode disposed on and electrically connected to the transparent electrode.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a reflective display panel.

Background

In the reflective display panel, gaps exist between adjacent sub-pixels, and light reflected by the metal electrodes may leak out of the gaps, thereby causing poor contrast. Therefore, how to reduce the light leakage of the reflective display panel is one of the important research problems for improving the display quality.

Disclosure of Invention

The invention aims to solve the technical problem of reducing light leakage of a display panel so as to improve the display quality.

In order to solve the above technical problems, the present invention provides a display panel, which includes a display area and a non-display area, wherein the non-display area is disposed on at least one side of the display area. The display panel comprises a first substrate, a first sub-pixel, a first metal layer, a second metal layer, a transparent conductive layer and a third metal layer. The first sub-pixel is disposed on the first substrate and in the display area, and the first sub-pixel includes a first switching element. The first metal layer is arranged on the first substrate, the first metal layer comprises a plurality of first signal lines which are arranged in the display area, the first signal lines comprise first scanning lines which are electrically connected with the first switch element, and the first scanning lines extend along a first direction. The second metal layer is arranged on the first metal layer and comprises a first pixel electrode of the first sub-pixel and a plurality of second signal lines. The first pixel electrode is electrically connected to the first switching element. The second signal line is arranged in the display area, the second signal line comprises a data line which is electrically connected with the first switch element, the data line extends along a second direction, the first direction and the second direction are different, and a part of the data line comprises a blackening layer. The transparent conductive layer is arranged on the second metal layer, the second metal layer is arranged between the transparent conductive layer and the first metal layer, the transparent conductive layer comprises a first transparent electrode of the first sub-pixel, and the first transparent electrode is arranged on the first pixel electrode and is electrically connected with the first pixel electrode. The third metal layer is arranged on the transparent conductive layer, the transparent conductive layer is arranged between the third metal layer and the second metal layer, the third metal layer comprises a first reflecting electrode of the first sub-pixel, and the first reflecting electrode is arranged on the first transparent electrode and is electrically connected with the first transparent electrode.

In the display panel of the invention, part or all of the metal layer positioned below the gap comprises the blackened layer, so that reflected light can be reduced, light leakage can be reduced, and further, the contrast can be improved.

Drawings

Fig. 1 is a schematic top view of a display panel according to a first embodiment of the invention.

Fig. 2 is a schematic top view of a pixel structure of a display panel according to a first embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a blackened layer according to a first embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a blackened layer according to a first variation of the first embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view of a blackened layer according to a second variation of the first embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention.

Reference numerals illustrate: 10-a display panel; 100. 200-a substrate; 100 s-upper surface; 102. 108, 116-metal layers; 104. 110, 112-insulating layers; 114-a transparent conductive layer; 1180-first part; 1182-a second part; 1200-third part; 1202-fourth section; 1220. 1221, 1260, 1261-edges; 124-blacking layer; 1280. 1282, 1284-sublayers; 300-a liquid crystal layer; an AA-display area; a CH-semiconductor layer; CE1, CE2, 202-common electrode; CL-common signal line; d-drain electrode; DL1, DL2, DL 3-data lines; a G-gate; GL1, GL 2-scan lines; GP-gap; IL-ambient light; PA-non-display area; PE1, PE 2-pixel electrodes; RE1, RE 2-reflective electrodes; s-source electrode; SP, SP1, SP 2-sub-pixels; SW1, SW 2-switching elements; TE1, TE 2-transparent electrodes; v1 and V2-contact holes; w1-a first width; w2-a second width; x, Y, Z-direction.

Detailed Description

The following description sets forth the preferred embodiments of the invention and, together with the drawings, provides further details of the invention and its intended advantages, as will be apparent to those skilled in the art. It should be noted that the drawings are simplified schematic diagrams, and thus only show components and combinations related to the present invention, so as to provide a clearer description of the basic architecture or implementation of the present invention, and actual components and arrangements may be more complex. In addition, for convenience of explanation, the components shown in the drawings of the present invention are not drawn in the same scale as the number, shape, size, etc. of actual implementations, and the detailed proportion thereof may be adjusted according to the design requirements.

A direction X (or alternatively referred to as a first direction), a direction Y (or alternatively referred to as a second direction), and a direction Z (or alternatively referred to as a perpendicular projection direction) are indicated in the following figures. The direction Z may be perpendicular to an upper surface 100s of a substrate 100 (as shown in fig. 3), and the directions X and Y may be parallel to the upper surface 100s of the substrate 100. The direction Z may be perpendicular to the direction X and the direction Y, and the direction X may be perpendicular to the direction Y. The following figures may describe the spatial relationship of structures in terms of directions X, Y, and Z.

Referring to fig. 1 to 4, fig. 1 is a schematic top view of a display panel according to a first embodiment of the present invention, fig. 2 is a schematic top view of a pixel structure of the display panel according to the first embodiment of the present invention, fig. 3 is a schematic cross-sectional view of the display panel according to the first embodiment of the present invention, and fig. 4 is a schematic cross-sectional view of a blackening layer according to the first embodiment of the present invention. The structure of fig. 3 may correspond to the section lines A-A ', B-B ' and C-C ' in fig. 2. The display panel of the present embodiment may be a reflective liquid crystal panel, but the present invention is not limited thereto.

As shown in fig. 1, the display panel 10 includes a display area AA and a non-display area PA. The non-display area PA is disposed on at least one side of the display area AA, as shown in fig. 1, the non-display area PA may surround the display area AA, but is not limited thereto. In addition, the display panel 10 includes a plurality of subpixels SP disposed in the display area AA. As shown in fig. 1 and 2, the display panel 10 includes a sub-pixel SP1 (or may be referred to as a first sub-pixel) and a sub-pixel SP2 (or may be referred to as a second sub-pixel), and the sub-pixel SP1 and the sub-pixel SP2 are adjacently disposed in the direction X. Each sub-pixel SP includes at least one switching element. As shown in fig. 2, the sub-pixel SP1 includes a switching element SW1 (or may be called a first switching element), and the sub-pixel SP2 includes a switching element SW2 (or may be called a second switching element).

The switching element may include a thin film transistor, for example, but not limited to, a bottom gate thin film transistor (bottom-gate thin film transistor), and in other embodiments, the thin film transistor may be a top gate thin film transistor (top-gate thin film transistor). In addition, the thin film transistor may be a low temperature polysilicon (low temperature poly-silicon, LTPS) thin film transistor, an indium gallium zinc oxide (indium gallium zinc oxide, IGZO) thin film transistor, or an amorphous silicon (a-Si) thin film transistor, but is not limited thereto.

As shown in fig. 3, the display panel 10 includes a substrate 100 (or may be referred to as a first substrate), a substrate 200 (or may be referred to as a second substrate), and a liquid crystal layer 300, wherein the substrate 200 is disposed opposite to the substrate 100 in a direction Z, and the liquid crystal layer 300 is disposed between the substrate 100 and the substrate 200. The subpixels SP1 and SP2 and the switching elements SW1 and SW2 are provided on the substrate 100.

The substrate 100, 200 may include a hard substrate such as a glass substrate, a plastic substrate, a quartz substrate or a sapphire substrate, but is not limited thereto. The substrate 100, 200 may also include a flexible substrate such as a Polyimide (PI) substrate or a polyethylene terephthalate (polyethylene terephthalate, PET) substrate, but is not limited thereto. The liquid crystal layer 300 may include any suitable type of liquid crystal, but is not limited thereto.

Referring to fig. 3, the display panel 10 includes a metal layer 102 (or may be referred to as a first metal layer), an insulating layer 104, a metal layer 108 (or may be referred to as a second metal layer), an insulating layer 110, an insulating layer 112, a transparent conductive layer 114, and a metal layer 116 (or may be referred to as a third metal layer), but is not limited thereto.

The metal layer 102 is disposed on the substrate 100, and the metal layer 102 includes a gate G of each switching element (e.g., the switching element SW 1). The metal layer 102 includes a plurality of first signal lines disposed in the display area AA, as shown in fig. 2, the first signal lines may include at least one scanning line GL1 (or may be referred to as a first scanning line), one scanning line GL2 (or may be referred to as a second scanning line), and a common signal line CL, but not limited thereto. The scan lines GL1, GL2 and the common signal line CL extend along the direction X, the scan lines GL1 and GL2 are arranged along the direction Y, and the common signal line CL is disposed between the scan lines GL1 and GL2 in the direction Y, i.e. one common signal line may be disposed between two adjacent scan lines in the direction Y, but not limited thereto.

The scanning line GL1 is electrically connected to the gate G of the switching element SW1, and the scanning line GL2 is electrically connected to the gate G of the switching element SW 2. In addition, the metal layer 102 includes a common electrode CE1 (or may be referred to as a first common electrode) of the sub-pixel SP1 and a common electrode CE2 (or may be referred to as a second common electrode) of the sub-pixel SP2, the common electrode CE1 and the common electrode CE2 are arranged along the direction X, and the common signal line CL is electrically connected to the common electrode CE1 and the common electrode CE2.

As shown in fig. 3, each switching element (e.g., switching element SW 1) includes a semiconductor layer CH, the semiconductor layer CH and the metal layer 108 are disposed on the metal layer 102, and the insulating layer 104 is disposed between the semiconductor layer CH and the metal layer 102 and between the metal layer 108 and the metal layer 102. The semiconductor layer CH includes, but is not limited to, polysilicon, amorphous silicon or metal oxide.

The metal layer 108 includes a plurality of second signal lines disposed in the display area AA, and as shown in fig. 2, the second signal lines may include at least one data line DL1, one data line DL2 and one data line DL3, but not limited thereto. The data lines DL1, DL2, and DL3 extend along the direction Y and are arranged along the direction X, and the data line DL1 is disposed between the data lines DL2 and DL3 in the direction X. The data line DL1 is electrically connected to a source S of the switching element SW1 and to a source S of the switching element SW 2.

The metal layer 108 includes a pixel electrode of each sub-pixel, as shown in fig. 2, and the metal layer 108 includes a pixel electrode PE1 (or referred to as a first pixel electrode) of the sub-pixel SP1 and a pixel electrode PE2 (or referred to as a second pixel electrode) of the sub-pixel SP 2. The pixel electrode PE1 is electrically connected to a drain D of the switching element SW1, the pixel electrode PE2 is electrically connected to a drain D of the switching element SW2, and the metal layer 108 includes a source S and a drain D of each sub-pixel.

As shown in fig. 2, in the direction Z, the common electrode CE1 is disposed between the pixel electrode PE1 and the substrate 100, and the common electrode CE2 is disposed between the pixel electrode PE2 and the substrate 100. In the direction Y, the pixel electrode PE1, the common electrode CE1, the pixel electrode PE2, and the common electrode CE2 are disposed between the scanning line GL1 and the scanning line GL2, the pixel electrode PE1 and the common electrode CE1 are disposed above the switching element SW1 and the scanning line GL1, and the pixel electrode PE2 and the common electrode CE2 are disposed below the switching element SW2 and the scanning line GL 2.

As shown in fig. 3, the insulating layer 110 is disposed on the metal layer 108 and the semiconductor layer CH, and the insulating layer 112, the transparent conductive layer 114 and the metal layer 116 are disposed on the insulating layer 110 in sequence, but not limited thereto. The thickness of the insulating layer 112 may be greater than that of the insulating layer 110, but is not limited thereto. The insulating layer 104, the insulating layer 110, and the insulating layer 112 may include inorganic or organic insulating materials, but are not limited thereto.

The insulating layer 110 includes a plurality of contact holes V1, and each contact hole V1 may expose an upper surface of a portion of one pixel electrode. As shown in fig. 3, the contact hole V1 passes through the insulating layer 110 and exposes a portion of the upper surface of the pixel electrode PE 1. The insulating layer 112 includes a plurality of contact holes V2, and each contact hole V2 may expose one contact hole V1. As shown in fig. 3, the contact hole V2 passes through the insulating layer 112 and exposes the contact hole V1 and a portion of the upper surface of the insulating layer 110.

The transparent conductive layer 114 is disposed on the metal layer 108, and the metal layer 108 is disposed between the transparent conductive layer 114 and the metal layer 102. The transparent conductive layer 114 includes a transparent electrode of each sub-pixel, as shown in fig. 2, and the transparent conductive layer 114 includes a transparent electrode TE1 (or referred to as a first transparent electrode) of the sub-pixel SP1 and a transparent electrode TE2 (or referred to as a second transparent electrode) of the sub-pixel SP 2.

The transparent electrode TE1 is disposed on the pixel electrode PE1 and electrically connected to the pixel electrode PE1, and the transparent electrode TE2 is disposed on the pixel electrode PE2 and electrically connected to the pixel electrode PE2. As shown in fig. 3, the transparent electrode TE1 may extend into the contact hole V2 and the contact hole V1 and may be in contact with the pixel electrode PE 1. Similarly, the transparent electrode TE2 in fig. 2 may also extend into the corresponding contact hole V2 and contact hole V1 and may be in contact with the pixel electrode PE2. The transparent conductive layer 114 may include Indium Tin Oxide (ITO), indium zinc oxide (indium zinc oxide, IZO), or aluminum zinc oxide (aluminum zinc oxide, AZO), but is not limited thereto.

A metal layer 116 is disposed on the transparent conductive layer 114, and the transparent conductive layer 114 is disposed between the metal layer 116 and the metal layer 108. The metal layer 116 includes a reflective electrode of each sub-pixel, as shown in fig. 2, and the metal layer 116 includes a reflective electrode RE1 (or referred to as a first reflective electrode) of the sub-pixel SP1 and a reflective electrode RE2 (or referred to as a second reflective electrode) of the sub-pixel SP 2.

As shown in fig. 3, the reflective electrode RE1 is disposed on the transparent electrode TE1 and electrically connected to the transparent electrode TE1, the reflective electrode RE1 may contact the transparent electrode TE1, and the reflective electrode RE1 may also extend into the contact hole V2 and the contact hole V1. Similarly, the reflective electrode RE2 is disposed on the transparent electrode TE2 and electrically connected to the transparent electrode TE2, the reflective electrode RE2 may be in contact with the transparent electrode TE2, and the reflective electrode RE2 may also extend into the contact hole V2 and the contact hole V1.

The metal layers 102 and 108 may include single metal layers of aluminum, copper, titanium, tungsten, or composite metal layers of molybdenum/aluminum/molybdenum, titanium/aluminum/titanium, titanium/copper …, but are not limited thereto. The metal layer 116 may comprise silver or other suitable reflective metal material, and the conductive layer 116 may comprise a single metal layer or a composite metal layer, but is not limited thereto.

The reflective electrode RE1, the transparent electrode TE1, and the pixel electrode PE1 may be electrically connected to each other and may serve as a pixel electrode together, and similarly, the reflective electrode RE2, the transparent electrode TE2, and the pixel electrode PE2 may be electrically connected to each other and may serve as a pixel electrode together, but not limited thereto.

A gap GP is provided between the reflective electrode RE1 and the reflective electrode RE 2. For example, the gap GP may be located between an edge 1220 of the reflective electrode RE1 and an edge 1221 of the reflective electrode RE2, but is not limited thereto.

As shown in fig. 3, a portion of the data line DL1 located below the gap GP in the direction Z includes a blackened layer 124. In other words, the gap GP and the blackened layer 124 of a portion of the data line DL1 partially overlap in the direction Z. The data line DL1 may also include the blackening layer 124, but is not limited thereto. In addition, as shown in fig. 2, the data lines DL1, DL2 and DL3 may be located below the corresponding gaps GP and may all include the blackening layer 124 partially or completely, but not limited thereto.

The gap GP is excessively large when the reflective electrode RE1 and the reflective electrode RE2 are fabricated, which may cause an electric field in the display panel 10 to be unstable in a region near the gap GP, and thus liquid crystals located in the region cannot be effectively controlled. At this time, when an ambient light IL is incident into the display panel 10 from the substrate 200 and reflected by the metal layer (such as the data line DL 1) under the gap GP, the reflected light may penetrate through the gap GP and exit the display panel 10 to cause light leakage, which may further cause poor contrast.

However, in the present embodiment, part or all of the metal layer (such as the data line DL 1) located below the gap GP includes the blackening layer 124, so that the light leakage caused by the reflection of the ambient light IL incident into the display panel 10 by the metal layer can be reduced, and the contrast can be improved. In addition, the provision of a shielding layer (e.g., a black matrix) on the substrate 200 may be omitted. Therefore, the shielding layer is not disposed on the substrate 200 in the present embodiment, so as to save the cost.

In addition, in the metal layer 108 of the present embodiment, the rest portion may not include the blackened layer except for the portion (such as the data line DL1, the data line DL2 and/or the data line DL 3) under the gap GP, but is not limited thereto. In addition, the metal layer 102 of the present embodiment may not include a blackening layer, but is not limited thereto.

As shown in fig. 4, in the present embodiment, the blackening layer 124 may include a single layer structure, and the single layer structure includes a blackened metal. The blackened metal may include, but is not limited to, molybdenum blacken.

Furthermore, as shown in fig. 2, the transparent electrode may include designs of different widths. The transparent electrode TE1 includes a first portion 1180 and a second portion 1182. The pixel electrode PE1 may overlap a portion of the first portion 1180 in the direction Z, and the first portion 1180 includes a first width W1 in the direction X. The second portion 1182 is disposed on one side of the first portion 1180 in the direction Y, as shown in fig. 2, the second portion 1182 may be disposed above the first portion 1180 in the direction Y, but is not limited thereto. The second portion 1182 includes a second width W2 in the direction X, and the second width W2 is greater than the first width W1.

The transparent electrode TE2 includes a third portion 1200 and a fourth portion 1202. As shown in fig. 2, the pixel electrode PE2 may overlap a portion of the third portion 1200 in the direction Z. The fourth portion 1202 is disposed on one side of the third portion 1200 in the direction Y, as shown in fig. 2, and the fourth portion 1202 may be disposed below the third portion 1200 in the direction Y, but is not limited thereto. The width of the fourth portion 1202 in direction X is greater than the width of the third portion 1200 in direction X.

In the design of the existing display panel, the transparent electrode does not have a receded portion, i.e. the edge of the transparent electrode is aligned or overlapped with the edge of the reflective electrode in the direction Z. However, in some embodiments of the present invention, the transparent electrode TE1 includes a first portion 1180 that is tapered and the transparent electrode TE2 includes a third portion 1200 that is tapered to increase the distance of the gap between the transparent electrode TE1 and the transparent electrode TE2 and to cause an edge 1260 of the transparent electrode TE1 to be away from the edge 1220 of the reflective electrode RE1 and not overlap each other and to cause an edge 1261 of the transparent electrode TE2 to be away from the edge 1221 of the reflective electrode RE2 and not overlap each other.

In addition, as shown in fig. 3, the display panel 10 includes a common electrode 202 disposed on the substrate 200, and the common electrode 202 is disposed between the liquid crystal layer 300 and the substrate 200. In the present embodiment, the common electrode 202 may be formed on the substrate 200 entirely and not patterned, but is not limited thereto. In some embodiments, the common electrode 202 may be patterned.

The display panel of the present invention is not limited to the above embodiments. Other embodiments of the present invention will be further disclosed below, however, in order to simplify the description and highlight differences between the embodiments or variations, like components are labeled below with like reference numerals, and redundant descriptions thereof will not be provided.

Fig. 5 is a schematic cross-sectional view of a blackened layer according to a first variation of the first embodiment of the present invention. The difference from the first embodiment is that the blackened layer 124 in this modified embodiment includes a laminated structure. As shown in fig. 5, the stacked structure may include a sub-layer 1280 and a sub-layer 1282, but the number of sub-layers is not limited thereto. The sub-layer 1280 is disposed on the sub-layer 1282, since the darkening layer 124 may be disposed on the substrate 100, the sub-layer 1282 may be closer to the substrate 100 and the sub-layer 1280 may be farther from the substrate 100, and the sub-layer 1282 may be disposed between the sub-layer 1280 and the substrate 100. In the stacked structure, the sub-layer farthest from the substrate 100 (i.e., sub-layer 1280) includes a blackened metal (e.g., blackened molybdenum), but is not limited thereto. The sub-layer 1282 may include non-blackened metal, such as aluminum, but is not limited thereto. The stacked structure of the blackened layer 124 in the present variation can be applied to other embodiments of the present invention.

Fig. 6 is a schematic cross-sectional view of a blackened layer according to a second variation of the first embodiment of the present invention. The difference from the first variant embodiment is that the stacked structure in this variant embodiment may include a sub-layer 1280, a sub-layer 1282 and a sub-layer 1284, but the number of sub-layers is not limited thereto.

Since the darkening layer 124 may be disposed on the substrate 100, the sub-layer 1284 may be closer to the substrate 100, the sub-layer 1280 may be farther from the substrate 100, the sub-layer 1284 may be disposed between the sub-layer 1280 and the substrate 100, and the sub-layer 1282 may be disposed between the sub-layer 1280 and the sub-layer 1284.

In the stacked structure, the sub-layer farthest from the substrate 100 (i.e., sub-layer 1280) includes a blackened metal (e.g., blackened molybdenum), but is not limited thereto. The sub-layers 1282 and 1284 may include non-blackened metal. The sub-layer 1282 may include aluminum, and the sub-layer 1284 may include molybdenum, but is not limited thereto. The stacked structure of the blackened layer 124 in the present variation can be applied to other embodiments of the present invention.

Fig. 7 is a schematic cross-sectional view of a display panel according to a second embodiment of the invention. The difference from the first embodiment is that the metal layer 102 and the metal layer 108 in this embodiment both include the blackening layer 124, but not limited thereto. In more detail, the entire metal layer 102 and the entire metal layer 108 include the blackened layer 124, and thus, all devices in the metal layer 102 and all devices in the metal layer 108 may be formed of the blackened layer 124.

In some embodiments, the entire metal layer 108 may include the blackened layer 124, and the metal layer 102 may not include the blackened layer 124, but is not limited thereto. In some embodiments, the whole or part of the metal layer 108 may include the stacked structure of the blackened layer 124 in fig. 5 or fig. 6, but is not limited thereto. In some embodiments, the whole or part of the metal layer 102 may include the stacked structure of the blackened layer 124 in fig. 5 or fig. 6, but is not limited thereto.

In summary, in the display panel of the present invention, part or all of the metal layer located below the gap includes the blackened layer, so that the light leakage caused by the reflection of the ambient light incident into the display panel by the metal layer can be reduced, and the contrast can be improved. The transparent electrode includes a tapered portion such that edges of the transparent electrode are away from edges of the reflective electrode and no longer overlap each other. Even if the manufacturing deviation of the reflecting electrode is larger, the phenomenon of residual metal material of the reflecting electrode can be reduced, and the short circuit caused by the migration of residual metal ions is also reduced.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A display panel, comprising:

a display area and a non-display area, the non-display area is arranged on at least one side of the display area;

a first substrate;

a first sub-pixel disposed on the first substrate and in the display area, wherein the first sub-pixel includes a first switching element;

the first metal layer is arranged on the first substrate, the first metal layer comprises a plurality of first signal lines which are arranged in the display area, the plurality of first signal lines comprise a first scanning line which is electrically connected with the first switch element, and the first scanning line extends along a first direction;

a second metal layer is disposed on the first metal layer, the second metal layer comprising:

a first pixel electrode of the first sub-pixel, and the first pixel electrode is electrically connected with the first switch element; and

a plurality of second signal lines disposed in the display region, the plurality of second signal lines including a data line electrically connected to the first switching element, the data line extending along a second direction, the first direction being different from the second direction, and a portion of the data line including a blackened layer;

the transparent conductive layer is arranged on the second metal layer, the second metal layer is arranged between the transparent conductive layer and the first metal layer, the transparent conductive layer comprises a first transparent electrode of the first sub-pixel, and the first transparent electrode is arranged on the first pixel electrode and is electrically connected with the first pixel electrode; and

the third metal layer is arranged on the transparent conductive layer, the transparent conductive layer is arranged between the third metal layer and the second metal layer, the third metal layer comprises a first reflecting electrode of the first sub-pixel, and the first reflecting electrode is arranged on the first transparent electrode and is electrically connected with the first transparent electrode.

2. The display panel of claim 1, further comprising a second sub-pixel disposed on the first substrate, the first sub-pixel and the second sub-pixel being disposed adjacent in the first direction, and the second sub-pixel comprising:

a second switching element disposed on the first substrate;

a second pixel electrode electrically connected to the second switching element, and the second metal layer includes the second pixel electrode;

a second transparent electrode disposed on and electrically connected to the second pixel electrode, wherein the transparent conductive layer includes the second transparent electrode; and

the second reflective electrode is arranged on the second transparent electrode and is electrically connected with the second transparent electrode, the third metal layer comprises the second reflective electrode, a gap is arranged between the first reflective electrode and the second reflective electrode, and the gap and the blackening layer of the part of the data line are partially overlapped in a vertical projection direction, wherein the vertical projection direction is perpendicular to an upper surface of the first substrate.

3. The display panel of claim 2, wherein the first metal layer comprises a first common electrode of the first subpixel, a second common electrode of the second subpixel, and a common signal line, and the plurality of first signal lines of the first metal layer comprises a second scan line,

wherein the second scan line extends along the first direction and is electrically connected to the second switching element, and the second switching element is electrically connected to the data line,

wherein the first common electrode is disposed between the first pixel electrode and the first substrate, the second common electrode is disposed between the second pixel electrode and the first substrate, and the common signal line extends along the first direction and electrically connects the first common electrode and the second common electrode.

4. The display panel of claim 1, wherein all of the second metal layers include the blackened layer.

5. The display panel of claim 4, wherein all of the first metal layers comprise the blackened layer.

6. The display panel of claim 1, wherein the blackened layer comprises a stacked structure, and a first sub-layer of the stacked structure furthest from the first substrate comprises a blackened metal.

7. The display panel of claim 6, wherein the laminate structure includes a second sub-layer disposed between the first sub-layer and the first substrate, and the second sub-layer includes a non-blackened metal.

8. The display panel of claim 6, wherein the laminate structure includes a second sub-layer and a third sub-layer, the second sub-layer is disposed between the first sub-layer and the first substrate, the third sub-layer is disposed between the first sub-layer and the second sub-layer, and the second sub-layer and the third sub-layer include a non-blackened metal.

9. The display panel of claim 1, wherein the blackened layer comprises a single layer structure and the single layer structure comprises a blackened metal.

10. The display panel of claim 1, further comprising:

the second substrate is arranged opposite to the first substrate in a vertical projection direction, and a shielding layer is not arranged on the second substrate; and

and the liquid crystal layer is arranged between the first substrate and the second substrate.