CN117480768A

CN117480768A - Communication device and message transmission method

Info

Publication number: CN117480768A
Application number: CN202180099253.7A
Authority: CN
Inventors: 吴博强; 刘荣国; 程传宁
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-06
Filing date: 2021-12-06
Publication date: 2024-01-30
Also published as: WO2023102682A1

Abstract

The embodiment of the disclosure provides a communication device and a message transmission method. The communication device includes a first interface and a second interface, wherein the first interface is configured to: acquiring a first message from the inside of a communication device, wherein the first message has a first timestamp; acquiring a second timestamp of a second message from a second interface; determining a sequence number of the first message based at least on the first timestamp and the second timestamp; and transmitting the first message based on the sequence number of the first message. In this way, the first interface of the communication device can determine that the acquired message is global in sequence number, and send the message based on the sequence number, so that the timing sequence of the messages of the plurality of interfaces can be ensured. And the time stamps can be synchronized with each other among the interfaces, so that the condition that only one interface can be used due to the order-preserving requirement of the message is avoided, the time sequence of the message is ensured on the premise of fully utilizing the bandwidths of the interfaces, and further, the subsequent correct processing of the message can be ensured.

Description

Communication device and message transmission method

Technical Field

The embodiment of the disclosure relates generally to the field of chips, and more particularly, to a communication device and a message transmission method.

Background

With the development of artificial intelligence, cloud computing, and the like, communication apparatuses that rely on only a single interface for communication have not been able to meet the demands for computing power and large data transmission, and therefore, it is a necessary trend to provide a plurality of interfaces on the communication apparatuses and simultaneously utilize the message rates of the plurality of interfaces.

However, as the number of interfaces increases, the disorder degree of network messages transmitted by the communication device increases. How to ensure the timing of messages transmitted by multiple interfaces is one of the problems that needs to be solved at present.

Disclosure of Invention

Embodiments of the present disclosure provide a communication apparatus capable of ensuring timing of messages between a plurality of interfaces.

In a first aspect of the present disclosure, there is provided a communication apparatus comprising a first interface and a second interface, wherein the first interface is configured to: acquiring a first message from the inside of a communication device, wherein the first message has a first timestamp; acquiring a second timestamp of a second message from a second interface; determining a sequence number of the first message based at least on the first timestamp and the second timestamp; and transmitting the first message based on the sequence number of the first message.

Thus, the first interface of the communication device can acquire the second timestamp of the message of the second interface, determine the sequence number of the message based on the first timestamp and the second timestamp, and send the message based on the sequence number, so that the time sequence of the messages of the interfaces can be ensured. In this way, in the embodiment of the present disclosure, the time stamps can be synchronized with each other between the multiple interfaces, so that the state that only one interface can be used due to the order-preserving requirement of the message is avoided, and thus, the embodiment of the present disclosure ensures the time sequence of the message and further can ensure the subsequent correct processing of the message on the premise of fully utilizing the bandwidths of the multiple interfaces.

In some embodiments of the first aspect, the first interface is configured to: during a first time period, acquiring a first message with a first timestamp; acquiring a second timestamp of a second message from the second interface during a second time period, the second message being acquired by the second interface during the first time period; and during the third time period, determining a sequence number of the first message based at least on the first timestamp and the second timestamp.

Optionally, the first interface may obtain a first packet with a first timestamp in a first period of time; acquiring a second timestamp of a second message from the second interface in a second time period, and determining a sequence number of the first message based on at least the first timestamp and the second timestamp, wherein the second message is acquired by the second interface in the first time period; and sending the first message in a third time period.

In some embodiments of the first aspect, the second period of time immediately follows the first period of time, and the third period of time immediately follows the second period of time.

In some embodiments of the first aspect, the second time period has a time length less than or equal to the time length of the first time period, and the third time period has a time length less than or equal to the time length of the first time period.

Therefore, the time length of the first time period in the embodiment of the disclosure is longest because the data volume of the interface when acquiring the message is larger, the data volume of the acquired timestamp is smaller and the time consumption for determining the sequence number is shorter, so that the full acquisition of the message can be ensured, and the waste of time resources is avoided.

In some embodiments of the first aspect, the first time period, the second time period, and the third time period are equal in time length. The first interface may periodically perform processing on the message.

In some embodiments of the first aspect, the first interface may perform three operations on the message in a time period, in particular, the first interface obtains the first message with the first timestamp in a certain specific time period; acquiring a second timestamp of a second message from the second interface, and determining a sequence number of the message acquired in a previous time period based at least on the timestamp and the second timestamp of the message acquired by the first interface in the previous time period, wherein the second message is acquired by the second interface in the previous time period of the specific time period; and transmitting a third message based on the sequence number of the third message determined in the previous time period, wherein the third message is acquired by the first interface in the time period before the previous time period.

In this manner, the first interface may perform pipelined processing on the messages, that is, may perform segmentation operations over a period of time, perform acquisition operations on a first portion of the messages (e.g., acquire time stamps of the messages to be sent), perform synchronization operations on a second portion of the messages (e.g., acquire time stamps from other interfaces and determine sequence numbers), and perform transmission operations on a third portion of the messages (e.g., transmit based on the determined sequence numbers). Therefore, the full utilization of the interface can be realized, and the efficiency of interface processing is further improved.

In some embodiments of the first aspect, the first interface is further configured to provide the first timestamp of the first message to the second interface.

Therefore, the time stamp synchronization among the interfaces can be realized, and each interface can conveniently determine the sequence number of the message.

In some embodiments of the first aspect, the first interface is configured to: determining a temporal ordering of the first timestamp and the second timestamp; and determining a sequence number based on the location of the first timestamp in the temporal ordering.

Therefore, the first interface can determine the sequence number of the message at the first interface based on all the time stamps of the plurality of interfaces, can characterize the time sequence of the global message and ensures the correct processing of the message.

In some embodiments of the first aspect, the second interface is configured to: acquiring a second message from the inside of the communication device, wherein the second message has a second timestamp; acquiring a first timestamp of a first message from a first interface; determining a sequence number of the second message based at least on the first timestamp and the second timestamp; and sending the second message based on the sequence number of the second message.

In some embodiments of the first aspect, the first interface and the second interface are located on the same chip, or the first interface and the second interface belong to different chips.

As such, the communication device may be applied to a plurality of different scenarios, in one example, a plurality of interfaces may be integrated in the same chip as a processor, each interface may be implemented as a module within the chip, such as a built-in network card; in one example, the multiple interfaces may be implemented as separate chips, such as an external network card.

In a second aspect of the present disclosure, there is provided a communication device comprising a first interface and a processor, wherein the first interface is configured to: receiving a first message, the first message including a first sequence number, providing a first execution application for the first message to a processor of the communication device, the first execution application including the first sequence number of the first message, and operating on the first message based on a first execution permission from the processor; the processor is configured to obtain a first execution application from the first interface and provide a first execution permission for the first execution application to the first interface.

In some embodiments of the second aspect, the method further comprises a second interface configured to: receiving a second message, the second message including a second sequence number, providing a second execution application for the second message to the processor, the second execution application including the second sequence number of the second message, and operating on the second message based on a second execution permission from the processor; and wherein the processor is further configured to obtain a second execution application from the second interface; based on the size relationship of the first sequence number and the second sequence number, an order in which the first execution permission is provided to the first interface and the second execution permission is provided to the second interface is determined.

In a third aspect of the present disclosure, a method for transmitting a message is provided, including: a first interface of the communication device acquires a first message from the inside of the communication device, wherein the first message has a first time stamp; the first interface obtains a second timestamp of a second message from the second interface; the first interface determines a sequence number of the first message based at least on the first timestamp and the second timestamp; and the first interface sends the first message based on the sequence number of the first message.

In some embodiments of the third aspect, the first interface obtaining the first packet includes: the first interface acquires a first message with a first timestamp during a first time period; the first interface obtaining the second timestamp includes: the first interface obtains a second timestamp of a second message from the second interface during a second time period, the second message being obtained by the second interface during the first time period; the first interface determining the sequence number includes: the first interface determines a sequence number of the first message during a third time period based at least on the first timestamp and the second timestamp.

In some embodiments of the third aspect, the second period of time immediately follows the first period of time, and the third period of time immediately follows the second period of time.

In some embodiments of the third aspect, the second time period has a time length less than or equal to the time length of the first time period, and the third time period has a time length less than or equal to the time length of the first time period.

In some embodiments of the third aspect, the method further comprises the first interface providing a first timestamp of the first message to the second interface.

In some embodiments of the third aspect, the first interface determining the sequence number comprises: the first interface determining a temporal ordering of the first timestamp and the second timestamp; and the first interface determining the sequence number based on the location of the first timestamp in the temporal ordering.

In some embodiments of the third aspect, the first interface and the second interface are located on the same chip, or the first interface and the second interface belong to different chips.

In a fourth aspect of the present disclosure, a method for transmitting a message is provided, including: a first interface of the communication device receives a first message, wherein the first message comprises a first serial number; the first interface provides a first execution application for a first message to a processor of the communication device, wherein the first execution application comprises a first serial number of the first message; the processor provides a first execution permission for the first execution application to the first interface; and the first interface operates on the first message based on the first execution permission from the processor.

In some embodiments of the fourth aspect, further comprising: a second interface of the communication device receives a second message, wherein the second message comprises a second serial number; the second interface provides a second execution application for the second message to the processor, wherein the second execution application comprises a second serial number of the second message; and the processor determining an order in which to provide the first execution permission to the first interface and the second execution permission to the second interface based on a size relationship of the first sequence number and the second sequence number.

In a fifth aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a computer or processor, perform operations according to the method in the third aspect or any embodiment thereof described above, or perform operations according to the method in the fourth aspect or any embodiment thereof described above.

In a sixth aspect of the present disclosure, a computer program or computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and comprises computer-executable instructions which, when executed, implement operations in accordance with the method in the third aspect or any embodiment thereof described above, or implement operations in accordance with the method in the fourth aspect or any embodiment thereof described above.

In a seventh aspect of the present disclosure, a chip or chip system is provided. The chip or chip system comprises processing circuitry configured to perform operations according to the method in the third aspect or any of its embodiments described above, or to perform operations according to the method in the fourth aspect or any of its embodiments described above.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 shows a schematic diagram of a scenario in which some embodiments of the present disclosure may be applied;

fig. 2 illustrates a block diagram of one example of a first communication device, according to some embodiments of the present disclosure;

fig. 3 illustrates a schematic flow diagram of a message transmission process according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of messages processed by an interface during different time periods according to some embodiments of the present disclosure;

FIG. 5 illustrates a schematic diagram of a manner of determining a sequence number of a first message, according to some embodiments of the present disclosure;

fig. 6 illustrates a schematic flow diagram of a message transmission process according to some embodiments of the present disclosure;

fig. 7 illustrates a schematic interaction diagram of a message transmission process according to some embodiments of the present disclosure; and

FIG. 8 illustrates a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.

With the development of artificial intelligence (Artificial Intelligence, AI), cloud computing, etc., the computing power of a single chip cannot meet the actual computing power demand, so more chips are required to form a larger-scale computing network, but the disorder degree of network messages on multiple interfaces is increased. In addition, due to the expansion of the network scale, a single chip also needs a plurality of interfaces and improves the network bandwidth in cooperation with the multipath technology. Here, a solution is needed to ensure packet timing between multiple interfaces to fully utilize the bandwidths of the multiple interfaces.

In view of this, in the embodiments of the present disclosure, time stamps of respective received messages may be synchronized among a plurality of interfaces of a communication device, and a sequence number of the message is determined based on the time stamps, so that a timing sequence of the message among the plurality of interfaces is ensured. And further, the bandwidth of a plurality of interfaces can be fully utilized, and the condition that only one interface can be used due to the order-preserving requirement of the messages is avoided.

Fig. 1 shows a schematic diagram of a scenario 100 in which some embodiments of the present disclosure may be applied. In the scenario 100, a first communication device 110, a second communication device 120, and a third communication device 130 are included.

The first communication device 110 includes a processor 112, an interface 114-1, an interface 114-2, and an interface 114-3. The processor 112 may be configured to run an operating system, software protocol stack, or the like. For brevity, interfaces 114-1, 114-2, and 114-3 are collectively referred to as interfaces 114. The processor 112 and the interface 114 may be connected by a bus 116, e.g., the bus 116 is a system bus. The processor 112 and interface 114 may communicate instructions, data, etc. over a system bus.

In some embodiments, processor 112 and interface 114 may be implemented as multiple interfaces within a single chip, e.g., processor 112 and interface 114 are integrated on the same chip, e.g., a single application specific integrated circuit (Application Specific Integrated Circuit, ASIC).

In some embodiments, processor 112 and interface 114 may be implemented as a single-chip managed multi-external interface, e.g., processor 112 is implemented as a processor chip and interface 114 is implemented as an external chip. Fig. 2 illustrates a block diagram of one example 200 of the first communication device 110, according to some embodiments of the present disclosure. Fig. 2 may be understood as implementing the interface 114 of the first communication device 110 in fig. 1 as an external network card (hereinafter referred to simply as a network card in the embodiment). In FIG. 2, processor 112 is connected to network card 214-1, network card 214-2, and network card 214-3 (collectively referred to as network cards 214) via bus 116 and through peripheral interfaces. It will be appreciated that embodiments of the present disclosure are not limited to a particular form of network card 214, for example, it may be affixed to a processor chip, or may be pluggable, etc. It should be understood that the network card 214 shown in fig. 2 is only one way of implementing the interface 114 externally, and may be implemented in other forms in practical applications, which is not limited in this disclosure.

In some embodiments, some of interfaces 114 (e.g., interfaces 114-1) and processor 112 are implemented on the same chip, while the remaining interfaces (e.g., interfaces 114-1 and 114-3) are implemented as external chips.

Illustratively, the first communication device 110 may also include a memory 118.

It should be noted that although the number of interfaces 114 of the first communication device 110 is 3 is shown in fig. 1, the present disclosure is not limited thereto and may be 2 or more, for example. That is, the first communication device 110 includes a plurality of interfaces, and accordingly, the first communication device 110 may be referred to as a multi-interface communication device, and the plurality of interfaces are connected to each other to enable communication.

The second communication device 120 includes a processor 122 and an interface 124, wherein the processor 122 may be configured to run an operating system, a software protocol stack, or the like. The processor 122 and the interface 124 may be connected by a bus 126, e.g., the bus 126 is a system bus. Processor 122 and interface 124 may transmit instructions, data, etc. over a system bus. Illustratively, the second communication device 120 may also include a memory 128. As illustrated, the second communication device 120 includes a single interface and accordingly may be referred to as a single interface communication device.

The third communication device 130 includes a processor 132, an interface 134-1, an interface 134-2, and an interface 134-3. The processor 132 may be configured to run an operating system, software protocol stack, or the like. For brevity, interface 134-1, interface 134-2, and interface 134-3 are collectively referred to as interface 134. The processor 132 and the interface 134 may be connected by a bus 136, for example, the bus 136 is a system bus. Processor 132 and interface 134 may communicate instructions, data, etc. over a system bus. Illustratively, the third communications device 130 may also include a memory 138.

It will be appreciated that the number of interfaces 134 of the third communication device 130 shown in fig. 1 is merely illustrative, and in a practical scenario, the number of interfaces 134 may be 2 or more, and accordingly, the third communication device 130 may be referred to as a multi-interface communication device. For the specific implementation of the interface 134, reference may be made to the embodiment of the interface 114 described above in connection with the first communication device 110, and for brevity, a detailed description is omitted here.

In the scenario 100, the first communication device 110, the second communication device 120, the third communication device 130 may communicate with each other, for example, the first communication device 110 may send messages to the second communication device 120 and/or the third communication device 130 via the interface 114. It should be noted that, the embodiments of the present disclosure do not limit the manner of transmitting the message between the first communication apparatus 110 and the second communication apparatus 120 and/or the third communication apparatus 130, and may be implemented by a switch or the like, for example.

The process by which the first communication device 110 transmits a message will be described below with reference to fig. 3 to 5. Fig. 3 illustrates a schematic flow diagram of a message transmission process 300 according to some embodiments of the present disclosure. The process 300 may be performed by the first communication device 110 as shown in fig. 1.

At block 310, the first interface obtains a first message from within the first communication device 110, the first message having a first timestamp.

At block 320, the first interface obtains a second timestamp of a second message from a second interface of the first communication device 110.

At block 330, the first interface determines a sequence number of the first message based at least on the first timestamp and the second timestamp.

At block 340, the first interface sends the first message based on the sequence number of the first message.

In process 300, the first interface may be any interface of the first communication device 110, that is, each interface of the first communication device 110 may be configured to perform the process 300 as shown in fig. 3. In connection with fig. 1, the processor 112 of the first communication device 110 may send a message request to each interface 114 based on actual traffic demands. Specifically, processor 112 may send message requests to interface 114-1, interface 114-2, and interface 114-3, respectively, for the same destination. Further, each interface 114 may obtain messages with different time stamps based on the message requests from the processor 112.

In process 300, the second interface may be the remaining interfaces of the first communication device 110 other than the first interface. In connection with fig. 1, for example, a first interface may interface 114-1 and a second interface may include interface 114-2 and interface 114-3.

In some embodiments, the first interface may execute in a pipelined fashion for messages it is to transmit. Specifically, the first interface may obtain a first message having a first timestamp during a first time period. The first interface then obtains a second timestamp of a second message from the second interface during a second time period, wherein the second message is obtained by the second interface during the first time period. After that, the first interface may determine a sequence number of the first message during the third time period based at least on the first timestamp and the second timestamp. Optionally, the second period of time immediately follows the first period of time, and the third period of time immediately follows the second period of time.

During a first time period, a first interface (e.g., interface 114-1) may obtain a message from within the first communication device 110 (e.g., processor 112 or memory 118), and record an absolute timestamp of the obtained message. It is appreciated that during a first period of time, the first interface may obtain a plurality of messages and record a timestamp for each message. Similarly, during the first time period, the second interface (e.g., interface 114-2 and interface 114-3) may also obtain a message from the interior of the first communication device 110 (e.g., processor 112 or memory 118), and record an absolute timestamp of the obtained message. It is appreciated that during the first period of time, the second interface may obtain a plurality of messages and record a timestamp for each message. Alternatively, the first period of time may be referred to as a reception period or a message acquisition period.

Optionally, each interface may store the acquired plurality of messages in a message queue based on the recorded time stamps.

Fig. 4 shows a schematic diagram of a message 400 processed by an interface during different time periods according to some embodiments of the present disclosure. In fig. 4, in the time period T1, the interface 114-1 acquires 5 first messages, and records 5 first timestamps corresponding to the 5 first messages, which are assumed to be T11 to T15 respectively. In the time period T1, the interface 114-2 acquires 4 second messages, and records 4 second timestamps corresponding to the 4 second messages, which are assumed to be T21 to T24 respectively. In the time period T1, the interface 114-3 acquires 4 third messages, and records 4 third timestamps corresponding to the 4 third messages, which are assumed to be T31 to T34 respectively. It will be appreciated that the number of first, second, and third messages shown in fig. 4 is merely illustrative. And it can be understood that, for the message indicated by oblique lines in fig. 4, the period T1 is a reception period.

During the second time period, each interface provides the time stamp of the message it acquired during the first time period to the remaining interfaces. A second timestamp from the second interface may be obtained. That is, a first interface (e.g., interface 114-1) may obtain a timestamp of a message that a second interface (e.g., interface 114-2 and interface 114-3) obtained during a first time period, and the first interface may also provide the timestamp of the message that the first interface obtained during the first time period to the second interface. Alternatively, the second period of time period may be referred to as a synchronization period or a timestamp synchronization period.

Alternatively, each interface may provide its own time stamp recorded during the last time period to the remaining interfaces in the form of a broadcast.

In connection with FIG. 4, during time period T2, interface 114-1 provides T11 through T15 to interfaces 114-2 and 114-3, and interface 114-1 may obtain T21 through T24 and T31 through T34. It can be understood that, for the message indicated by oblique lines in fig. 4, the period T2 is a synchronization period.

It should be noted, however, that during time period T2, interface 114-1 continues to obtain subsequent messages after the 5 first messages having time stamps T11 through T15, e.g., the 4 first messages having time stamps T16 through T19, respectively. Similarly, interfaces 114-2 and 114-3 also continue to obtain subsequent second and third messages, and so on. It can be appreciated that, for the message represented by the horizontal line in fig. 4, the period T2 is a reception period.

During the third time period, each interface determines the sequence number of the message it acquired during the first time period, respectively. Taking the first interface as an example, the first interface may determine a time ordering of all timestamps (including the timestamps recorded during the first time period and the timestamps acquired during the second time period), so that the sequence number of the first message may be determined based on the position of the first timestamp in the time ordering.

Taking interface 114-1 as an example in connection with fig. 4, interface 114-1 may determine a temporal ordering of 13 timestamps in total of t11 through t15, t21 through t24, and t31 through t34, then determine a sequence number of the first message with timestamp t11 based on a position of t11 in the temporal ordering, determine a sequence number of the first message with timestamp t12 based on a position of t12 in the temporal ordering, determine a sequence number of the first message with timestamp t13 based on a position of t13 in the temporal ordering, determine a sequence number of the first message with timestamp t14 based on a position of t14 in the temporal ordering, and determine a sequence number of the first message with timestamp t15 based on a position of t15 in the temporal ordering. For example, if t11 is located first in the time ordering, the sequence number of the first message of timestamp t11 may be determined to be a predefined minimum sequence number (e.g., 0 or 1 or other value). For example, if t15 is located at the nth bit in the time ordering, the sequence number of the first message of the timestamp t15 may be determined to be a predefined minimum sequence number (e.g., 0 or 1 or other value) +n.

Fig. 5 illustrates a schematic diagram of a manner 500 of determining a sequence number of a first message, according to some embodiments of the present disclosure. Specifically, it is shown in FIG. 5 how interface 114-1 determines the sequence number of the first message with timestamp t 11. The interface 114-1 may represent the first time stamp of the first message acquired by the interface 114-1 during the first period of time as a first queue 510, the first time stamps in the first queue 510 being ordered from small to large, i.e., t11< t12< t13< t14< t15, wherein a smaller time stamp indicates an earlier acquired time and a larger time stamp indicates a later acquired time. The interface 114-1 may also represent the second time stamp of the interface 114-2 acquired during the second time period as a second queue 520, the second time stamps in the second queue 520 being ordered from small to large, i.e., t21< t22< t23< t24. The interface 114-1 may also represent the third timestamp of the interface 114-3 acquired during the second time period as a third queue 530, the third timestamps in the third queue 530 ordered from small to large, i.e., t31< t32< t33< t34.

The interface 114-1 may sequentially determine the sequence numbers of the corresponding first messages in the order of the time stamps in the first queue 510. For example, for a message with a sequence number to be determined (e.g., a message with a timestamp t 11), the interface 114-1 may determine a number of timestamps less than the timestamp t11, and determine the sequence number based on the number.

Referring to FIG. 5, three timestamps in three queues located on dashed line 512 may be compared, and if t11> t21, t21 may be popped up, and then t11 and t22 may be compared; if t11> t31, t31 may be popped up and t11 and t32 may be compared. In this way, until t11 is smallest of the three timestamps in the three queues on the dashed line, as shown by dashed line 514 in fig. 5, where t11< t13 and t11< t32. The sequence number of the first message corresponding to t11 may be further determined based on the number of the ejected time stamps, in fig. 5, the ejected time stamps include t21, t22 and t31 in total 3, so it may be determined that the sequence number of the first message corresponding to t11 may be 4. In the same manner, the interface 114-1 may determine the sequence number of the first packet corresponding to the time stamps t11 to t15, which will not be described herein for brevity.

It will be appreciated that although an embodiment of interface 114-1 determining a sequence number is described above in connection with fig. 5, the manner in which interface 114-2 and interface 114-3 determine sequence numbers is similar and will not be elaborated upon in this disclosure.

During the third time period, each interface may also send a message based on the determined sequence number. Taking the first interface (such as interface 114-1) as an example, the messages acquired during the first time period may be sequentially sent in order of sequence number from smaller to larger. For example, for 5 first messages in t11< t12< t13< t14< t15 in fig. 4, a first message with a time stamp of t11 may be sent first, and then a second message with a time stamp of t12 may be sent, …. However, the first packet sent may not carry the first time stamps t11 to t15, but instead the first packet carries the corresponding sequence number, for example the first packet with the time stamp t11 carries the sequence number 4. In this way, the amount of transmitted information can be reduced, the channel occupation is reduced, and the transmission efficiency is improved. Alternatively, the third period of time may be referred to as a transmission period or a message transmission period.

Referring to FIG. 4, interfaces 114-2 and 114-3 may perform similar operations as interface 114-1. And it can be understood that, for the message indicated by oblique lines in fig. 4, the period T3 is a transmission period.

It should be noted, however, that during time period T3, interface 114-1 provides interface 114-2 and interface 114-3 with time stamps T16 through T19 acquired during time period T2, and similarly, interface 114-1 also acquires the time stamps acquired by interface 114-2 and interface 114-3 during time period T2. It can be appreciated that for the message represented by the horizontal line in fig. 4, the period T3 is a synchronization period.

And, during the period of time T3, the interface 114-1 continues to obtain subsequent first messages, such as the messages shown by the vertical lines in fig. 4, after the 4 first messages with time stamps T16 to T19. Similarly, interfaces 114-2 and 114-3 also continue to obtain subsequent second and third messages, and so on. It can be appreciated that for the message represented by the vertical line in fig. 4, the period T3 is the reception period.

It should be noted that although the first, second, and third time periods are described above in connection with fig. 4-5, it is understood that the above process is merely illustrative. For example, in an actual scenario, timestamp synchronization between the various interfaces may be achieved during the second time period and a sequence number determined based on the synchronized timestamp, and a message may be sent during the third time period based on the sequence number determined during the second time period. That is, the process of determining the sequence number of the message may be performed during the second time period or the third time period, which is not limited in this disclosure.

In some embodiments, the length of time of the second time period is less than or equal to the length of time of the first time period, and the length of time of the third time period is less than or equal to the length of time of the first time period. That is, the first period is the largest among the first period, the second period, and the third period.

In some embodiments, the time lengths of the first, second, and third time periods are equal. That is, each interface is equally periodic in the process of sending messages. Referring to fig. 4, t1=t2=t3. For example, all equal to 1000 clock cycles.

As such, in embodiments of the present disclosure, each interface may be partitioned according to a time period, and receive, synchronize, and transmit different messages respectively, so as to process in a pipelined manner. Thus, message order preservation among a plurality of interfaces can be realized, and the processing efficiency of the mode is high.

In connection with the scenario 100 shown in fig. 1, the first communication device 110 may send a message to the second communication device 120 or the third communication device 130.

Assuming that the first communication device 110 transmits a message to the second communication device 120, since the second communication device 120 is a single interface communication device, the interface 124 of the second communication device 120 may receive messages from the plurality of interfaces 114 of the first communication device 110. Further, the interface 124 may perform subsequent operations based on the sequence number carried by the received message, such as writing the message to the memory 128 according to the sequence number.

Assuming that the first communication device 110 sends a message to the third communication device 130, since the second communication device 130 is a multi-interface communication device, the interfaces 134 of the third communication device 130 need to cooperate to complete the order preserving process for the message.

Fig. 6 illustrates a schematic flow diagram of a message transmission process 600 according to some embodiments of the present disclosure. The process 600 may be performed by the third communication device 130 as shown in fig. 1.

At block 610, a first interface of the third communication device 130 receives a first message, the first message including a first sequence number.

At block 620, the first interface provides a first execution application for the first message to the processor 132 of the third communication device 130, the first execution application including the first sequence number.

At block 630, the processor 132 provides a first execution license for the first execution application to the first interface.

At block 640, the first interface operates on the first message based on the first execution permission from the processor 132.

In the process 600, the first interface may be any interface of the third communication device 130, that is, each interface of the third communication device 130 may be configured to perform the process 600 as shown in fig. 6, such as the operations in block 610, block 620, and block 640. Accordingly, it is understood that the processor 132 may obtain execution applications from the various interfaces, and that the processor 132 may provide execution permissions for each interface.

In some embodiments, the second interface of the third communication device 130 receives a second message, the second message including a second sequence number; the second interface provides a second execution application for the second message to the processor 132, the second execution application including a second sequence number of the second message. The processor 132 may determine an order in which to provide the first execution permission to the first interface and the second execution permission to the second interface based on a size relationship of the first sequence number and the second sequence number.

Specifically, each interface of the third communication device 130 may provide an execution application for the message to the processor 132 after receiving the message from the first communication device 110. After acquiring execution requests from multiple interfaces (e.g., interfaces 134-1, 134-2, and 134-3), processor 132 may sequentially provide execution permissions to the corresponding interfaces in order of sequence numbers from smaller to larger. Further, the interface receiving the execution permission may operate on the corresponding message, for example, writing the message to the memory 138.

Alternatively, the execution application may be processed by a specific module (e.g., an order preserving module) internal to the processor 132.

It should be noted that while the embodiment of fig. 6 illustrates processing of an execution application from an interface by the processor 132, the present disclosure is not so limited, as the execution application may also be serviced by an order keeping module or the like that is independent of the processor 132 (i.e., external to the processor 132).

Thus, the time sequence processing of the message can be ensured based on the sequence number in the received message, so that the message processing can be ensured not to be wrong due to disorder.

Fig. 7 illustrates a schematic interaction diagram of a message transmission process 700 according to some embodiments of the present disclosure. The process 700 involves the first communication device 110 and the third communication device 130.

Processor 112 provides 701 message a to interface 114-1, message b to interface 114-2, and message c to interface 114-3.

Interface 114-1 record 711 obtains timestamp t1 of message a, interface 114-2 record 712 obtains timestamp t2 of message b, and interface 114-3 record 713 obtains timestamp t3 of message c.

Interface 114-1 returns 721 an ACK response to processor 112, interface 114-2 returns 722 an ACK response to processor 112, and interface 114-3 returns 723 an ACK response to processor 113.

Alternatively, for 701 to 723 in fig. 7, it is assumed that part of the code executed at the processor 112 is as follows:

it is assumed that the processor 112, after the above partial code, also executes the following code:

the instruction "Barrier" is a memory Barrier instruction, meaning that after the data processing following the instruction is completed, the data after the execution can be continued to be processed. Specifically, after receiving ACKs (corresponding to 721, 722, and 723 in fig. 7) from the corresponding interfaces for all of message a, message b, and message c, the processor 112 provides message d following the "Barrier" instruction to the interface.

As shown in FIG. 7, processor 112 provides 731 message d to interface 114-1, interface 114-1 records 732 the timestamp t4 of the acquired message d, and interface 114-1 returns 733 an ACK response to processor 112.

It is appreciated that interfaces 114-1, 114-2, and 114-3 perform timestamp synchronization with each other and determine the sequence number of the acquired message, as described above in connection with fig. 3-5, and shown in fig. 7 by block 740, which is not repeated.

For the purposes of the following description, it is assumed that interface 114-1 determines that the sequence number of message a is 0 and that the sequence number of message d is 3. Interface 114-2 determines that the sequence number of message b is 1. Interface 114-3 determines that the sequence number of message c is 2.

As shown in fig. 7, interface 114-1 sends 741 a message a and interface 114-1 sends 742 a message d. Interface 114-2 sends 743 message b. Interface 114-3 sends 744 message c.

It will be appreciated that the process of sending messages between the interfaces is independent of each other, but for interface 114-1, it sends message a with sequence number 0 and then sends message d with sequence number 3.

For convenience in describing the processing procedure of the third communication device 130, it is assumed that the interface 134-1 receives the message d, the interface 134-2 receives the message a and the message b, and the interface 134-3 receives the message c.

Interface 134-1 provides 751 a first execution request to processor 132 that includes sequence number 3 of message d. Interface 134-2 provides 752 a second execution request to processor 132 that includes sequence number 0 of message a. Interface 134-2 provides 753 a third execution request to processor 132 that includes sequence number 1 of message b. The interface 134-3 provides 754 a fourth execution request to the processor 132 that includes the sequence number 2 of message c.

It will be appreciated that the transmission of messages in the network may occur out of order, that is, the order in which the messages are received by interface 134 may not be consistent with the order in which the messages are sent by interface 114. Then, correspondingly, the order of the execution requests acquired by the processor 132 may also be out of order, in which case the processor 132 issues execution permissions in sequence according to the sequence number in the execution request.

Processor 132 provides 761 execution permission 1 for the second execution request to interface 134-2. After the response from interface 134-2 is obtained 771, an execution permission 2 for the third execution request is provided 762 to interface 134-2. After the response from interface 134-2 is obtained 772, interface 134-3 is provided 763 with execution permission 3 for the fourth execution request. After the response from interface 134-3 is obtained 773, interface 134-1 is provided 764 with execution permission 4 for the first execution request, and the response from interface 134-1 is obtained 774.

It will be appreciated that after obtaining an execution permission from the processor 132, the interface 134 may write (not shown in fig. 7) a corresponding message to the memory 138 and return a response to the processor 132 associated with the execution permission for the processor 132 to process the execution request of the next sequence number.

Thus, embodiments of the present disclosure provide a mechanism for timing processing end-to-end messages in a multi-interface scenario. The multi-interface communication device for sending the message can determine the sequence number of the message at each interface based on the time stamp, so that the sequence of the message is marked by the sequence number, the correct processing of the message by the communication device for receiving the message is ensured, and the message processing error caused by disorder is avoided.

It should be appreciated that while the above embodiments are illustrated with three interfaces 114 and three interfaces 134 as examples, the present disclosure is not so limited. For example, although the first communication device 110 includes three interfaces 114, the first communication device 110 may also transmit messages through only two of the interfaces (e.g., interface 114-1 and interface 114-2). Similarly, although the third communication device 130 includes three interfaces 134, the third communication device 130 may receive messages through only two of the interfaces (e.g., interface 134-1 and interface 134-2).

It should be understood that in embodiments of the present disclosure, "first," "second," "third," etc. are merely intended to indicate that multiple objects may be different, but at the same time do not exclude that the objects are identical. The terms "first," "second," "third," and the like should not be construed as limiting the embodiments of the present disclosure in any way.

It should also be understood that the manner, case, category, and division of embodiments in the embodiments of the present disclosure are for descriptive convenience only and should not be construed as being particularly limiting, and that the features of the various manners, categories, cases, and embodiments may be combined with one another in a logical manner.

It should also be understood that the above is only intended to assist those skilled in the art in better understanding the embodiments of the present disclosure, and is not intended to limit the scope of the embodiments of the present disclosure. Various modifications, variations, combinations, etc. may be made by those skilled in the art in light of the above teachings. Such modifications, variations, or combinations are also within the scope of embodiments of the present disclosure.

It should also be appreciated that the foregoing description focuses on differences between the various embodiments and that the same or similar features may be referred to or otherwise referred to herein for brevity and clarity.

Fig. 8 shows a schematic block diagram of an example device 800 that may be used to implement embodiments of the present disclosure. The apparatus 800 may be implemented to include the first communication device 110, the second communication device 120, or the third communication device 130 shown in fig. 1.

As shown, the apparatus 800 includes a central processing unit (Central Processing Unit, CPU) 801, a Read-Only Memory (ROM) 802, and a random access Memory (Random Access Memory, RAM) 803. The CPU 801 may perform various appropriate actions and processes according to computer program instructions stored in the RAM 802 and/or the RAM 803 or computer program instructions loaded from the storage unit 808 into the ROM 802 and/or the RAM 803. Various programs and data required for operation of device 800 may also be stored in ROM 802 and/or RAM 803. The CPU 801 and ROM 802 and/or RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804. It is appreciated that the I/O interface 805 is implemented to include a plurality of interfaces, and accordingly, the device 800 is a multi-interface device.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The CPU 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples that may be implemented include, but are not limited to, a graphics processing unit (Graphics Processing Unit, GPU), various dedicated artificial intelligence (Artificial Intelligence, AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (Digital Signal Processor, DSP), and any suitable processor, controller, microcontroller, etc., which may accordingly be referred to as a computing unit. In some examples, the CPU 801 may be implemented as the data processing apparatus 100 as described above.

By way of example, device 800 in fig. 8 may be implemented as an electronic device, such as a mobile handset, desktop computer, laptop computer, notebook computer, tablet computer, personal communication system device, personal navigation device, personal digital assistant (Personal Digital Assistant, PDA), electronic book device, gaming device, internet of things (Internet of Things, ioT) device, in-vehicle device, aircraft, virtual Reality (VR) device, augmented Reality (Augmented Reality, AR) device, wearable device, television, cloud server, data center, and the like. Embodiments of the present disclosure are not limited in this regard.

Embodiments of the present disclosure also provide a chip within which the processor 112 and interface 114 as shown in fig. 1 may be integrated.

Embodiments of the present disclosure also provide a system chip that may include an input interface, an output interface, and a processing circuit. In the embodiment of the disclosure, the interaction of the signaling or data can be completed by the input interface and the output interface, and the generation and the processing of the signaling or data information can be completed by the processing circuit.

Embodiments of the present disclosure also provide a processor for coupling with a memory, the memory storing instructions that, when executed by the processor, cause the processor to perform the methods and functions referred to in any of the embodiments above.

Embodiments of the present disclosure also provide a computer program product containing instructions which, when run on a computer, cause the computer to perform the methods and functions involved in any of the embodiments described above.

Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, cause the processor to perform the methods and functions referred to in any of the embodiments above.

In general, the various embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor or other computing device. While various aspects of the embodiments of the disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product comprises computer executable instructions, such as instructions included in program modules, being executed in a device on a real or virtual processor of a target to perform the processes/methods as described above with reference to the figures. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between program modules as desired. Machine-executable instructions for program modules may be executed within local or distributed devices. In distributed devices, program modules may be located in both local and remote memory storage media.

Computer program code for carrying out methods of the present disclosure may be written in one or more programming languages. These computer program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the computer or other programmable data processing apparatus, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of this disclosure, computer program code or related data may be carried by any suitable carrier to enable an apparatus, device, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like. Examples of signals may include electrical, optical, radio, acoustical or other form of propagated signals, such as carrier waves, infrared signals, etc.

A computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a computer-readable storage medium include an electrical connection with one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Furthermore, although the operations of the methods of the present disclosure are depicted in the drawings in a particular order, this is not required to or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform. It should also be noted that features and functions of two or more devices according to the present disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided into multiple devices to be embodied.

The foregoing has described implementations of the present disclosure, and the foregoing description is exemplary, not exhaustive, and not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims

A communication device comprising a first interface and a second interface, wherein the first interface is configured to:

acquiring a first message from the inside of the communication device, wherein the first message has a first timestamp;

acquiring a second timestamp of a second message from the second interface;

determining a sequence number of the first message based at least on the first timestamp and the second timestamp; and

and sending the first message based on the serial number of the first message.
The apparatus of claim 1, wherein the first interface is configured to:

acquiring the first message with the first timestamp during a first time period;

obtaining the second timestamp of the second message from the second interface during a second time period, the second message being obtained by the second interface during the first time period; and

during a third time period, the sequence number of the first message is determined based at least on the first timestamp and the second timestamp.
The apparatus of claim 2, wherein the second period of time immediately follows the first period of time and the third period of time immediately follows the second period of time.
A device according to claim 2 or 3, wherein the second time period has a time length less than or equal to the time length of the first time period and the third time period has a time length less than or equal to the time length of the first time period.
The apparatus of any of claims 1-4, wherein the first interface is further configured to: providing the first timestamp of the first message to the second interface.
The apparatus of any of claims 1-5, wherein the first interface is configured to:

determining a temporal ordering of the first timestamp and the second timestamp; and

the sequence number is determined based on the location of the first timestamp in the temporal ordering.
The apparatus of any of claims 1-6, wherein the first interface and the second interface are located on the same chip or the first interface and the second interface belong to different chips.
A communication device comprising a first interface and a processor, wherein:

the first interface is configured to:

receiving a first message, the first message including a first sequence number,

providing a first execution application for the first message to a processor of the communication device, the first execution application including a first sequence number of the first message, and

Operating the first message based on a first execution permission from the processor;

the processor is configured to:

acquiring the first execution application from the first interface, and

the first interface is provided with the first execution permission for the first execution application.
The apparatus of claim 8, further comprising:

a second interface configured to:

receiving a second message, the second message including a second sequence number,

providing a second execution application for the second message to the processor, wherein the second execution application comprises a second serial number of the second message, and

operating on the second message based on a second execution permission from the processor;

and wherein the processor is further configured to:

acquiring the second execution application from the second interface;

determining an order in which the first execution permission is provided to the first interface and the second execution permission is provided to the second interface based on a size relationship of the first sequence number and the second sequence number.
A message transmission method comprises the following steps:

a first interface of a communication device acquires a first message from the inside of the communication device, wherein the first message has a first timestamp;

The first interface obtains a second timestamp of a second message from the second interface;

the first interface determines a sequence number of the first message based at least on the first timestamp and the second timestamp; and

the first interface sends the first message based on the sequence number of the first message.
The method of claim 10, wherein,

the first interface obtaining the first message includes: the first interface obtains the first message with the first timestamp during a first time period;

the first interface obtaining the second timestamp includes: the first interface obtaining the second timestamp of the second message from the second interface during a second time period, the second message being obtained by the second interface during the first time period; and

the first interface determining the sequence number includes: the first interface determines the sequence number of the first message during a third time period based at least on the first timestamp and the second timestamp.
The method of claim 11, wherein the second period of time immediately follows the first period of time and the third period of time immediately follows the second period of time.
The method of claim 11 or 12, wherein the second time period has a time length less than or equal to a time length of the first time period and the third time period has a time length less than or equal to a time length of the first time period.
The method of any of claims 10 to 13, further comprising: the first interface provides the first timestamp of the first message to the second interface.
The method of any of claims 10 to 14, wherein the first interface determining the sequence number comprises:

the first interface determining a temporal ordering of the first timestamp and the second timestamp; and

the first interface determines the sequence number based on a position of the first timestamp in the temporal ordering.
The method of any of claims 10 to 15, wherein the first interface and the second interface are located on the same chip or the first interface and the second interface belong to different chips.
A message transmission method comprises the following steps:

a first interface of a communication device receives a first message, wherein the first message comprises a first serial number;

the first interface provides a first execution application for the first message to a processor of the communication device, wherein the first execution application comprises a first serial number of the first message;

The processor providing the first execution permission for the first execution application to the first interface; and

the first interface operates on the first message based on a first execution permission from the processor.
The apparatus of claim 17, further comprising:

a second interface of the communication device receives a second message, wherein the second message comprises a second serial number;

the second interface provides a second execution application for the second message to the processor, wherein the second execution application comprises a second serial number of the second message; and

the processor determines an order in which the first execution permission is provided to the first interface and the second execution permission is provided to the second interface based on a size relationship of the first sequence number and the second sequence number.
A computer-readable storage medium storing computer-executable instructions that, when executed by a computer or processor, implement the method of any one of claims 1 to 9.
A computer program product comprising computer executable instructions thereon, which when executed, implement the method according to any of claims 1 to 9.