CN117478091A

CN117478091A - Method for manufacturing semiconductor device and semiconductor device

Info

Publication number: CN117478091A
Application number: CN202311277036.XA
Authority: CN
Inventors: 魏青云; 赖志国; 杨清华
Original assignee: Suzhou Huntersun Electronics Co Ltd
Current assignee: Suzhou Huntersun Electronics Co Ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2024-01-30

Abstract

The invention provides a method for manufacturing a semiconductor device, which comprises providing a substrate; forming a groove and a first sacrificial layer filling the groove in a first area of the upper surface of the substrate, and forming a second sacrificial layer on a second area of the upper surface of the substrate; depositing a lower electrode layer material on the substrate and performing patterning operation on the lower electrode layer material to form a first lower electrode covering the first sacrificial layer and a second lower electrode covering the second sacrificial layer; depositing a piezoelectric layer material covering the two lower electrodes and performing flattening or patterning operation on the piezoelectric layer material to form a first piezoelectric layer stacked on the first lower electrode and a second piezoelectric layer stacked on the second lower electrode, wherein the thickness of the first piezoelectric layer is larger than that of the second piezoelectric layer; forming a first upper electrode stacked on the first piezoelectric layer and a second upper electrode stacked on the second piezoelectric layer; and removing the sacrificial layer to form a cavity. The invention also provides a semiconductor device. By implementing the invention, the film bulk acoustic resonators with different effective electromechanical coupling coefficients can be formed.

Description

Method for manufacturing semiconductor device and semiconductor device

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.

Background

Existing typical filters generally include at least one series resonator in series between an input port and an output port, and at least one parallel resonator in parallel between the input port and the output port, where the series resonator and the parallel resonator have different frequencies. The following describes a conventional filter manufacturing process by taking an example in which a series resonator and a parallel resonator are both implemented using a thin film bulk acoustic resonator, and the frequency of the series resonator is higher than that of the parallel resonator.

Specifically, a substrate is first provided; then etching the substrate to form grooves on regions where the series resonator and the parallel resonator are to be formed, respectively, and filling the grooves with a sacrificial material (hereinafter, for convenience of description, the groove corresponding to the series resonator is referred to as a groove a and the sacrificial material filled in the groove a is referred to as a sacrificial material a, the groove corresponding to the parallel resonator is referred to as a groove B and the sacrificial material filled in the groove is referred to as a sacrificial material B); depositing a layer of first metal material on the substrate and performing patterning operation on the first metal material to form a lower electrode A covering the sacrificial material A and a lower electrode B covering the sacrificial material B; depositing a layer of piezoelectric material on the substrate and patterning the piezoelectric material to form a piezoelectric layer A covering the lower electrode A and a piezoelectric layer B covering the lower electrode B; depositing a layer of second metal material and performing patterning operation on the second metal material to form an upper electrode A above the piezoelectric layer A and an upper electrode B above the piezoelectric layer B; then, a mass loading layer for adjusting the frequency of the resonator is formed on the upper electrode B by a lift-off process, specifically, for the structure obtained after the upper electrode A and the upper electrode B are formed, a photoresist layer covering the upper surface of the structure is coated in a rotating way and patterned so as to expose the upper electrode B, a layer of a third metal material is deposited to cover the upper electrode B and the photoresist layer, and the photoresist layer is removed after the deposition is finished, wherein the third metal material covering the photoresist layer is removed simultaneously with the photoresist layer is removed, so that a metal layer (namely a mass loading layer) is formed on the upper electrode B; finally, the sacrificial material a is removed to form a cavity a under the lower electrode a and a cavity B under the lower electrode B. Wherein the upper electrode A, the piezoelectric layer A and the lower electrode A form a laminated structure A, the laminated structure A and the cavity A and a substrate part positioned below form a series resonator, and an overlapping area A exists between the upper electrode A, the piezoelectric layer A, the lower electrode A and the cavity A in the thickness direction of the device, and the overlapping area A forms an effective resonance area A of the series resonator; the mass loading layer, the upper electrode B, the piezoelectric layer B and the lower electrode B form a laminated structure B, the laminated structure B and the cavity B and a substrate part positioned below form a parallel resonator, and an overlapping area B exists between the mass loading layer, the upper electrode B, the piezoelectric layer B, the lower electrode B and the cavity B in the thickness direction of the device, and the overlapping area B forms an effective resonance area B of the parallel resonator. To this point the filter is formed. Fig. 1 is a schematic cross-sectional view of a conventional filter in the prior art, in which only one series resonator 1A and one parallel resonator 1B are schematically drawn, and the drawing of the connection structure between the resonators is omitted. In fig. 1, the substrate is denoted by reference numeral 10, the lower electrode a, the piezoelectric layer a, the upper electrode a, and the cavity a are denoted by reference numerals 11a, 12a, 13a, and 15a, respectively, and the lower electrode B, the piezoelectric layer B, the upper electrode B, the mass-loaded layer, and the cavity B are denoted by reference numerals 11B, 12B, 13B, 14B, and 15B, respectively.

It is known to those skilled in the art that the effective electromechanical coupling coefficient of a thin film bulk acoustic resonator is primarily dependent on the thickness of the piezoelectric layer in its effective resonant region. Based on this, for the filter formed by the foregoing method, since the thickness of the piezoelectric layer a in the effective resonance region a of the series resonator and the thickness of the piezoelectric layer B in the effective resonance region B of the parallel resonator are the same, all resonators in the filter have the same effective electromechanical coupling coefficient. However, in some application scenarios, the resonators in the filter are designed to have different effective electromechanical coupling coefficients according to the performance requirements of the filter, and it is obvious that the prior art cannot well meet the above requirements.

Disclosure of Invention

In order to overcome the above-described drawbacks of the prior art, the present invention provides a method of manufacturing a semiconductor device, the method comprising: providing a substrate; forming a groove and a first sacrificial layer filling the groove in a first area of the upper surface of the substrate, and forming a second sacrificial layer over a second area of the upper surface of the substrate; depositing a lower electrode layer material on the substrate and performing patterning operation on the lower electrode layer material to form a first lower electrode covering the first sacrificial layer and a second lower electrode covering the second sacrificial layer; depositing a piezoelectric layer material covering the first lower electrode and the second lower electrode and performing a planarization operation or a patterning operation on the piezoelectric layer material to form a first piezoelectric layer stacked on the first lower electrode and a second piezoelectric layer stacked on the second lower electrode, wherein the thickness of the first piezoelectric layer is greater than that of the second piezoelectric layer; forming and patterning an upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer to form a first upper electrode stacked over the first piezoelectric layer and a second upper electrode stacked over the second piezoelectric layer; the first sacrificial layer and the second sacrificial layer are removed to form a first cavity under the first lower electrode and a second cavity under the second lower electrode.

According to another aspect of the present invention, in the manufacturing method, the step of forming a recess and a first sacrificial layer filling the recess in a first region of the upper surface of the substrate, and forming a second sacrificial layer over a second region of the upper surface of the substrate includes: etching an upper surface of the substrate to form a recess in the first region, depositing a first sacrificial material on the upper surface of the substrate having a thickness greater than a depth of the recess; flattening the first sacrificial material to enable the upper surface of the first sacrificial material to be flush with the upper surface of the substrate, and forming the first sacrificial layer by the first sacrificial material filled in the groove; a second sacrificial material is deposited on the upper surface of the substrate and patterned to form a second sacrificial layer over the second region of the upper surface of the substrate.

According to still another aspect of the present invention, in the manufacturing method, after performing a planarization operation or a patterning operation on the piezoelectric layer material, the manufacturing method further includes: and adding a mass load to the first upper electrode and/or the second upper electrode.

According to still another aspect of the present invention, in the manufacturing method, in the case where the piezoelectric layer material is subjected to a planarization operation, the step of adding a mass load to the first upper electrode and/or the second upper electrode includes: forming the upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer using a deposition or electroplating method; etching the upper electrode layer material to enable the thickness of a part, overlapped with the first lower electrode and/or the second lower electrode, of the upper electrode layer material in the thickness direction of the device to be larger than the thickness of other parts of the upper electrode layer material; and patterning the upper electrode layer material to form the first upper electrode and the second upper electrode.

According to still another aspect of the present invention, in the manufacturing method, in the case where the piezoelectric layer material is subjected to a patterning operation, the step of adding a mass load to the first upper electrode and/or the second upper electrode includes: forming the upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer using a deposition method; treating an upper surface of the upper electrode layer material using a planarization operation such that a thickness of a portion of the upper electrode layer material overlapping the first lower electrode and/or the second lower electrode in a device thickness direction is greater than a thickness of other portions of the upper electrode layer material; and patterning the upper electrode layer material to form the first upper electrode and the second upper electrode.

According to still another aspect of the present invention, in the manufacturing method, after forming the first upper electrode and the second upper electrode, the manufacturing method further includes: a passivation layer is formed to cover the first upper electrode and the second upper electrode.

According to still another aspect of the present invention, the manufacturing method further includes: forming a through hole penetrating the piezoelectric layer; and filling conductive materials in the through holes, wherein the conductive materials respectively contact the second upper electrode and the first lower electrode, so that the second upper electrode and the first lower electrode form electrical connection.

The present invention also provides a semiconductor device including at least a first thin film bulk acoustic resonator and a second thin film bulk acoustic resonator, wherein: the first film bulk acoustic resonator comprises a substrate, a first cavity, a first lower electrode, a first piezoelectric layer and a first upper electrode, wherein the first lower electrode, the first piezoelectric layer and the first upper electrode are sequentially stacked above the first cavity; the second film bulk acoustic resonator comprises a substrate, a second cavity, a second lower electrode, a second piezoelectric layer and a second upper electrode which are sequentially stacked on the substrate, wherein the second cavity is positioned between the substrate and the second lower electrode, and extends towards the direction of the second lower electrode in an effective resonance area of the second film bulk acoustic resonator; the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer in the effective resonance areas of the first film bulk acoustic resonator and the second film bulk acoustic resonator.

According to another aspect of the present invention, in the semiconductor device, thicknesses of the first upper electrode and the second upper electrode are not equal, wherein the first upper electrode and/or the second upper electrode has an adjusting structure for adjusting a mass load.

According to still another aspect of the present invention, in the semiconductor device, the adjustment structure is stacked over the first upper electrode and/or the second upper electrode.

According to still another aspect of the present invention, in the semiconductor device, the adjustment structure is disposed between the first upper electrode and the first piezoelectric layer, and/or the adjustment structure is disposed between the second upper electrode and the second piezoelectric layer; the upper surfaces of both the first upper electrode and the second upper electrode are flush.

According to still another aspect of the present invention, in the semiconductor device, a material of the adjustment structure is the same as a material of the first upper electrode and/or the second upper electrode.

According to still another aspect of the present invention, in the semiconductor device, the first piezoelectric layer is connected to the second piezoelectric layer.

According to still another aspect of the present invention, the semiconductor device further includes: and a passivation layer covering the first upper electrode and the second upper electrode.

According to still another aspect of the present invention, the semiconductor device further includes: conductive material contacting the second upper electrode and the first lower electrode, respectively.

The manufacturing method of the semiconductor device provided by the invention has the following advantages: the thin film bulk acoustic resonators with different piezoelectric layer thicknesses are formed on one substrate, so that the thin film bulk acoustic resonators with different effective electromechanical coupling coefficients are obtained, and the thin film bulk acoustic resonators are further suitable for application scenes with different requirements on the effective electromechanical coupling coefficients of the thin film bulk acoustic resonators. Correspondingly, the semiconductor device provided by the invention can well meet application scenes with different requirements on the effective electromechanical coupling coefficient of the film bulk acoustic resonator.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic cross-sectional view of a conventional filter of the prior art;

fig. 2 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 3-9 are schematic cross-sectional views of various stages of a semiconductor device fabricated in accordance with the method flow shown in fig. 2;

fig. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

FIGS. 11-16 are schematic cross-sectional views of stages of adding mass loading to a first upper electrode and a second upper electrode, according to an embodiment of the invention;

fig. 17 and 18 are schematic cross-sectional views of a semiconductor device formed on the basis of the structure shown in fig. 16 in accordance with two embodiments of the present invention;

fig. 19 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 20 through 27 are schematic cross-sectional views of various stages of a semiconductor device fabricated in accordance with the method flow shown in fig. 19;

fig. 28 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

FIG. 29 is a schematic cross-sectional view of adding mass loading to a first upper electrode and a second upper electrode, in accordance with an embodiment of the invention;

fig. 30 and 31 are schematic cross-sectional views of semiconductor devices formed on the basis of the structure shown in fig. 29, in accordance with two embodiments of the present invention.

The same or similar reference numbers in the drawings refer to the same or similar parts.

Detailed Description

For a better understanding and explanation of the present invention, reference will be made to the following detailed description of the invention taken in conjunction with the accompanying drawings.

The invention provides a method for manufacturing a semiconductor device. As shown in fig. 2, the manufacturing method includes:

in step S101, a substrate is provided;

in step S102, forming a recess and a first sacrificial layer filling the recess in a first region of an upper surface of a substrate, and forming a second sacrificial layer over a second region of the upper surface of the substrate;

in step S103, a lower electrode layer material is deposited on the substrate and patterned to form a first lower electrode overlying the first sacrificial layer and a second lower electrode overlying the second sacrificial layer;

in step S104, a piezoelectric layer material covering the first lower electrode and the second lower electrode is deposited and subjected to a planarization operation to form a first piezoelectric layer stacked on the first lower electrode and a second piezoelectric layer stacked on the second lower electrode, the thickness of the first piezoelectric layer being greater than the thickness of the second piezoelectric layer;

In step S105, an upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer is formed and subjected to patterning operation to form a first upper electrode stacked on the first piezoelectric layer and a second upper electrode stacked on the second piezoelectric layer;

in step S106, the first sacrificial layer and the second sacrificial layer are removed to form a first cavity under the first lower electrode and a second cavity under the second lower electrode.

The above steps will be described in detail with reference to fig. 3 to 9.

Specifically, in step S101, as shown in fig. 3, a substrate 101 is provided. The material of the substrate 101 is not limited in any way, and may be implemented using materials that may be present or may be present in the future for manufacturing a thin film bulk acoustic resonator substrate, such as silicon, germanium, silicon germanium, etc., and for the sake of brevity, all possible materials of the substrate 101 are not listed here. In addition, the dimensions (including thickness, etc.) of the substrate 101 may be tailored to actual design requirements.

In this embodiment, two types of thin film bulk acoustic resonators having different effective electromechanical coupling coefficients will be formed on the substrate 101, and hereinafter, the two types of thin film bulk acoustic resonators will be referred to as a first thin film bulk acoustic resonator and a second thin film bulk acoustic resonator, respectively, wherein the first thin film bulk acoustic resonator has a first effective electromechanical coupling coefficient and the second thin film bulk acoustic resonator has a second effective electromechanical coupling coefficient, and the first effective electromechanical coupling coefficient is different from the second effective electromechanical coupling coefficient. In addition, in the present embodiment, the acoustic reflection structures of the first film bulk acoustic resonator and the second film bulk acoustic resonator are cavities, wherein the cavity of the first film bulk acoustic resonator is referred to as a first cavity, and the cavity of the second film bulk acoustic resonator is referred to as a second cavity. After step S101 is performed and before step S102 is performed, a region of the upper surface of the substrate 101 corresponding to the first cavity (hereinafter referred to as a first region) and a region of the upper surface of the substrate 101 corresponding to the second cavity (hereinafter referred to as a second region) are predetermined according to actual design requirements.

In addition, it should be noted that, the specific number of each of the first film bulk acoustic resonator and the second film bulk acoustic resonator in the semiconductor device is determined by the actual design requirement, which is not limited in any way by the present invention. In the description of the subsequent steps, only the process of forming one first thin film bulk acoustic resonator and one second thin film bulk acoustic resonator on the substrate 101 is schematically depicted in the drawings for the sake of simplicity.

In step S102, as shown in fig. 4 and 5, a groove and a first sacrificial layer 102 filling the groove are formed in a first region of the upper surface of the substrate 101, and a second sacrificial layer 103 is formed over a second region of the upper surface of the substrate 101.

The formation steps of the first sacrificial layer 102 are explained below.

First, a groove is formed. The groove is formed as follows: first, an upper surface of a substrate is etched to form a recess in a first region. Specifically, a photoresist layer (not shown) is formed on the upper surface of the substrate 101, and the photoresist layer is patterned to expose a first region of the upper surface of the substrate 101; then, etching the first area exposed on the upper surface of the substrate 101 by using the photoresist layer as a mask; and finally removing the photoresist. Based on different application scenarios, various dry etching processes or wet etching processes may be employed for etching. The depth of the grooves may be set as desired, and the embodiment of the present invention is not limited thereto.

After forming the recess, a first sacrificial material having a thickness greater than the depth of the recess is deposited on the upper surface of the substrate 101. In this embodiment, the first sacrificial material may be silicon nitride (SiN). It should be noted that the first sacrificial material is not limited to silicon nitride, and other suitable materials may be selected according to practical design requirements, for example, conventional sacrificial materials such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), intrinsic silicon dioxide (USG), and the like, where the material that can ensure that the sacrificial layer has etching selectivity in the subsequent step of releasing the sacrificial layer is suitable for the present invention. Since the choice of material for the sacrificial layer is related to the material of the other parts of the thin film bulk acoustic resonator, all possible materials for the sacrificial layer are not listed here for the sake of brevity.

Finally, a planarization operation is performed on the first sacrificial material, so that the upper surface of the first sacrificial material is flush with the upper surface of the substrate 101 (as shown in fig. 4), and the first sacrificial material filled in the recess forms the first sacrificial layer 102. It should be noted that the term "flush" means that the difference in height between the two is within the allowable range of process error, and the same applies hereinafter.

The formation of the first sacrificial layer 102 is described above, and the formation steps of the second sacrificial layer 103 are described below in this embodiment.

A second sacrificial material is deposited on the upper surface of the substrate 101 and patterned to form a second sacrificial layer 103 over a second region of the upper surface of the substrate 101 (as shown in fig. 5). The shape of the second sacrificial layer is not particularly limited, in this embodiment, the shape of the second sacrificial layer is a shape with a vertical section having an equal width, and in other embodiments, the second sacrificial layer may be other shapes, for example, a shape with a vertical section having a trapezoid shape. The second sacrificial material may also be any of the first sacrificial materials listed above, such as silicon nitride (SiN).

It is to be understood that one positional relationship of the first region and the second region is shown in fig. 5 by way of example only, but the positional relationship of the first region and the second region is not limited to the above, and may be provided at other positions of the substrate 101 and form other positional relationships according to the specific layout of the resonator, the size of the substrate, and the like.

In step S103, as shown in fig. 6, a lower electrode layer material is deposited on the substrate 101 and patterned to form a first lower electrode 104 covering the first sacrificial layer 102 and a second lower electrode 105 covering the second sacrificial layer 103.

The invention is not limited in any way to the material of the lower electrode layer, and can be realized by using materials which are used for manufacturing the thin film bulk acoustic resonator electrode and can occur in the prior or future, such as silicon, germanium, silicon germanium, selenium, molybdenum and the like. The thickness of the lower electrode may range from 200nm to 900nm.

Since the first lower electrode 104 and the second lower electrode 105 are formed using the same lower electrode layer material, they have the same thickness. However, the first lower electrode 104 and the second lower electrode 105 are formed to have different heights due to different arrangement manners of the first sacrificial layer 102 and the second sacrificial layer 103. The difference in height between the first lower electrode 104 and the second lower electrode 105 means that the height of the upper surface of the first lower electrode 104 located above the first sacrificial layer 102 is different from the height of the upper surface of the second lower electrode 105 located above the second sacrificial layer 103. More specifically, as shown in fig. 6, the height of the upper surface of the first lower electrode 104 located at the portion above the first sacrificial layer 102 is lower than the height of the upper surface of the second lower electrode 105 located at the portion above the second sacrificial layer 103.

The patterning of the bottom electrode may be formed using conventional processes, and for brevity, the process of patterning the bottom electrode will not be described in detail herein.

In step S104, as shown in fig. 7, a piezoelectric layer material covering the first lower electrode 104 and the second lower electrode 105 is deposited and subjected to a planarization operation to form a first piezoelectric layer 106 stacked on the first lower electrode 104 and a second piezoelectric layer 107 stacked on the second lower electrode 105. In this embodiment, the first piezoelectric layer 106 and the second piezoelectric layer 107 are connected, that is, the first piezoelectric layer 106 and the second piezoelectric layer 107 are in an integrated structure. In other embodiments, both the first piezoelectric layer 106 and the second piezoelectric layer 107 may not be connected according to actual design requirements. It should be noted that, in order to ensure the formation of the second piezoelectric layer 107, the thickness of the second sacrificial layer 103 needs to be reasonably set, specifically, the thickness of the second sacrificial layer 103 needs to be smaller than the thickness of the piezoelectric layer material, otherwise, the portion of the piezoelectric layer material located above the second sacrificial layer 103 after planarization will be completely removed, and the effective second piezoelectric layer 107 cannot be formed.

The piezoelectric layer material may be implemented using conventional piezoelectric materials such as aluminum nitride, zinc oxide, lithium niobate, lead zirconate titanate, and the like.

After the planarization operation, the upper surface of the first piezoelectric layer 106 is made flush with the upper surface of the second piezoelectric layer 107. But the thicknesses of the first piezoelectric layer 106 and the second piezoelectric layer 107 are different due to the difference in height of the first lower electrode 104 and the second lower electrode 105. Here, the thickness of the first piezoelectric layer 106 and the second piezoelectric layer 107 being different means that the thickness of the portion of the first piezoelectric layer 106 located above the first sacrifice layer 102 and the thickness of the portion of the second piezoelectric layer 107 located above the second sacrifice layer 103 are different. More specifically, as shown in fig. 7, the thickness (denoted by y1 in the figure) of the portion of the first piezoelectric layer 106 located above the first sacrificial layer 102 is larger than the thickness (denoted by y2 in the figure) of the portion of the second piezoelectric layer 107 located above the second sacrificial layer 103.

In this embodiment, the thickness range of the first piezoelectric layer 106 (i.e., the thickness range of the portion of the first piezoelectric layer 106 located above the first sacrificial layer 102) may be 500nm to 1000nm, for example, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, etc., and the thickness range of the second piezoelectric layer 107 (i.e., the thickness of the portion of the second piezoelectric layer 107 located above the second sacrificial layer 103) may be 100nm to 400nm, for example, 100nm, 200nm, 300nm, 400nm, etc.

In step S105, an upper electrode layer material covering the first piezoelectric layer 106 and the second piezoelectric layer 107 is formed and subjected to patterning operation to form a first upper electrode 108 stacked on the first piezoelectric layer 106 and a second upper electrode 109 stacked on the second piezoelectric layer 107. In the present embodiment, the thickness of each of the first upper electrode 108 and the second upper electrode 109 may be in the range of 100nm to 300nm, and it may be the same as or similar to the material of the lower electrode (i.e., the first lower electrode 104 and the second lower electrode 105), for example, molybdenum (Mo) is used. The first upper electrode 108 and the second upper electrode 109 may be formed using conventional processes, and a detailed description of the manufacturing process of the first upper electrode 108 and the second upper electrode 109 is omitted herein for the sake of brevity.

In step S106, as shown in fig. 9, the first sacrificial layer 102 and the second sacrificial layer 103 are removed to form a first cavity 110 under the first lower electrode 104 and a second cavity 111 under the second lower electrode 105. The present invention is not limited in particular to the manner of removing the sacrificial layer, and may be realized, for example, by forming a release hole exposing the sacrificial layer and removing the sacrificial layer through the release hole using an etching solution.

In this embodiment, the first upper electrode 108, the first piezoelectric layer 106, the first lower electrode 104, the first cavity 110 and the underlying substrate portion together form a first thin film bulk acoustic resonator, where an overlapping area exists between the first cavity 110 and the first lower electrode 104, the first piezoelectric layer 106 and the first upper electrode 108 in the device thickness direction, and the overlapping area is an effective resonance area of the first thin film bulk acoustic resonator (an area located between the dashed line a1 and the dashed line a2 above the substrate 101 in fig. 9, which is simply expressed, simply referred to as a "first effective resonance area"). The second upper electrode 109, the second piezoelectric layer 107, the second lower electrode 105, the second cavity 111, and the underlying substrate portion together form a second thin film bulk acoustic resonator, where an overlapping area exists between the second cavity 111 and the second lower electrode 105, the second piezoelectric layer 107, and the second upper electrode 109 in the thickness direction of the device, and the overlapping area is an effective resonance area of the second thin film bulk acoustic resonator (an area located between a dashed line a3 and a dashed line a4 above the substrate 101 in fig. 9, which is simply expressed, and is simply referred to as a "second effective resonance area"). The first effective electromechanical coupling coefficient of the first film bulk acoustic resonator is mainly determined by the thickness of the first piezoelectric layer 106 in the first effective resonance region, and the second effective electromechanical coupling coefficient of the second film bulk acoustic resonator is mainly determined by the thickness of the second piezoelectric layer 107 in the second effective resonance region, and since the thickness of the first piezoelectric layer 106 in the first effective resonance region is different from the thickness of the second piezoelectric layer 107 in the second effective resonance region, the first effective electromechanical coupling coefficient of the first film bulk acoustic resonator is different from the second effective electromechanical coupling coefficient of the second film bulk acoustic resonator.

According to the manufacturing method of the semiconductor device, due to the fact that the arrangement modes of the first sacrificial layer and the second sacrificial layer are different, the thin film bulk acoustic wave resonators with different thicknesses of the piezoelectric layers can be formed on one substrate only by carrying out one-time planarization operation on the piezoelectric layer materials, so that the thin film bulk acoustic wave resonators with different effective electromechanical coupling coefficients are obtained, and the manufacturing method is further suitable for application scenes with different requirements on the effective electromechanical coupling coefficients of the thin film bulk acoustic wave resonators.

In this embodiment, two types of thin film bulk acoustic resonators having different effective electromechanical coupling coefficients, i.e., a first thin film bulk acoustic resonator and a second thin film bulk acoustic resonator, are formed on a substrate. It will be appreciated by those skilled in the art that in other embodiments, N types of film bulk acoustic resonators having different effective electromechanical coupling coefficients may also be formed on the substrate according to actual design requirements, where N is an integer greater than 2. For convenience of description, the N kinds of thin film bulk acoustic resonators will be hereinafter referred to as a first thin film bulk acoustic resonator, a second thin film bulk acoustic resonator, …, and an nth thin film bulk acoustic resonator, respectively. The description will be made taking the cavity as the sound reflection structure of N film bulk acoustic resonators as an example, wherein the cavity of the first film bulk acoustic resonator is called a first cavity, the cavity of the second film bulk acoustic resonator is called a second cavity, and the cavity of the nth film bulk acoustic resonator of … is called an nth cavity. Specifically, first, a first region of the upper surface of the substrate corresponding to the first cavity, a second region corresponding to the second cavity, …, and an nth region corresponding to the nth cavity are predetermined according to actual design requirements. Next, the first region is etched to form a recess and a first sacrificial layer is formed in the recess, a second sacrificial layer is formed over the second region …, and an nth sacrificial layer is formed over the nth region, wherein the second sacrificial layer, …, and the nth sacrificial layer are different in thickness. Then depositing a piezoelectric layer material on the substrate and performing planarization operation on the piezoelectric layer material to form a first piezoelectric layer over the first sacrificial layer, a second piezoelectric layer over the second sacrificial layer, …, and an N piezoelectric layer over the N sacrificial layer, wherein the thicknesses of the first piezoelectric layer, the second piezoelectric layer, …, and the N piezoelectric layer are different; next, forming a first upper electrode on the first piezoelectric layer, forming a second upper electrode on the second piezoelectric layer, …, and forming an nth upper electrode on the nth piezoelectric layer; finally, removing the first sacrificial layer to form a first cavity, removing the second sacrificial layer to form a second cavity, …, and removing the Nth sacrificial layer to form an Nth cavity, thereby forming a first film bulk acoustic resonator, a second film bulk acoustic resonator, …, and an Nth film bulk acoustic resonator, respectively, wherein the first film bulk acoustic resonator, the second film bulk acoustic resonator, …, and the Nth film bulk acoustic resonator have different effective electromechanical coupling coefficients.

As shown in fig. 10, the manufacturing method provided by the present invention may further include forming a passivation layer 112 covering the first upper electrode 108 and the second upper electrode 109. Specifically, a passivation material is deposited on the upper surface of the structure obtained after the step S105 is performed and planarized, thereby forming a passivation layer 112 covering the first and second upper electrodes 108 and 109. The passivation material planarization operation can form a passivation layer with a flat surface, so as to form the thin film bulk acoustic resonator with the flat surface. After the passivation layer 112 is formed, the process continues to step S106. It will be appreciated by those skilled in the art that in other embodiments, the passivation layer 112 may also be formed directly by depositing a passivation material without a planarization operation, and the present invention is not limited in this regard. The passivation layer 112 may be implemented using aluminum nitride (AlN) and may have a thickness ranging from 100nm to 300nm. It will be appreciated that the material and thickness of the passivation layer 112 are merely exemplary and not limiting, and that other materials and thicknesses of passivation layer may be selected and fabricated as desired by one skilled in the art. The passivation layer 112 may protect the lower electrode and serve as an insulation function.

It should be noted that, a plurality of thin film bulk acoustic resonators on the same substrate 101 need to be electrically connected to form a filter. In this embodiment, as shown in fig. 10, after the passivation layer 112 is formed and before the first sacrificial layer 102 and the second sacrificial layer 103 are released, a through hole (not shown in the drawing) penetrating the passivation layer 112 and the piezoelectric layer may be formed, which exposes at least a part of the above-described second upper electrode 109 (a right side portion upper surface and an entire right side wall of the second upper electrode 109 as shown in fig. 10) and a part of the above-described first lower electrode 104 (a left side portion upper surface of the first lower electrode 104 as shown in fig. 10). The portions of the second upper electrode 109 and the first lower electrode 104 exposed through the via hole shown in fig. 10 may make the length of the conductive material used therebetween short, thereby not only facilitating wiring but also saving costs. The vias may be fabricated using existing processes and will not be described in detail herein. Next, the via hole is filled with a conductive material 113, and the conductive material 113 and the via hole together form a conductive via structure for electrically connecting the second upper electrode 109 and the first lower electrode 104. The conductive material 113 may be a metal, an alloy (e.g., copper alloy, aluminum alloy, or the like), a composite metal (e.g., titanium steel composite, copper steel composite, titanium zinc composite, or the like), or the like.

Based on different application scenarios, the above electrical connection may also be achieved by metal wires. It will be appreciated by those skilled in the art that the above-mentioned conductive hole structures and metal wires are exemplary, and should not be construed as limiting the electrical connection structure between different film bulk acoustic resonators, and any structure capable of achieving electrical connection between different film bulk acoustic resonators is suitable for the present invention, and for brevity, all the possibilities of the electrical connection structure are not listed here. It should be noted that, in fig. 10, the electrical connection between the first thin film bulk acoustic resonator and the second thin film bulk acoustic resonator is implemented by connecting the first lower electrode 104 and the second upper electrode 109 through the conductive hole structure, which is only an embodiment, and the electrical connection between the first thin film bulk acoustic resonator and the second thin film bulk acoustic resonator may be implemented by, for example, electrical connection between the first upper electrode 108 and the second upper electrode 109 (for example, a connection portion where the first upper electrode 108 and the second upper electrode 109 are formed while etching the upper electrode layer material), and also by, for example, electrical connection between the first lower electrode 104 and the second lower electrode 105 (for example, a connection portion where the first lower electrode 104 and the second lower electrode 105 are formed while etching the lower electrode layer material), and also by, for example, electrical connection between the first upper electrode 108 and the second lower electrode 105, which may be designed accordingly according to practical design requirements.

It will be appreciated by those skilled in the art that for embodiments that do not include a passivation layer in the semiconductor device, the electrical connection between the second upper electrode 109 and the first lower electrode 104 may be formed after the first upper electrode 108 and the second upper electrode 109 are formed.

In some application scenarios, according to practical design requirements, besides different effective electromechanical coupling coefficients of different film bulk acoustic resonators, the frequency of the film bulk acoustic resonator needs to be adjusted. In a preferred embodiment, after the planarization operation is performed on the piezoelectric layer material, the method for manufacturing a semiconductor device provided by the present invention further includes: and adding mass load to the first upper electrode and/or the second upper electrode. In the following, with reference to fig. 11 to 16, a description will be given of how to add mass load to the first upper electrode and the second upper electrode in a specific embodiment based on the structure shown in fig. 7.

Specifically, first, as shown in fig. 11, an upper electrode layer material 1081' covering the first piezoelectric layer 106 and the second piezoelectric layer 107 is formed using a deposition or plating method. The upper electrode layer material 1081' may be the same as the upper electrode layer material described above, and the deposition may be a physical vapor deposition method. In this embodiment, the thickness of the upper electrode layer material 1081' is in the range of 100nm to 800nm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, or the like. More preferably, the thickness of the upper electrode layer material 1081' ranges from 200nm to 600nm.

Then, as shown in fig. 12, a photoresist layer is spin-coated on the upper surface of the upper electrode layer material 1081' and patterned to form a photoresist layer 120, the photoresist layer 120 being located over the first sacrificial layer 102.

Next, as shown in fig. 13, the exposed area of the upper surface of the upper electrode layer material 1081' is etched using the photoresist layer 120 as a mask, and the photoresist layer 120 is removed after the etching is completed. The etching depth of the upper electrode layer material 1081 'in this step is defined as a first etching depth, wherein the first etching depth is smaller than the upper electrode layer material 1081'. Preferably the first etch depth is in the range of 10nm to 200nm.

Next, as shown in fig. 14, a photoresist layer is continuously spin-coated on the upper surface of the structure shown in fig. 13 and patterned to form a photoresist layer 121 and a photoresist layer 122, wherein the photoresist layer 121 is located above the first sacrificial layer 102 and the photoresist layer 122 is located above the second sacrificial layer 103.

Next, as shown in fig. 15, the exposed areas of the upper surface of the upper electrode layer material 1081' are etched using the photoresist layer 121 and the photoresist layer 122 as masks, and the photoresist layer 121 and the photoresist layer 122 are removed after the etching is completed. The etching depth of the upper electrode layer material 1081 'in this step is defined as a second etching depth, which is smaller than the difference between the upper electrode layer material 1081' and the first etching depth. Preferably the second etch depth is in the range of 10nm to 200nm. Up to this point, the upper electrode layer material 1081' subjected to the etching twice forms the bump 108' over the first sacrificial layer 102 and the bump 109' over the second sacrificial layer 103.

Finally, as shown in fig. 16, the upper electrode layer material 1081' is patterned to form a first upper electrode and a second upper electrode, where the patterned upper electrode layer material is located above the first piezoelectric layer 106, i.e., the first upper electrode, and the patterned upper electrode layer material is located above the second piezoelectric layer 107, i.e., the second upper electrode. In this embodiment, the first upper electrode includes a protrusion 108 'and a portion located below the protrusion 108' (hereinafter, denoted as a first base 108 "), and the second upper electrode includes a protrusion 109 'and a portion located below the protrusion 109' (hereinafter, denoted as a second base 109"). Wherein protrusion 108' may act to adjust the mass loading of the first upper electrode, hereinafter protrusion 108' is referred to as first adjustment structure 108'; the projection 109 'may serve to adjust the mass loading of the second upper electrode, hereinafter referred to as the second adjustment structure 109'. The thickness of the first and second adjustment structures 108', 109' is responsive to actual design requirements.

In the embodiment, the base and the corresponding adjusting structure are made of the same material and are in an integral structure, and the base and the corresponding adjusting structure are manually divided by using a dotted line in the figure, which is only for convenience of description of the positional relationship of the base and the corresponding adjusting structure. In other embodiments, the upper electrode layer may be made of two different materials, so that the adjusting structure and the corresponding substrate are made of different materials, which is not limited in the present invention.

After forming the first and second upper electrodes having the adjustment structure, as shown in fig. 17, the first and second sacrificial layers 102 and 103 are removed to form the first cavity 110 under the first lower electrode 104 and the second cavity 111 under the second lower electrode 105, respectively.

In this embodiment, the first adjusting structure 108 'and the second adjusting structure 109' with different thicknesses are formed by etching the upper electrode layer material twice (in this embodiment, the thickness of the first adjusting structure 108 'is greater than that of the second adjusting structure 109'), so as to realize the adjustment of the mass loads of the first upper electrode and the second upper electrode, and further, the frequencies of the first film bulk acoustic resonator and the second film bulk acoustic resonator can well meet the design requirement. As mentioned in the background, the frequency adjustment of the thin film bulk acoustic resonator is currently mainly realized by forming a mass loading layer through a lift-off (lift-off) process, and the lift-off process has complicated steps, is not easy to realize and has higher cost, so that the overall manufacturing process of the device is correspondingly complicated, is not easy to realize and has higher cost. The invention can form the adjusting structure without using a lift-off process, thereby realizing the adjustment of the frequency of the film bulk acoustic resonator. That is, compared to the prior art, the process of the present invention is simpler to implement, easier to implement, and relatively lower in cost.

It should be noted that:

(1) In this embodiment, the thickness of the first adjustment structure 108 'is greater than the thickness of the second adjustment structure 109'. It will be appreciated by those skilled in the art that in other embodiments, the thickness of the first adjustment structure 108 'may be made smaller than the thickness of the second adjustment structure 109' by etching twice according to actual design requirements.

(2) In this embodiment, the first and second adjustment structures 108 'and 109' are formed by two etches. It will be appreciated by those skilled in the art that in other embodiments, the first adjusting structure for adjusting the mass load of the first upper electrode or the second adjusting structure for adjusting the mass load of the second upper electrode may be formed by only one etching according to actual design requirements, which is not limited in the present invention.

(3) In the present embodiment, after forming the first upper electrode having the first adjustment structure 108 'and the second upper electrode having the second adjustment structure 109', the first sacrificial layer 102 and the second sacrificial layer 103 are removed to form the first cavity 110 and the second cavity 111. It will be appreciated by those skilled in the art that in other embodiments, after forming the first upper electrode having the first adjustment structure 108 'and the second upper electrode having the second adjustment structure 109', as shown in fig. 18, a passivation layer 112 covering the first upper electrode and the second upper electrode may be formed first, then a conductive material 113 for making electrical connection between the thin film bulk acoustic resonators may be formed according to actual design requirements, and finally the first sacrificial layer 102 and the second sacrificial layer 103 may be removed to form the first cavity 110 and the second cavity 111, respectively.

(4) In this embodiment, two thicknesses of the adjusting structure are formed by two times of etching, that is, a first adjusting structure for adjusting the mass load of the first upper electrode in the first film bulk acoustic resonator and a second adjusting structure for adjusting the mass load of the second upper electrode in the second film bulk acoustic resonator. Those skilled in the art will appreciate that in other embodiments, M thickness adjustment structures may be formed according to actual design requirements, where M is an integer greater than 2. Let m=3 be taken as an example for illustration. It is assumed that the design requirement is that the first upper electrodes of all the first thin film bulk acoustic resonators have an adjustment structure a, that the second upper electrodes of part of the second thin film bulk acoustic resonators have an adjustment structure B, and that the second upper electrodes of the other second thin film bulk acoustic resonators have an adjustment structure C, wherein the thickness of the adjustment structure a is greater than that of the adjustment structure B, and that the thickness of the adjustment structure B is greater than that of the adjustment structure C. Based on the above, after the upper electrode layer material is deposited, first etching is performed on the region of the upper electrode layer material, where the adjusting structure a is to be formed, then second etching is performed on the region of the upper electrode layer material, where the adjusting structure a is to be formed, and the region of the upper electrode layer material, where the adjusting structure B is to be formed, and then third etching is performed on the region of the upper electrode layer material, where the adjusting structure a, the adjusting structure B, and the adjusting structure C, where the thicknesses are different, are formed. The specific value of M and the specific forming position of each adjusting structure are determined by actual design requirements, and the foregoing examples are only for illustrative purposes, and should not be construed as limiting the invention. In addition, for the case where M is greater than 3, and so on, a description thereof will not be repeated here.

The invention provides a method for manufacturing a semiconductor device. As shown in fig. 19, the manufacturing method includes:

in step S401, a substrate is provided;

in step S402, forming a recess and a first sacrificial layer filling the recess in a first region of an upper surface of a substrate, and forming a second sacrificial layer over a second region of the upper surface of the substrate;

in step S403, a lower electrode layer material is deposited on the substrate and patterned to form a first lower electrode overlying the first sacrificial layer and a second lower electrode overlying the second sacrificial layer;

in step S404, a piezoelectric layer material covering the first lower electrode and the second lower electrode is deposited and patterned to form a first piezoelectric layer stacked on the first lower electrode and a second piezoelectric layer stacked on the second lower electrode, the thickness of the first piezoelectric layer being greater than the thickness of the second piezoelectric layer;

in step S405, an upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer is formed and patterned to form a first upper electrode stacked over the first piezoelectric layer and a second upper electrode stacked over the second piezoelectric layer;

in step S406, the first sacrificial layer and the second sacrificial layer are removed to form a first cavity under the first lower electrode and a second cavity under the second lower electrode.

The above steps will be described in detail with reference to fig. 20 to 27.

Specifically, in step S401, as shown in fig. 20, a substrate 401 is provided.

In step S402, as shown in fig. 21 and 22, a groove and a first sacrificial layer 402 filling the groove are formed in a first region of an upper surface of a substrate 401, and a second sacrificial layer 403 is formed over a second region of the upper surface of the substrate 401.

In step S403, as shown in fig. 23, a lower electrode layer material is deposited on the substrate 401 and patterned to form a first lower electrode 404 covering the first sacrificial layer 402 and a second lower electrode 405 covering the second sacrificial layer 403.

The steps S401 to S403 may refer to the steps S101 to S103 in the foregoing embodiments, and are not described herein.

In step S404, first, as shown in fig. 24, a piezoelectric layer material 4061 is deposited that covers the first lower electrode 404 and the second lower electrode 405. The piezoelectric layer material 4061 is then patterned to form a first piezoelectric layer stacked over the first lower electrode 404 and a second piezoelectric layer stacked over the second lower electrode 405, wherein the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer. Here, the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer, which means that the thickness of the portion of the first piezoelectric layer located above the first sacrificial layer 402 is greater than the thickness of the portion of the second piezoelectric layer located above the second sacrificial layer 403. The piezoelectric layer material may be implemented using conventional piezoelectric materials such as aluminum nitride, zinc oxide, lithium niobate, lead zirconate titanate, and the like.

In this embodiment, the patterning operation of the piezoelectric layer material 4061 is performed as follows: first, a first photoresist layer (not shown) is spin-coated on the upper surface of the piezoelectric layer material 4061 and patterned to expose the region of the piezoelectric layer material 4061 above the first sacrificial layer 402; the exposed areas of piezoelectric layer material 4061 are then etched to form recesses (hereinafter first recesses) over first sacrificial layer 402; then removing the first photoresist layer; a second photoresist layer (not shown) is then spin-coated on the upper surface of the piezoelectric layer material 4061 and patterned to expose the region of the piezoelectric layer material 4061 above the second sacrificial layer 403; the exposed region of the piezoelectric layer material 4061 is then etched to form a recess (hereinafter referred to as a second recess) above the second sacrificial layer 403, wherein the portion of the piezoelectric layer material 4061 above the second sacrificial layer 403 is etched to a greater depth than the portion of the piezoelectric layer material 4061 above the first sacrificial layer 402; the second photoresist layer is then removed. Thus, a first piezoelectric layer and a second piezoelectric layer having different thicknesses are formed (specifically, the thickness of the first piezoelectric layer is larger than that of the second piezoelectric layer). Preferably, as shown in fig. 25, the portion of the piezoelectric layer material 4061 located above the second sacrificial layer 403 is etched to a depth greater than the thickness of the second sacrificial layer 403. In addition, a first recess formed by etching the piezoelectric layer material 4061 over the first sacrificial layer 402 is denoted by reference numeral 406a in fig. 25, and a second recess formed by etching the piezoelectric layer material 4061 over the second sacrificial layer 403 is denoted by reference numeral 407 a.

It will be appreciated by those skilled in the art that in other embodiments, only the first recess 406a or only the second recess 407a may be formed, as long as the first and second piezoelectric layers having different thicknesses are formed by patterning the piezoelectric layer materials.

In step S405, as shown in fig. 26, an upper electrode layer material covering the first piezoelectric layer 406 and the second piezoelectric layer 407 is formed and subjected to patterning operation to form a first upper electrode 408 stacked on the first piezoelectric layer 406 and a second upper electrode 409 stacked on the second piezoelectric layer 407. The first upper electrode 408 and the second upper electrode 409 may be formed using conventional processes, and a detailed description of the manufacturing process of the first upper electrode 408 and the second upper electrode 409 is omitted herein for the sake of brevity.

In step S406, as shown in fig. 27, the first sacrificial layer 402 and the second sacrificial layer 403 are removed to form a first cavity 410 under the first lower electrode 404 and a second cavity 411 under the second lower electrode 405.

In this embodiment, the first upper electrode 408, the first piezoelectric layer 406, the first lower electrode 404, the first cavity 410 and the underlying substrate portion together form a first thin film bulk acoustic resonator, where an overlapping area exists between the first cavity 410 and the first lower electrode 404, the first piezoelectric layer 406 and the first upper electrode 408 in the device thickness direction, and the overlapping area is a first effective resonance area of the first thin film bulk acoustic resonator (an area located between the dashed line d1 and the dashed line d2 on the substrate 401 in fig. 27). The second upper electrode 409, the second piezoelectric layer 407, the second lower electrode 405, the second cavity 411, and the underlying substrate portion together form a second thin film bulk acoustic resonator, where an overlapping area exists between the second cavity 411 and the second lower electrode 405, the second piezoelectric layer 407, and the second upper electrode 409 in the device thickness direction, and the overlapping area is a second effective resonance area of the second thin film bulk acoustic resonator (an area located between the dashed line d3 and the dashed line d4 on the substrate 401 in fig. 27). The first effective electromechanical coupling coefficient of the first film bulk acoustic resonator is mainly determined by the thickness of the first piezoelectric layer 406 in the first effective resonance region, and the second effective electromechanical coupling coefficient of the second film bulk acoustic resonator is mainly determined by the thickness of the second piezoelectric layer 407 in the second effective resonance region, and since the thickness of the first piezoelectric layer 406 in the first effective resonance region is different from the thickness of the second piezoelectric layer 407 in the second effective resonance region, the first effective electromechanical coupling coefficient of the first film bulk acoustic resonator is different from the second effective electromechanical coupling coefficient of the second film bulk acoustic resonator.

The manufacturing method of the semiconductor device provided by the invention can further form the film bulk acoustic wave resonators with different thicknesses of the piezoelectric layers on one substrate by patterning the piezoelectric layer material, so that the film bulk acoustic wave resonators with different effective electromechanical coupling coefficients are obtained, and the manufacturing method is further suitable for application scenes with different requirements on the effective electromechanical coupling coefficients of the film bulk acoustic wave resonators.

In this embodiment, the first piezoelectric layer and the second piezoelectric layer with different thicknesses are formed by patterning the piezoelectric layer material, so that two types of thin film bulk acoustic resonators with different effective electromechanical coupling coefficients are formed on the substrate. It will be appreciated by those skilled in the art that in other embodiments, according to practical design requirements, L piezoelectric layers with different thicknesses (where L is an integer greater than 2) may be patterned to form L thin film bulk acoustic resonators with different effective electromechanical coupling coefficients on the substrate.

As shown in fig. 28, the manufacturing method provided by the present invention may further include forming a passivation layer 412 covering the first upper electrode 408 and the second upper electrode 409. The passivation layer 412 may be formed by referring to the passivation layer 112 in fig. 10, and is not described herein for brevity.

It should be noted that, a plurality of thin film bulk acoustic resonators on the same substrate 401 need to be electrically connected to form a filter. In this embodiment, as shown in fig. 28, a conductive hole structure filled with a conductive material 413 is formed for making an electrical connection between the second upper electrode 409 and the first lower electrode 404. The formation process of the conductive via structure may refer to the formation process of the conductive via structure in fig. 10, which is not described herein for brevity.

In some application scenarios, according to practical design requirements, besides different effective electromechanical coupling coefficients of different film bulk acoustic resonators, the frequency of the film bulk acoustic resonator needs to be adjusted. In a preferred embodiment, after patterning the piezoelectric layer material, the method for manufacturing a semiconductor device provided by the present invention further includes: and adding mass load to the first upper electrode and/or the second upper electrode. Next, with reference to fig. 29, a description will be given of how to add mass load to the first upper electrode and the second upper electrode in a specific embodiment based on the structure shown in fig. 25.

Specifically, first, an upper electrode layer material covering the first piezoelectric layer 406 and the second piezoelectric layer 407 is formed using a deposition or plating method on the basis of the structure shown in fig. 25. In this embodiment, the thickness of the upper electrode layer material is in the range of 300nm to 1000nm, for example, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, or the like. More preferably, the upper electrode layer material has a thickness in the range of 400nm to 800nm. Then, the upper electrode layer material is planarized, in this embodiment, the portion of the planarized upper electrode layer material above the first recess 406a has a thickness greater than the depth of the first recess 406a, and the portion of the planarized upper electrode layer material above the second recess 407a has a thickness greater than the depth of the second recess 407 a. Finally, the planarized upper electrode layer material is patterned to form a first upper electrode and a second upper electrode as shown in fig. 29, wherein the first upper electrode is located above the first piezoelectric layer 406, and the second upper electrode is located above the second piezoelectric layer 407. In this embodiment, the first upper electrode includes a portion located within first recess 406a and a portion located above first recess 406a (hereinafter referred to as first base 408 "), and the second upper electrode includes a portion located within second recess 407a and a portion located above second recess 407a (hereinafter referred to as second base 409"). Wherein the portion located in the first recess 406a may serve as a tuning of the mass loading of the first upper electrode, hereinafter referred to as a first tuning feature 408'; the portion located within second recess 407a may serve to adjust the mass loading of the second upper electrode, hereinafter referred to as second adjustment structure 409'. In the embodiment, the base and the corresponding adjusting structure are made of the same material and are in an integral structure, and the base and the corresponding adjusting structure are manually divided by using a dotted line in the figure, which is only for convenience of description of the positional relationship of the base and the corresponding adjusting structure. In other embodiments, the material of the adjusting structure and the material of the corresponding substrate may be different, which is not limited in any way by the present invention.

After forming the first upper electrode having the first adjustment structure 408 'and the second upper electrode having the second adjustment structure 409', as shown in fig. 30, the first sacrificial layer 402 and the second sacrificial layer 403 are removed to form a first cavity 410 under the first lower electrode 404 and a second cavity 411 under the second lower electrode 405, respectively.

In this embodiment, the piezoelectric layer materials are patterned to form the first piezoelectric layer and the second piezoelectric layer with different thicknesses, and the first recess 406a and the second recess 407a formed in the patterning process just form the first adjusting structure 408 'and the second adjusting structure 409' after the upper electrode layer materials are filled, so that the mass loads of the first upper electrode and the second upper electrode are adjusted, and the frequencies of the first film bulk acoustic resonator and the second film bulk acoustic resonator can well meet the design requirements. As mentioned in the background, the frequency adjustment of the thin film bulk acoustic resonator is currently mainly realized by forming a mass loading layer through a lift-off (lift-off) process, and the lift-off process has complicated steps, is not easy to realize and has higher cost, so that the overall manufacturing process of the device is correspondingly complicated, is not easy to realize and has higher cost. The invention can form the adjusting structure without using a lift-off process, thereby realizing the adjustment of the frequency of the film bulk acoustic resonator. That is, compared to the prior art, the process of the present invention is simpler to implement, easier to implement, and relatively lower in cost.

It should be noted that:

(1) In order to make the first adjustment structure 408 'and the second adjustment structure 409' different in effect on the mass adjustment of the upper electrode, it is necessary to make the thicknesses thereof different. That is, in patterning the piezoelectric layer material, the depths of the first recess 406a formed on the first piezoelectric layer 406 and the second recess 407a formed on the second piezoelectric layer 407 need to be different.

(2) In this embodiment, the thickness of the first adjustment structure 408 'is greater than the thickness of the second adjustment structure 409'. It will be appreciated by those skilled in the art that in other embodiments, the thickness of the first adjustment structure 408 'may be made smaller than the thickness of the second adjustment structure 409' depending on the actual design requirements.

(3) In this embodiment, a first adjustment structure 408 'and a second adjustment structure 409' are formed. It will be appreciated by those skilled in the art that in other embodiments, only the first adjustment structure 408 'for adjusting the mass load of the first upper electrode or only the second adjustment structure 409' for adjusting the mass load of the second upper electrode may be formed according to actual design requirements, which the present invention is not limited in any way.

(4) In the present embodiment, after forming the first upper electrode having the first adjustment structure 408 'and the second upper electrode having the second adjustment structure 409', the first sacrificial layer 402 and the second sacrificial layer 403 are removed to form the first cavity 410 and the second cavity 411. It will be appreciated by those skilled in the art that in other embodiments, after forming the first upper electrode having the first adjustment structure 408 'and the second upper electrode having the second adjustment structure 409', as shown in fig. 31, a passivation layer 412 covering the first upper electrode and the second upper electrode may be formed first, then a conductive material 413 for making electrical connection between the thin film bulk acoustic resonators may be formed according to actual design requirements, and finally the first sacrificial layer 402 and the second sacrificial layer 403 may be removed to form the first cavity 410 and the second cavity 411, respectively.

(5) In the present embodiment, two thickness adjustment structures, i.e., a first adjustment structure for adjusting the mass load of the first upper electrode in the first thin film bulk acoustic resonator and a second adjustment structure for adjusting the mass load of the second upper electrode in the second thin film bulk acoustic resonator, are formed. Those skilled in the art will appreciate that in other embodiments, K thickness adjustment structures may be formed according to actual design requirements, where K is an integer greater than 2. Let k=3 be taken as an example. It is assumed that the design requirement is that the first upper electrodes of all the first thin film bulk acoustic resonators have an adjustment structure a ', that the second upper electrodes of part of the second thin film bulk acoustic resonators have an adjustment structure B', and that the second upper electrodes of the other second thin film bulk acoustic resonators have an adjustment structure C ', wherein the thicknesses of the adjustment structure a', the adjustment structure B ', and the adjustment structure C' are different. Based on this, when patterning the piezoelectric layer material, grooves of different thicknesses are formed at positions corresponding to the adjustment structures a ', B' and C ', so that the adjustment structures a', B 'and C' of different thicknesses can be formed. The specific value of K and the specific forming position of each adjusting structure are determined by actual design requirements, and the foregoing examples are only for illustrative purposes, and should not be construed as limiting the invention. In addition, for the case where K is greater than 3, and so on, a description thereof will not be repeated here.

Correspondingly, the invention also provides a semiconductor device, which at least comprises a first film bulk acoustic resonator and a second film bulk acoustic resonator, wherein:

the first film bulk acoustic resonator comprises a substrate, a first cavity, a first lower electrode, a first piezoelectric layer and a first upper electrode, wherein the first lower electrode, the first piezoelectric layer and the first upper electrode are sequentially stacked above the cavity;

the second film bulk acoustic resonator comprises the substrate, a second cavity, a second lower electrode, a second piezoelectric layer and a second upper electrode which are sequentially stacked on the substrate, wherein the second cavity is positioned between the substrate and the second lower electrode, and extends towards the direction of the second lower electrode in an effective resonance area of the second film bulk acoustic resonator;

the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer in the effective resonance region of the first film bulk acoustic resonator and the second film bulk acoustic resonator.

The respective constituent parts of the above-described semiconductor device will be described in detail below with reference to fig. 9 and 27 in a specific embodiment.

Specifically, as shown in fig. 9 and 27, the semiconductor device provided by the present invention includes a first thin film bulk acoustic resonator and a second thin film bulk acoustic resonator, in which: the first thin film bulk acoustic resonator includes a substrate (denoted by reference numeral 101 in fig. 9, denoted by reference numeral 401 in fig. 27), a first cavity (denoted by reference numeral 110 in fig. 9, denoted by reference numeral 410 in fig. 27), a first lower electrode (denoted by reference numeral 104 in fig. 9, denoted by reference numeral 404 in fig. 27) stacked in this order over the first cavity, a first piezoelectric layer (denoted by reference numeral 106 in fig. 9, denoted by reference numeral 406 in fig. 27), and a first upper electrode (denoted by reference numeral 108 in fig. 27. The first cavity is located between the substrate and the first lower electrode, wherein the first cavity is surrounded by a groove opened on the substrate and the first lower electrode, that is, the first cavity extends in the direction of the substrate within an effective resonance region of the first thin film bulk acoustic resonator.

The effective resonance region of the first thin film bulk acoustic resonator may be understood as the "first effective resonance region" described above. The depth of the first cavity may be determined as needed and its shape may be set as needed, for example, a structure having an inverted trapezoidal shape in longitudinal section as shown in fig. 9 and 27.

The second film bulk acoustic resonator includes a substrate (denoted by reference numeral 101 in fig. 9, denoted by reference numeral 401 in fig. 27), a second cavity (denoted by reference numeral 111 in fig. 9, denoted by reference numeral 411 in fig. 27), a second lower electrode (denoted by reference numeral 105 in fig. 9, denoted by reference numeral 405 in fig. 27) stacked in this order over the substrate, a second piezoelectric layer (denoted by reference numeral 107 in fig. 27, denoted by reference numeral 407 in fig. 9), and a second upper electrode (denoted by reference numeral 109 in fig. 27), the second cavity being located between the substrate and the second lower electrode, wherein the second cavity is formed over the substrate, surrounded by the substrate and the second lower electrode protruding upward, that is, the second cavity extends in the direction of the second lower electrode within the effective resonance region of the second film bulk acoustic resonator.

The effective resonance region of the second thin film bulk acoustic resonator can be understood as the "second effective resonance region" described above. The shape of the second cavity may be set as desired, for example, it may be a structure of the same width up and down in the longitudinal section shown in fig. 9 and 27, which facilitates deposition of the layers thereon.

In this embodiment, the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer. The thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer, which means that the thickness of the portion of the first piezoelectric layer located in the first effective resonance region is greater than the thickness of the portion of the second piezoelectric layer located in the second effective resonance region.

In particular, to the structure shown in fig. 9, the thicknesses of the first lower electrode 104 and the second lower electrode 105 are the same, but the upper surface of the first lower electrode 104 in the first effective resonance region of the first bulk acoustic wave resonator is lower than the lower surface of the second lower electrode 105 in the second effective resonance region of the second bulk acoustic wave resonator due to the difference in the arrangement positions of the first cavity 110 and the second cavity 111, and thus the lower surface of the first piezoelectric layer 106 in the first effective resonance region is lower than the lower surface of the second piezoelectric layer 107 in the second effective resonance region. And the upper surfaces of both the first piezoelectric layer 106 and the second piezoelectric layer 107 are flush, such that the thickness of the first piezoelectric layer 106 in the first effective resonance region is greater than the thickness of the second piezoelectric layer 107 in the second effective resonance region. In the present embodiment, (1) the first bottom electrode 104 and the second bottom electrode 105 have the same thickness, so that both are formed by depositing the bottom electrode layer material at one time. In other implementations, the thicknesses of the first lower electrode 104 and the second lower electrode 105 may also be different, but the thicknesses need to be controlled such that the upper surface of the first lower electrode 104 in the first effective resonance region is lower than the upper surface of the second lower electrode 105 in the second effective resonance region, thereby ensuring that the thickness of the first piezoelectric layer 106 in the first effective resonance region is greater than the thickness of the second piezoelectric layer 107 in the second effective resonance region. (2) In this embodiment, the first upper electrode 108 and the second upper electrode 109 have the same thickness, so that both can be formed by one deposition of the upper electrode layer material. In other embodiments, the thicknesses of the first upper electrode 108 and the second upper electrode 109 may be different, which is not limited in the present invention. (3) The upper surfaces of the first piezoelectric layer 106 and the second piezoelectric layer 107 are flush and can be achieved by a single planarization operation after deposition of the piezoelectric layer material.

In particular, to the structure shown in fig. 27, by forming the first recess on the first piezoelectric layer 406 and the second recess on the second piezoelectric layer 407, the thickness of the portion of the first piezoelectric layer 406 in the first effective resonance region is made larger than the thickness of the portion of the second piezoelectric layer 407 in the second effective resonance region. In the present embodiment, (1) grooves are formed in each of the first piezoelectric layer 406 and the second piezoelectric layer 407. In other embodiments, only the first recess may be formed on the first piezoelectric layer 406, or only the second recess may be formed on the second piezoelectric layer, so long as the thickness of the portion of the first piezoelectric layer 406 in the first effective resonance region may be made greater than the thickness of the portion of the second piezoelectric layer 407 in the second effective resonance region, which is not limited in the present invention. (2) In this embodiment, the first bottom electrode 404 and the second bottom electrode 405 have the same thickness, so that both can be formed by one deposition of the bottom electrode layer material. In other implementations, the thicknesses of the first bottom electrode 404 and the second bottom electrode 405 may also be different. (3) In this embodiment, the first upper electrode 408 and the second upper electrode 409 have the same thickness, so that both can be formed by one deposition of the upper electrode layer material. In other embodiments, the thicknesses of the first upper electrode 408 and the second upper electrode 409 may be different, which is not limited in the present invention. (4) The first recess on the first piezoelectric layer 406 and the second recess on the second piezoelectric layer 407 may be formed by patterning the piezoelectric layer material after deposition of the piezoelectric layer material.

In addition, (1) in the present embodiment, as shown in fig. 9 and 27, the first piezoelectric layer is connected to the second piezoelectric layer, thereby forming an integrated structure. In other embodiments, the first piezoelectric layer and the second piezoelectric layer may not be connected to each other in order to meet the requirements of the corresponding scenario. (2) The materials and dimensions of the substrate, the first lower electrode, the second lower electrode, the first piezoelectric layer, the second piezoelectric layer, the first upper electrode, and the second upper electrode, etc. may be referred to as those of the corresponding portions, and for brevity, descriptions thereof will not be repeated.

The semiconductor device provided by the invention comprises the first film bulk acoustic resonator and the second film bulk acoustic resonator, wherein the thickness of the first piezoelectric layer in the first effective resonance area of the first film bulk acoustic resonator is larger than that of the second piezoelectric layer in the second effective resonance area of the second film bulk acoustic resonator, so that the effective electromechanical coupling coefficients of the first film bulk acoustic resonator and the second film bulk acoustic resonator are different, and the semiconductor device is further suitable for application scenes with different requirements on the effective electromechanical coupling coefficients of the film bulk acoustic resonators.

According to practical design requirements, as shown in fig. 10 and 28, the semiconductor device provided by the present invention may further include a passivation layer (denoted by reference numeral 112 in fig. 10 and reference numeral 412 in fig. 28) covering the first upper electrode and the second upper electrode. The material, dimensions, etc. of the passivation layer may be referred to in the corresponding parts of the foregoing, and for the sake of brevity, the description will not be repeated here.

Multiple thin film bulk acoustic resonators on the same substrate need to be electrically connected to form a filter. In one embodiment, as shown in fig. 10 and 28, the first lower electrode of the first film bulk acoustic resonator is connected to the second upper electrode of the second film bulk acoustic resonator through a conductive via structure. The conductive via structure is composed of a via hole penetrating the passivation layer and the piezoelectric layer and a conductive material (denoted by reference numeral 113 in fig. 10 and reference numeral 413 in fig. 28) filled in the via hole. The selection of conductive materials, etc. may be referred to in the corresponding parts of the foregoing, and for brevity, description will not be repeated here. It should be noted that (1) in other embodiments, the electrical connection between the thin film bulk acoustic resonators may also be implemented by, for example, metal wires, and for the sake of brevity, all possible electrical connection modes are not listed here. (2) In other embodiments, the electrical connection between the first film bulk acoustic resonator and the second film bulk acoustic resonator may be implemented by, for example, electrical connection between the first upper electrode and the second upper electrode, or by, for example, electrical connection between the first lower electrode and the second lower electrode, or by, for example, electrical connection between the first upper electrode and the second lower electrode, which is not limited in this respect, and may be designed accordingly according to actual design requirements. (3) In this embodiment, the conductive via structure penetrates through the passivation layer and the piezoelectric layer, and in other embodiments, if the semiconductor device does not include a passivation layer, the conductive via structure penetrates through only the piezoelectric layer.

In some application scenarios, according to practical design requirements, besides different effective electromechanical coupling coefficients of different film bulk acoustic resonators, the frequency of the film bulk acoustic resonator needs to be adjusted. In a preferred embodiment, the thicknesses of the first upper electrode of the first film bulk acoustic resonator and the second upper electrode of the second film bulk acoustic resonator are not equal, wherein the first upper electrode and/or the second upper electrode has an adjusting structure for adjusting the mass load (the first upper electrode has an adjusting structure of a first adjusting structure, and the second upper electrode has an adjusting structure of a second adjusting structure). Here, the thicknesses of the first upper electrode and the second upper electrode are not equal, which means that the thickness of the first upper electrode in the first effective resonance region is different from the thickness of the second upper electrode in the second effective resonance region. In the following, an example will be described in which the first upper electrode has a first adjustment structure and the second upper electrode has a second adjustment structure, with reference to fig. 17 and 30.

As shown in fig. 17, the adjustment structure is stacked on top of its corresponding upper electrode. In this embodiment, the first upper electrode includes a first base 108 "and a first adjustment structure 108', the first adjustment structure 108' being located above the first base 108" for adjustment of the mass load of the first upper electrode; the second upper electrode comprises a second base body 109 "and a second adjustment structure 109', the second adjustment structure 109' being located on the second base body 109" for adjustment of the mass load of the second upper electrode.

As shown in fig. 30, the adjustment structure is located between the upper electrode and the piezoelectric layer corresponding thereto. In this embodiment, a first recess is formed on the first piezoelectric layer 406, a second recess is formed on the second piezoelectric layer 407, a first upper electrode is formed on the first piezoelectric layer 406, and a second upper electrode is formed on the second piezoelectric layer 407, wherein upper surfaces of both the first upper electrode and the second upper electrode are flush. For the first upper electrode, it includes a first base 408 "and a first adjustment structure 408', where the first adjustment structure 408' is located in a first recess on the first piezoelectric layer 406 for adjusting the mass load of the first upper electrode, the first base 408" is located above the first adjustment structure 408', i.e. the first adjustment structure 408' is disposed between the first upper electrode and the first piezoelectric layer 406; for the second upper electrode, it comprises a second base 409 "and a second adjustment structure 409', wherein the second adjustment structure 409' is located in a second recess on the second piezoelectric layer 407 for adjusting the mass load of the second upper electrode, the second base 409" is located above the second adjustment structure 409', i.e. the second adjustment structure 409' is arranged between the second upper electrode and the second piezoelectric layer 407.

It should be noted that (1) for the structures shown in fig. 17 and 30, the adjusting structure is the same as the upper electrode material, that is, the first adjusting structure, the first substrate, the second adjusting structure and the second substrate are the same, and accordingly, the first substrate and the first adjusting structure are integrated, the second substrate and the second adjusting structure are integrated, and the substrates and the corresponding adjusting structures are manually divided by using dashed lines in the figure, so that only the positional relationship between the two is convenient to be described; it will be appreciated by those skilled in the art that in other embodiments, the adjustment structure may be made of a different material than the upper electrode, for example, the first adjustment structure and the second adjustment structure may be made of the same material, but different from the first substrate and the second substrate, etc., which is not limited in any way. (2) For the structure shown in fig. 17, in order to realize the adjustment function of the mass load of the upper electrode, the first adjustment structure 108', the first base 108", the first piezoelectric layer 106, the first lower electrode 104, and the first cavity 110 have an overlap region in the device thickness direction, and similarly, the second adjustment structure 109', the second base 109", the second piezoelectric layer 107, the second lower electrode 105, and the second cavity 111 have an overlap region in the device thickness direction. (3) For the structure shown in fig. 17, the first adjusting structure 108 'and the second adjusting structure 109' are correspondingly formulated according to actual design requirements, and typically, the thicknesses of the first adjusting structure 108 'and the second adjusting structure 109' are different. The thicknesses of the first adjusting structure 108 'and the second adjusting structure 109' may refer to the content of the corresponding portions, and for brevity, the description will not be repeated here. For the structure shown in fig. 30, the thickness of the first adjustment structure 408 'and the second adjustment structure 409' are related to the depth of the grooves in the first piezoelectric layer and the second piezoelectric layer. (4) With respect to the structures shown in fig. 17 and 30, in other embodiments, only the first upper electrode may have the first adjustment structure, or only the second upper electrode may have the second adjustment structure, which is not limited in any way by the present invention. (5) For the structure shown in fig. 17, the first and second accommodating structures 108 'and 109' may be formed by patterning after depositing the upper electrode layer material; for the structure shown in fig. 30, the piezoelectric layer material is patterned to form a first recess on the first piezoelectric layer 406 and a second recess on the second piezoelectric layer 407, and the first adjustment structure 408 'and the second adjustment structure 409' can be formed by means of the first recess and the second recess. Compared with the existing semiconductor device with the upper electrode quality load layer formed by the lift-off process, the semiconductor device provided by the invention has the advantages of simpler process, easiness in implementation and relatively lower cost.

The semiconductor device having the adjustment structure for the upper electrode may further include a passivation layer (denoted by reference numeral 112 in fig. 18 and reference numeral 412 in fig. 31) covering the first upper electrode and the second upper electrode as shown in fig. 18 and fig. 31. In addition, for the semiconductor device of which the upper electrode has a specific adjustment structure, the connection manner between the two thin film bulk acoustic resonators can be referred to as the case where the upper electrode has no adjustment structure in the foregoing. Fig. 17 and 30 show a specific connection manner, that is, a first lower electrode of the first film bulk acoustic resonator is connected to a second upper electrode of the second film bulk acoustic resonator through a conductive hole structure. The conductive via structure is composed of a via hole penetrating the passivation layer and the piezoelectric layer and a conductive material filled in the via hole (denoted by reference numeral 113 in fig. 18 and reference numeral 413 in fig. 31).

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements, units or steps, and that the singular does not exclude a plurality. Various components, units or means recited in the system claims may also be implemented by means of software or hardware by means of one component, unit or means.

The foregoing disclosure is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming a groove and a first sacrificial layer filling the groove in a first area of the upper surface of the substrate, and forming a second sacrificial layer over a second area of the upper surface of the substrate;

depositing a lower electrode layer material on the substrate and performing patterning operation on the lower electrode layer material to form a first lower electrode covering the first sacrificial layer and a second lower electrode covering the second sacrificial layer;

depositing a piezoelectric layer material covering the first lower electrode and the second lower electrode and performing a planarization operation or a patterning operation on the piezoelectric layer material to form a first piezoelectric layer stacked on the first lower electrode and a second piezoelectric layer stacked on the second lower electrode, wherein the thickness of the first piezoelectric layer is greater than that of the second piezoelectric layer;

forming and patterning an upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer to form a first upper electrode stacked over the first piezoelectric layer and a second upper electrode stacked over the second piezoelectric layer;

The first sacrificial layer and the second sacrificial layer are removed to form a first cavity under the first lower electrode and a second cavity under the second lower electrode.

2. The manufacturing method according to claim 1, wherein the steps of forming a recess and a first sacrificial layer filling the recess in a first region of the upper surface of the substrate, and forming a second sacrificial layer over a second region of the upper surface of the substrate include:

etching an upper surface of the substrate to form a recess in the first region, depositing a first sacrificial material on the upper surface of the substrate having a thickness greater than a depth of the recess;

flattening the first sacrificial material to enable the upper surface of the first sacrificial material to be flush with the upper surface of the substrate, and forming the first sacrificial layer by the first sacrificial material filled in the groove;

a second sacrificial material is deposited on the upper surface of the substrate and patterned to form a second sacrificial layer over the second region of the upper surface of the substrate.

3. The manufacturing method according to claim 1, further comprising, after performing a planarization operation or a patterning operation on the piezoelectric layer material:

And adding a mass load to the first upper electrode and/or the second upper electrode.

4. A manufacturing method according to claim 3, wherein the step of adding a mass load to the first upper electrode and/or the second upper electrode in the case where the piezoelectric layer material is subjected to a flattening operation comprises:

forming the upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer using a deposition or electroplating method;

etching the upper electrode layer material to enable the thickness of a part, overlapped with the first lower electrode and/or the second lower electrode, of the upper electrode layer material in the thickness direction of the device to be larger than the thickness of other parts of the upper electrode layer material;

and patterning the upper electrode layer material to form the first upper electrode and the second upper electrode.

5. A manufacturing method according to claim 3, wherein the step of adding a mass load to the first upper electrode and/or the second upper electrode in the case where the piezoelectric layer material is subjected to a patterning operation comprises:

forming the upper electrode layer material covering the first piezoelectric layer and the second piezoelectric layer using a deposition method;

Treating an upper surface of the upper electrode layer material using a planarization operation such that a thickness of a portion of the upper electrode layer material overlapping the first lower electrode and/or the second lower electrode in a device thickness direction is greater than a thickness of other portions of the upper electrode layer material;

6. The manufacturing method according to claim 1, further comprising, after forming the first upper electrode and the second upper electrode:

a passivation layer is formed to cover the first upper electrode and the second upper electrode.

7. The manufacturing method according to claim 1 or 6, further comprising, after forming the first upper electrode and the second upper electrode:

forming a through hole penetrating the piezoelectric layer;

and filling conductive materials in the through holes, wherein the conductive materials respectively contact the second upper electrode and the first lower electrode, so that the second upper electrode and the first lower electrode form electrical connection.

8. A semiconductor device comprising at least a first thin film bulk acoustic resonator and a second thin film bulk acoustic resonator, wherein:

The first film bulk acoustic resonator comprises a substrate, a first cavity, a first lower electrode, a first piezoelectric layer and a first upper electrode, wherein the first lower electrode, the first piezoelectric layer and the first upper electrode are sequentially stacked above the first cavity;

the second film bulk acoustic resonator comprises a substrate, a second cavity, a second lower electrode, a second piezoelectric layer and a second upper electrode which are sequentially stacked on the substrate, wherein the second cavity is positioned between the substrate and the second lower electrode, and extends towards the direction of the second lower electrode in an effective resonance area of the second film bulk acoustic resonator;

the thickness of the first piezoelectric layer is greater than the thickness of the second piezoelectric layer in the effective resonance areas of the first film bulk acoustic resonator and the second film bulk acoustic resonator.

9. The semiconductor device of claim 8, wherein:

the thicknesses of the first upper electrode and the second upper electrode are not equal, wherein the first upper electrode and/or the second upper electrode is provided with an adjusting structure for adjusting mass load.

10. The semiconductor device of claim 9, wherein:

the adjustment structure is stacked over the first upper electrode and/or the second upper electrode.

11. The semiconductor device of claim 9, wherein:

the adjusting structure is arranged between the first upper electrode and the first piezoelectric layer, and/or the adjusting structure is arranged between the second upper electrode and the second piezoelectric layer;

the upper surfaces of both the first upper electrode and the second upper electrode are flush.

12. The semiconductor device according to claim 10 or 11, wherein:

the material of the adjusting structure is the same as that of the first upper electrode and/or the second upper electrode.

13. The semiconductor device according to any one of claims 8 to 11, wherein:

the first piezoelectric layer is connected with the second piezoelectric layer.

14. The semiconductor device according to any one of claims 8 to 11, further comprising:

and a passivation layer covering the first upper electrode and the second upper electrode.

15. The semiconductor device according to any one of claims 8 to 11, further comprising:

conductive material contacting the second upper electrode and the first lower electrode, respectively.