TWI839228B - Piezoelectric structure and methods for forming the same - Google Patents

Abstract

A piezoelectric structure includes a substrate, a seed layer over the substrate, a bottom electrode over the seed layer, a piezoelectric material layer over the bottom electrode, a top electrode over the piezoelectric material layer, and a passivation layer over the piezoelectric material layer and covering the top electrode. The substrate includes a base and an oxide layer on the base. The oxide layer has a cavity. The piezoelectric structure further includes a loading material layer above the cavity. The bottom electrode, the piezoelectric material layer and the top electrode are stacked over the substrate in a first direction.The loading material layer is disposed under one of the bottom electrode and the top electrode.

Description

Piezoelectric structure and method for forming the same

The present invention relates to a piezoelectric structure and a method for forming the same, and more particularly to a piezoelectric structure comprising a load material layer manufactured by a semiconductor process and a method for forming the same.

Filters are often used in electronic devices to capture signals within a specific frequency range and remove unnecessary noise. Filters can allow signals within a specific frequency band to pass through, while attenuating all signals outside this specific frequency band. Filters can be divided into low pass filters, high pass filters, band pass filters, and band reject filters according to their functions. The film bulk acoustic resonator (FBAR) filter in the filter converts electrical energy into sound waves to form resonance through the piezoelectric effect of the piezoelectric film. It has the characteristics of small size, low cost, high quality factor (Q), strong power handling ability, high frequency and compatibility with IC technology. It has good application prospects in the new generation of wireless communication systems and ultra-trace biochemical detection fields. Although the existing processes of piezoelectric filter devices (such as metal lift-off processes) can achieve their original intended purposes, they are not satisfactory in all aspects. For example, the existing processes are not compatible with semiconductor processes. Therefore, there are still problems that need to be further overcome and room for improvement in the formation method of piezoelectric structures.

Some embodiments of the present disclosure provide a piezoelectric structure, including a substrate, including a base material and an oxide layer located on the base material, wherein the oxide layer has a cavity; a seed layer located above the substrate; a bottom electrode located above the seed layer; a piezoelectric material layer located above the bottom electrode; a top electrode located above the piezoelectric material layer; a protective layer located on the piezoelectric material layer and covering the top electrode; and a load material layer corresponding to the cavity, and the bottom electrode, the piezoelectric material layer and the top electrode are stacked on the substrate along a first direction, wherein the load material layer is located below one of the bottom electrode and the top electrode.

Some embodiments of the present disclosure also provide a method for forming a piezoelectric structure, comprising providing a substrate, the substrate comprising a base material and an oxide layer located on the base material, wherein the oxide layer has a cavity; and forming a stacked structure on the substrate along a first direction. The stacked structure comprises a seed layer formed on the substrate, a bottom electrode formed on the seed layer, a piezoelectric material layer formed on the bottom electrode, a top electrode formed on the piezoelectric material layer, a protective layer formed on the piezoelectric material layer, and a load material layer corresponding to the cavity. The protective layer covers the top electrode, and the bottom electrode, the piezoelectric material layer and the top electrode are stacked along a first direction, wherein the load material layer is formed below one of the bottom electrode and the top electrode.

The following disclosure provides many embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which additional components are formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present invention may repeatedly reference numbers and/or letters in different examples. Such repetition is for the sake of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments discussed.

Furthermore, spatially relative terms such as "below", "beneath", "below", "above", "upper" and other similar terms may be used in the following description to simplify the description of the relationship between one element or component and other elements or components as shown in the figures. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

Some variations of the embodiments are described below. In the different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It is understood that additional steps may be provided before, during, or after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

The present disclosure provides a piezoelectric structure, a method for forming the same, and a piezoelectric filter device using the same. The piezoelectric structure of some embodiments includes a load material layer below one of a bottom electrode layer and a top electrode layer. The piezoelectric structure provided with the load material layer can generate different resonant frequencies due to different load effects with the piezoelectric structure not provided with the load material layer, so that the applied piezoelectric filter device can achieve a filtering effect. In some of the following embodiments, a film bulk acoustic resonator (FBAR) filter is used as an embodiment of a related component of the piezoelectric filter device.

FIG. 1A is a circuit diagram of a piezoelectric filter device according to some embodiments of the present disclosure. According to FIG. 1A, a ladder type piezoelectric filter device is shown, which includes a plurality of resonators connected. A general ladder type piezoelectric filter device, such as a thin film bulk acoustic wave resonator filter, includes a series resonator with a resonant frequency of fs and a shunt resonator with a resonant frequency of fp. A combination of a series resonator and a shunt resonator is a stage, and a ladder type filter can be composed of multiple-stage resonators. FIG. 1A is an example of a piezoelectric filter device including a third-order resonator, but the invention is not limited thereto.

FIG. 1B is a diagram showing the simulated relationship between the frequency and the corresponding return loss of the series/parallel resonator of the piezoelectric filter device shown in FIG. 1A. The curve Cseries represents the relationship between the frequency and the corresponding return loss (vertical axis; logarithmic value) of the series resonator, wherein the return loss is at the maximum and minimum values at the anti-resonance frequency f1 and the resonance frequency f2 (fs), respectively. The curve Cshunt represents the relationship between the frequency and the corresponding impedance (vertical axis; logarithmic value) of the parallel resonator, wherein the return loss is at the maximum and minimum values at the anti-resonance frequency f3 and the resonance frequency f4 (fp), respectively. When the series resonator is at the anti-resonance frequency f1, the reflection loss is the largest and the signal cannot pass through, forming an open circuit. When the parallel resonator is at the resonant frequency f4, the reflection loss is the smallest and the signal can pass through, forming a short circuit.

FIG. 1C is a diagram showing the simulated relationship between the frequency and the corresponding insertion loss of a piezoelectric filter device shown in FIG. 1A. Referring to FIG. 1B and FIG. 1C at the same time, the signal frequency in the frequency band between frequency f4 and frequency f1 can pass with low loss. The signal frequency outside the aforementioned pass band cannot pass with high loss. In practical applications, the pass bandwidth and its corresponding frequency required by the piezoelectric filter device can be obtained by adjusting the film bulk acoustic wave resonance process. A filter having this frequency response type as shown in FIG. 1B and FIG. 1C is also called a bandpass filter.

The following is an example of a method for manufacturing a series resonator and a parallel resonator in a piezoelectric filter device as shown in FIG. 1A, and a loading material layer is set in the piezoelectric structure of the parallel resonator to reduce the resonant frequency of the piezoelectric structure to achieve the band pass filtering effect as shown in FIG. 1C above. The following multiple embodiments are used to illustrate different settings of the loading material layer in the piezoelectric structure.

FIGS. 2A to 2H are schematic cross-sectional views of a piezoelectric filter device at various intermediate manufacturing stages according to some embodiments of the present disclosure.

Referring to FIG. 2A , according to some embodiments, a substrate S is provided. The substrate S includes a base material 100, an oxide layer 102 located on the base material 100, and a sacrificial layer 103 buried in the oxide layer 102. In subsequent processes, the sacrificial layer 103 will be removed to form a cavity in the piezoelectric structure, so as to facilitate the stacked material layers of the manufactured piezoelectric structure to oscillate above the cavity, for example, oscillate along the first direction D1.

In some embodiments, the substrate 100 may be a block-shaped semiconductor substrate, such as a semiconductor wafer. In this embodiment, the substrate 100 is a silicon wafer. The substrate 100 may also include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 100 may include a compound semiconductor, such as silicon carbide, gallium nitride. In some embodiments, the substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide or other suitable substrates. In some embodiments, the substrate 100 may be composed of multiple layers of materials, such as silicon/silicon germanium, silicon/silicon carbide.

The steps for forming the oxide layer 102 and the sacrificial layer 103 of some embodiments are as follows. First, an oxide film is formed on the substrate 100; then a sacrificial material layer is formed on the oxide film, and the sacrificial material layer is patterned by a suitable lithography patterning process (for example, by a patterning mask and an etching process) to define the sacrificial layer 103. Then, an oxide material layer is deposited on the oxide film and the sacrificial layer 103, and the oxide material layer covers the sacrificial layer 103. Then, a planarization process is performed on the oxide material layer, such as a chemical-mechanical polishing (CMP) process, to planarize the oxide material layer and expose the top surface of the sacrificial layer 103. The oxide film and the planarized oxide material layer constitute a bottom oxide layer 1021. Then, a cap oxide layer 1022 is deposited on the bottom oxide layer 1021 and the sacrificial layer 103.

For simplicity of explanation, the bottom oxide layer 1021 and the cap oxide layer 1022 are collectively referred to as the oxide layer 102 of these embodiments and subsequent embodiments, wherein the sacrificial layer 103 is buried in the oxide layer 102. The bottom surface of the sacrificial layer 103 is separated from the substrate 100 by a distance in the first direction D1. In addition, the thickness of the oxide film in the process of manufacturing the substrate S (in the first direction D1) is, for example but not limited to, about 1000 nm, the thickness of the sacrificial material layer (in the first direction D1) is, for example but not limited to, about 1500 nm, the thickness of the oxide material layer (in the first direction D1) is, for example but not limited to, about 1500 nm, and the thickness of the cap oxide layer (in the first direction D1) is, for example but not limited to, about 100 nm.

Furthermore, in some embodiments, the oxide layer 102 (including the bottom oxide layer 1021 and the cap oxide layer 1022) includes silicon oxide or other suitable materials, such as tetraethoxysilane (Tetraethyl Silicate, TEOS). In some embodiments, the sacrificial layer 103 includes amorphous silicon or other suitable materials. Furthermore, the deposition process includes a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of the aforementioned processes. The etching process includes a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the aforementioned processes. Furthermore, in some embodiments, the sacrificial layer 103 includes amorphous silicon or other suitable materials.

Then, referring to FIG. 2B , according to some embodiments, a load material layer 104 is formed on the substrate S. The position of the load material layer 104 corresponds to the sacrificial layer 103. Specifically, the load material layer 104 of this embodiment is formed on the oxide layer 102, for example, on the capping oxide layer 1022, and the load material layer 104 and the sacrificial layer 103 are separated by the capping oxide layer 1022, for example.

In some embodiments, the load material layer 104 includes a metal, a metal nitride, a dielectric material, or a combination of the above materials. The dielectric material includes, for example, a nitride, an oxynitride, or a combination of the above materials. The metal and metal nitride include, for example, tungsten (W), molybdenum (Mo), titanium (Ti), aluminum (Al), platinum (Pt), tantalum (Ta), other suitable metals, alloys of the above materials, and nitrides of the above metals (e.g., tantalum nitride (TaN), titanium nitride (TiN)). Furthermore, according to an embodiment, the load material layer 104 may include the same or different materials as the bottom electrode and/or the top electrode to be formed subsequently. For example, the load material layer 104 and the bottom electrode and/or the top electrode include different metal materials. Alternatively, the load material layer 104 includes a dielectric material that is different from the metal material included in the bottom electrode and/or the top electrode. Furthermore, the load material layer 104 can be a single-layer structure or a multi-layer structure including the above materials.

According to some embodiments, a carrier material (not shown) may be first formed on the substrate S, for example, by a deposition process, and then a lithography patterning process and an etching process may be performed to remove a portion of the carrier material to define the carrier material layer 104. In some embodiments, the lithography patterning process includes forming a patterned photoresist layer (not shown) above the carrier material. Then, etching is performed based on the patterned photoresist layer to remove the portion of the carrier material not covered by the patterned photoresist layer to form the carrier material layer 104 as shown in FIG. 2B. The etching process may be a dry etching process, a wet etching process, other suitable processes, or a combination of the aforementioned processes. Dry etching processes include plasma etching and reactive ion etching.

Furthermore, in some embodiments, the thickness of the load material layer 104 (in the first direction D1) is in the range of about 100 Å (Angstrom) to about 400 Å. However, the thickness of the load material layer 104 disclosed herein is not limited to the aforementioned range and value. In an embodiment in which the load material layer 104 includes multiple material layers, the load material layer 104 includes (but is not limited to) a metal titanium (Ti) layer of about 100 Å and a titanium nitride (TiN) layer of about 150 Å on the metal titanium (Ti) layer.

Thereafter, referring to FIG. 2C , according to some embodiments, a seed layer 106 is formed on the substrate S, and the seed layer 106 covers the load material layer 104. The seed layer 106 may include silicon dioxide, silicon oxynitride, aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or other suitable materials. Furthermore, in some embodiments, the seed layer 106 and the subsequently formed piezoelectric material layer 120 ( FIG. 2D ) include the same material to provide a growth surface for the piezoelectric material layer 120. The seed layer 106 may be formed on the capping oxide layer 1022 of the substrate S by a deposition method. The deposition method includes a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes or a combination of the aforementioned processes. Furthermore, the thickness of the seed layer 106 is, for example, in the range of (but not limited to) about 100 Angstrom to about 300 Angstrom, for example, about 200 Angstrom. However, the thickness of the seed layer 106 disclosed in the present invention is not limited to the aforementioned range and value.

It is worth noting that the surface texture of the seed layer 106 disposed on the substrate S (e.g., on the oxide layer 102) will affect the crystallinity of each material layer deposited thereon. Since the seed layer 106 of this embodiment is formed after the carrier material layer 104 is formed, the material layer subsequently deposited on the seed layer 106 does not directly contact the carrier material layer 104, and therefore the carrier material layer 104 of this embodiment does not affect the subsequent deposition of each material layer above the seed layer 106.

Then, referring to FIG. 2C , a bottom electrode layer 110 is formed on the seed layer 106. When viewed from the top of the substrate S, the bottom electrode layer 110 has a suitable pattern design (not shown) depending on the requirements of the application device. According to some embodiments, although the bottom electrode layer 110 is shown as a plurality of separated sections in the cross section of this figure due to its pattern design, it may be connected outside this cross section, and the bottom electrode layer 110 is electrically connected to an input terminal (not shown) to input an operating voltage to the bottom electrode layer 110.

In this embodiment, the bottom electrode layer 110 includes a first bottom electrode 111 and a second bottom electrode 112 adjacent to the first bottom electrode 111, which are formed on the seed layer 106 along the first direction D1 and are separated by a distance in the second direction D2. Furthermore, as shown in FIG. 2C , in this embodiment, the first bottom electrode 111 and the second bottom electrode 112 are located above the sacrificial layer 103 (which will be removed in a subsequent process to form a cavity), and the first bottom electrode 111 is located above the load material layer 104.

In this embodiment, the stacked structure formed on the sacrificial layer 103 is used as an illustration of the piezoelectric structure of a series resonator and a parallel resonator of an application device. According to an application of this embodiment, the piezoelectric structure of a parallel resonator includes a load material layer 104, a seed layer 106, a first bottom electrode 111, and layers and components subsequently stacked thereon. The piezoelectric structure of a series resonator includes a seed layer 106, a second bottom electrode 112, and layers and components subsequently stacked thereon, and does not include a load material layer.

In some embodiments, the bottom electrode layer 110 includes a conductive oxide, a metal, a conductive nitride, an alloy containing the aforementioned materials, or other suitable conductive materials, or a combination of the aforementioned materials. The aforementioned conductive oxide is, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or other suitable oxides. The aforementioned metal is, for example, tungsten (W), molybdenum (Mo), titanium (Ti), aluminum (Al), platinum (Pt), tantalum (Ta), or other suitable metals, or alloys of the aforementioned materials, or a combination of the aforementioned materials. The aforementioned conductive nitride is, for example, tantalum nitride (TaN), titanium nitride (TiN), or other suitable nitrides.

According to some embodiments, a bottom electrode material layer is first deposited on the seed layer 106. In some embodiments, the bottom electrode material layer can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the aforementioned processes. Afterwards, a suitable lithography patterning process and an etching process are performed to form a bottom electrode layer 110 having a suitable pattern.

Furthermore, in some embodiments, the thickness of the formed bottom electrode layer 110 (in the first direction D1) is in the range of about 100 nm to about 250 nm. The thickness of the bottom electrode layer 110 disclosed herein is not limited to the aforementioned range and value.

Thereafter, referring to FIG. 2D , according to some embodiments, a piezoelectric material layer 120 is formed on the seed layer 106 and the bottom electrode layer 110, and the piezoelectric material layer 120 covers the seed layer 106 and the bottom electrode layer 110. In some embodiments, the piezoelectric material layer 120 includes silicon dioxide, silicon oxynitride, zinc oxide, aluminum nitride, indium nitride, indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum nitride (AlScN), lead zirconate titanate (PZT), other suitable materials, or a combination of the foregoing materials. Furthermore, in some embodiments, the piezoelectric material layer 120 and the seed layer 106 include the same material. The piezoelectric material layer 120 can be continuously grown based on the crystallization surface provided by the seed layer 106.

In some embodiments, the piezoelectric material layer 120 is deposited on the seed layer 106 along the first direction D1. The above-mentioned deposition method includes a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or other suitable processes. Furthermore, in some embodiments, the thickness of the piezoelectric material layer 120 (in the first direction D1) is in the range of about 400nm to about 1000nm. The thickness of the piezoelectric material layer 120 disclosed in the present invention is not limited to the aforementioned range and value.

Then, referring to FIG. 2D , according to some embodiments, a top electrode layer 130 is formed on the piezoelectric material layer 120. When viewed from the substrate S, the top electrode layer 130 has a suitable pattern design (not shown) depending on the requirements of the application device. Depending on the requirements of the applied piezoelectric filter device, the patterns of the bottom electrode layer 110 and the top electrode layer 130 can be designed so that the manufactured piezoelectric filter device has a good bandpass filtering effect and the bandpass filter shown in FIG. 1C has a good waveform, such as a more stable low feed loss (dB) in the passband and a more vertical steep rise and fall in feed loss difference corresponding to the cutoff frequencies f1 and f4 (i.e., the passband is closer to a square) and other effects. According to some embodiments, although the top electrode layer 130 is shown as a plurality of separated segments in the cross section of FIG. 2D due to its graphic design, it may be connected outside this cross section, and the top electrode layer 130 is electrically connected to an input terminal (not shown) to input an operating voltage to the top electrode layer 130.

In this embodiment, the top electrode layer 130 includes a first top electrode 131 and a second top electrode 132 adjacent to the first top electrode 131 formed on the piezoelectric material layer 120. In this cross section, the first top electrode 131 and the second top electrode 132 are separated by a distance in the second direction D2. Furthermore, as shown in FIG. 2D, in this embodiment, the first top electrode 131 and the second top electrode 132 are located above the sacrificial layer 103 (which will be removed in a subsequent process to form a cavity). According to the embodiment, the first top electrode 131 corresponds to the top of the first bottom electrode 111 and also corresponds to the top of the load material layer 104. The second top electrode 132 corresponds to the upper portion of the second bottom electrode 112.

In some embodiments, the top electrode layer 130 includes a conductive oxide, a metal, a conductive nitride, an alloy containing the aforementioned materials, or other suitable conductive materials, or a combination of the aforementioned materials. The aforementioned conductive oxide is, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or other suitable oxides. The aforementioned metal is, for example, tungsten, molybdenum, titanium, aluminum, platinum, tungsten, or other suitable metals, or alloys of the aforementioned materials, or a combination of the aforementioned materials. The aforementioned conductive nitride is, for example, tungsten nitride (TaN), titanium nitride (TiN), or other suitable nitrides. The top electrode layer 130 and the bottom electrode layer 110 may include different materials or the same material. In some embodiments, the top electrode layer 130 and the bottom electrode layer 110 include the same material, such as molybdenum.

According to some embodiments, a top electrode material layer is first deposited on the piezoelectric material layer 120. In some embodiments, the top electrode material layer can be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the aforementioned processes. Thereafter, a top electrode layer 130 having a suitable pattern is formed by a suitable lithography patterning process and an etching process. The aforementioned etching process stops on the top surface of the piezoelectric material layer 120. In this embodiment, the piezoelectric material layer 120 has an extremely high etching selectivity for etching the top electrode layer 130.

Furthermore, in some embodiments, the thickness of the formed top electrode layer 130 (in the first direction D1) is in the range of about 100 nm to about 250 nm. The thickness of the top electrode layer 130 disclosed herein is not limited to the aforementioned range and value.

According to some embodiments of the present disclosure, a piezoelectric filter device includes a first piezoelectric structure 10-1 and a second piezoelectric structure 10-2. The first piezoelectric structure 10-1 includes a load material layer 104, a seed layer 106, a first bottom electrode 111, a piezoelectric material layer 120, and a first top electrode 131 stacked along a first direction D1. The second piezoelectric structure 10-2 includes a seed layer 106, a second bottom electrode 112, a piezoelectric material layer 120, and a second top electrode 132 stacked along the first direction D1. Compared to the second piezoelectric structure 10-2 without the load material layer, the first piezoelectric structure 10-1 with the load material layer is thicker and has a lower resonant frequency. In one application, the parallel resonator and the series resonator shown in FIG. 1A respectively have the first piezoelectric structure 10-1 and the second piezoelectric structure 10-2 to achieve the aforementioned band pass filtering effect as shown in FIG. 1C.

In addition, according to the first piezoelectric structure 10-1 of some embodiments, the width W1 of the load material layer 104 (in the second direction D2) may be smaller than, approximately equal to, or slightly larger than the width W2 of the first bottom electrode 111 (in the second direction D2). In some embodiments, the width W1 of the load material layer 104 may be smaller than, approximately equal to, or slightly larger than the width W3 of the first top electrode 131 (in the second direction D2). The actual width of the load material layer 104 depends on the application requirements, as long as the load material layer 104 is within the device region of the first piezoelectric structure 10-1, it should be within the practicable range.

2E , according to some embodiments, a protective layer 140 is formed on the piezoelectric material layer 120 and the top electrode layer 130, and the protective layer 140 covers the piezoelectric material layer 120 and the top electrode layer 130. The protective layer 140 can be used to passivate and/or protect the top electrode layer 130, the piezoelectric material layer 120, the bottom electrode layer 110, and the load material layer 104 below.

According to some embodiments, the protective layer 140 may include silicon dioxide, silicon oxynitride, zinc oxide, aluminum nitride, indium nitride, indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum nitride (AlScN), lead zirconium titanate (PZT), other suitable materials, or a combination of the foregoing materials. The protective layer 140 and the piezoelectric material layer 120 may include different or the same materials. In one embodiment, the protective layer 140 and the piezoelectric material layer 120 include aluminum nitride. In some embodiments, the protection layer 140 may be formed on the piezoelectric material layer 120 by a deposition method such as physical vapor deposition, chemical vapor deposition or other suitable processes.

Furthermore, in some embodiments, the thickness of the formed protective layer 140 (in the first direction D1) is in the range of about 100 nm to about 300 nm. However, the thickness of the protective layer 140 disclosed herein is not limited to the aforementioned range and value, and can achieve the function of passivation and protection of the underlying material layer.

Then, referring to FIG. 2F , according to some embodiments, a dielectric layer 150 is formed on the protective layer 140, and a contact hole 160 is formed to expose the electrode, for example, a first contact hole 161 is formed to expose the top electrode layer 130, and a second contact hole 162 is formed to expose the bottom electrode layer 110. In some embodiments, the dielectric layer 150 includes an oxide layer, such as a TEOS layer. In some embodiments, the thickness of the dielectric layer 150 is in the range of about 100 nm to about 200 nm, for example, about 100 nm, but the thickness of the dielectric layer 150 disclosed herein is not limited to the aforementioned range and value.

According to some embodiments, the dielectric layer 150 may be deposited by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable processes, or a combination of the aforementioned processes. Thereafter, a first contact hole 161 and a second contact hole 162 are formed by a suitable lithography patterning process and an etching process. The etching process may include a dry etching process, a wet etching process, other suitable processes, or a combination of the aforementioned processes. In some embodiments, as shown in FIG. 2F , the first contact hole 161 penetrates the dielectric layer 150 and the protective layer 140 to expose the top electrode layer 130. Furthermore, the second contact hole 162 penetrates the dielectric layer 150 , the protection layer 140 , the top electrode layer 130 , and the piezoelectric material layer 120 to expose the bottom electrode layer 110 .

Then, referring to FIG. 2G , according to some embodiments, contact pads are formed at the contact holes to contact the corresponding electrodes below. For example, a first contact pad 171 is formed in the first contact hole 161, and a second contact pad 172 is formed in the second contact hole 162. The first contact pad 171 contacts the top electrode layer 130 below to be electrically connected to the top electrode layer 130. The second contact pad 172 contacts the bottom electrode layer 110 below to be electrically connected to the bottom electrode layer 110.

In some embodiments, the materials of the first contact pad 171 and the second contact pad 172 may include conductive materials, such as aluminum copper (AlCu), aluminum silicon copper (AlSiCu), other similar metal materials, other suitable conductive materials, or a combination thereof. And these contact pads may be a single-layer structure or a multi-layer structure. To simplify the diagram, a single-layer first contact pad 171 and a second contact pad 172 are shown here to facilitate a clear description of the embodiment.

According to some embodiments, a metal material layer (e.g., an aluminum-copper layer) is first formed on the dielectric layer 150, and is conformally formed on the sidewalls and bottom of the first contact hole 161 and the second contact hole 162. Afterwards, the metal material layer and the dielectric layer are etched to form the first contact pad 171 and the second contact pad 172 through a suitable lithography patterning process and an etching process, leaving the dielectric layer 150' below the contact pad pattern, and the etching stops on the top surface of the protective layer 140. In this embodiment, the protective layer 140 has an extremely high etching selectivity for contact pad etching.

In some embodiments, the metal material layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, other suitable processes, or a combination of the aforementioned processes. Furthermore, the etching process may be a dry etching process, a wet etching process, other suitable processes, or a combination of the aforementioned processes. Furthermore, in some embodiments, the thickness of the formed first contact pad 171 and the second contact pad 172 (in the first direction D1) is, for example but not limited to, in the range of about 800 nm to about 2000 nm. The thickness of the first contact pad 171 and the second contact pad 172 disclosed in the present embodiment is not limited to the aforementioned range and value.

Then, referring to FIG. 2G , according to some embodiments, through appropriate lithography patterning processes and etching processes, holes are formed to penetrate the protective layer 140, the piezoelectric material layer 120, the seed layer 106, and the capping oxide layer 1022 to expose the sacrificial layer 103, such as a first via 181 and a second via 182. In this embodiment, the first via 181 is located on one side of the first piezoelectric structure 10-1 and does not exceed the side edge of the sacrificial layer 103. The second via 182 is located on one side of the second piezoelectric structure 10-2 and does not exceed the other side edge of the sacrificial layer 103. Furthermore, when viewed from above the substrate S, the first hole 181 and the second hole 182 may be circular or in other shapes, and are respectively located within the range of the sacrificial layer 103 .

Thereafter, referring to FIG. 2H , according to some embodiments, the sacrificial layer 103 is removed to form a cavity 183. Specifically, a suitable etching process can be used to remove the sacrificial layer 103 in the substrate S through the first hole 181 and the second hole 182. The etching process can be a dry etching process, a wet etching process, other suitable processes, or a combination of the aforementioned processes. In one embodiment, for the material of the sacrificial layer 103 (e.g., amorphous silicon), dry etching can be used together with a fluorine-containing gas, such as sulfur hexafluoride (SF ₆ ) or xenon difluoride (XeF ₂ ), other applicable gases, or a combination of the aforementioned processes.

Furthermore, the above-mentioned etching process is a selective etching process, which has high etching selectivity for the material of the sacrificial layer 103 (e.g., amorphous silicon), so that the sacrificial layer 103 can be completely removed without affecting other surrounding layers/components, including the protective layer 140, the piezoelectric material layer 120, and the seed layer 106 including aluminum nitride (AlN). For example, the embodiment uses dry etching of sulfur hexafluoride (SF ₆ ) or xenon difluoride (XeF ₂ ).

According to the above, in the piezoelectric filter device of some embodiments of the present disclosure, a voltage can be applied to the top electrode layer 130 and the bottom electrode layer 110 through the first contact pad 171 and the second contact pad 172 to make the piezoelectric structure vibrate. The piezoelectric structure with the load material layer 104 (e.g., the first piezoelectric structure 10-1 in FIG. 2D ) has a lower resonant frequency than the piezoelectric structure without the load material layer 104 (e.g., the second piezoelectric structure 10-2 in FIG. 2D ). In this embodiment, the first piezoelectric structure 10-1 has a greater loading effect than the second piezoelectric structure 10-2 by forming the loading material layer 104 before forming the bottom electrode layer 110, and thus has a lower resonant frequency. By changing the thickness and/or shape of the loading material layer 104, the bandwidth and filtering effect of the band pass of the filter device can be adjusted. For example, in some application cases of the piezoelectric filter device shown in FIG. 1A , one or more parallel resonators may have the first piezoelectric structure 10-1 of this embodiment, one or more series resonators may have the second piezoelectric structure 10-2 of this embodiment, and the first piezoelectric structure 10-1 may have the load material layer 104 as described above, so that the piezoelectric filter device can achieve the bandpass filtering effect as shown in FIG. 1C and the purpose of adjusting the bandwidth of the filter device.

In addition to the manufacturing method proposed in Figures 2A to 2H, the piezoelectric filter device of some embodiments of the present disclosure can also be manufactured by other manufacturing methods to obtain a piezoelectric structure with a load effect. Figures 3A to 3D are cross-sectional schematic diagrams of another piezoelectric filter device at various intermediate manufacturing stages in some embodiments of the present disclosure. The same or similar components in Figures 3A to 3D as those in Figures 2A to 2H above use the same or similar reference numbers, and the contents of these components in the above embodiments can be referred to.

Referring to FIG. 3A , a substrate S is first provided. The substrate S includes a base material 100, an oxide layer 102 located on the base material 100, and a sacrificial layer 103 buried in the oxide layer 102. A load material layer 104, a buffer oxide layer 202, a seed layer 106, and a bottom electrode layer 110 are sequentially formed on the substrate S. The bottom electrode layer 110 includes, for example, a first bottom electrode 111 and a second bottom electrode 112.

Different from the manufacturing method of FIGS. 2A to 2H above, the manufacturing method of FIGS. 3A to 3D is to first form a buffer oxide layer 202 on the substrate S after forming the load material layer 104, and the buffer oxide layer 202 covers the load material layer 104, and then form a seed layer 106 on the buffer oxide layer 202. That is, the load material layer 104 is covered by the oxide layer 102 and the buffer oxide layer 202, so the seed layer 106 does not directly contact the load material layer 104.

According to some embodiments, the buffer oxide layer 202 includes silicon oxide or other suitable materials, such as tetraethoxysilane (TEOS). The buffer oxide layer 202 may include the same material as the oxide layer 102. The buffer oxide layer 202 may be deposited on the substrate S and cover the load material layer 104 by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, other suitable processes, or a combination of the aforementioned processes. Furthermore, in one embodiment, the thickness of the buffer oxide layer 202 (in the first direction D1) is in the range of about 100 nm to about 200 nm. The thickness of the buffer oxide layer 202 disclosed herein is not limited to the aforementioned range and value.

Furthermore, the details of the configuration, materials and manufacturing methods of the components shown in Figure 3A, such as the substrate 100, the oxide layer 102 (including the bottom oxide layer 1021 and the covering oxide layer 1022), the sacrificial layer 103, the load material layer 104, the seed layer 106 and the bottom electrode layer 110 (including the first bottom electrode 111 and the second bottom electrode 112), can be referred to the description of the relevant contents of the above-mentioned Figures 2A, 2B, and 2C, and will not be repeated here.

Then, referring to FIG. 3B , according to some embodiments, a piezoelectric material layer 120 is formed on the seed layer 106 and the bottom electrode layer 110, and the piezoelectric material layer 120 covers the seed layer 106 and the bottom electrode layer 110. Then, a top electrode layer 130 is formed on the piezoelectric material layer 120. From the top view of the substrate S, the bottom electrode layer 110 and the top electrode layer 130 have a suitable pattern design (not shown) depending on the requirements of the application device. The top electrode layer 130, for example, includes a first top electrode 131 and a second top electrode 132. Afterwards, a protective layer 140 is formed on the piezoelectric material layer 120 and the top electrode layer 130 to passivate and/or protect the stacked material layer below. In one embodiment, the protective layer 140, the piezoelectric material layer 120 and the seed layer 106 may include the same material, such as aluminum nitride or other suitable materials. The top electrode layer 130 and the bottom electrode layer 110 may include the same material, such as molybdenum or other suitable materials.

Furthermore, the configuration, material, thickness and manufacturing method of the components shown in FIG. 3B, such as the piezoelectric material layer 120, the top electrode layer 130 (including the first top electrode 131 and the second top electrode 132) and the protective layer 140, can be referred to the description of the relevant contents of the above-mentioned FIGS. 2D and 2E, and will not be repeated here.

Thereafter, referring to FIG. 3C , according to some embodiments, a dielectric layer is formed on the protective layer 140, and contact holes are formed to expose corresponding electrodes, such as forming a first contact hole 161 to expose the top electrode layer 130, and a second contact hole 162 to expose the bottom electrode layer 110. Then, contact pads are formed at the contact holes to contact the corresponding electrodes below. For example, a first contact pad 171 is formed in the first contact hole 161, and a second contact pad 172 is formed in the second contact hole 162. In one embodiment, a metal material layer (e.g., an aluminum-copper layer) can be formed on the dielectric layer, and the metal material layer is conformally formed on the side walls and bottom of the first contact hole 161 and the second contact hole 162. The metal material layer and the dielectric layer are then etched through a suitable lithography patterning process and an etching process to form a first contact pad 171 and a second contact pad 172, leaving a dielectric layer 150' under the contact pad pattern. The components shown in FIG. 3C , such as the dielectric layer, the first contact hole 161 and the second contact hole 162 , the first contact pad 171 and the second contact pad 172 , their configuration, materials, thickness, manufacturing methods and other details can be referred to the description of the relevant contents of the above-mentioned FIGS. 2F and 2G , and will not be repeated here.

Then, referring to FIG. 3D , according to some embodiments, holes such as the first hole 181 and the second hole 182 are formed through the protective layer 140, the piezoelectric material layer 120, the seed layer 106, the buffer oxide layer 202 and the cap oxide layer 1022 to expose the sacrificial layer 103. Then, the sacrificial layer 103 in the substrate S is removed through the first hole 181 and the second hole 182 to form a cavity 183. The configuration, material, thickness and manufacturing method of the components shown in FIG. 3D , such as the first hole 181, the second hole 182 and the cavity 183, can be referred to the description of the relevant contents in the above-mentioned FIGS. 2G and 2H , and will not be repeated here.

According to the embodiment, when operating the piezoelectric device, a voltage can be applied to the top electrode layer 130 and the bottom electrode layer 110 through the first contact pad 171 and the second contact pad 172 to make the piezoelectric structure vibrate. The first piezoelectric structure 10-1 with the load material layer 104 has a higher load effect than the second piezoelectric structure 10-2 without the load material layer, and thus has a lower resonant frequency. By changing the thickness and shape of the load material layer 104, the bandwidth and filtering effect of the band pass of the filter device can be adjusted. Furthermore, in the embodiment, after forming the load material layer 104, a buffer oxide layer 202 is formed to cover the load material layer 104, so that the seed layer 106 is formed on the buffer oxide layer 202 without directly contacting the load material layer 104. That is, the buffer oxide layer 202 further reduces the influence of the load material layer 104 on the crystallization of the seed layer 106. Therefore, the piezoelectric material layer 120 subsequently deposited on the seed layer 106 has a better quality factor (Q).

In the piezoelectric filter device proposed above as shown in FIG. 2H and FIG. 3D , the load material layer 104 is located below the first bottom electrode 111, and the load material layer 104 is located below the seed layer 106 (FIG. 2H) or the seed layer 106 and the buffer oxide layer 202 (FIG. 3D). However, the present disclosure is not limited to this. In some embodiments, the load material layer 104 may also be located above the seed layer 106 and directly contact the bottom of the first bottom electrode 111.

Figures 4A to 4H are cross-sectional schematic diagrams of another piezoelectric filter device at various intermediate manufacturing stages according to some embodiments of the present disclosure. The same or similar components in Figures 4A to 4H as those in Figures 2A to 2H above are given the same or similar reference numbers, and the contents of these components in the above embodiments can be referred to.

Referring to FIG. 4A , a substrate S is first provided. The substrate S comprises a base material 100, an oxide layer 102 on the base material 100, and a sacrificial layer 103 buried in the oxide layer 102. The configuration, materials, and manufacturing methods of the components shown in FIG. 4A may refer to the description of the relevant contents of FIG. 2A above, and will not be repeated here.

Then, referring to FIG. 4B , according to some embodiments, a seed layer 106 is first formed on the substrate S, and then a carrier material layer 304 is formed on the seed layer 106. That is, the details of the configuration, materials, and manufacturing methods of the components shown in FIG. 4B , such as the seed layer 106 and the carrier material layer 304, can be referred to the description of the relevant contents of FIG. 2B above, and will not be repeated here.

Then, referring to FIG. 4C , according to some embodiments, a bottom electrode layer 310 is formed on the seed layer 106, and the bottom electrode layer 310 covers the load material layer 304. Looking down from the substrate S, the bottom electrode layer 310 has a suitable pattern design depending on the requirements of the application device, and a plurality of separated sections are shown in the cross section of this figure, but may be connected outside this cross section (not shown). In this embodiment, the bottom electrode layer 310 includes a first bottom electrode 311 and a second bottom electrode 312, which are formed on the seed layer 106 along the first direction D1. Furthermore, the load material layer 304, the first bottom electrode 311 and the second bottom electrode 312 are correspondingly located above the sacrificial layer 103 (which will be removed in subsequent processes to form a cavity).

It is worth noting that in this embodiment, the first bottom electrode 311 is formed on the load material layer 304. The details of the material and manufacturing method of the bottom electrode layer 310 shown in FIG. 4C can be referred to the description of the relevant content of the above-mentioned FIG. 2C, which will not be repeated here.

Thereafter, referring to FIG. 4D , according to some embodiments, a piezoelectric material layer 120 is formed on the seed layer 106 and the bottom electrode layer 310, and the piezoelectric material layer 120 covers the seed layer 106 and the bottom electrode layer 310. Then, a top electrode layer 330 is formed on the piezoelectric material layer 120. Looking down from the substrate S, the top electrode layer 330 has a suitable pattern design depending on the requirements of the application device, and a cross section of this figure shows several separated sections (for example, including a first top electrode 331 and a second top electrode 332), but may be connected outside this cross section (not shown).

Furthermore, according to this embodiment, since the first bottom electrode 311 covers the load material layer 304, the width W1 of the load material layer 304 (in the second direction D2) is smaller than the width W2 of the first bottom electrode 311 (in the second direction D2). Furthermore, the width W3 of the first top electrode 331 (in the second direction D2) may be smaller than, substantially equal to, or slightly larger than the width W2 of the first bottom electrode 311. The actual widths of the load material layer 304, the first bottom electrode 311, and the first top electrode 331 depend on the application requirements, as long as the load material layer 304 is within the region of the first piezoelectric structure 10-1, it should be within the practicable range.

In some embodiments, the piezoelectric material layer 120 and the seed layer 106 may include (but not limited to) the same material, such as aluminum nitride (AlN) or other suitable materials. In some embodiments, the top electrode layer 330 and the bottom electrode layer 310 may include (but not limited to) the same material, such as molybdenum (Mo) or other suitable materials. In some embodiments, the load material layer 304 may include the same or different materials as the bottom electrode layer 310. The components shown in Figure 4D, such as the piezoelectric material layer 120 and the top electrode layer 330 (the first bottom electrode 311 and the first top electrode 331), the details of their configuration, materials and manufacturing methods can refer to the description of the relevant content of the above-mentioned Figure 2D, which will not be repeated here.

Then, referring to FIG. 4E , according to some embodiments, a protective layer 140 is formed to cover the piezoelectric material layer 120 and the top electrode layer 330. In some embodiments, the protective layer 140, the piezoelectric material layer 120 and the seed layer 106 may include (but not limited to) the same material, such as aluminum nitride (AlN) or other suitable materials. The configuration, material and manufacturing method of the protective layer 140 shown in FIG. 4E can be referred to the description of the relevant content of FIG. 2E above, and will not be repeated here.

Then, referring to FIG. 4F , according to some embodiments, a dielectric layer 150 is formed on the protective layer 140, and contact holes that can expose the electrodes are formed. For example, a first contact hole 161 that exposes the top electrode layer 330 and a second contact hole 162 that exposes the bottom electrode layer 310. The components shown in FIG. 4F , including the dielectric layer 150, the first contact hole 161, and the second contact hole 162, can refer to the description of the relevant contents of the above-mentioned FIG. 2F for details of their configuration, materials, and manufacturing methods, which will not be repeated here.

Thereafter, referring to FIG. 4G , according to some embodiments, contact pads are formed at the contact holes to contact the corresponding electrodes below. For example, a first contact pad 171 is formed in the first contact hole 161, and the first contact pad 171 contacts and electrically connects to the top electrode layer 330. A second contact pad 172 is formed in the second contact hole 162, and the second contact pad 172 contacts and electrically connects to the bottom electrode layer 310. Then, holes such as the first hole 181 and the second hole 182 are formed to penetrate the protective layer 140, the piezoelectric material layer 120, the seed layer 106, and the capping oxide layer 1022 to expose the sacrificial layer 103. The components shown in FIG. 4G include contact pads (e.g., first contact pad 171 and second contact pad 172) and holes (e.g., first hole 181 and second hole 182). Details of their configuration, materials, and manufacturing methods can be found in the description of the relevant contents of FIG. 2G above and will not be repeated here.

Then, referring to FIG. 4H, according to some embodiments, the sacrificial layer 103 in the substrate S is removed through the first hole 181 and the second hole 182 to form a cavity 183. The method of removing the sacrificial layer 103 can refer to the description of the relevant content of FIG. 2H above, which will not be repeated here. According to the above, the manufacture of a piezoelectric filter device is completed.

In an embodiment, when operating the piezoelectric device, a voltage can be applied to the top electrode layer 330 and the bottom electrode layer 310 through the first contact pad 171 and the second contact pad 172 to cause the piezoelectric structure to vibrate. The first piezoelectric structure 10-1 provided with the load material layer 304 has a higher load effect and a lower resonant frequency than the second piezoelectric structure 10-2 without the load material layer. By changing the thickness and/or shape of the load material layer 304, the bandwidth and filtering effect of the band pass of the filter device can be adjusted. Furthermore, the seed layer 106 of this embodiment is formed on the oxide layer 102 of the substrate S, and the load material layer 304 is covered by the bottom electrode layer 310 (e.g., the first bottom electrode 311), so the piezoelectric material layer 120 is deposited on the seed layer 106 without directly contacting the load material layer 304, and the formed piezoelectric material layer 120 can have a good quality factor (Q).

In the piezoelectric filter device shown in FIG. 2H, FIG. 3D and FIG. 4H in the above-mentioned embodiments, the load material layer 104, 304 is located below the bottom electrode layer 110, 310 (e.g., the first bottom electrode 111, 311). However, the present disclosure is not limited to this. In some embodiments, the load material layer may also be located between the top electrode layer and the bottom electrode layer.

Figures 5A to 5F are cross-sectional schematic diagrams of another piezoelectric filter device at various intermediate manufacturing stages according to some embodiments of the present disclosure. The same or similar components in Figures 5A to 5F as those in Figures 2A to 2H or Figures 4A to 4H are given the same or similar reference numbers, and the contents of these components in the above embodiments can be referred to. Furthermore, the components shown in Figures 5A to 5F, including various material layers and holes, and the details of their configuration, materials and manufacturing methods can be referred to the description of the relevant contents of Figures 2A to 2H above, which will not be repeated here.

In this embodiment, different from the above-mentioned embodiment, as shown in FIG. 5B , after forming the seed layer 106, the bottom electrode layer 410 (including the first bottom electrode 411 and the second bottom electrode 412) and the piezoelectric material layer 120 on the substrate S, a load material layer 404 is formed. The load material layer 404 is located above the sacrificial layer 103 and is disposed in a component region of a piezoelectric structure (e.g., the first piezoelectric structure 10-1). Thereafter, as shown in FIG. 5C , a top electrode layer 430 (including the first top electrode 431 and the second top electrode 432) is formed on the piezoelectric material layer 120, and the top electrode layer 430 covers the load material layer 404.

Then, a protective layer 140 and a dielectric layer 150 are sequentially formed on the piezoelectric material layer 120, and a first contact hole 161 that can expose the top electrode layer 430 and a second contact hole 162 that can expose the bottom electrode layer 410 are formed (FIG. 5D). Then, a first contact pad 171 and a second contact pad 172 are formed in the first contact hole 161 and the second contact hole 162, respectively (FIG. 5E). Afterwards, holes such as the first hole 181 and the second hole 182 are formed through the protective layer 140, the piezoelectric material layer 120, the seed layer 106 and the capping oxide layer 1022 to expose the sacrificial layer 103, and the sacrificial layer 103 in the substrate S is removed through these holes and appropriate processes to form a cavity 183 (FIG. 5F). Thus, the manufacturing of a piezoelectric filter device is completed.

In the embodiment shown in FIGS. 5A to 5F , since the load material layer 404 is fabricated after the seed layer 106 and the piezoelectric material layer 120 are formed, the load material layer will not affect the deposition of the piezoelectric material layer, and thus the formed piezoelectric material layer 120 has a good quality factor (Q).

In summary, according to some embodiments of the present disclosure, a piezoelectric structure provided with a load material layer and a piezoelectric structure not provided with a load material layer have different load effects and thus generate different resonant frequencies. The load material layer proposed in the embodiments is located below one of the bottom electrode layer and the top electrode layer, and is not in direct contact with the upper surface of the bottom electrode layer and the top electrode layer. For example, the load material layer of some embodiments is located below the bottom electrode layer (FIG. 2H, FIG. 3D, and FIG. 4H). For example, the load material layer of some embodiments is located below the top electrode layer (FIG. 5F). Furthermore, according to some embodiments of the present disclosure, the load material layer can be made of the same or different material as the bottom electrode layer and/or the top electrode layer, and the load material layer can be formed before the bottom electrode layer is formed or before the top electrode layer is formed. The manufacturing method proposed in the embodiment can flexibly select any suitable material to make the load material layer according to the requirements of the piezoelectric device in actual application through the semiconductor process, and the thickness of the load material layer can be adjusted. Therefore, the formation method proposed in the embodiment can be compatible with the existing process to simply manufacture a piezoelectric filter device.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of some embodiments of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each patent application and embodiment.

S: Substrate

10-1: The first piezoelectric structure

10-2: Second piezoelectric structure

100: Base material

102: Oxide layer

1021: Bottom oxide layer

1022: Covering oxide layer

103: Sacrifice layer

104,304,404: Loading material layer

106: Seed layer

110,310,410: bottom electrode layer

111,311,411: First bottom electrode

112,312,412: Second bottom electrode

120: Piezoelectric material layer

130,330,430: Top electrode layer

131,331,431: first top electrode

132,332,432: Second top electrode

140: Protective layer

150,150’: Dielectric layer

160: Contact hole

161: First contact hole

162: Second contact hole

171: First contact pad

172: Second contact pad

181: First hole

182: Second hole

183: Cavity

202: Buffer oxide layer

Cseries, Cshunt: Return loss curves of series and parallel resonators

fs: the resonance frequency of the series resonator

fp: the resonance frequency of the parallel resonator

f1,f2,f3,f4: frequency

W1,W2,W3: Width

D1: First direction

D2: Second direction

FIG. 1A is a circuit diagram of a piezoelectric filter device according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram of the simulated relationship between the frequency and the corresponding return loss (return loss) of the series/parallel resonator of a piezoelectric filter device shown in FIG. 1A. FIG. 1C is a schematic diagram of the simulated relationship between the frequency and the corresponding insertion loss (insertion loss) of a piezoelectric filter device shown in FIG. 1A. FIG. 2A to FIG. 2H are schematic cross-sectional views of a piezoelectric filter device at various intermediate manufacturing stages in some embodiments of the present disclosure. FIG. 3A to FIG. 3D are schematic cross-sectional views of another piezoelectric filter device at various intermediate manufacturing stages in some embodiments of the present disclosure. Figures 4A to 4H are schematic cross-sectional views of another piezoelectric filter device at various intermediate manufacturing stages according to some embodiments of the present disclosure. Figures 5A to 5F are schematic cross-sectional views of another piezoelectric filter device at various intermediate manufacturing stages according to some embodiments of the present disclosure.

S: Substrate

10-1: The first piezoelectric structure

10-2: The second piezoelectric structure

100: Base material

102: Oxide layer

1021: Bottom oxide layer

1022: Covering oxide layer

104: Loading material layer

106: Seed layer

110: Bottom electrode layer

111: First bottom electrode

112: Second bottom electrode

120: Piezoelectric material layer

130: Top electrode layer

131: first top electrode

132: Second top electrode

140: Protective layer

150’: Dielectric layer

160: Contact hole

161: First contact hole

162: Second contact hole

171: First contact pad

172: Second contact pad

181: First hole

182: Second hole

183: Cavity

D1: First direction

D2: Second direction

Claims (19)

A piezoelectric structure comprises: a substrate comprising a base material and an oxide layer located on the base material, wherein the oxide layer comprises a bottom oxide layer and a covering oxide layer located on the base material, the bottom oxide layer has a cavity therein, and the covering oxide layer is located on the cavity; a seed layer located above the covering oxide layer of the oxide layer; a bottom electrode located above the seed layer; a piezoelectric material layer located above the base material; electrode; a top electrode located above the piezoelectric material layer; a protective layer located on the piezoelectric material layer, and the protective layer covers the top electrode; and a load material layer corresponding to the cavity and located above the covering oxide layer, and the bottom electrode, the piezoelectric material layer and the top electrode are stacked on the substrate along a first direction, wherein the load material layer is located below one of the bottom electrode and the top electrode. A piezoelectric structure as claimed in claim 1, wherein the load material layer is located between the bottom electrode and the substrate. A piezoelectric structure as claimed in claim 2, wherein the load material layer is located on the covering oxide layer of the oxide layer, and the seed layer covers the load material layer. The piezoelectric structure of claim 2, wherein the load material layer is located on the covering oxide layer of the oxide layer, the piezoelectric structure further includes a buffer oxide layer covering the load material layer, and the seed layer is formed on the buffer oxide layer. A piezoelectric structure as claimed in claim 2, wherein the load material layer is located on the seed layer, and the bottom electrode covers the load material layer. A piezoelectric structure as claimed in claim 1, wherein the load material layer is located on the piezoelectric material layer, and the top electrode covers the load material layer. The piezoelectric structure of claim 1, wherein the load material layer comprises metal, metal nitride, dielectric material, or a combination thereof, and the dielectric material comprises silicon nitride, silicon oxynitride, or a combination thereof. The piezoelectric structure of claim 1, wherein the bottom electrode is a first bottom electrode, and the piezoelectric structure further comprises a second bottom electrode disposed adjacent to the first bottom electrode, wherein in a cross section, the second bottom electrode is separated from the first bottom electrode in a second direction, and the first direction is different from the second direction, wherein the load material layer is located below the first bottom electrode. A piezoelectric structure as claimed in claim 8, wherein the seed layer covers the load material layer, the second bottom electrode and the first bottom electrode are located on the seed layer, and the load material layer is located below the first bottom electrode and the seed layer. A piezoelectric structure as claimed in claim 8, wherein the load material layer is located on the oxide layer, a buffer oxide layer covers the load material layer, the seed layer is located on the buffer oxide layer, and the second bottom electrode and the first bottom electrode are located on the seed layer, wherein the load material layer is located below the first bottom electrode, the seed layer and the buffer oxide layer. A piezoelectric structure as claimed in claim 8, wherein the load material layer is located on the seed layer, the second bottom electrode and the first bottom electrode are located on the seed layer, and the first bottom electrode covers the load material layer. A piezoelectric structure as claimed in claim 1, wherein the top electrode is a first top electrode, and the piezoelectric structure further comprises a second top electrode disposed adjacent to the first top electrode, wherein in a cross section, the second top electrode is separated from the first top electrode in a second direction, and the first direction is different from the second direction, wherein the load material layer is located on the piezoelectric material layer, and the first top electrode covers the load material layer. A method for forming a piezoelectric structure comprises: providing a substrate, the substrate comprising a base material and an oxide layer located on the base material, wherein the oxide layer comprises a bottom oxide layer and a covering oxide layer located on the base material, the bottom oxide layer has a cavity therein, and the covering oxide layer is located on the cavity; and forming a stacking structure on the substrate along a first direction, the stacking structure comprising: a seed layer formed above the covering oxide layer of the oxide layer; a bottom electrode, formed on the seed layer; a piezoelectric material layer formed on the bottom electrode; a top electrode formed on the piezoelectric material layer; a protective layer formed on the piezoelectric material layer, and the protective layer covers the top electrode; and a load material layer corresponding to the cavity and located above the covering oxide layer, and the bottom electrode, the piezoelectric material layer and the top electrode are stacked along a first direction, wherein the load material layer is formed below one of the bottom electrode and the top electrode. A method for forming a piezoelectric structure as claimed in claim 13, wherein the load material layer is formed between the bottom electrode and the substrate. A method for forming a piezoelectric structure as claimed in claim 14, wherein forming the stacked structure comprises: forming the load material layer on the capping oxide layer; forming the seed layer on the capping oxide layer and covering the load material layer; forming the bottom electrode on the seed layer; forming the piezoelectric material layer on the bottom electrode; and forming the top electrode on the piezoelectric material layer. A method for forming a piezoelectric structure as claimed in claim 14, wherein forming the stacked structure comprises: forming the load material layer on the capping oxide layer; forming a buffer oxide layer on the capping oxide layer and covering the load material layer; forming the seed layer on the buffer oxide layer; forming the bottom electrode on the seed layer; forming the piezoelectric material layer on the bottom electrode; and forming the top electrode on the piezoelectric material layer. A method for forming a piezoelectric structure as claimed in claim 14, wherein forming the stacked structure comprises: forming the seed layer on the covering oxide layer; forming the load material layer on the seed layer; forming the bottom electrode on the seed layer, and the bottom electrode covers the load material layer; forming the piezoelectric material layer on the bottom electrode; and forming the top electrode on the piezoelectric material layer. A method for forming a piezoelectric structure as claimed in claim 13, wherein the load material layer is formed between the piezoelectric material layer and the top electrode. A method for forming a piezoelectric structure as claimed in claim 18, wherein forming the stacked structure comprises: forming the seed layer on the capping oxide layer; forming the bottom electrode on the seed layer; forming the piezoelectric material layer on the bottom electrode; forming the load material layer on the piezoelectric material layer; and forming the top electrode on the piezoelectric material layer, and the top electrode covers the load material layer.

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