CN117478075A - Low noise amplifier integrated with switch and filter without inverse filtering function - Google Patents
Low noise amplifier integrated with switch and filter without inverse filtering function Download PDFInfo
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The invention aims to provide a low-noise amplifier integrating a switch and a filter without an anti-filtering function, and belongs to the technical field of low-noise amplifiers. The amplifier realizes high-density integration of the two-stage broadband low-noise amplifier, the reflection-free filter and the switch by reasonably designing a circuit structure, and simultaneously, the performance of the low-noise amplifier is improved by introducing a feedback network and a notch network; the integrated circuit has the advantages of high integration level, small volume, excellent performance, convenience in control and the like.
Description
Technical Field
The invention belongs to the technical field of low noise amplifiers, and particularly relates to a low noise amplifier integrating a switch and a filter without an anti-filtering function.
Background
The low noise amplifier is one of the most important active devices of all radar receivers, and is located at the first stage after the whole receiver antenna and array switch, and its noise figure is the main source of the noise figure of the whole receiver. Modern radar receivers place requirements on low noise amplifiers, such as wide frequency band, low noise amplification, and low power consumption. With the development of radar receiver technology, more and more radar receivers require low noise amplifier to realize multifunctional integration. The multifunctional integration can effectively reduce the volume and the power consumption of the whole receiver, and greatly simplify the number of elements of the whole receiver. In terms of performance indexes, the multifunctional integration can effectively reduce the problems of unmatched device impedance, deterioration of standing-wave ratio, low device isolation and the like caused by device welding.
However, the multifunctional integration of the low noise amplifier is mainly developed around two aspects, namely, the integration of the low noise amplifier and the filter is realized, and the integration of the low noise amplifier and the switch is realized. But there has been no report on a low noise amplifier integrating a filter and a switch at the same time.
Furthermore, the low noise amplifier and the subsequent circuit of the filter are mixers, the mixers can only process signals with specific frequency, the unprocessed signals can be reflected back to the antenna through the microwave link, if the isolation of the switch is not high enough, parasitic harmonic wave can be generated in the whole receiver link, and the sensitivity and the dynamic range of the receiver are further deteriorated. One possible way to solve this problem is to change the filter before the mixer into a reflectionless filter, but the reflectionless filter has a larger size.
Therefore, how to design a low noise amplifier so that it can integrate a switch and a filter without an anti-filtering function is an important point of research.
Disclosure of Invention
In view of the problem that a plurality of elements of the current radar receiver between an antenna and a mixer cannot be integrated and lack a reflection-free filtering function in the prior art, the invention aims to provide a low-noise amplifier integrating a switch and a filter without the reflection-free filtering function. The amplifier realizes high-density integration of the two-stage broadband low-noise amplifier, the reflection-free filter and the switch by reasonably designing a circuit structure, and simultaneously, the performance of the low-noise amplifier is improved by introducing a feedback network and a notch network; the integrated circuit has the advantages of high integration level, small volume, excellent performance, convenience in control and the like.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the low noise amplifier comprises an input matching unit, a notch network, a cascode amplifier, a switch control network, a feedback network, an interstage matching unit, a parallel peaking load amplifier, an output matching unit and a reflectionless filter network;
the input matching unit consists of microstrip lines which are distributed in a three-section T-shaped structure, one end of a first microstrip line TL1 is connected with an input port of the low-noise amplifier, the other end of the first microstrip line TL1 is connected with one end of a second microstrip line TL2 and one end of a third microstrip line TL3, and the other end of the second microstrip line TL2 is connected with a grid electrode of a first transistor FET1 in the common-source common-gate amplifier and one end of a twelfth inductor L12 in the switch control network;
the notch network consists of a first inductor L1, a first capacitor C1 and a second capacitor C2; one end of the first inductor L1 is grounded, and the other end of the first inductor L1 is connected with one end of the first capacitor C1 and one end of the second capacitor C2; the other end of the first capacitor C1 is connected with the drain electrode of the first transistor FET1 in the common-source common-gate amplifier and the source electrode of the second transistor FET2 in the common-source common-gate amplifier; the other end of the second capacitor C2 is grounded;
the cascode amplifier consists of a first transistor FET1, a second transistor FET2, a third capacitor C3, a fourth capacitor C4 and a first resistor R1; the source of the first transistor FET1 is grounded; the drain electrode of the second transistor FET2 is connected with one end of a fourth microstrip line and one end of a sixth microstrip line in the interstage matching unit; the grid electrode of the second transistor FET2 is connected with one end of the fourth capacitor C4 and one end of the first resistor R1; the other end of the fourth capacitor C4 is grounded; the other end of the first resistor R1 is connected with one end of a third capacitor C3 and a direct current power supply VCC;
the switch control network is composed of a twelfth inductor L12, a thirteenth inductor L13, a ninth microstrip line TL9, a tenth microstrip line TL10, an eleventh microstrip line TL11, a twelfth microstrip line TL12, an eleventh capacitor C11, a twelfth capacitor C12, a fourth transistor FET4 and a fifth transistor FET 5; the other end of the twelfth inductor L12 is connected with one end of a ninth microstrip line TL9, and the other end of the ninth microstrip line TL9 is connected with one end of an eleventh microstrip line TL11 and the drain electrode of the fourth transistor FET 4; the grid electrode of the fourth transistor FET4 is connected with the control voltage, and the source electrode is grounded; the other end of the eleventh microstrip line TL11 is connected to one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the twelfth microstrip line TL12, and the control voltage; the other end of the twelfth microstrip line TL12 is connected to one end of the tenth microstrip line TL10 and the drain of the fifth transistor FET 5; the source electrode of the fifth transistor FET5 is grounded, and the grid electrode is connected with the control voltage; the other end of the tenth microstrip line TL10 is connected to one end of the thirteenth inductance L13; the other end of the thirteenth inductance L13 is connected with the other end of the fifth microstrip line TL5 in the interstage matching unit and the gate of the third transistor FET3 in the parallel peaking load amplifier;
the feedback network is composed of a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth microstrip line TL8, a first coupling line CTL1 and a fourth inductor L4; one end of the fifth capacitor C5 is grounded, and the other end of the fifth capacitor C is connected with the coupling end of the first coupling line CTL 1; an input end of the first coupling line CTL1 is connected to one end of the eighth microstrip line TL8, an isolation end is connected to one end of the seventh capacitor C7, and an output end is connected to the drain electrode of the second transistor FET 2; the other end of the eighth microstrip line TL8 is connected with one end of a sixth capacitor C6, and the other end of the sixth capacitor C6 is connected with one end of a direct current power supply VCC and one end of a fourth inductor L4; the other end of the seventh capacitor C7 is grounded;
the interstage matching unit consists of a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10; the other end of the fourth microstrip line TL4 is connected with one end of an eighth capacitor C8, the other end of the eighth capacitor C8 is connected with one end of a fifth microstrip line TL5, and the other end of the fifth microstrip line TL5 is connected with one end of a seventh microstrip line TL7, the other end of a thirteenth inductor L13 in a switch control network and the grid of a third transistor FET3 in the parallel peaking load amplifier; the other end of the seventh microstrip line TL7 is connected with one end of a tenth capacitor C10, and the other end of the tenth capacitor C10 is grounded; the other end of the sixth microstrip line TL6 is connected with one end of a ninth capacitor C9, and the other end of the ninth capacitor C9 is grounded;
the parallel peaking load amplifier consists of a third transistor FET3 and a fourth inductor L4; the drain electrode of the third transistor FET3 is connected with the other end of the fourth inductor L4 and one end of a thirteenth microstrip line TL13 in the output matching unit, and the source electrode of the third transistor FET3 is grounded; the parallel peaking load amplifier and the feedback network share a fourth inductance L4;
the output matching unit consists of microstrip lines which are distributed in a three-section T-shaped structure, one end of a thirteenth microstrip line TL13 is connected with the other end of the fourth inductor L4, and the other end of the thirteenth microstrip line TL13 is connected with one end of a fourteenth microstrip line TL14 and one end of a fifteenth microstrip line TL 15; the other end of the fourteenth microstrip line TL14 is connected to the first port of the second coupling line CTL2 in the non-inverse filter network; the other end of the fifteenth microstrip line TL15 is open;
the reflectionless filter network consists of a second coupling line CTL2, a third coupling line CTL3, a thirteenth capacitor C13, a fourteenth capacitor C14, a second resistor R2, a third resistor R3, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17 and an eighteenth microstrip line TL 18; the second port of the second coupling line CTL2 is connected with one end of the second resistor R2 and one end of the thirteenth capacitor C13, and the third port of the second coupling line CTL2 is connected with the first port of the third coupling line CTL 3; the other end of the second resistor R2 is connected with one end of the sixteenth microstrip line TL16 and one end of the eighteenth microstrip line TL 18; the second port of the third coupling line CTL3 is connected with the output port of the low noise amplifier, and the third port of the third coupling line CTL3 is connected with one end of the fourteenth capacitor C14 and one end of the third resistor R3; the fourth port of the second coupled line CTL2 and the fourth port of the third coupled line CTL3 are both open; the other end of the third resistor R3 is connected with the other end of the eighteenth microstrip line TL18 and one end of the seventeenth microstrip line TL 17; the other end of the thirteenth capacitor C13, the other end of the sixteenth microstrip line TL16, the other end of the seventeenth microstrip line TL17, and the other end of the fourteenth capacitor C14 are all grounded.
Further, the low noise amplifier further comprises an input blocking capacitor C1 and an output blocking capacitor C16, wherein the input blocking capacitor is arranged between the input matching unit and the input end of the low noise amplifier, and the output blocking capacitor is arranged between the output matching unit and the output end of the low noise amplifier and is used for realizing direct current isolation; the capacitance of the blocking capacitor is preferably 30fF.
Further, the characteristic impedance and the electrical length of the microstrip line in the input matching unit are adjusted to achieve broadband matching, and the number of microstrip lines is increased between the input capacitance and the first microstrip line TL1 to enhance the bandwidth characteristics of the low noise amplifier.
Further, the resonance frequency is adjusted by adjusting the capacitance value of the second capacitor C2 in the notch network, and the resonance frequency of the notch network is adjusted to be outside the upper sideband of the low-noise amplifier, so that the out-of-band anti-interference capability of the low-noise amplifier can be improved, and the in-band ripple characteristic of the low-noise amplifier can be adjusted; the inductance value of the first inductor L1 and the first capacitor C1 form a resonant network to S at the center frequency point 21 The suppression depth is also different, and the smaller the inductance value is, the deeper the suppression depth is.
Further, the input end and the output end of the first coupling line CTL1 are in a cross structure, and can be mutually converted, that is, after the microstrip line on one side is used as the input port, the microstrip line on the other side is used as the output port.
Further, by adjusting the characteristic impedance and the electrical length of the microstrip line in the output matching unit to achieve broadband matching, the low noise amplifier bandwidth characteristics are enhanced by increasing the number of microstrip lines between the second coupling line CTL2 and the fourteenth microstrip line TL 14.
Further, the switch control network is of a bilateral symmetry structure, and the non-inverse filter network is of a symmetry bridging structure.
Further, the switch control network realizes the simultaneous on or off of the first transistor FET1 and the crystal third transistor FET3 through the regulation and control of the control voltage.
Further, the feedback network is in the form of positive feedback with a gain of-2C k T k Wherein C k For coupling coefficient of feedback network, T k Is the penetration coefficient of the feedback network; the smaller the coupling coefficient k of the first coupled line, the smaller the gain of the feedback network, but the larger the gain fluctuation.
Further, by adjusting nothingA thirteenth capacitor C13, a fourteenth capacitor C14, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17, a second resistor R2 and a third resistor R3 in the anti-filter network, so that S 21 The return loss of the parameter in-band is 7-10dB.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. the invention integrates the switching function in the low noise amplifier, reduces the complex impedance transformation caused by the independent design of the switch and the low noise amplifier in the traditional circuit structure, and reduces the volume and the complexity of the system; meanwhile, standing wave ratio deterioration caused by mismatching of the switch and the low-noise amplifier can be avoided.
2. The invention integrates a novel feedback network in the low noise amplifier and has a phase shifting function, and the characteristic impedance, the electrical length and other parameters of the microstrip lines in the input unit and the output matching unit can be adjusted to improve the lower sideband roll off coefficient of the low noise amplifier and improve the working bandwidth of the low noise amplifier.
3. According to the invention, the anti-filtering network is integrated in the low-noise amplifier, so that the reflection energy outside the frequency mixer is consumed through the resistor, parasitic harmonic wave and spurious emission generated by intermodulation effect after the reflection energy enters the antenna through the low-noise amplifier are avoided, and the anti-interference capability of the low-noise amplifier is improved.
Drawings
Fig. 1 is an exploded view of the integrated function of the low noise amplifier of the present invention.
Fig. 2 is a circuit configuration diagram of a low noise amplifier according to the present invention.
Fig. 3 is a noise figure simulation diagram of embodiment 1 of the present invention.
Fig. 4 is a P1dB simulation diagram of embodiment 1 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the embodiments and the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
A low noise amplifier integrating a switch and a filter without an anti-filtering function is shown in an integrated functional exploded view as shown in figure 1, and comprises an input capacitor, an input matching unit, a notch network, a cascode amplifier, a switch control network, a feedback network, an interstage matching unit, a parallel peaking load amplifier, an output matching unit, a non-reflection filter network and an output capacitor.
A specific circuit configuration of the low noise amplifier is shown in fig. 2. The input matching network is a T-shaped matching network formed by three sections of microstrip lines (TL 1, TL2 and TL 3), the matching aim is to realize the conjugate matching of the minimum noise coefficient point of a transistor FET1 in the cascode amplifier, the broadband matching of the low-noise amplifier is realized by adjusting the characteristic impedance and the electrical length of the microstrip lines, and the bandwidth characteristic can be enhanced by increasing the number of the microstrip lines of the matching network when necessary.
The notch network consists of a parallel capacitor C2, an inductor L1 and a series capacitor C1; the parallel capacitor with one end grounded and the inductor with one end grounded are connected in parallel and then connected in series with the fixed capacitor; the resonance frequency of the whole network is changed by adjusting the parallel capacitance, and the resonance frequency of the notch network is adjusted to be outside the upper side band of the low noise amplifier, so that the out-of-band anti-interference capability of the low noise amplifier can be improved, and the in-band ripple characteristic of the low noise amplifier can be adjusted.
The cascode amplifier group mainly consists of a first transistor FET1 and a second transistor FET 2; the first transistor FET1 is of a common-source structure, the second transistor FET2 is of a common-gate structure, and the two transistors form the common-source common-gate structure together; the grid electrode of the second transistor FET2 is connected with a direct current power supply VCC after being isolated by a resistor R1, and two capacitors (C3 and C4) with single-end grounding are respectively added at two sides of an inductor to realize power supply filtering in order to increase the anti-interference characteristic of the power supply.
The switch control network is a three-port network with a bilateral symmetry structure, and the three ports are respectively an external voltage control port, a left control port and a right control port, and consist of a microstrip line, a transistor FET4, a transistor FET5, an inductor and a capacitor. The transistor FET4 and the transistor FET5 adopt a common source mode, one ends of the drains of the two transistors are connected to an external voltage control interface through microstrip lines (TL 11 and TL 12), and the other ends of the drains are connected to ports to be controlled after series inductance (L2 and L3) of the microstrip lines (TL 9 and TL 10). To achieve power supply filtering, capacitors (C11, C12) are connected in parallel at the external voltage control interface. The left control port of the switch control network is connected with the grid electrode of the transistor FET1, and the right control port is connected with the source electrode of the transistor FET 3; the simultaneous on or off control of the transistor FET1 and the transistor FET3 is realized through the voltage control port.
The feedback network consists of capacitors (C5, C6, C7), microstrip lines TL8, coupled lines CTL1 and inductors. One end of the feedback network is connected with a direct current power supply, and sequentially connected with an inductor L3, a series capacitor C6, a series microstrip line TL8 and a series coupling line CTL1 in parallel, and then connected to the drain electrode of a transistor FET 2; the inductance L3 belongs to an interoperable device, and participates in a feedback network, and forms a parallel peaking load structure with the transistor FET 3. The input/output port of the coupling line CTL1 is a cross structure, i.e. after the microstrip line on one side is used as the input port, the microstrip line on the other side is used as the output port, and the remaining ports are connected to the ground through single-ended grounding capacitors (C5, C7).
The interstage matching unit is composed of a microstrip line TL4, a capacitor C8 and a microstrip line TL5, and microstrip lines (TL 6 and TL 7) and capacitors (C9 and C10) grounded at a single end are connected in parallel at two sides of the two microstrip lines (TL 4 and TL 5) to realize impedance conjugate matching of high-pass characteristics from the transistor FET2 to the transistor FET 3.
The output matching unit is a T-shaped matching network formed by three sections of microstrip lines (TL 13, TL14 and TL 15), the matching aim is to realize the conjugate matching of the minimum noise coefficient point of the transistor FET3, the broadband matching of the low-noise amplifier is realized by adjusting the characteristic impedance and the electrical length of the microstrip lines, and the bandwidth characteristic can be enhanced by increasing the number of the microstrip lines of the matching network when necessary.
The non-inverse filter network consists of a coupling line CTL2, a coupling line CTL3, single-end grounding capacitors (C13 and C14), resistors (R3 and R4) and microstrip lines (TL 16, TL17 and TL 18); the non-inverse filter network comprises two branches, wherein each branch comprises a coupling line, a single-end grounding capacitor, a resistor and a microstrip line; the two branches are connected in series through a third microstrip line to form a symmetrical bridging structure. The coupling line CTL2 and the coupling line CTL3 are connected in series and then respectively connected with an output port of the transistor FET3 and one end of an output capacitor, the remaining ports of the coupling line CTL2 and the coupling line CTL3 are respectively connected to the ground through a resistor and a microstrip line, and parallel single-end grounding capacitors (C13, C14) are added between the resistor and the coupling line to improve the resonance characteristics of the filter.
Example 1
In the embodiment, the low noise amplifier is manufactured by adopting a pHEMT MMIC process of a GaAs substrate of 0.15 μm, the material of the dielectric substrate is gallium arsenide, the dielectric constant is 12.91, the thickness of the dielectric substrate is 100 μm, all circuits are etched on the upper surface of the dielectric substrate by micro-nano processing, and the lower surface of the dielectric substrate is grounded by a flat metal layer.
Calculating to obtain the input impedance and the output impedance of the low-noise amplifier through an equivalent model; and the optimal noise coefficient matching is realized by using a T-shaped microstrip line matching method, the gain is increased as much as possible when the optimal noise coefficient is ensured, and the matching network is optimized to show the band-pass filtering characteristic. To achieve dc isolation, a capacitance of 30fF is connected in series between the input match and the input, and a capacitance of 30fF is connected in series between the output match and the output.
Considering that the Q value of the on-chip inductor is smaller, the inductance value of the notch network is selected to be as smaller as possible, and the different inductance values L1 and the series capacitor C1 form S at the center frequency point after forming the resonance network 21 The inhibition depth is also different: the smaller the inductance value, the deeper the suppression depth. In the embodiment, the inductance value of 1nH is selected, and meanwhile, the capacitance value of the series capacitor is adjusted to enable the series capacitor to achieve notch at the frequency of 3.5GHz, so that the anti-interference capacity of the outer side of the upper side band is improved; the value of the parallel capacitor C2 is 100fF, and the parallel capacitor can be adjusted to realize the improvement of the inhibition depth. The capacitance is implemented in MIM (metal-insulator-metal) form.
The first-stage amplifying circuit adopts a cascode structure and is connected with a power supply VCC through a resistor R1; the capacitance values of the single-ended grounding capacitors (C3, C4) on both sides of the resistor R1 are respectively selected to be 1pF and 180fF, the resistor is selected to be 1kΩ, and the specifications of the transistor FET1 and the transistor FET2 are 2×20 μm.
The inter-stage matching unit takes the form of a high pass filter to improve gain flatness in-band. The two parallel microstrip lines (TL 6, TL 7) are grounded through capacitors (C9, C10) respectively. In the embodiment, the capacitance value of the capacitor is selected to be 150fF, and the two parallel branches resonate at low frequency to present a lower impedance value, so that gain fluctuation of the upper-stage amplifier can be effectively restrained. Adjusting the values of the series microstrip lines (TL 4, TL 5) and the capacitance (C8) achieves conjugate matching from the transistor FET2 to the transistor FET 3.
The feedback network is in the form of positive feedback, wherein the gain is-2C k T k Wherein C k For coupling coefficient of feedback network, T k The penetration coefficients of the feedback network are respectively in functional relation with the coupling coefficients k of the coupling lines. In general, the smaller the coupling coefficient k of the coupled line, the smaller the gain of the feedback network, but the larger the gain fluctuation. And comprehensively considering the balance between the gain and the gain fluctuation, selecting the coupling coefficient of the coupling line to be 0.2 and the length to be 300 mu m, and adjusting other parameters to optimize the gain fluctuation of the low-noise amplifier in the frequency band.
The switch is realized by adopting a common source transistor, the starting voltage is required to be smaller than-1.8V, the switching-off voltage is 0V, the two transistors (FET 4 and FET 5) select the specification of 2 multiplied by 10 mu m, and the parallel single-end grounding capacitors (C11 and C12) still select the specification of 180fF, so that the power supply filtering is realized. The lengths of the microstrip lines (TL 9, TL10, TL11, TL 12) are selected to be characteristic impedance of 50Ω, the electrical lengths are selected to be 10 DEG, and the influence on the interstage matching network is reduced. The inductance values (L2, L3) have a certain influence on the matching network, so that the inductance values are adjusted to optimize the whole circuit. One end of the switching network is connected with the grid electrode of the transistor FET1, the other end is connected with the source electrode of the transistor FET3, and the switching-off and switching-on of the two transistors are realized synchronously by controlling the switching optical network.
The second-stage amplifying circuit adopts a parallel peaking load structure, so that the bandwidth of the low-noise amplifier is increased. The value L of the inductance (L4), the parasitic resistance value R of the inductance L and the output equivalent capacitance C of the transistor FET3 out The construction of the resonant structure is considered in combination. By optimizing inductance L, time constant C of capacitor and resistor out R: inductance and resistance determined time constant L/r=2: 1, the effect of expanding the bandwidth by 180% is realized.
The non-inverse filter network adopts a symmetrical structure form based on the coupled line, and defines the coupling coefficient of the whole non-inverse filter network as ρ, then the even mode resistance of the coupled lineResistance to diseasesOdd mode impedance is +.>The values of the parallel capacitors (C13, C14), the parallel microstrip lines (TL 16, TL 17) and the resistors (R2, R3) are regulated to ensure that S 21 The return loss of the parameter in the band is 7-10dB, and the excessive return loss can reduce the gain coefficient of the low noise amplifier, so that two indexes are required to be comprehensively balanced.
The implementation is only one example, all values of the whole low noise amplifier can be set as variables, and the whole parameters can be optimized by optimizing an algorithm and fusing the gain, the gain fluctuation, the noise coefficient and the maximum power into an optimized objective function.
Fig. 3 is a noise figure simulation diagram of embodiment 1 of the present invention. As can be seen from the figure, the low noise amplifier of the embodiment has a center frequency point of 4.0-6.0GHz, a noise coefficient after simulation of 1.71-1.95dB, and the noise coefficient is better than 1.75dB at the frequency of 4.4-5.6 GHz. Fig. 4 is a P1dB simulation diagram of embodiment 1 of the present invention. P1dB fluctuates between-2.2 dBm and-2.0 dBm in the frequency band of 4.0-6.0GHz, and has better linearity. The working frequency band of the low-noise amplifier exceeds 40%, and the low-noise amplifier has good broadband characteristics.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (10)
1. The low noise amplifier is characterized by comprising an input matching unit, a notch network, a cascode amplifier, a switch control network, a feedback network, an interstage matching unit, a parallel peaking load amplifier, an output matching unit and a reflectionless filter network;
the input matching unit consists of microstrip lines which are distributed in a three-section T-shaped structure, one end of a first microstrip line TL1 is connected with an input port of the low-noise amplifier, the other end of the first microstrip line TL1 is connected with one end of a second microstrip line TL2 and one end of a third microstrip line TL3, and the other end of the second microstrip line TL2 is connected with a grid electrode of a first transistor FET1 in the common-source common-gate amplifier and one end of a twelfth inductor L12 in the switch control network;
the notch network consists of a first inductor L1, a first capacitor C1 and a second capacitor C2; one end of the first inductor L1 is grounded, and the other end of the first inductor L1 is connected with one end of the first capacitor C1 and one end of the second capacitor C2; the other end of the first capacitor C1 is connected with the drain electrode of the first transistor FET1 in the common-source common-gate amplifier and the source electrode of the second transistor FET2 in the common-source common-gate amplifier; the other end of the second capacitor C2 is grounded;
the cascode amplifier consists of a first transistor FET1, a second transistor FET2, a third capacitor C3, a fourth capacitor C4 and a first resistor R1; the source of the first transistor FET1 is grounded; the drain electrode of the second transistor FET2 is connected with one end of a fourth microstrip line and one end of a sixth microstrip line in the interstage matching unit; the grid electrode of the second transistor FET2 is connected with one end of the fourth capacitor C4 and one end of the first resistor R1; the other end of the fourth capacitor C4 is grounded; the other end of the first resistor R1 is connected with one end of a third capacitor C3 and a direct current power supply VCC;
the switch control network is composed of a twelfth inductor L12, a thirteenth inductor L13, a ninth microstrip line TL9, a tenth microstrip line TL10, an eleventh microstrip line TL11, a twelfth microstrip line TL12, an eleventh capacitor C11, a twelfth capacitor C12, a fourth transistor FET4 and a fifth transistor FET 5; the other end of the twelfth inductor L12 is connected with one end of a ninth microstrip line TL9, and the other end of the ninth microstrip line TL9 is connected with one end of an eleventh microstrip line TL11 and the drain electrode of the fourth transistor FET 4; the grid electrode of the fourth transistor FET4 is connected with the control voltage, and the source electrode is grounded; the other end of the eleventh microstrip line TL11 is connected to one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the twelfth microstrip line TL12, and the control voltage; the other end of the twelfth microstrip line TL12 is connected to one end of the tenth microstrip line TL10 and the drain of the fifth transistor FET 5; the source electrode of the fifth transistor FET5 is grounded, and the grid electrode is connected with the control voltage; the other end of the tenth microstrip line TL10 is connected to one end of the thirteenth inductance L13; the other end of the thirteenth inductance L13 is connected with the other end of the fifth microstrip line TL5 in the interstage matching unit and the gate of the third transistor FET3 in the parallel peaking load amplifier;
the feedback network is composed of a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth microstrip line TL8, a first coupling line CTL1 and a fourth inductor L4; one end of the fifth capacitor C5 is grounded, and the other end of the fifth capacitor C is connected with the coupling end of the first coupling line CTL 1; an input end of the first coupling line CTL1 is connected to one end of the eighth microstrip line TL8, an isolation end is connected to one end of the seventh capacitor C7, and an output end is connected to the drain electrode of the second transistor FET 2; the other end of the eighth microstrip line TL8 is connected with one end of a sixth capacitor C6, and the other end of the sixth capacitor C6 is connected with one end of a direct current power supply VCC and one end of a fourth inductor L4; the other end of the seventh capacitor C7 is grounded;
the interstage matching unit consists of a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10; the other end of the fourth microstrip line TL4 is connected with one end of an eighth capacitor C8, the other end of the eighth capacitor C8 is connected with one end of a fifth microstrip line TL5, and the other end of the fifth microstrip line TL5 is connected with one end of a seventh microstrip line TL7, the other end of a thirteenth inductor L13 in a switch control network and the grid of a third transistor FET3 in the parallel peaking load amplifier; the other end of the seventh microstrip line TL7 is connected with one end of a tenth capacitor C10, and the other end of the tenth capacitor C10 is grounded; the other end of the sixth microstrip line TL6 is connected with one end of a ninth capacitor C9, and the other end of the ninth capacitor C9 is grounded;
the parallel peaking load amplifier consists of a third transistor FET3 and a fourth inductor L4; the drain electrode of the third transistor FET3 is connected with the other end of the fourth inductor L4 and one end of a thirteenth microstrip line TL13 in the output matching unit, and the source electrode of the third transistor FET3 is grounded; the parallel peaking load amplifier and the feedback network share a fourth inductance L4;
the output matching unit consists of microstrip lines which are distributed in a three-section T-shaped structure, one end of a thirteenth microstrip line TL13 is connected with the other end of the fourth inductor L4, and the other end of the thirteenth microstrip line TL13 is connected with one end of a fourteenth microstrip line TL14 and one end of a fifteenth microstrip line TL 15; the other end of the fourteenth microstrip line TL14 is connected to the first port of the second coupling line CTL2 in the non-inverse filter network; the other end of the fifteenth microstrip line TL15 is open;
the reflectionless filter network consists of a second coupling line CTL2, a third coupling line CTL3, a thirteenth capacitor C13, a fourteenth capacitor C14, a second resistor R2, a third resistor R3, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17 and an eighteenth microstrip line TL 18; the second port of the second coupling line CTL2 is connected with one end of the second resistor R2 and one end of the thirteenth capacitor C13, and the third port of the second coupling line CTL2 is connected with the first port of the third coupling line CTL 3; the other end of the second resistor R2 is connected with one end of the sixteenth microstrip line TL16 and one end of the eighteenth microstrip line TL 18; the second port of the third coupling line CTL3 is connected with the output port of the low noise amplifier, and the third port of the third coupling line CTL3 is connected with one end of the fourteenth capacitor C14 and one end of the third resistor R3; the fourth port of the second coupled line CTL2 and the fourth port of the third coupled line CTL3 are both open; the other end of the third resistor R3 is connected with the other end of the eighteenth microstrip line TL18 and one end of the seventeenth microstrip line TL 17; the other end of the thirteenth capacitor C13, the other end of the sixteenth microstrip line TL16, the other end of the seventeenth microstrip line TL17, and the other end of the fourteenth capacitor C14 are all grounded.
2. The low noise amplifier of claim 1, further comprising an input blocking capacitor C1 and an output blocking capacitor C16, the input blocking capacitor being disposed between the input matching unit and the input of the low noise amplifier, the output blocking capacitor being disposed between the output matching unit and the output of the low noise amplifier for dc isolation.
3. The low noise amplifier of claim 1, wherein the low noise amplifier bandwidth characteristic is enhanced by increasing the number of microstrip lines between the input capacitance and the first microstrip line TL1 by adjusting the characteristic impedance and the electrical length of the microstrip line in the input matching unit to achieve broadband matching.
4. The low noise amplifier of claim 1, wherein the adjusting of the resonant frequency by adjusting the capacitance of the second capacitor C2 in the notch network adjusts the resonant frequency of the notch network out of the upper sideband of the low noise amplifier to improve the out-of-band anti-interference capability of the low noise amplifier and adjust the in-band ripple characteristic of the low noise amplifier; the inductance value of the first inductor L1 and the first capacitor C1 form a resonant network to S at the center frequency point 21 The suppression depth is different, and the smaller the inductance value is, the deeper the suppression depth is.
5. A low noise amplifier according to claim 1, wherein the input and output terminals of the first coupling line CTL1 are of a cross structure, and are mutually convertible, i.e. one side microstrip line is used as an input port and the other side microstrip line is used as an output port.
6. The low noise amplifier according to claim 1, wherein the low noise amplifier bandwidth characteristic is enhanced by increasing the number of microstrip lines between the second coupling line CTL2 and the fourteenth microstrip line TL14 by adjusting the characteristic impedance and the electrical length of the microstrip line in the output matching unit to achieve broadband matching.
7. The low noise amplifier of claim 1, wherein the switch control network is a bilateral symmetry structure and the non-inverse filter network is a symmetry bridging structure.
8. A low noise amplifier according to claim 1, wherein the switching control network enables simultaneous switching on or off of the first transistor FET1 and the crystalline third transistor FET3 by regulation of the control voltage.
9. A low noise amplifier according to claim 1, wherein the feedback network is in the form of positive feedback with a gain of-2C k T k Wherein C k For coupling coefficient of feedback network, T k Is the penetration coefficient of the feedback network; the smaller the coupling coefficient k of the first coupled line, the smaller the gain of the feedback network, but the larger the gain fluctuation.
10. The low noise amplifier of claim 1, wherein S is caused by adjusting parameter values of a thirteenth capacitor C13, a fourteenth capacitor C14, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17, a second resistor R2, a third resistor R3 in the non-inverse filter network 21 The return loss of the parameter in-band is 7-10dB.
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