CN117476589A

CN117476589A - Chip packaging structure

Info

Publication number: CN117476589A
Application number: CN202311823803.2A
Authority: CN
Inventors: 段海洁; 郭旭东
Original assignee: Xi'an Geyi Anchuang Integrated Circuit Co ltd
Current assignee: Xi'an Geyi Anchuang Integrated Circuit Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-01-30
Anticipated expiration: 2043-12-28
Also published as: CN117476589B

Abstract

The invention provides a chip packaging structure. The chip packaging structure comprises: the die comprises a first internal lead, a first access pad and a plurality of functional pads, wherein the first access pad and the functional pads are positioned on the surface of the die, the die is provided with a first side and a second side which are adjacent, the first access pad is arranged on the first side, the functional pads are arranged on the first side and the second side, and the first access pad is electrically connected with the functional pads of the first side through the first internal lead; the first pin is positioned on one side of the bare chip and is a power pin or a grounding pin; and the plurality of bonding wires comprise a first bonding wire and at least one second bonding wire crossing over the bare chip, the first bonding wire is electrically connected with the first pin and the first access pad, and the second bonding wire is electrically connected with one functional pad of the first side and one functional pad of the second side. Thus, a single power pin or a single ground pin package is realized, and the impedance of electrical conduction can be reduced.

Description

Chip packaging structure

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure.

Background

Currently, chip package structures often require multiple sets of power/ground pads to ensure power robustness. For the package form with only a single power pin and a single ground pin, since there is only one access point for external power/ground and internal power/ground of the die, the external power/ground needs to be conducted to the die through the internal metal wire of the die connected with the access point, and the voltage drop (IR drop), electrostatic discharge (ESD), electromagnetic compatibility (EMC) and other performances of the die are greatly affected due to the large resistance of the internal metal wire of the die.

Disclosure of Invention

One of the purposes of the present invention is to provide a chip package structure, which can realize the package form of a single power pin and/or a single ground pin, effectively reduce the impedance of the electric conduction of a bare chip, and improve the voltage drop performance, the electrostatic discharge performance and the electromagnetic compatibility of the bare chip.

In order to achieve the above object, the present invention provides a chip package structure. The chip packaging structure comprises: a die including a first internal wire located inside the die and a plurality of pads located on a surface of the die, the plurality of pads including a first access pad and a plurality of functional pads; the bare chip is provided with a first side and a second side which are adjacent, the first access pad is arranged on the first side, the functional pads are arranged on the first side and the second side, and the first access pad is electrically connected with the functional pads on the first side through the first internal lead; the first pin is positioned on one side of the bare chip and is a power pin or a ground pin; and a plurality of bond wires including a first bond wire electrically connecting the first lead and the first access pad and at least one second bond wire electrically connecting one of the functional pads of the first side and one of the functional pads of the second side traversing over the die.

Optionally, the two functional pads electrically connected by the second bonding wire are further electrically connected by the first internal wire, and a portion of the first internal wire between the two functional pads is connected in parallel with the second bonding wire.

Optionally, each side of the die is provided with at least two functional pads, and the functional pads located on the same side are electrically connected through the first internal wires; for any two adjacent sides of the bare chip, one functional bonding pad of one side corresponds to one functional bonding pad of the other side, and the corresponding two functional bonding pads are electrically connected through one second bonding wire.

Optionally, all the functional pads are disposed above and electrically connected by the first internal conductor.

Optionally, the first internal conductor includes a plurality of portions electrically connected or a plurality of segments disconnected.

Optionally, the first internal wires are distributed in a metal layer within the die; alternatively, the first internal wires are distributed in multiple metal layers within the die, and the first internal wires in multiple metal layers are connected in parallel through vias.

Optionally, the first pin is the power supply pin, and the functional pad is a power supply pad.

Optionally, the chip package structure further includes a second pin located at one side of the die, where the second pin is a ground pin; the die also has a second internal wire located inside the die; the plurality of bonding pads further comprises a second access bonding pad and a plurality of grounding bonding pads, and the plurality of grounding bonding pads comprises a first grounding bonding pad and a second grounding bonding pad; the second access pad and the second pin are electrically connected through a third bonding wire, the second access pad and the first grounding pad are arranged on the same side of the bare chip and are electrically connected through the second internal wire, and the first grounding pad and the second grounding pad are respectively arranged on two adjacent sides of the bare chip and are electrically connected through a fourth bonding wire crossing over the bare chip.

Optionally, the first ground pad and the second ground pad are further electrically connected by a second internal wire, and a portion of the second internal wire between the first ground pad and the second ground pad is connected in parallel with the fourth bonding wire.

Optionally, all the grounding pads are disposed above the second internal wire and electrically connected through the second internal wire; each side edge of the bare chip is provided with at least two grounding pads; for any two adjacent sides of the bare chip, one grounding pad of one side corresponds to one grounding pad of the other side, and the two corresponding grounding pads are electrically connected through one fourth bonding wire.

Optionally, the package structure includes a package frame, the package frame includes a base island and the first pins located on sides of the base island, and the die is mounted on the base island.

Optionally, the first pin and the second pin are disposed near different sides of the die, or the first pin and the second pin are disposed near the same side of the die.

In the chip packaging structure provided by the invention, the first pin is a power pin or a grounding pin, the first side of the bare chip is provided with the first access pad and the functional pad which are electrically connected through the first internal lead, the first pin is electrically connected with the first access pad through the first bonding wire, the second side of the bare chip adjacent to the first side is also provided with the functional pad, and one functional pad of the first side is electrically connected with one functional pad of the second side through the second bonding wire, namely, the functional pad of the adjacent side of the bare chip is electrically connected through the bonding wire crossing over the bare chip. Because the linewidth of the bonding wire is generally larger than that of the wire inside the bare chip, compared with the fact that the functional bonding pads on the adjacent sides are electrically connected only through the metal wire inside the bare chip, the functional bonding pads on the adjacent sides of the bare chip can reduce the impedance of electric conduction through the electric connection of the bonding wire, and then the voltage drop performance, the electrostatic discharge performance and the electromagnetic compatibility of the bare chip can be improved; in addition, because the distance between the functional bonding pads on the adjacent side edges is relatively smaller, the functional bonding pads on the adjacent side edges of the bare chip are electrically connected through bonding wires, the problem of wire collapse of the bonding wires can be avoided, the reliability of the chip packaging structure can be further improved, and the effect on the bare chip with a large area is particularly remarkable.

Further, the two functional pads electrically connected with the second bonding wire are also electrically connected through the first internal lead, and the part of the first internal lead between the two functional pads is connected with the second bonding wire in parallel, so that the impedance of electric conduction can be further reduced.

Drawings

Fig. 1 is a schematic plan view of a chip package structure according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention.

Fig. 4 is a schematic plan view of a chip package structure according to another embodiment of the invention.

Reference numerals illustrate: 10-die; 11-a first side; 12-a second side; 13-a third side; 14-fourth side; 15-a first inner wire; 16-a second inner wire; 17-via holes; 110-a first access pad; 111-a first power supply pad; 112-a second power pad; 113-a third power pad; 114-fourth power pads; 115-fifth power pads; 116-sixth power pads; 117-seventh power pads; 118-eighth power pads; 120-second access pads; 121-a first ground pad; 122-a second ground pad; 123-a third ground pad; 124-fourth ground pads; 125-fifth ground pads; 126-sixth ground pads; 127-seventh ground pad; 128-eighth ground pads; 20-packaging a frame; 21-a first pin; 22-second pins; 23-islands; 301-a first bond wire; 302-one of the second bond wires; 303-second bond wires; 304-third of the second bond wires; 305-fourth of the second bond wires; 306-third bond wire; 307-one of the fourth bond wires; 308-second fourth bond wires; 309-third fourth bond wires; 310-fourth bond wire.

Detailed Description

The chip package structure according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The terms "first," "second," and the like in the description of the present invention, are not used for any order, quantity, or importance, but are used for distinguishing between different components. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper/upper" and/or "lower/lower" and the like are used for convenience of description and are not limited to one position or one spatial orientation.

In order to realize the packaging form of a single power pin and/or a single grounding pin, reduce the impedance of electric conduction and improve the voltage drop performance, the electrostatic discharge performance and the electromagnetic compatibility of a bare chip, the invention provides a chip packaging structure.

Fig. 1 is a schematic plan view of a chip package structure according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention. Referring to fig. 1 and 2, the present embodiment provides a chip package structure including a die 10, a first lead 21, and a plurality of bonding wires.

The die 10 includes a first internal wire 15 located inside the die 10 and a plurality of pads located on the surface of the die 10, the plurality of pads including a first access pad 110 and a plurality of functional pads; the die 10 has adjacent first and second sides 11, 12, a first access pad 110 is disposed on the first side 11, the first and second sides 11, 12 are each provided with a functional pad, and the functional pads of the first access pad 110 and the first side are electrically connected by a first internal wire 15.

The first pin 21 is located on one side of the die 10, and the first pin 21 is a power pin or a ground pin.

The plurality of bonding wires includes a first bonding wire 301 and at least one second bonding wire crossing over the die 10, the first bonding wire 301 electrically connecting the first lead 21 and the first access pad 110, i.e., one end of the first bonding wire 301 is soldered on the first lead 21 and the other end is soldered on the first access pad 110, the second bonding wire electrically connecting one functional pad of the first side 11 and one functional pad of the second side 12.

Specifically, as shown in fig. 2, the chip package structure may include a package frame 20 (lead frame), where the package frame 20 includes a base island (die attached pad) 23 and a first lead 21 located on a side of the base island 23, and the die 10 is mounted on the base island 23.

The material of the first pin 21 is metal, and in a specific embodiment, the material of the first pin 21 may be one or more of W, al, cu, ti, ag, au, pt, ni.

The material of the islands 23 may be the same as or different from the material of the first pins 21. In some embodiments, the material of the islands 23 is a metal or an insulating material, the metal may be one or more of W, al, cu, ti, ag, au, pt, ni, the insulating material may be an inorganic insulating material or an organic insulating material, the inorganic insulating material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, the organic insulating material may be an epoxy resin, a polyimide resin, a benzocyclobutene resin, or a polybenzoxazole resin, or the organic insulating material may also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.

In the present embodiment, the die (die) 10 is a chip particle obtained by dicing a wafer, and has not undergone a packaging process. The die 10 has opposite front and back sides, and the back side of the die 10 may be adhered to the land 23 by an adhesive paste, but is not limited thereto. The front side of die 10 has a plurality of pads. The material of the pad may include copper, nickel, stainless steel, or beryllium copper, but is not limited thereto.

In this embodiment, the chip Package structure may be a QFN (Quad Flat No-packages Package) Package structure, a QFP (Quad Flat Package) Package structure, or an LQFP (Low-profile Quad Flat Package) Package structure.

Illustratively, as shown in fig. 1, the die 10 may be rectangular with a first side 11, a second side 12, and a third side 13 and a fourth side 14 circumscribing the rectangle.

The die 10 may have multiple metal layers inside, such as 4 or 8 layers, etc. The multi-layer metal layer inside the die 10 includes a first internal wire 15. In some embodiments, as shown in fig. 2, the first internal wires 15 may be distributed in a metal layer within the die 10. Fig. 3 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. In some embodiments, as shown in fig. 3, the first internal wires 15 may be distributed in multiple metal layers within the die 10, such as in two metal layers, with the first internal wires 15 in the multiple metal layers being connected and in parallel relationship by vias 17, which helps reduce resistance.

As shown in fig. 1 and 2, the plurality of pads on the front side of the die 10 includes a first access pad 110 and a plurality of functional pads. The first side 11 and the second side 12 of the die are adjacent, the first access pad 110 is disposed on the first side 11 of the die, the first side 11 and the second side 12 are both provided with functional pads, and the first internal wire 15 electrically connects the first access pad 110 and the functional pads of the first side 11.

In this embodiment, the first pins 21 are power pins, and the functional pads are power pads. In other embodiments, the first pin 21 may be a ground pin and the functional pad may be a ground pad. Hereinafter, the first pin 21 is taken as a single power pin, and the functional pad is taken as a power pad.

As shown in fig. 1 and 2, the first side 11 of the die 10 is further provided with a first power supply pad 111, the first access pad 110 is electrically connected to the first power supply pad 111 through a first internal wire 15, and the second side 12 of the die 10 is provided with a second power supply pad 112.

In this embodiment, the bonding wire is, for example, a gold wire, a silver wire, or a copper wire. The wire diameter (line width) of the bond wire may be larger than 10 μm, for example 18 μm.

With continued reference to fig. 1 and 2, the plurality of bond wires includes a first bond wire 301 and at least one second bond wire traversing over the die 10, the first bond wire 301 electrically connecting the first lead 21 and the first access pad 110, one of the second bond wires 302 electrically connecting the first power pad 111 and the second power pad 112.

It should be noted that, the line width of the internal wires of the die is usually smaller than 1 μm or nanoscale, the line width of the internal wires of the die is far smaller than the line width of the bonding wire, and the resistance value of the internal wires of the die with the same length is far greater than the bonding wire. In this embodiment, the first power supply pad 111 and the second power supply pad 112 on adjacent side edges are electrically connected through one of the second bonding wires 302, so that the impedance of electrical conduction can be reduced, and the voltage drop performance, the electrostatic discharge performance and the electromagnetic compatibility of the bare chip 10 can be further improved; in addition, because the distance between the power supply pads on the adjacent side edges is relatively smaller, the power supply pads on the adjacent side edges of the bare chip are connected through bonding wires, so that the problem of wire collapse of the bonding wires can be avoided, the reliability of the chip packaging structure can be improved, and the effect on the bare chip with a large area is particularly remarkable.

Further, although the wider the line width of the bonding wire is, the smaller the resistance thereof is, the more effective the impedance can be reduced, in practical application, the resistance of the bonding wire is far smaller than the resistance of the metal wire inside the bare chip, and under the condition that the conduction resistance reaches the target value, the bonding wire with the minimum line width can be selected, so that the resistance of electric conduction can be greatly reduced, and the packaging cost can be reduced.

In some embodiments, the wire widths of the bond wires and the wire widths of the internal wires may be determined by simulation of the bond wire model and the internal metal wire model, respectively, so that an optimal combination of bond wire widths and internal wire widths may be selected. The bonding wire model can be established through packaging data; the internal metal wire model may be built up from layout (layout) data.

With continued reference to fig. 1 and 2, in the present embodiment, the two functional pads (i.e., the first power pad 111 and the second power pad 112) electrically connected by one of the second bonding wires 302 are also electrically connected by the first internal conductive line 15, and the portion of the first internal conductive line 15 between the first power pad 111 and the second power pad 112 is connected in parallel with one of the second bonding wires 302, which can significantly reduce the impedance of the electrical conduction as compared with the case where the first power pad and the second power pad are electrically connected by only the bonding wires or by only the die internal conductive line.

In the present embodiment, at least two power pads are disposed on each side of the die 10, and the power pads on the same side are electrically connected through the first internal wires, but not limited thereto. In other embodiments, power pads may be provided on portions of adjacent sides of die 10.

In this embodiment, for any two adjacent sides of the die 10, one power supply pad of one side corresponds to one power supply pad of the other side, and the two corresponding power supply pads are electrically connected by a second bonding wire, so that the resistance can be significantly reduced. In other embodiments, only a portion of the power pads on adjacent sides of die 10 are electrically connected by the second bond wire.

In this embodiment, as shown in fig. 2, all power supply pads are disposed above the first internal wire 15 and electrically connected to the first internal wire 15 through the via hole 17.

Illustratively, as shown in fig. 1, the first side 11 of the die is provided with a first power supply pad 111 and an eighth power supply pad 118, and the first power supply pad 111 and the eighth power supply pad 118 may be disposed at both sides of the first access pad 110 and electrically connected to the first access pad 110 through the first internal wire 15; the second side 12 of the die is provided with a second power supply pad 112 and a third power supply pad 113, the second power supply pad 112 and the third power supply pad 113 being electrically connected by a first internal wire 15; the third side 13 of the die is provided with a fourth power supply pad 114 and a fifth power supply pad 115, and the fourth power supply pad 114 and the fifth power supply pad 115 are electrically connected by a first internal wire 15; the fourth side 14 of the die is provided with a sixth power supply pad 116 and a seventh power supply pad 117, and the sixth power supply pad 116 and the seventh power supply pad 117 are electrically connected by the first internal wire 15.

In this embodiment, as shown in fig. 1, the first internal wire 15 may be a plurality of parts electrically connected, and the first internal wire 15 electrically connects the first power supply pad 111 and the second power supply pad 112, the third power supply pad 113 and the fourth power supply pad 114, the fifth power supply pad 115 and the sixth power supply pad 116, and the seventh power supply pad 117 and the eighth power supply pad 118. In other embodiments, the first internal conductive line 15 between the first power supply pad 111 and the second power supply pad 112, between the third power supply pad 113 and the fourth power supply pad 114, between the fifth power supply pad 115 and the sixth power supply pad 116, and between the seventh power supply pad 117 and the eighth power supply pad 118 may be disconnected, i.e., the first internal conductive line 15 may include disconnected segments.

In this embodiment, as shown in fig. 1, the plurality of second bonding wires may further include a second bonding wire 303, a third bonding wire 304, and a fourth bonding wire 305. The second bonding wire 303 may electrically connect the third power supply pad 113 and the fourth power supply pad 114, and a portion of the first internal lead 15 between the third power supply pad 113 and the fourth power supply pad 114 is connected in parallel with the second bonding wire 303. The third of the second bond wires 304 may electrically connect the fifth power pad 115 and the sixth power pad 116, and a portion of the first internal wire 15 between the fifth power pad 115 and the sixth power pad 116 is connected in parallel with the third of the second bond wires 304. The fourth 305 of the second bond wire may electrically connect the seventh power pad 117 and the eighth power pad 118, with a portion of the first internal wire 15 between the seventh power pad 117 and the eighth power pad 118 being in parallel with the fourth 305 of the second bond wire.

In another embodiment of the present application, the chip package structure may have a single power pin and a single ground pin at the same time, and the chip package structure in this case is described below.

Fig. 4 is a schematic plan view of a chip package structure according to another embodiment of the invention. As shown in fig. 4, the chip package structure includes a first pin 21 and a second pin 22 located at the side of the die 10, where the first pin 21 may be a power pin and the second pin 22 may be a ground pin. The electrical connection between the first pin 21 and the first access pad 110 of the die 10 and the electrical connection between the first pin and the plurality of power pads on the surface of the die 10 are as described above, and are not described herein.

As shown in fig. 4, the die 10 may also have a second internal wire 16 located inside the die 10. The plurality of pads on the surface of the die 10 may also include a second access pad 120 and a plurality of ground pads.

The plurality of ground pads includes a first ground pad 121 and a second ground pad 122. The second access pad 120 and the second pin 22 are electrically connected by a third bond wire 306. The second access pad 120 and the first ground pad 121 are disposed on the same side of the die 10, for example, both disposed on the third side 13 of the die, and are electrically connected by the second internal wire 16. The first and second ground pads 121 and 122 are disposed on two adjacent sides of the die 10, respectively, and are electrically connected by one of the fourth bond wires 307 that spans over the die 10.

As shown in fig. 4, the first ground pad 121 and the second ground pad 122 are also electrically connected by the second internal wire 16, and a portion of the second internal wire 16 between the first ground pad 121 and the second ground pad 122 is connected in parallel with one of the fourth bonding wires 307 connecting the first ground pad 121 and the second ground pad 122, so that the resistance can be further reduced.

In this embodiment, all the ground pads may be disposed over the second internal conductor 16 and electrically connected through the second internal conductor 16.

In this embodiment, each side of the die 10 may be provided with at least two ground pads; for any two adjacent sides of the die 10, one ground pad of one side corresponds to one ground pad of the other side, and the corresponding two ground pads are also electrically connected by a fourth bond wire, but is not limited thereto.

As illustrated in fig. 4, the third side 13 of the die is provided with a first ground pad 121 and an eighth ground pad 128, and the first ground pad 121 and the eighth ground pad 128 may be disposed at both sides of the second access pad 120 and electrically connected to the second access pad 120 through the second internal wire 16; the second side 12 of the die 10 is provided with a second ground pad 122 and a third ground pad 123, the second ground pad 122 and the third ground pad 123 being electrically connected by the second internal wire 16; the first side 11 of the die is provided with fourth and fifth ground pads 124, 125, and the fourth and fifth ground pads 124, 125 are electrically connected by the second internal wire 16; the fourth side 14 of the die is provided with sixth and seventh ground pads 126, 127, and the sixth and seventh ground pads 126, 127 are electrically connected by the second internal wires 16.

As shown in fig. 4, the second internal lead 16 may be a plurality of parts electrically connected, and the second internal lead 16 may also electrically connect the first and second ground pads 121 and 122, the third and fourth ground pads 123 and 124, the fifth and sixth ground pads 125 and 126, and the seventh and eighth ground pads 127 and 128. In other embodiments, the second inner wire 16 between the first ground pad 121 and the second ground pad 122, between the third ground pad 123 and the fourth ground pad 124, between the fifth ground pad 125 and the sixth ground pad 126, and between the seventh ground pad 127 and the eighth ground pad 128 may be disconnected, i.e., the second inner wire 16 includes disconnected segments.

As shown in fig. 4, the plurality of fourth bonding wires may further include a second 308 of the fourth bonding wires, a third 309 of the fourth bonding wires, and a fourth 310 of the fourth bonding wires. The second 308 of the fourth bond wires may electrically connect the third ground pad 123 and the fourth ground pad 124, and a portion of the second internal lead 16 between the third ground pad 123 and the fourth ground pad 124 is connected in parallel with the second 308 of the fourth bond wires. The third 309 of fourth bond wires may electrically connect the fifth ground pad 125 and the sixth ground pad 126, with a portion of the second inner wire 16 between the fifth ground pad 125 and the sixth ground pad 126 being in parallel with the third 309 of fourth bond wires. The fourth wire bond 310 may electrically connect the seventh ground pad 127 and the eighth ground pad 128, and a portion of the second internal lead 16 between the seventh ground pad 127 and the eighth ground pad 128 may be connected in parallel with the fourth wire bond 310.

As shown in fig. 4, in the present embodiment, the first pins 21 and the second pins 22 are disposed near different sides of the die 10. In other embodiments, the first pin 21 and the second pin 22 may be disposed near the same side of the die 10. The plurality of ground pads are disposed at the periphery of the plurality of power pads, or the plurality of power pads are disposed at the periphery of the plurality of ground pads, but is not limited thereto.

In the chip package structure provided by the invention, the first pin 21 is a power pin or a ground pin, the first side 11 of the bare chip 10 is provided with a first access pad 110 and a functional pad which are electrically connected through a first internal wire 15, the first pin 21 is electrically connected with the first access pad 110 through a first bonding wire 301, the second side 12 of the bare chip 10 adjacent to the first side 11 is also provided with a functional pad, and one functional pad of the first side 11 is electrically connected with one functional pad of the second side 12 through a bonding wire crossing over the bare chip 10, namely, the functional pad of the adjacent side of the bare chip 10 is electrically connected through a second bonding wire crossing over the bare chip 10. Because the linewidth of the bonding wire is generally larger than that of the wire inside the bare chip, compared with the fact that the functional pads on the adjacent sides are electrically connected only through the metal wire inside the bare chip, the functional pads on the adjacent sides of the bare chip 10 are electrically connected through the second bonding wire, so that the impedance of electric conduction can be reduced, and the voltage drop performance, the electrostatic discharge performance and the electromagnetic compatibility of the bare chip 10 can be improved; in addition, because the distance between the functional pads on the adjacent sides is relatively smaller, the functional pads on the adjacent sides of the bare chip 10 are electrically connected through bonding wires, the problem of wire collapse of the bonding wires can be avoided, the reliability of the chip packaging structure can be improved, and the effect on the bare chip with a large area is particularly obvious.

Further, the two functional pads electrically connected to the second bonding wire are also electrically connected through the first internal lead 15, and the portion of the first internal lead 15 between the two functional pads is connected in parallel to the second bonding wire, so that the impedance of electrical conduction can be further reduced.

It should be noted that, in the present description, the differences between the parts described in the following description and the parts described in the previous description are emphasized, and the same or similar parts are referred to each other.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims

1. A chip package structure, characterized in that the chip package structure comprises:

a die including a first internal wire located inside the die and a plurality of pads located on a surface of the die, the plurality of pads including a first access pad and a plurality of functional pads; the bare chip is provided with a first side and a second side which are adjacent, the first access pad is arranged on the first side, the functional pads are arranged on the first side and the second side, and the first access pad is electrically connected with the functional pads on the first side through the first internal lead;

the first pin is positioned on one side of the bare chip and is a power pin or a ground pin; and

a plurality of bond wires including a first bond wire electrically connecting the first lead and the first access pad and at least one second bond wire electrically connecting one of the functional pads of the first side and one of the functional pads of the second side traversing over the die.

2. The chip package structure of claim 1, wherein two of the functional pads electrically connected by the second bond wire are further electrically connected by the first internal wire, a portion of the first internal wire between the two functional pads being in parallel with the second bond wire.

3. The chip package structure of claim 1, wherein each side of the die is provided with at least two functional pads, and the functional pads on the same side are electrically connected by the first internal wires; for any two adjacent sides of the bare chip, one functional bonding pad of one side corresponds to one functional bonding pad of the other side, and the corresponding two functional bonding pads are electrically connected through one second bonding wire.

4. The chip package structure of claim 3, wherein all of the functional pads are disposed over and electrically connected by the first internal leads.

5. The chip package structure of claim 1, wherein the first internal conductor includes a plurality of portions electrically connected or a plurality of segments disconnected.

6. The chip package structure of claim 1, wherein the first internal wires are distributed in a metal layer within the die; alternatively, the first internal wires are distributed in multiple metal layers within the die, and the first internal wires in multiple metal layers are connected in parallel through vias.

7. The chip package structure of claim 1, wherein the first pin is the power pin and the functional pad is a power pad.

8. The chip package structure of claim 7, further comprising a second pin on a side of the die, the second pin being a ground pin;

the die also has a second internal wire located inside the die;

the plurality of bonding pads further comprises a second access bonding pad and a plurality of grounding bonding pads, and the plurality of grounding bonding pads comprises a first grounding bonding pad and a second grounding bonding pad; the second access pad and the second pin are electrically connected through a third bonding wire, the second access pad and the first grounding pad are arranged on the same side of the bare chip and are electrically connected through the second internal wire, and the first grounding pad and the second grounding pad are respectively arranged on two adjacent sides of the bare chip and are electrically connected through a fourth bonding wire crossing over the bare chip.

9. The chip package structure of claim 8, wherein the first ground pad and the second ground pad are further electrically connected by a second internal wire, a portion of the second internal wire between the first ground pad and the second ground pad being in parallel with the fourth bond wire.

10. The chip package structure of claim 8, wherein all of the ground pads are disposed over and electrically connected by the second internal leads; each side edge of the bare chip is provided with at least two grounding pads; for any two adjacent sides of the bare chip, one grounding pad of one side corresponds to one grounding pad of the other side, and the two corresponding grounding pads are electrically connected through one fourth bonding wire.

11. The chip package structure of claim 1, wherein the package structure comprises a package frame including a base island and the first leads located on sides of the base island, the die being mounted on the base island.

12. The chip package structure of claim 8, wherein the first pin and the second pin are disposed proximate different sides of the die or the first pin and the second pin are disposed proximate the same side of the die.