JP3324571B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a ball grid array type semiconductor device (hereinafter referred to as "BGA type semiconductor device") in which a semiconductor element, a lead frame and a TAB tape are combined and sealed with a resin to provide external terminals. ).

[0002]

2. Description of the Related Art In recent years, high integration and miniaturization of semiconductor devices,
Along with this, the pitch has been reduced, and the semiconductor package on which it is mounted has also been reduced in size and pitch.

As a semiconductor package, a QFP type package is currently mainstream, but a ball grid array (BGA) package which can be made smaller than that is beginning to flow on the market. Then, the ball grid array (B
A semiconductor device using a GA) package is called a BGA type semiconductor device.

[0004] As a BGA type semiconductor device, there is a molded BGA type semiconductor device (hereinafter referred to as a molded BGA) in which a semiconductor element and a lead frame are combined, resin-sealed, and external terminals are provided.

A conventional mold BGA (conventional example 1) will be described with reference to a schematic sectional view of the structure of the mold BGA in FIG.
As shown in FIG. 5, this mold BGA uses a lead frame 2, a semiconductor element 1 is mounted on a lead 3 of the lead frame 2 via an insulating film 21, and a bonding pad (not shown) of the semiconductor element 1 is provided. ) And the lead 3 of the lead frame 2 are connected by a bonding wire 22 which is a thin metal wire, and sealed so as to cover the semiconductor element 1, the bonding wire 22 and the lead frame 2 excluding the mounting portion (land) of the external terminal. It has a solder ball 8 which is an external terminal provided in a lattice on a mounting portion (land) of the lead 3 of the lead frame 2 and sealed with a resin 7.

There is a conventional mold BGA having a LOC structure (conventional example 2), which will be described with reference to a schematic sectional view of the structure of a mold BGA having a LOC structure in FIG. As shown in FIG. 6, a lead frame 2 is used in the mold BGA. The leads 3 of the lead frame 2 are adhered on the semiconductor element 1 via an insulating tape 23, and bonding pads (not shown) of the semiconductor element 1 are formed. ) And the lead 3 of the lead frame 2 are connected by a bonding wire 22 which is a thin metal wire, and sealed so as to cover the semiconductor element 1, the bonding wire 22 and the lead frame 2 excluding the mounting portion (land) of the external terminal. Lead frame 2 sealed with resin 7
And solder balls 8 as external terminals provided in a grid on the mounting portion (land) of the lead 3.

In addition, there is a tape BGA type semiconductor device (hereinafter referred to as a tape BGA) in which a semiconductor element and a TAB tape are combined and sealed with resin to provide external terminals.

FIG. 7 shows a conventional tape BGA (conventional example 3).
A schematic sectional view of the structure of the tape BGA of FIG. FIG.
As shown in FIG. 2, a TAB tape 4 is used for the tape BGA, and a metal reinforcing plate (stiffener) 24 for preventing warpage of the TAB tape 4 is adhered to the TAB tape 4. 1 is connected to one end of the TAB wiring 6 of the TAB tape 4 by a bonding pad (not shown), and the connection surface (front surface) of the semiconductor element 1 with the TAB wiring 6 and the connection part of the TAB wiring 6 with the semiconductor element 1 And a solder ball 8 which is an external terminal provided in a grid on the mounting portion (land) of the TAB tape 4 so as to cover the solder ball 8.

[0009]

In the above-described conventional mold BGA (both conventional examples 1 and 2), wiring is performed by leading the leads 3 of the lead frame 2, so that the degree of integration of the semiconductor element 1 is increased and the number of pins is increased. Even if the number of external terminals increases), there is a limit in increasing the number of external terminals of the mold BGA, and there is a problem that it is difficult to cope with the increase.

This is because the number of leads 3 of the lead frame 2 must be increased in order to increase the number of external terminals of the mold BGA. For this purpose, the thickness of the lead frame 2 must be reduced, but the thickness of the lead frame 2 is limited to 0.125 mm to 0.100 mm. This limit exists regardless of the etching lead frame and the stamping (press) lead frame. If the thickness of the lead frame 2 is further reduced, the leads 3 of the lead frame 2 are deformed and cannot be used in terms of strength. Then, the number of leads 3 is determined by the lead 3 depending on the thickness of the lead frame 2, and there is a limit to increasing the number of leads 3, that is, the number of external terminals. For example, in the case of the plate thickness of the lead frame 2, when the pitch (interval) of the land, which is the mounting portion of the external terminal of the lead 3 of the lead frame 2, is 0.8 mm (when it is narrow), the lead 3 of the lead frame 2 is not formed. Landing of the land-
The limit is two wires between lands. In this case, for example, a mold BGA having a size of 7 mm × 11 mm (width × length) is used.
Are 60 maximum external terminals.

In the above-described conventional mold BGA (both conventional examples 1 and 2), the bonding pads of the semiconductor element 1 and the leads 3 of the lead frame 2 are connected by bonding wires 22. Varies in height. For example, when the bonding wire 22 is a φ30 μm gold wire, a variation of ± 50 μm occurs. Therefore, when the height of the bonding wire 22 increases, the bonding wire 22
There is a problem that it is exposed on the surface of the package (that is, the package). Particularly, the mold BGA having the LOC structure of the conventional example 2
Then, the thickness of the sealing resin 7 above the lead frame 3 is thin,
This problem is likely to occur.

Further, since the bonding pads of the semiconductor element 1 and the leads 3 of the lead frame 2 are connected by the bonding wires 22, the bonding pads of the semiconductor element 1 and the leads 3 of the lead frame 2 are crossed and connected. There is a problem that cannot be done. This is because, when the bonding pads of the semiconductor element 1 and the leads 3 of the lead frame 2 are connected to each other with the bonding wires 22 intersecting, the intersecting bonding wires 22 are short-circuited. Alternatively, even if there is no short circuit at the time of connection, the bonding wire 22 crossed by the sealing resin 7 injected into the sealing mold is deformed and short-circuited when sealing with the sealing resin 7 after connection. It is.
For example, when the bonding wire 22 is a φ30 μm gold wire, the distance between the intersecting bonding wires 22 is 30 μm.
If it is less than m, it will be short-circuited.

On the other hand, the above-described conventional tape BGA (conventional example 3) only covers the connection surface (surface) of the semiconductor element 1 with the TAB wiring 6 and the connection portion of the TAB wiring 6 with the semiconductor element 1. The back surface and the like of the semiconductor element 1 are not sealed with the sealing resin 24 and are sealed (covered) with the sealing resin 24.
Not in. Therefore, transfer molding such as a mold BGA or QFP is performed, and the reliability such as moisture resistance is lower than that of a package in which the entire surface of the semiconductor element 1 (that is, the entire package) is sealed (covered) with the sealing resin 7. There is a problem.

Accordingly, it is an object of the present invention to cope with the increase in the number of pins due to the high integration of the semiconductor element (multiple external terminals) and the bonding wire (the connecting member between the bonding pad of the semiconductor element and the lead of the lead frame). Is to provide a mold BGA that can prevent the resin from being exposed to the surface of the sealing resin (package).

Another object of the present invention is to provide a mold BGA which can connect a bonding pad of a semiconductor element and a lead of a lead frame crossing each other. Still another object of the present invention is to seal (cover) the entire surface of the semiconductor element with a sealing resin even using a TAB tape.
An object of the present invention is to provide a highly reliable mold BGA.

[0016]

SUMMARY OF THE INVENTION A feature of the present invention is that a lead is provided.
Semiconductor device via TAB tape on frame lead
Is mounted, and one end of the TAB wiring of the TAB tape is
The other end connected to the bonding pad of the semiconductor element
Is connected to the lead, the whole of the semiconductor element, the
The entire TAB tape and the leads are sealed with a sealing resin.
External terminals connected to the land portions of the leads are sealed.
The semiconductor device protrudes from the sealing resin. Departure
Another feature of the light source is the semiconductor element between the leads of the leadframe.
Is provided, and one end of the TAB wiring of the TAB tape is in front.
The other end is connected to the bonding pad of the semiconductor element.
Connected to the lead, the entirety of the semiconductor element, the T
The entire TAB tape excluding the AB tape land
And the leads are sealed with a sealing resin, and the TAB
External terminals connected to the lands of the
In a protruding semiconductor device. Another feature of the invention is that
Semi-conductive on the lead of the lead frame via TAB tape
Body element is mounted, and one of the TAB wires of the TAB tape is mounted.
An end side is connected to a bonding pad of the semiconductor element.
The other end is connected to the semiconductor element side of the lead.
Test TAB tape with electrical property test pads
Is connected to the opposite side of the lead from the semiconductor element side.
And the entirety of the semiconductor element and the entirety of the TAB tape.
The body and the leads are sealed with a sealing resin.
External terminals connected to the land of the
Projecting, the test TAB tape is larger than the sealing resin.
The electrical property test pad protrudes from the outside of the sealing resin.
Side of the semiconductor device. Or of the present invention
Another feature is that the semiconductor element is placed between the leads of the lead frame.
Provided between the lead frame and the semiconductor element.
A first TAB tape having a first TAB wiring
A second TAB tape having a second TAB wiring is provided.
And one end of the first TAB wiring is connected to the semiconductor element.
A second TAB wiring connected to a bonding pad;
Is connected to the lead, and the first and second
Are connected to each other at the other end of the TAB wiring of
Child, the first TAB tape, the second
Of the second TAB tape except for the land portion of the TAB tape
The whole and the leads are sealed with a sealing resin, and the
External terminal connected to the land of TAB tape No. 2
The semiconductor device protrudes from the sealing resin. This place
If the second TAB wiring of the second TAB tape is a single layer
Structure can be. Alternatively, the second TAB
The second TAB wiring on the tape can be a multilayer structure
You.

[0017]

[0018]

[0019]

Further, the external terminals are solder balls.

The lands are provided with leads or TABs.
Part of a line.

[0022]

According to the present invention, the wiring is not conducted by the lead of the lead frame but by the patterned metal wiring (TAB wiring). It can be narrowed, and the maximum number of external terminals of the semiconductor device (mold BGA) can be increased.

Also, since a TAB tape is used instead of a bonding wire as a connecting member between the bonding pad of the semiconductor element and the lead of the lead frame, there is almost no variation in the height of the connecting member.

Also, since the metal wiring (TAB wiring) of the TAB tape may be multi-layered and may cross, the bonding pads of the semiconductor element and the leads of the lead frame can be crossed and connected.

Further, even if a TAB tape is used, the entire surface of the semiconductor element (ie, the entire package) is sealed and covered with a sealing resin.

Further, when conducting the electrical characteristic test, the contact pins of the IC socket of the electrical characteristic test device come into contact with the electrical characteristic test pad portion of the TAB tape which protrudes outside the package of the semiconductor device (mold BGA), and A characteristic test is performed, and no contact is made with a solder ball that is an external terminal of the semiconductor device (mold BGA).

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
It is an outline sectional view showing the structure of an embodiment.

As shown in FIG. 1, the mold BGA of this embodiment uses a lead frame 2 and a TAB wiring 6 patterned on a TAB base film 5 which is an insulator instead of a bonding wire. The bonded TAB tape 4 is used. TAB tape 4
Is formed by bonding a TAB wiring 6 which is a patterned copper wiring on a TAB base film 5 which is a polyimide, for example. The semiconductor element 1 is ILB-connected to one end of the TAB wiring 6 of the TAB tape 4 by a bonding pad (not shown) of the semiconductor element 1, and the TAB connected to the ILB is connected.
The other end of the TAB wiring 6 of the tape 4 is OLB connected on the lead 3 of the lead frame 2, and the TAB base film 5 of the TAB tape 4 is interposed between the TAB wiring 6 and the semiconductor element 1. A semiconductor device 1, a TAB tape 4, and a lead frame 2 excluding mounting portions (lands) of external terminals are covered with a sealing resin 7 by a transfer molding method using a sealing mold (not shown). And a solder ball 8 which is an external terminal provided in a grid on the mounting portion (land) of the lead 3 of the lead frame 2.

Here, in the mold BGA, the wiring is not conducted by the leads 3 of the lead frame 2 but by the patterned TAB wiring 6. Therefore, the wiring width can be reduced, and the number of external terminals provided on the mounting portion (land) of the lead 3 of the lead frame 2 can be increased (increased). For example, the wiring width can be reduced from 100 μm (for the lead 3) to 35 μm (for the TAB wiring 6). And, for example, a size of 7 mm
The maximum number of external terminals of the molded BGA of this embodiment of × 11 mm is 90.

A connecting member between the bonding pad of the semiconductor element 1 and the lead 3 of the lead frame 2 is a TA.
Since the B tape 4 is used, there is almost no variation in the height of the connecting members. The variation in the height (thickness) of the TAB tape 4 is, for example, ± 10 μm.

Further, even when the TAB tape 4 is used, the entire surface of the semiconductor element 1 (that is, the entire package) is sealed and covered with the sealing resin 7.

FIG. 2 is a schematic sectional view showing the structure of the second embodiment of the present invention. As shown in FIG. 2, the mold BGA of this embodiment is different from the first embodiment shown in FIG. 1 in that the other end of the TAB wiring 6 of the TAB tape 4 is connected to the bonding pad of the semiconductor device 1 at one end by ILB. OLB connection is performed on the upper surface of the lead 3 of the frame 2, and the solder ball 8, which is an external terminal after resin sealing, is
The semiconductor device 1 has one end connected to the bonding pad of the semiconductor device 1 in a grid pattern on the mounting portion (land) on the lower surface of the semiconductor device 1.
The other end of the TAB wire 6 of the LB-connected TAB tape 4 is OLB-connected to the lower surface of the lead 3 of the lead frame 2,
Solder balls 8 which are external terminals after resin sealing are provided in a grid on a mounting portion (land) on the lower surface of the TAB wiring 6 of the TAB tape 4. Here, the mounting portion (land) provided on the lower surface of the TAB wiring 6 of the TAB tape 4 is a part of the TAB wiring 6 which is a copper wiring, and has a size of, for example, φ0.3 mm.

Here, in the mold BGA, the wiring routing is not performed by the leads 3 of the lead frame 2 but by the patterned TAB wiring 6, so that the wiring width can be reduced. . Since the solder balls 8 as the external terminals are provided in a grid on the mounting portion (land) of the TAB wiring 6 of the TAB tape 4, the number of external terminals provided can be increased (increased). For example, a mold B of this embodiment having a size of 7 mm × 11 mm
The maximum number of external terminals of the GA is 120.

A connecting member between the bonding pad of the semiconductor element 1 and the lead 3 of the lead frame 2 is a TA.
Since the B tape 4 is used, there is almost no variation in the height of the connecting members.

Further, even when the TAB tape 4 is used, the entire surface of the semiconductor element 1 (that is, the entire package) is covered with the sealing resin 7.

FIGS. 3A and 3B are a schematic sectional view and a schematic bottom view showing the structure of the third embodiment of the present invention. As shown in FIGS. 3A and 3B, the mold BGA of the present embodiment has a TAB wiring patterned on a TAB base film 5 which is an insulator of the first embodiment shown in FIG. (One kind) TAB with 6 bonded
The tape 4 is used, and the semiconductor element 1 is connected to the bonding pad (not shown) of the semiconductor element 1 by the TAB tape 4.
ILB is connected to one end of the B wiring 6, and T
The other end of the TAB wiring 6 of the AB tape 4 is the lead frame 2
OLB connection on lead 3 of TAB tape 4
A sealing die is provided so that the B base film 5 is interposed between the TAB wiring 6 and the semiconductor element 1, and covers the semiconductor element 1, the TAB tape 4, and the lead frame 2 excluding the mounting portion (land) of the external terminal. (Not shown), which is sealed with a sealing resin 7 by a transfer molding method, whereas a TAB base which is an insulator for connecting the semiconductor element 1 and the lead frame 2 similar to the first embodiment. A TAB tape 4a having a TAB wiring 6a patterned on a film 5a adhered thereto and a TAB wiring 6b patterned on a TAB base film 5b which is an insulator and provided with a pad portion 9 for an electrical property test on an outer peripheral portion. Two types of TAB tapes 4 are used, ie, a bonded TAB tape 4b.

Here, the TAB wiring 6 of the TAB tape 4b
b is a part of the TAB wiring 6b which is a copper wiring, is provided on the TAB base film 5b, and has a size of, for example, φ0.35 mm and a pad pitch (p) of 0. 0.5 mm. Note that the arrangement of the electrical characteristic test pad sections 9 may be a staggered arrangement as shown in FIG. 3B or a single-row arrangement (not shown).

Then, as in the first embodiment, the semiconductor element 1 is ILB-connected to one end of the TAB wiring 6a of the TAB tape 4a by the bonding pad of the semiconductor element 1, and ILB is connected.
The other end of the TAB wiring 6a of the connected TAB tape 4a is OLB connected inside the lead 3 of the lead frame 2 and the TAB base film 5a of the TAB tape 4a is
Between the AB wiring 6a and the semiconductor element 1;
The TAB of the TAB tape 4b is arranged such that the electrical property test pad 9 provided on the outer periphery of the TAB wiring 6b of the AB tape 4b protrudes from the lead 3 of the lead frame 2 to the outside.
One end of the B wiring 6 b is OLB connected outside the lead 3 of the lead frame 2. Then, the semiconductor element 1, the TAB tape 4a, and the TAB tape 4b provided on the outer peripheral portion of the TAB wiring 6b except for the electrical property test pad 9 and the lead frame 2 excluding the mounting portion (land) of the external terminal are covered. As described above, the semiconductor device is sealed with the sealing resin 7 by the transfer molding method using a sealing mold. Then, solder balls 8 as external terminals are provided on the mounting portions (lands) of the leads 3 of the lead frame 2.
Are provided in a lattice shape.

Here, this mold BGA is used by an electric characteristic tester I
A contact pin (not shown) of the C socket comes into contact with the electrical property test pad 9 of the TAB tape 4b protruding outside the package, and an electrical property test is performed. After completion of the electrical property test, the electrical property test pad portion 9 of the TAB tape 4b protruding outside the package is completely cut by a cutting die (not shown). In the conventional mold BGA and tape BGA and the mold BGA of the first and second embodiments, the I
The contact pins of the C socket make contact with the solder balls 8 which are external terminals of the package.

In this embodiment, the TAB tape 4 is used to connect the semiconductor element 1 to the lead frame 2.
An AB tape 4a and a TAB tape 4b provided with an electrical property test pad 9 are used. However, the present invention is not limited to this. The TAB tape 4 is composed of the semiconductor element 1 and the lead frame 2. Wiring 6a that connects
May be formed, the TAB wiring 6a may be extended in the outer peripheral direction, and the electrical characteristic test pad 9 may be provided (integrated). In this case, the OLB connection of the TAB wiring 6a of the TAB tape 4 on the lead 3 of the lead frame 2 may be performed only once.

FIGS. 4 (a) and 4 (b) are a schematic sectional view and a schematic bottom view showing the structure of the fourth embodiment of the present invention, and FIG. 4 (c) is the book of FIG. 4 (a). It is a schematic sectional view showing the detail of the structure of a part (TAB wiring) of a 4th embodiment of the present invention. As shown in FIGS. 4A and 4B,
In the mold BGA of this embodiment, the TAB wiring 6 patterned on a TAB base film 5 which is an insulator in the second embodiment shown in FIG.
B tape 4 is used, and one end of the TAB tape 4 is connected to the bonding pad of the semiconductor device 1 by ILB.
The other end of the wiring 6 is connected to the lower surface of the lead 3 of the lead frame 2 by O.
LB connection, solder ball 8 which is an external terminal after resin sealing
Are provided in a grid on the mounting portion (land) on the lower surface of the TAB wiring 6 of the TAB tape 4, whereas the semiconductor device 1
TAB tape which is patterned on a TAB base film 5c which is an insulator and has a TAB wiring joint 11c which is a joint with another TAB tape 4d and which is bonded to the bonding pad 10 by ILB to the bonding pad 10 4c, a solder ball 8 as an external terminal is provided, and the OLB connection to the lead 3 of the lead frame 2 is made on a TAB base film 5d as an insulator. ) 12 and other T
TAB wiring joint 11 which is a joint with AB tape 4c
In this example, two types of TAB tapes 4 are used, which are divided from a TAB tape 4d to which a TAB wiring 6d having a d is attached.

Here, the TAB wiring 6 of the TAB tape 4c
The TAB wiring junction 11c of c is a part of the TAB wiring 6c which is a copper wiring, and the TAB wiring 6d of the TAB tape 4d.
TAB wiring 6 is also a copper wiring.
part of d. And the size of the joint is □ 50μm
It is about.

Further, the TAB tape 4d is shown in FIG.
As shown in (a), one or more TAB wirings 6d may be provided.
As shown in FIG. 4C, the TAB wiring 6d may be a multilayer (here, two layers). In this case, the TAB interlayer film 13 which is an insulator is provided between the two layers of the TAB wiring 6d, and the upper and lower TAB wirings 6d are connected to the TAB interlayer film 13d.
Are connected via a through-hole 14 provided at the end. In this case, the upper TAB wiring 6d has a TAB wiring joint 11d, and the lower TAB wiring 6d has a mounting portion (land) 12 for an external terminal. Further, the upper and lower TAB wirings 6 d are interposed via the TAB interlayer film 13.
It may be crossed (as viewed from above). First, the TAB wiring joint 11c of the TAB wiring 6c of the TAB tape 4c and the TA of the TAB wiring 6d of the TAB tape 4d.
The B wiring bonding portion 11d is overlapped and bonded by OLB technology.

The semiconductor element 1 is connected to the bonding pad 10 of the semiconductor element 1 by the TAB wiring 6 of the TAB tape 4c.
TAB wiring 6 of a TAB tape 4d that is connected to one end of the TAB tape 4c by ILB connection to one end of the TAB tape 4c connected to the ILB connection
The other end of “d” is OLB at the lower surface of the lead 3 of the lead frame 2.
Connected, TAB base film 5 of TAB tape 4c
c is interposed between the TAB wiring 6c and the semiconductor element 1. Then, a sealing resin is formed by a transfer molding method using a sealing mold so as to cover the joined TAB tape 4c and TAB tape 4d except for the mounting portion (land) 12 of the external terminal and the external terminal and the lead frame 2. Sealed at 7.
A solder ball 8 as an external terminal is mounted on a mounting portion (land) 12 of the TAB wiring 6d of the TAB tape 4d.

Here, in this mold BGA, the TAB wiring 6d of the TAB tape 4d may be a single layer or a multi-layer and may intersect. Therefore, the bonding pads 10 of the semiconductor element 1 and the leads 3 of the lead frame 2 are connected. Can be crossed and connected. And by this,
The TAB tapes 4c and T correspond to various types (each semiconductor element 1) using the same lead frame 2 for multiple types of semiconductor devices of the same external package having the same number of external terminals and terminal positions.
This can be performed with the AB tape 4d.

[0047]

As described above, according to the present invention, since the wiring is not routed by the lead of the lead frame but by the patterned TAB wiring, the wiring width is reduced. Can be reduced, the maximum number of external terminals of the mold BGA can be increased, and the effect of increasing the number of pins due to the higher integration of semiconductor elements (multiple external terminals) can be obtained. Specifically, for example, a size of 7 mm
The maximum number of external terminals of the molded BGA of 11 mm increases from 90 in the related art to 90 in the first embodiment and to 120 in the second embodiment.

Further, since a TAB tape is used instead of a bonding wire as a connecting member between the bonding pad of the semiconductor element and the lead of the lead frame, there is almost no variation in the height of the connecting member, and the connecting member of the molded BGA is sealed. The effect that exposure to the surface of the resin (package) can be prevented can also be obtained. Specifically, the variation in the height of the conventional bonding wire is, for example, ± 50 μm.
The variation in the height (thickness) of the TAB tape of the present embodiment is, for example, ± 10 μm.

Further, since the TAB wiring of the TAB tape may be a single layer or a multi-layer and may be crossed, the bonding pads of the semiconductor element and the leads of the lead frame can be crossed and connected. As a result, there is also obtained an effect that a variety of molded BGAs of the same external package having the same number of external terminals and the same terminal positions can be made to correspond to each type (each semiconductor element) using the same lead frame with a TAB tape. Can be (Fourth Embodiment) In addition, even if a TAB tape is used, the entire surface of the semiconductor element (that is, the entire package) is sealed and covered with a sealing resin, so that the effect of improving the reliability of the mold BGA can be obtained.

Further, when conducting the electric characteristic test, the contact pin of the IC socket of the electric characteristic test device comes into contact with the electric characteristic test pad portion of the TAB tape protruding outside the package of the molded BGA, and the electric characteristic test is performed. Since it does not come into contact with the solder balls which are the external terminals of the mold BGA, the conventional mold BGA or tape BG
An effect is also obtained in that a problem (such as short-circuiting of the solder ball) at the time of mounting on the mounting board due to the contact pin contacting the solder ball as in A or the like and the solder ball being damaged or deformed can be prevented. (Third embodiment)

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a structure according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a structure of a second embodiment of the present invention.

FIG. 3 is a schematic sectional view and a schematic bottom view showing a structure of a third embodiment of the present invention.

FIG. 4 is a schematic sectional view and a schematic bottom view showing the structure of a fourth embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view illustrating a conventional technique.

FIG. 6 is a schematic sectional view illustrating another conventional technique.

FIG. 7 is a schematic sectional view illustrating still another conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Lead frame 3 Lead 4, 4a, 4b, 4c, 4d TAB tape 5, 5a, 5b, 5c, 5d TAB base film 6, 6a, 6b, 6c, 6d TAB wiring 7, 25 Sealing resin 8 Solder Ball 9 Pad part for electrical property test 10 Bonding pad 11c, 11d TAB wiring joint part 12 Mounting part (land) 13 TAB interlayer film 14 Through hole 21 Insulating film 22 Bonding wire 23 Insulating tape 24 Reinforcing plate (Stiffener)

Claims (8)

(57) [Claims] 1. A TAB tape on a lead of a lead frame.
The semiconductor element is mounted via the tape and the TAB tape
One end of the TAB wiring is a bonding path of the semiconductor element.
And the other end is connected to the lead,
The entirety of the conductor element, the entirety of the TAB tape, and the
The lead is sealed with a sealing resin, and
A semiconductor device, wherein a connected external terminal protrudes from the sealing resin . 2. A semiconductor device between leads of a lead frame.
Is provided, and one end of the TAB wiring of the TAB tape is
Connected to the bonding pad of the semiconductor element and the other end is forward
And the entirety of the semiconductor element, the TA
The entire TAB tape except for the land of the B tape, and
The lead is sealed with a sealing resin, and the TAB tape is
External terminals connected to the land portions of the
A semiconductor device, which is provided. 3. A TAB tape on a lead of a lead frame.
The semiconductor element is mounted via the tape and the TAB tape
One end of the TAB wiring is a bonding path of the semiconductor element.
And the other end side is the semiconductor element side of the lead.
Test with electrical property test pads connected to
TAB tape is opposite to the semiconductor element side of the lead.
Connected to the opposite side, the entirety of the semiconductor element, the T
Seal the entire AB tape and the leads with a sealing resin
And the external terminal connected to the land of the lead is
The test TAB tape projects from the sealing resin
The electrical property test pad protrudes beyond the sealing resin and is
A semiconductor device, which is located outside the sealing resin . 4. A semiconductor device between leads of a lead frame.
Is provided, and the lead frame and the semiconductor element
A first TAB tape having a first TAB wiring therebetween;
And a second TAB tape having a second TAB wiring is provided.
And one end of the first TAB wiring is the semiconductor element.
Of the second TAB line.
One end of a wire is connected to the lead, and the first and
2 are connected to each other at the other end of the TAB wiring,
The entire element, the entire first TAB tape, the second
The second TAB tape excluding the land of the TAB tape
And the leads are sealed with a sealing resin.
The external terminal connected to the land of the second TAB tape is
A semiconductor device protruding from the sealing resin . 5. A second TAB of the second TAB tape
The semiconductor device according to claim 4, wherein the wiring has a single-layer structure . 6. The second TAB of the second TAB tape
The semiconductor device according to claim 4, wherein the wiring has a multilayer structure . 7. The method according to claim 7, wherein said external terminals are solder balls.
The semiconductor device according to any one of claims 1 to 6, characterized in that: 8. The land portion may be the lead or the land.
4. A part of a TAB wiring, wherein:
The semiconductor device according to claim 6 .