CN117476581A - Power semiconductor device based on general assembly structure - Google Patents
Power semiconductor device based on general assembly structure Download PDFInfo
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- CN117476581A CN117476581A CN202311812508.7A CN202311812508A CN117476581A CN 117476581 A CN117476581 A CN 117476581A CN 202311812508 A CN202311812508 A CN 202311812508A CN 117476581 A CN117476581 A CN 117476581A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000003071 parasitic effect Effects 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 7
- 238000005476 soldering Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Power Conversion In General (AREA)
Abstract
The application provides a power semiconductor device based on general assembly structure, includes: a substrate; a first buffer layer disposed on one side of the substrate; the middle layer is arranged on one side of the first buffer layer, which faces away from the substrate; the conductive layer is arranged on one side of the middle layer, which is away from the first buffer layer; the chips are arranged on one side of the conductive layer, which is away from the middle layer; one end of the positive power terminal is connected to the conducting layer, and the other end of the positive power terminal is connected with the positive end of the bus capacitor so as to supply power for each chip; a negative power terminal, one end of which is connected to the conductive layer, and the other end of which is used for connecting with the negative end of the bus capacitor; the positive power terminal and the negative power terminal are partially stacked to cancel parasitic inductance formed by current flowing therethrough; and an AC output terminal connected to the conductive layer. The parasitic inductance can be effectively reduced, and the electrical performance of the device is improved.
Description
Technical Field
The invention relates to the field of application of semiconductor devices, in particular to a power semiconductor device based on a general assembly structure.
Background
The power semiconductor device is used as a core device in a power electronic converter, and is widely applied to the fields of new energy system inverters, battery management, electric drive systems, frequency converters and the like. The third generation semiconductor chips such as silicon carbide, gallium nitride and the like become the optimal choice of a high-power electronic converter system due to higher switching frequency and power density, and the packaging structure and the packaging process of the power semiconductor chips are also required better.
The parasitic inductance of the power semiconductor devices of the same type on the market is mostly about 20nH, and the conventional packaging structure is narrow in width and long in length, so that the current path in the module is longer, and the parasitic inductance is larger. Parasitic inductance can be reduced by shortening the current path, which is not preferable to change the size of the housing in order to facilitate the mutual replacement between the products; the current path can also be shortened without changing the size of the housing, reducing the size of its internal power substrate or concentrating the power chip on the dc power terminal side, but this can result in a concentration of heat sources in the power module, which cannot efficiently dissipate heat. In terms of vibration resistance, conventional designs may suffer from the fact that vibrations are transmitted through the power terminals into the interior of the power module, which may damage the connection of the power terminals to the power substrate.
Disclosure of Invention
In view of the problems in the prior art, the invention provides a power semiconductor device based on a general assembly structure, which mainly solves the problem of larger parasitic inductance of the conventional power semiconductor device.
In order to achieve the above and other objects, the present invention adopts the following technical scheme.
The application provides a power semiconductor device based on general assembly structure, includes: a substrate; a first buffer layer disposed on one side of the substrate; the middle layer is arranged on one side of the first buffer layer, which faces away from the substrate; the conductive layer is arranged on one side of the middle layer, which is away from the first buffer layer; the chips are arranged on one side of the conductive layer, which is away from the middle layer; one end of the positive power terminal is connected to the conducting layer, and the other end of the positive power terminal is connected with the positive end of the bus capacitor so as to supply power for each chip; a negative power terminal, one end of which is connected to the conductive layer, and the other end of which is used for connecting with the negative end of the bus capacitor; the positive power terminal and the negative power terminal are partially stacked to cancel parasitic inductance formed by current flowing therethrough; and an AC output terminal connected to the conductive layer.
In an embodiment of the present application, a trench structure is disposed on the conductive layer, and a current path is formed through the trench structure.
In an embodiment of the present application, the current path includes a positive current path and a negative current path, and a portion of the positive current path and the negative current path are close to each other and parallel to cancel parasitic inductance.
In an embodiment of the present application, the positive power terminal includes: a first pin end; one side of the first plane layer is connected with the first pin end; the power supply positive connection end is arranged on one side, far away from the first pin end, of the first plane, and comprises a first end face and a second end face, wherein the first end face is perpendicular to the first plane layer, and the second end face is parallel to the first plane layer.
In an embodiment of the present application, the negative power terminal includes: a second pin end; one side of the second plane layer is connected with the second pin end; the power supply negative connecting end is arranged on one side, far away from the second pin end, of the second plane layer, and comprises a third end face and a fourth end face, wherein the third end face is perpendicular to the second plane layer, and the fourth end face is parallel to the second plane layer.
In an embodiment of the present application, the third end surface is disposed opposite to the first end surface, and the second end surface is partially located below the fourth end surface.
In an embodiment of the present application, the conductive layer includes a first sub-layer and a second sub-layer that are arranged side by side and at intervals, the first sub-layer and the second sub-layer are connected through a connecting bridge, the positive power terminal and the negative power terminal are arranged on the first sub-layer, and the ac output terminal is arranged on the second sub-layer.
In an embodiment of the present application, the power semiconductor device further includes a plastic package housing, which is fixed to the substrate by rivets.
In an embodiment of the present application, the positive power terminal and the negative power terminal are welded to the conductive layer using an ultrasonic welding process.
In an embodiment of the present application, the power semiconductor device further includes a plastic package body housing, where the substrate, the first buffer layer, the intermediate layer, the conductive layer, and the plurality of chips are wrapped by the plastic package body housing; the positive power terminal, the negative power terminal and the alternating current output terminal extend out of the plastic package body shell.
As described above, the power semiconductor device based on the general assembly structure of the present invention has the following advantageous effects.
According to the design that the positive power terminal and the negative power terminal are partially stacked, because the current flow directions on the positive power terminal and the negative power terminal are opposite, parasitic inductance can be reduced by canceling each other, in addition, current flows into the conducting layer from the positive power terminal and then flows out from the negative power terminal, the current paths formed in the conducting layer can be parallel and reverse, parasitic inductance is further reduced, and the performance of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a power semiconductor device based on a general assembly structure according to an embodiment of the present application.
Fig. 2 is a schematic top view of a power semiconductor device according to an embodiment of the present application.
Fig. 3 is a schematic perspective view of a positive power terminal according to an embodiment of the present application.
Fig. 4 is a schematic perspective view of a negative power terminal according to an embodiment of the present application.
Fig. 5 is a schematic perspective view of a package housing of a power semiconductor device according to an embodiment of the present application.
Reference numerals illustrate:
01-substrate, 02-first buffer layer, 03-intermediate layer, 04-conductive layer, 041-first sub-layer, 042-second sub-layer, 05-positive power terminal, 06-negative power terminal, 07-alternating current output terminal, 08-first planar layer, 09-first end face, 10-second end face, 11-first pin end, 12-second pin end, 13-second planar layer, 14-third end face, 15-fourth end face, 16-nut, 17-fixed position, 18-plastic package body shell.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a power semiconductor device based on a general assembly structure according to an embodiment of the present application. The package structure provided by the invention comprises: a substrate 01, a first buffer layer 02, an intermediate layer 03, a conductive layer 04, a plurality of chips, a positive power terminal 05, a negative power terminal 06, and an ac output terminal 07. The parasitic inductance is reduced through the design of the packaging structure, and the overall performance of the device is improved. The substrate 01 may be an alumina ceramic substrate, an aluminum nitride ceramic substrate, a silicon nitride ceramic substrate, or a silicon carbide ceramic substrate. The first buffer layer 02 is provided on one side of the substrate 01, and the first buffer layer 02 may be soldered to the substrate 01, or may be attached to the surface of the substrate 01 by other means. Illustratively, the first buffer layer 02 may employ a copper layer. The first buffer layer 02 is provided with an intermediate layer 03 on a side facing away from the substrate 01, and the intermediate layer 03 may be made of insulating ceramic materials such as alumina, aluminum nitride, silicon nitride, etc. A conductive layer 04 is provided on the side of the intermediate layer 03 remote from the first buffer layer 02. Pads for mounting semiconductor chips are provided on the conductive layer 04, and each chip may be provided on a corresponding pad. The chip containing the gate may bond the gate to the corresponding trace of conductive layer 04 by a bond wire. Positive power terminal 05 and negative power terminal 06 are connected with conducting layer 04 respectively, through positive power terminal 05 and negative power terminal 06 being close to each other formation stacked structure, the direction of electric current that flows through positive power terminal 05 is just in opposite with the electric current that flows through negative power terminal 06, can offset induced current between the opposite face in the stacked structure, and then reduces parasitic inductance.
In an embodiment, a trench structure may be formed on the conductive layer 04 by etching, the trench structure being used to form a current path, wherein the current path may include a positive current path and a negative current path. In order to reduce parasitic inductance, when the groove structure is formed, the positive current path and the negative current path are adjacent and parallel to each other, and the current flow direction on the positive current path is opposite to the current flow direction on the negative current path, so that the induced currents cancel each other, and the effect of reducing parasitic inductance is achieved.
In an embodiment, the first buffer layer 02 and the conductive layer 04 may be bonded to opposite sides of the intermediate layer 03 by high temperature in advance to form a composite substrate, and the composite substrate may be fixed to the base 01 by a solder layer.
Referring to fig. 2, fig. 2 is a schematic top view of a power semiconductor device according to an embodiment of the present application. In an embodiment, the middle layer 03 may include two substrates, where the two substrates are disposed side by side, and a gap is left between the two substrates, and the specific gap width may be set and adjusted according to practical application requirements, which is not limited herein. Likewise, the conductive layer 04 may include a first sub-layer 041 and a second sub-layer 042, the first sub-layer 041 being disposed on the substrate of one of the intermediate layers 03 and the second sub-layer 042 being disposed on the substrate of the other intermediate layer 03. And a gap is reserved between the two sublayers, so that the stress can be released under the high-temperature working condition. For example, the first buffer layer 02 and the first sub-layer 041 may be coated on both side surfaces of one substrate by a DBC (Direct Bonded Copper, direct copper-clad) process, respectively, and the first buffer layer 02 and the second sub-layer 042 may be coated on both side surfaces of the other substrate by an AMB (Active Metal Brazing ) process, respectively. After the composite boards of the two substrates are obtained, the two composite boards are arranged on the substrate 01 side by side, so that the first sub-layer 041 and the second sub-layer 042 are arranged at intervals, and further, connection between the two sub-layers is established at the intervals through a chip. In another embodiment, the middle layer may also be made of an insulating ceramic material, and the first sub-layer and the second sub-layer are formed on the same side of the middle layer through a DBC process and an AMB process respectively, and a gap is left between the first sub-layer and the second sub-layer, so as to release stress under high-temperature working conditions.
In one embodiment, the power semiconductor device further comprises a plastic package body shell 18, wherein the substrate 01, the first buffer layer 02, the middle layer 03, the conductive layer 04 and the plurality of chips are wrapped by the plastic package body shell 18; the positive power terminal 05, the negative power terminal 06, and the ac output terminal 07 partially protrude from the plastic package case 18.
In one embodiment, the positive power terminal 05 is connected to the positive end of the bus capacitor, and the negative power terminal 06 is connected to the negative end of the bus capacitor. Current flows from the positive power terminal 05 into the conductive layer 04, and flows to the negative power terminal 06 via a current path provided in the conductive layer 04, forming a current loop. Since the current paths are mostly arranged in parallel, the current on the parallel current paths is reversed, and the induced current can be counteracted, so that parasitic inductance is reduced. The closer the parallel current paths are, the more obvious the cancellation effect is, and the more obvious the effect of reducing parasitic inductance is. By adjusting the layout mode of the current paths in the conductive layer 04, parasitic inductance in the package structure can be effectively reduced, and the performance of the device is improved.
Referring to fig. 3, fig. 3 is a schematic perspective view of a positive power terminal according to an embodiment of the present application. The positive power terminal 05 includes a first pin end 11, a first planar layer 08, and a power supply positive connection end. The first pin terminal 11 may include a plurality of pins, and the number and shape of the pins may be set according to practical application requirements, which is not limited herein. The first pin terminal 11 is disposed on one side of the first planar layer 08, and extends from the side of the first planar layer 08 to connect with the conductive layer 04, and the positive power supply connection terminal is disposed on one side of the first planar layer 08 away from the first pin terminal 11.
In an embodiment, the positive power connection terminal may include a first end surface 09 and a second end surface 10, where the first end surface 09 and the second end surface 10 are perpendicular to each other to form a rectangular structural member, and the first end surface 09 is perpendicular to the first plane layer 08, and the second end surface 10 is parallel to the first plane layer 08, so as to form a height difference between the second end surface 10 and the first plane layer 08.
In an embodiment, a connection hole is provided on the second end surface 10, through which a bolt passes to be fixed with the positive end of the bus capacitor, so that the positive power terminal 05 is connected to the positive end of the bus capacitor.
Referring to fig. 4, fig. 4 is a schematic perspective view of a negative power terminal 06 according to an embodiment of the present application. The negative power terminal 06 includes a second pin terminal 12, a second planar layer 13, and a power negative connection terminal. The second pin end 12 may also include a plurality of pins, and the specific pin number and shape may be set and adjusted according to practical application requirements, which is not limited herein. The second pin terminal 12 is disposed on a side of the second planar layer 13, and extends outwards from the side of the second planar layer 13, and the power negative connection terminal is disposed on a side of the second planar layer 13 away from the second pin terminal 12. The negative power connection comprises a third end face 14 and a fourth end face 15. The third end face 14 and the fourth end face 15 are perpendicular to each other to form a right angle shaped structural member. The third end face 14 is perpendicular to the second planar layer 13 and the fourth end face 15 is parallel to the second planar layer 13. Thereby, a height difference is formed between the fourth end face 15 and the second planar face 13.
In one embodiment, the second end face 10 is at a greater height than the first planar layer 08 than the fourth end face 15 is at a greater height than the second planar layer 13. After the connection of the positive power terminal 05 and the negative power terminal 06 to the conductive layer 04 is established, the positive power terminal 05 and the negative power terminal 06 are partially stacked to form a stacked structure. Specifically, the first planar layer 08 is partially stacked with the second planar layer 13, the first planar layer 08 is disposed below the second planar layer 13, and the current flowing through the first planar layer 08 is opposite to the current flowing through the second planar layer 13, so as to cancel the induced current and reduce the parasitic inductance. The closer the first end face 09 and the third end face 14 are, the better, the first end face 09 and the third end face 14 may be disposed opposite to each other, and the interval between the first end face 09 and the third end face 14 may be set to 2.7mm, for example. The specific intervals can also be adjusted according to practical application requirements, and are not limited herein.
In an embodiment, the difference in height between the second end surface 10 and the first planar layer 08 may be set to 7mm, and the difference in height between the fourth end surface 15 and the second planar layer 13 may be set to 7mm. Of course, the specific height difference can also be adjusted according to practical application requirements, and is not limited herein.
In one embodiment, the thickness of the first planar layer 08 and the second planar layer 13 may be set to 2mm, or may be set according to the requirement, which is not limited herein.
In an embodiment, the package structure may include two positive power terminals 05 and one negative power terminal 06, where the two positive power terminals 05 are respectively disposed on two sides of the negative power terminal 06, and are respectively partially stacked with the negative power terminal 06 to form a stacked structure. The direct current power supply positive end current flows in from the positive power terminals 05 at two sides and then flows out from the negative power terminal 06 in the middle, which is more favorable for forming parallel current paths with opposite flow directions on the conductive layer 04 and can effectively reduce parasitic inductance. The number and positions of the positive power terminals 05 and the negative power terminals 06 may also be set and adjusted according to actual circuit requirements, without limitation.
In one embodiment, the chip on the conductive layer 04 may be selected according to the actual circuit requirement, which is not limited herein.
Referring to fig. 2 and fig. 5, fig. 5 is a schematic perspective view illustrating a package housing of a power semiconductor device according to an embodiment of the present application. In order to improve the shock resistance, the positive power terminal and the negative power terminal can be welded at the corresponding positions of the conductive layers through an ultrasonic welding process, and compared with a traditional aluminum wire bonding mode, the mechanical strength of the connecting position can be effectively improved. At the same time, the nuts 16 connected with the external busbar can be packaged in the plastic package body shell 18, and the plastic package body shell 18 locks the nuts 16, so that vibration can be transmitted to the whole plastic package body more. The gap between the positive power terminal and the negative power terminal is filled with an insulating material by plastic packaging, and the rest is wrapped with the insulating material except for the portion for connection. The bottom substrate 01 of the power semiconductor device can be used for heat dissipation, the plastic package housing 18 can be provided with fixing positions 17, and the number of the fixing positions 17 can be set according to practical application requirements, which is not limited herein. The fixing position 17 of the plastic package body shell 18 can be firmly fixed with the substrate 01 through rivets, and finally vibration is transmitted to the substrate 01, so that the overall vibration resistance of the device is improved.
Based on the technical scheme in the embodiment of the application, mutual inductance cancellation is performed based on reverse current, so that parasitic inductance in a packaging structure is reduced; under the condition that the size of the power device shell is not changed, parasitic inductance can be effectively reduced through the structural design of the power terminal and the arrangement mode of the current paths, and the electrical performance of the device is improved. Parasitic inductance between P-N through Ansys Q3D simulation is 11.3nH, and parasitic parameters provided by the data manual of other existing products are mostly about 20nH, so that the performance of the packaging structure is obviously improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A power semiconductor device based on a universal assembly structure, comprising:
a substrate;
a first buffer layer disposed on one side of the substrate;
the middle layer is arranged on one side of the first buffer layer, which faces away from the substrate;
the conductive layer is arranged on one side of the middle layer, which is away from the first buffer layer;
the chips are arranged on one side of the conductive layer, which is away from the middle layer;
one end of the positive power terminal is connected to the conducting layer, and the other end of the positive power terminal is connected with the positive end of the bus capacitor so as to supply power for each chip;
a negative power terminal, one end of which is connected to the conductive layer, and the other end of which is used for connecting with the negative end of the bus capacitor; the positive power terminal and the negative power terminal are partially stacked to cancel parasitic inductance formed by current flowing therethrough;
and an AC output terminal connected to the conductive layer.
2. The power semiconductor device based on a generic assembly structure according to claim 1, characterized in that a trench structure is provided on the conductive layer, through which trench structure a current path is formed.
3. The universal mounting structure based power semiconductor device of claim 2, wherein the current path comprises a positive current path and a negative current path, portions of the positive current path and the negative current path being in close proximity and parallel to each other to cancel parasitic inductance.
4. The universal mounting structure based power semiconductor device of claim 1, wherein the positive power terminal comprises:
a first pin end;
one side of the first plane layer is connected with the first pin end;
the power supply positive connection end is arranged on one side, far away from the first pin end, of the first plane, and comprises a first end face and a second end face, wherein the first end face is perpendicular to the first plane layer, and the second end face is parallel to the first plane layer.
5. The universal mounting structure based power semiconductor device of claim 4, wherein the negative power terminal comprises:
a second pin end;
one side of the second plane layer is connected with the second pin end;
the power supply negative connecting end is arranged on one side, far away from the second pin end, of the second plane layer, and comprises a third end face and a fourth end face, wherein the third end face is perpendicular to the second plane layer, and the fourth end face is parallel to the second plane layer.
6. The universal mounting structure based power semiconductor device of claim 5, wherein the third end face is disposed opposite the first end face and the second end face portion is located below the fourth end face.
7. The power semiconductor device according to claim 1, wherein the conductive layer includes a first sub-layer and a second sub-layer arranged side by side and at an interval, the first sub-layer and the second sub-layer being connected by a connecting bridge, the positive power terminal and the negative power terminal being arranged on the first sub-layer, and the ac output terminal being arranged on the second sub-layer.
8. The power semiconductor device of claim 1, further comprising a plastic package housing secured to the substrate by rivets.
9. The universal mounting structure based power semiconductor device of claim 1, wherein the positive power terminal and the negative power terminal are soldered to the conductive layer using an ultrasonic soldering process.
10. The power semiconductor device based on the universal assembly structure according to claim 1, further comprising a plastic package body housing, wherein the substrate, the first buffer layer, the intermediate layer, the conductive layer, the plurality of chips are wrapped by the plastic package body housing; the positive power terminal, the negative power terminal and the alternating current output terminal extend out of the plastic package body shell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311812508.7A CN117476581A (en) | 2023-12-27 | 2023-12-27 | Power semiconductor device based on general assembly structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311812508.7A CN117476581A (en) | 2023-12-27 | 2023-12-27 | Power semiconductor device based on general assembly structure |
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| Publication Number | Publication Date |
|---|---|
| CN117476581A true CN117476581A (en) | 2024-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311812508.7A Pending CN117476581A (en) | 2023-12-27 | 2023-12-27 | Power semiconductor device based on general assembly structure |
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| CN (1) | CN117476581A (en) |
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| CN103779307A (en) * | 2014-01-25 | 2014-05-07 | 嘉兴斯达半导体股份有限公司 | Clean-free soldering power module and preparation method |
| US20210151416A1 (en) * | 2017-06-14 | 2021-05-20 | Yangzhou Guoyang Electronic Co.,Ltd. | Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module |
| CN113270374A (en) * | 2021-04-30 | 2021-08-17 | 深圳芯能半导体技术有限公司 | IGBT power device |
| CN114725076A (en) * | 2022-03-23 | 2022-07-08 | 华中科技大学 | Power module and three-phase motor driver |
| CN115513163A (en) * | 2022-09-28 | 2022-12-23 | 上海海姆希科半导体有限公司 | Optimized structure of positive and negative busbars of power module |
| US20230225044A1 (en) * | 2022-01-13 | 2023-07-13 | Semiconductor Components Industries, Llc | Stray inductance reduction in power semiconductor device modules |
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2023
- 2023-12-27 CN CN202311812508.7A patent/CN117476581A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779307A (en) * | 2014-01-25 | 2014-05-07 | 嘉兴斯达半导体股份有限公司 | Clean-free soldering power module and preparation method |
| US20210151416A1 (en) * | 2017-06-14 | 2021-05-20 | Yangzhou Guoyang Electronic Co.,Ltd. | Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module |
| CN113270374A (en) * | 2021-04-30 | 2021-08-17 | 深圳芯能半导体技术有限公司 | IGBT power device |
| US20230225044A1 (en) * | 2022-01-13 | 2023-07-13 | Semiconductor Components Industries, Llc | Stray inductance reduction in power semiconductor device modules |
| CN114725076A (en) * | 2022-03-23 | 2022-07-08 | 华中科技大学 | Power module and three-phase motor driver |
| CN115513163A (en) * | 2022-09-28 | 2022-12-23 | 上海海姆希科半导体有限公司 | Optimized structure of positive and negative busbars of power module |
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