CN117475926A - Gate drive circuit and OLED display panel - Google Patents

Abstract

The application discloses a gate driving circuit and an OLED display panel, wherein the gate driving circuit comprises a wire inlet unit and a plurality of cascaded GOA driving units comprising a Pscan signal control circuit; the incoming line unit is provided with a first clock signal line unit and comprises at least one clock signal line; the Pscan signal control circuit is connected with the first clock signal line unit, receives the data writing control signal Pscan transmitted by the GOA driving unit of the previous stage under the control of the first clock signal, outputs the data writing control signal Pscan of the current stage, and inputs the data writing control signal Pscan of the current stage to the GOA driving unit of the next stage; the first clock signal line unit is provided with a first load adjusting part for adjusting a first load of the first clock signal line unit, and the first load and the temperature of the screen body are in positive correlation. The brightness compensation is realized by adjusting the first load to adjust the delay time of each row of data writing control signals Pscan.

Description

Gate drive circuit and OLED display panel

Technical Field

The application relates to the technical field of display, in particular to a grid driving circuit and an OLED display panel.

Background

An OLED (Organic Light-Emitting Diode), i.e., an Organic Light-Emitting Diode. Unlike conventional LCD display modes, OLED display technology does not require a backlight, but is driven by an electric field. When a current is passed, the organic semiconductor material and the light-emitting material emit light after being injected and recombined by the carriers. The OLED display screen can be made lighter and thinner, has larger visual angle, can remarkably save power consumption, and ensures that the OLED technology is widely applied to the fields of televisions, computer displays, mobile phones, flat plates and the like at present.

The OLED panel display circuit mainly comprises a pixel driving circuit and a grid driving circuit, wherein the pixel driving circuit mainly realizes the change of luminous intensity through the current control of an OLED device, and the grid driving circuit mainly controls the switching time sequence of the luminous device.

In the using process of the OLED panel, the temperature of the screen body is increased due to the current heating effect, so that the device is aged, and the phenomenon of display brightness attenuation of the screen body occurs.

Disclosure of Invention

The technical purpose of the application is to provide a grid driving circuit and an OLED display panel, wherein the display brightness level self-adaptive compensation is realized when the temperature of a screen changes through adjustment of the grid driving circuit.

In a first aspect, the present application provides a gate driving circuit applied to an OLED display panel, where the gate driving circuit includes a wire inlet unit and a plurality of cascaded GOA driving units, and each stage of GOA driving unit includes a Pscan signal control circuit;

the first clock signal line unit is arranged in the incoming line unit and comprises at least one clock signal line;

the Pscan signal control circuit is connected with the first clock signal line unit and is used for receiving the data writing control signal Pscan (n-1) transmitted by the GOA driving unit at the previous stage according to the clock signal on the clock signal line, outputting the data writing control signal Pscan (n) at the current stage and inputting the data writing control signal Pscan at the current stage into the GOA driving unit at the next stage;

the first load adjusting part is used for adjusting a first load of the first clock signal line unit, and the first load and the screen temperature of the OLED display panel are in positive correlation.

In some embodiments, the first clock signal line unit includes a first clock signal line CK1 and the second clock signal line CK2, and the first load adjusting part includes a first thermistor and a second thermistor; the first clock signal line CK1 is connected with the first thermistor in series, and the second clock signal line CK2 is connected with the second thermistor in series.

In some embodiments, the first thermistor and the second thermistor are both positive temperature coefficient thermistors.

In some embodiments, the resistance of the first thermistor is the same as the resistance of the second thermistor.

In some embodiments, the resistance value of the first thermistor and the resistance value of the second thermistor are in a range of 100 Ω to 200 Ω.

In some embodiments, the first clock signal line CK1 and the second clock signal line CK2 are connected between a display driving chip and the GOA driving units of each stage, and the first clock signal line CK1 and the second clock signal line CK2 are connected to each of the GOA driving units via the first thermistor and the second thermistor, respectively.

In some embodiments, the second clock signal line unit is connected to each stage of the GOA driving units 10, and each GOA driving unit 10 further includes an Nscan signal control circuit 103, where the Nscan signal control circuit 103 is connected to the second clock signal line unit, and is configured to output a row scan signal Nscan.

In some embodiments, the data writing control signal Pscan is connected to a pixel driving circuit of the OLED display panel;

the pixel driving circuit comprises a driving transistor T1, a data transistor T2, a compensation transistor T3, a first reset transistor T7, a second reset transistor T4, a first light-emitting control transistor T6, a second light-emitting control transistor T5, a light-emitting device, a first storage capacitor Cst and a second storage capacitor Cboost;

the gate of the data transistor T2 is electrically connected to the current level data write control signal Pscan (n); the grid electrode of the first reset transistor T7 is electrically connected with a previous-stage data writing control signal Pscan (n-1); the first reset transistor T7 is used for resetting the anode of the light-emitting device;

the gate of the compensation transistor T3 is electrically connected to the current row scan signal Nscan (n), the gate of the second reset transistor T4 is electrically connected to the previous row scan signal Nscan (n-5) of the fifth row, and the second reset transistor T4 is used for resetting the gate (Q point) of the driving transistor T1.

In some embodiments, the second clock signal line unit is provided with a second load adjusting part, and the second load adjusting part is used for adjusting a second load of the second clock signal line unit, and the second load is in a negative correlation with the screen temperature of the OLED display panel (1000).

In some embodiments, the incoming line unit includes a third clock signal line unit arranged therein, the third clock signal line unit including a fifth clock signal line CK5 and a sixth clock signal line CK6, and each of the GOA driving units further includes an EM signal control circuit connected to the fifth clock signal line CK5 and the sixth clock signal line CK6, respectively, for outputting a pixel emission control signal EM.

In some embodiments, a start signal line STV is further arranged in the incoming unit, and the start signal line STV is connected to the start GOA driving unit, and is used for transmitting a frame start signal.

In a second aspect, the present application provides an OLED display panel, including an array substrate having a display area and a non-display area;

the display area is provided with a pixel array, the pixel array comprises a plurality of pixel units of N rows and M columns, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 2;

the non-display area is provided with the gate driving circuit as described above to control data writing of the pixel unit.

In some embodiments, the OLED display panel is further provided with a pixel driving circuit and a display driving chip;

the gate driving circuit is used for providing a row scanning signal Nscan to the pixel driving circuit through a scanning signal line, and providing a data writing control signal Pscan to the pixel driving circuit through a data writing control signal line, and providing a light emitting control signal EM to the pixel driving circuit through a light emitting control signal line;

the display driving chip is used for providing a DATA signal DATA to the pixel driving circuit through a DATA line, providing a first reset signal Vi_Gate to the pixel driving circuit through a first reset signal line, and providing a second reset signal Vi_Ano to the pixel driving circuit through a second reset signal line;

the pixel driving circuit is configured to generate a driving signal to drive the pixel unit according to the row scanning signal Nscan, the DATA writing control signal Pscan, the light emitting control signal EM, the DATA signal DATA, the first reset signal vi_gate, and the second reset signal vi_ano.

In a third aspect, the present application provides a display device comprising an OLED display panel as described above.

Compared with the prior art, the gate driving circuit provided by the embodiment of the application can increase the delay of the data writing control signal Pscan under the conditions of increasing the screen lighting time and increasing the temperature, thereby improving the brightness of the display screen and realizing automatic brightness compensation.

According to the OLED display panel provided by the embodiment of the application, the thermistor is connected in series on the clock signal line connected with the GOA driving unit and comprising the Pscan signal control circuit, so that the delay of the data writing control signal Pscan can be increased under the conditions of increasing the screen lighting time and increasing the temperature, the brightness of the display screen is improved, and automatic brightness compensation is realized.

According to the display device provided by the embodiment of the application, the delay of the data writing control signal Pscan can is increased along with the increase of the screen lighting time, the brightness of a display screen body is improved, and automatic brightness compensation is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an OLED display panel according to an embodiment of the present disclosure;

FIG. 4 is a conventional drive design;

FIG. 5 is a schematic diagram of the simulation of the relationship between the equivalent resistance R_CK of the clock signal line and OLED current;

fig. 6 is a schematic diagram of a Pscan signal control circuit in a gate driving circuit according to an embodiment of the present application;

FIG. 7 is a timing diagram of a Pscan signal control circuit in the gate drive circuit of FIG. 6;

FIG. 8 is a schematic diagram of a pixel driving circuit in an OLED display panel according to an embodiment of the present disclosure;

FIG. 9 is a signal timing diagram of the pixel driving circuit in the embodiment shown in FIG. 8;

FIG. 10 is a schematic diagram of simulation results of the effect of Pscan Delay on the current of the driving transistor T1 in the embodiment shown in FIG. 8;

FIG. 11 is a schematic diagram showing the simulation result of the effect of the equivalent resistor R_CK on the CK signal line on Pscan Delay in the embodiment shown in FIG. 8;

FIG. 12 is a schematic diagram of a pixel driving circuit in an OLED display panel according to another embodiment of the present disclosure;

fig. 13 is a schematic diagram of an Nscan signal control circuit in a gate driving circuit according to an embodiment of the present application;

fig. 14 is a schematic diagram of a relationship between a load of a second clock signal line unit in a gate driving circuit incoming unit and a step voltage of a row scan signal Nscan according to an embodiment of the present disclosure;

fig. 15 is a schematic diagram of a relationship between a load of a second clock signal line unit in a gate driving circuit line-in unit and a gate (Q point) voltage of a driving transistor of a pixel driving unit according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.

Reference numerals: the display device comprises a 10-GOA driving unit, a 101-Pscan signal control circuit, a 102-incoming line unit, a 11-first thermistor, a 12-second thermistor, a 13-third thermistor, a 14-fourth thermistor, a 103-Nscan signal control circuit, a 104-EM signal control circuit, a 20-pixel driving circuit, a 30-display driving chip, a 1000-OLED display panel and a 2000-display device.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the using process of the OLED panel, the temperature of the screen body is increased due to the current heating effect, so that the device is aged, and the phenomenon of display brightness attenuation of the screen body occurs.

The conventional driving design scheme is shown in fig. 4, the pixel switches of one stage are controlled in cascade by the left and right groups of gate driving circuits, and the progressive light emission of the pixels is realized through the progressive transmission of the GOA signals.

According to the conventional design scheme, after the GOA circuit is manufactured, the resistance on a Clock (CK) signal line is a fixed value; the GOA circuit controls the timing of the pixel emission without having an adaptive compensation for the pixel emission intensity.

The simulation shows that, as shown in fig. 5, the load size on the Clock (CK) signal line (r_ck is the equivalent resistance of the clock CK signal line) affects the Delay time (Pscan Delay) of the GOA output signal (such as the data writing control signal Pscan), and the Delay of the GOA signal affects the current of the pixel circuit, and as the Delay (Pscan Delay) of the GOA output signal increases, the current on the OLED also increases, so that the current flowing through the light emitting device can be controlled by changing the load on the CK signal line, thereby realizing the control of the light emitting intensity. The Delay time (e.g., pscan Delay) of the GOA output signal may be the time when the GOA output signal changes from Δv by 10% to Δv by 90%, where VGH is high, VGL is low, and Δv is the voltage difference of the high VGH minus the low VGL.

The OLED product has a major problem of lifetime, that is, as the lighting time of the screen increases, the brightness of the screen gradually decays, which affects the user experience. OLED lifetime is an important index for evaluating products; the lifetime is defined as the time required for the initial 95% reduction in brightness. The Pscan Delay can be increased by increasing the resistance on the CK signal line, so that the brightness of the display screen body is improved.

Further research shows that the grid driving circuit controls the pixel luminous time sequence and has a certain influence on the pixel luminous intensity, namely, the pixel luminous intensity can be changed to a certain extent by adjusting the grid driving circuit.

The embodiment of the application provides a gate driving circuit, as shown in fig. 1, which is applied to an OLED display panel 1000, wherein the gate driving circuit comprises a wire inlet unit 102 and a plurality of cascaded GOA driving units 10, and each stage of GOA driving unit 10 comprises a Pscan signal control circuit 101;

the incoming line unit 102 is arranged with a first clock signal line unit, and the first clock signal line unit comprises at least one clock signal line;

the Pscan signal control circuit 101 is connected to the first clock signal line unit, and is configured to receive the data write control signal Pscan transmitted by the previous-stage GOA driving unit 10, output the data write control signal Pscan of the present stage, and input the data write control signal Pscan of the present stage to the next-stage GOA driving unit 10 under control of the first clock signal;

the first clock signal line unit is provided with a first load adjusting portion, and the first load adjusting portion is configured to adjust a first load of the first clock signal line unit, where the first load and a temperature of a screen of the OLED display panel 1000 are in a positive correlation.

According to the gate driving circuit provided by the embodiment of the application, the delay time of the data writing control signal Pscan of each stage of GOA driving unit 10 is regulated according to the first load positive correlation, so that brightness compensation is realized.

In a specific embodiment, the first load adjustment portion may employ a thermistor.

In some embodiments, the first clock signal line unit includes a first clock signal line CK1 and a second clock signal line CK2.

The first load adjustment portion may include a first thermistor 11 and a second thermistor 12. The first clock signal line CK1 is connected in series with the first thermistor 11, and the second clock signal line CK2 is connected in series with the second thermistor 12.

In a specific embodiment, the thermistor used is a positive temperature system thermistor, and the resistance of the first thermistor 11 and the second thermistor 12 increases with the height of the temperature.

According to the grid driving circuit provided by the embodiment of the application, the delay of the data writing control signal Pscan can be increased under the conditions of increasing the lighting time and increasing the temperature of the screen body, so that the brightness of the display screen body is improved, and automatic brightness compensation is realized.

In some embodiments, in order to equalize the loads of the first clock signal line CK1 and the second clock signal line CK2, the resistance value of the first thermistor 11 and the resistance value of the second thermistor 12 are the same, and preferably, the performance parameters of both the thermistors are the same.

In a specific embodiment, the resistance of the thermistor can be selected through simulation. If the influence of Pscan Delay on the brightness is within 5%, the Pscan Delay variation amplitude is 0.05us, and the resistance value of the thermistor is determined by considering the self capacitance of the first clock signal line CK1 and the second clock signal line CK2, the material parameters of the first clock signal line CK1 and the second clock signal line CK2, the temperature variation amplitude and the Pscan Delay variation amplitude. In some embodiments, the resistance of the first thermistor 11 and the resistance of the second thermistor 12 range from 100 Ω to 200 Ω.

In some embodiments, the first and second clock signal lines CK1 and CK2 are connected between the display driving chip 30 and each stage GOA driving unit 10, and the first and second clock signal lines CK1 and CK2 are connected to each GOA driving unit 10 via the first and second thermistors 11 and 12, respectively.

As shown in fig. 2, the incoming unit 102 is arranged with a second clock signal line unit, the second clock signal line unit is connected to each stage of GOA driving units 10, each GOA driving unit 10 further includes an Nscan signal control circuit 103, and the Nscan signal control circuit 103 is connected to the second clock signal line unit for outputting a row scanning signal Nscan.

In some embodiments, the second clock signal line unit includes a third clock signal line CK3 and a fourth clock signal line CK4, and the Nscan signal control circuit 103 is connected to the third clock signal line CK3 and the fourth clock signal line CK4, respectively, for outputting the row scan signal Nscan.

In some embodiments, the second clock signal line unit is provided with a second load adjusting portion, where the second load adjusting portion is configured to adjust a second load of the second clock signal line unit, and the second load is in a negative correlation with a temperature of a screen of the OLED display panel 1000.

The second load adjustment portion may be a thermistor.

As shown in fig. 2, the second load adjusting part includes a third thermistor R13 and a fourth thermistor R14, the third clock signal line CK3 is connected in series with the third thermistor R13, and the fourth clock signal line CK4 is connected in series with the fourth thermistor R14.

The third thermistor R13 and the fourth thermistor R14 are negative temperature coefficient thermistors, that is, the thermistors decrease in resistance as the temperature of the panel increases.

In some embodiments, a schematic diagram of the control circuit of the row scan signal Nscan in the gate driving circuit is shown in fig. 13.

Under long-time operation, as shown in fig. 13, the gate Q of the transistor T9 is negative, the threshold voltage Vth of the transistor T9 is negative, vgs (voltage drop between the gate and the source of the transistor) is negative, the threshold voltage Vth is negative, so that the VGL output device out is poor, the transistor T9 is turned on and poor, the output is raised, the step voltage of the row scan signal Nscan is raised, the voltage of the Q point (the gate of the driving transistor T1) in the pixel driving circuit is raised, that is, vq is raised, the driving transistor T1 in the pixel driving circuit is turned on and poor, the brightness is reduced, and the service life of the screen is poor.

Fig. 14 is a schematic diagram of a relationship between a load of a second clock signal line unit in a gate driving circuit incoming unit and a step voltage of a row scan signal Nscan according to an embodiment of the present disclosure; fig. 15 is a schematic diagram of a relationship between a load of a second clock signal line unit in a gate driving circuit line-in unit and a gate (Q point) voltage of a driving transistor of a pixel driving unit according to an embodiment of the present application.

As can be seen from fig. 14, as the load (r_nscan_ck) of the second clock signal line unit in the gate driving circuit line unit decreases, r_nscan_ck decreases from 4K to 2K, and the step voltage of Nscan also decreases. As can be seen from fig. 15, as the load (r_nscan_ck) of the second clock signal line unit in the gate driving circuit line unit decreases, r_nscan_ck decreases from 4K to 2K, and the Q point (gate of the driving transistor T1) voltage in the pixel driving circuit decreases.

Therefore, the second load of the second clock signal line unit is adjusted by the second load adjusting part, so that the second load and the temperature of the screen body of the OLED display panel 1000 are in a negative correlation, and as the time of the electric lamp of the display panel increases, the temperature increases, the second load decreases, thereby achieving the purpose of reducing the Nscan step voltage, and realizing the brightness compensation and the improvement of the service life.

In some embodiments, the second load adjustment portion employs a negative temperature coefficient thermistor.

In some embodiments, the third clock signal line CK3 and the fourth clock signal line CK4 are connected between the display driving chip 30 and each stage GOA driving unit 10, and the third clock signal line CK3 and the fourth clock signal line CK4 are connected to each GOA driving unit 10 via a third thermistor R13 and a fourth thermistor R14, respectively.

In some embodiments, the two clock signal line units include a third clock signal line CK3 and a fourth clock signal line CK4, and each GOA driving unit 10 further includes an Nscan signal control circuit 103; the Nscan signal control circuit 103 is connected to the fifth clock signal line CK5 and the sixth clock signal line CK6, respectively, for outputting the row scanning signal Nscan.

In some embodiments, the incoming unit 102 has a third clock signal line unit arranged therein, the third clock signal line unit includes a fifth clock signal line CK5 and a sixth clock signal line CK6, each GOA driving unit 10 further includes an EM signal control circuit 104, and the EM signal control circuit 104 is connected to the fifth clock signal line CK5 and the sixth clock signal line CK6, respectively, for outputting the pixel emission control signal EM.

In some embodiments, a start signal line STV is further arranged in the incoming unit 102, and the start signal line STV is connected to the start GOA driving unit 10 for transmitting a frame start signal.

In some embodiments, the Pscan signal control circuit 101 is shown in fig. 6. The timing diagram of the Pscan signal control circuit 101 is shown in fig. 7. The circuit in fig. 6 is an 8t2c GOA shift register output circuit, and includes stage (1), stage (2), stage (3) and stage (4).

In phase (1) the potential is stored: CK1 low level, CK2 high level, scan (n-1) low level, transistor T1, transistor T2, transistor T3, transistor T5, transistor T6 and transistor T7 on, transistor T4 off, transistor T6 high level, scan (n-1) low level stored to Q point;

shift output at stage (2): CK1 keeps high level, CK2 keeps low level, and transistors T1, T2, T5, T7 turn off; transistor T3, transistor T4 and transistor T6 are turned on, scan (n-1) is held high, and Q point low potential shift output is performed;

in stage (3) output pull-up: CK1 low level, CK2 high level, scan (n-1) high level, GOA ends output, transistor T1, transistor T2, transistor T5 and transistor T7 are on, transistor T3, transistor T4 and transistor T6 are off, transistor T7 outputs high potential;

stabilizing the high potential in stage (4): the transistors T1, T2, T3 and T6 are turned off, the transistors T4 and T5 are turned on, and the Q point is maintained high during the GOA high output period.

As shown in fig. 3, the embodiment of the present application further provides an OLED display panel 1000, including an array substrate, where the array substrate has a display area AA and a non-display area NAA;

the display area AA is provided with a pixel array, the pixel array comprises a plurality of pixel units of N rows and M columns, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 2;

the non-display area NAA is provided with a gate driving circuit; the gate driving circuit is as the gate driving circuit above.

In some embodiments, the OLED display panel 1000 is further provided with a pixel driving circuit 20 and display driving chips 30, GOA driving unit 10 for supplying a row scan signal Nscan to the pixel driving circuit 20 through a scan signal line, and a data write control signal Pscan to the pixel driving circuit 20 through a data write control signal line, and a light emission control signal EM to the pixel driving circuit 20 through a light emission control signal line.

The display driving chip 30 is used to supply the DATA signal DATA to the pixel driving circuit 20 through the DATA line, and to supply the first reset signal vi_gate to the pixel driving circuit 20 through the first reset signal line, and to supply the second reset signal vi_ano to the pixel driving circuit 20 through the second reset signal line.

The pixel driving circuit 20 is configured to generate driving signals to drive the pixel units according to the row scan signal Nscan, the DATA write control signal Pscan, the light emission control signal EM, the DATA signal DATA, the first reset signal vi_gate, and the second reset signal vi_ano.

In some embodiments, a schematic diagram of the pixel driving circuit 20 in the OLED display panel 1000 is shown in fig. 8. The pixel driving circuit 20 includes a driving transistor T1, a data transistor T2, a compensation transistor T3, a first reset transistor T7, a second reset transistor T4, a first light emitting control transistor T6, a second light emitting control transistor T5, a light emitting device, a first storage capacitor Cst, and a second storage capacitor Cboost.

Wherein the drain of the driving transistor T1 is electrically connected to the first node A, the source of the driving transistor T1 is electrically connected to the second node B, the Gate of the driving transistor T1 is electrically connected to the third node Q, the drain of the DATA transistor T2 is electrically connected to the DATA signal line to receive the DATA signal DATA, the source of the DATA transistor T2 is electrically connected to the first node A, the Gate of the DATA transistor T2 is electrically connected to the DATA control signal line to respond to the present level DATA write control signal Pscan (n), the drain of the compensation transistor T3 is electrically connected to the second node B, the source of the compensation transistor T3 is electrically connected to the third node Q, the Gate of the compensation transistor T3 is electrically connected to the compensation control signal line to respond to the column scan signal NScan (n), the drain of the second reset transistor T4 is electrically connected to the second reset signal line to receive the second reset signal Vi_Gate, the source electrode of the second reset transistor T4 is electrically connected to the third node Q, the Gate electrode of the second reset transistor T4 is electrically connected to the reset control signal line in response to the reset control signal (in the embodiment shown in fig. 8, the Gate electrode of the second reset transistor T4 is electrically connected to the row scan signal Nscan (n-5) of the fifth row before the Gate electrode of the second reset transistor T4 is electrically connected to the row scan signal Nscan), the Gate electrodes of the second light-emitting control transistor T5 and the first light-emitting control transistor T6 are both electrically connected to the light-emitting control signal line in response to the light-emitting control signal EM, the drain electrode of the second light-emitting control transistor is electrically connected to the first power signal line to receive the first power signal VDD, the source electrode of the second light-emitting control transistor is electrically connected to the first node a, the drain electrode of the first light-emitting control transistor T6 is electrically connected to the second node B, the source electrode of the first light emitting control transistor T6 is electrically connected to the first electrode of the light emitting device LED, the second electrode of the light emitting device LED is electrically connected to the second power signal line to receive the second power signal VSS, the drain electrode of the first reset transistor T7 is electrically connected to the first reset signal line to receive the first reset signal vi_ano, the source electrode of the first reset transistor T7 is electrically connected to the first electrode of the light emitting device LED, the gate electrode of the first reset transistor T7 is electrically connected to the data control signal line to respond to the previous stage data writing control signal Pscan (n-1), one end of the first storage capacitor Cst is electrically connected to the drain electrode of the second control transistor, the other end of the first storage capacitor Cst is electrically connected to the third node Q, one end of the second storage capacitor Cboost is electrically connected to the data control signal line, and the other end of the second storage capacitor Cboost is electrically connected to the third node Q.

As shown in fig. 9, which is a timing chart of signals of the pixel driving circuit 20 shown in fig. 8, one light-emitting period of the pixel driving circuit 20 can be divided into four phases: t1, t2, t3 and t4. In the pixel driving circuit 20 of this embodiment, T1/T2/T5/T6/T7 is PTFT, low-potential on is effective, T3/T4 is NTFT, and high-potential on is effective.

In a period T1, the light-emitting control signal EM is turned off from VGL to VGH, T5/6, nscan (n-5) is turned on from VGL to VGH, and in a period T4, the first reset signal Vi_Gate resets the Q point;

in the T2 period, nscan (n) is started from VGL to VGH and T3, pscan (n) is started from VGH to VGL and T2, and Vdata is written into the Q point;

in the period t3, pscan (n) capacitively couples the Q point from VGH to VGL through a second storage capacitor Cboost, the Q point is lifted, the potential of the Q point is conditioned, and the Vdata range is adapted to the setting of the display driving chip 30;

t4 period, luminescence process;

when Pscan is turned on in the t2 stage, vdata is written, and the effect of writing is affected by Pscan Delay. As shown in fig. 10 and 11, the larger the Pscan Delay is, the higher the luminance is; the Pscan Delay is related to the equivalent resistance and the equivalent capacitance of the clock signal line connected to the Pscan signal control circuit 101, and the larger the equivalent resistance and the equivalent capacitance, the larger the Pscan Delay, and the larger the luminance improvement amplitude.

According to the OLED display panel 1000, the first clock signal line unit connected with the Pscan signal control circuit 101 in the GOA driving unit 10 is connected with the thermistor in series, and as the screen lighting time increases, the temperature increases, and the resistance of the thermistor increases, so that the Pscan Delay increases to compensate the brightness attenuation of the screen body.

It should be noted that, while the LTPO pixel driving circuit is shown in fig. 8, in practice, the inventive concept of the present application is also applicable to LTPS pixel circuits; the difference compared to LTPS pixel circuits is that the compensation transistor T3 and the second reset transistor T4 in LTPO pixel driving circuits are oxide thin film transistors.

Fig. 12 is a schematic diagram of a pixel driving circuit in an OLED display panel according to another embodiment of the present application, where the circuit is an 8T2C structure, and the 8T2C circuit is a structure commonly used in the pixel driving circuit, and is composed of 8 transmission gates (T) and 2 capacitors (C).

The pixel driving circuit 20 shown in fig. 12 includes a driving transistor T1, a data transistor T2, a compensation transistor T3, a first reset transistor T7, a second reset transistor T4, a third reset transistor T8, a first light emission control transistor T6, a second light emission control transistor T5, a light emitting device, a first storage capacitor Cst, and a second storage capacitor Cboost.

The gate of the data transistor T2 is electrically connected to the data writing control signal Pscan; the grid electrode of the first reset transistor T7 is electrically connected with a data writing control signal Pscan2; the first reset transistor T7 is for resetting the anode (point C) of the light emitting device;

the gate of the compensation transistor T3 is electrically connected to the row scan signal Nscan1, the gate of the second reset transistor T4 is electrically connected to the row scan signal Nscan2, and the second reset transistor T4 is used for resetting the gate (Q point) of the driving transistor T1.

The gate of the third reset transistor T8 is connected to the data write control signal Pscan2, and the third reset transistor T8 is used to reset the source (point a) of the driving transistor T1.

The embodiment of the application also provides a display device 2000, as shown in fig. 16, the display device 2000 includes the OLED display panel 1000 as above.

In summary, although the present invention has been described in terms of the preferred embodiments, the above-mentioned embodiments are not intended to limit the invention, and those skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention, so that the scope of the invention is defined by the appended claims.

Claims (10)

1. A gate driving circuit applied to an OLED display panel (1000), wherein the gate driving circuit comprises a wire inlet unit (102) and a plurality of cascaded GOA driving units (10), and each stage of GOA driving units (10) comprises a Pscan signal control circuit (101);

the first clock signal line unit is arranged in the wire inlet unit (102), and comprises at least one clock signal line;

the Pscan signal control circuit (101) is connected with the first clock signal line unit, and is used for receiving a data writing control signal Pscan (n-1) transmitted by the GOA driving unit (10) at the previous stage according to a clock signal on the clock signal line, outputting a data writing control signal Pscan (n) at the current stage, and inputting the data writing control signal Pscan (n) at the current stage into the GOA driving unit (10) at the subsequent stage;

the first clock signal line unit is provided with a first load adjusting part, the first load adjusting part is used for adjusting a first load of the first clock signal line unit, and the first load and the screen temperature of the OLED display panel (1000) are in positive correlation.

2. The gate driving circuit according to claim 1, wherein the first clock signal line unit includes a first clock signal line CK1 and a second clock signal line CK2; the first load adjustment part comprises a first thermistor (11) and a second thermistor (12); the first clock signal line CK1 is connected with the first thermistor (11) in series, and the second clock signal line CK2 is connected with the second thermistor (12) in series.

3. The gate drive circuit according to claim 2, wherein the first thermistor (11) and the second thermistor (12) are both positive temperature coefficient thermistors.

4. A gate driving circuit according to claim 2, wherein the first thermistor (11) and the second thermistor (12) have the same resistance value.

5. The gate drive circuit according to claim 2, wherein the resistance values of the first thermistor (11) and the second thermistor (12) are in a range of 100 Ω to 200 Ω.

6. A gate driving circuit according to claim 2, wherein said first clock signal line CK1 and said second clock signal line CK2 are connected between a display driving chip (30) and each stage of said GOA driving unit (10), and said first clock signal line CK1 and said second clock signal line CK2 are connected to each of said GOA driving units (10) via said first thermistor (11) and said second thermistor (12), respectively.

7. The gate driving circuit according to claim 1, wherein the incoming line unit (102) has arranged therein a second clock signal line unit including a third clock signal line CK3 and a fourth clock signal line CK4, each GOA driving unit (10) further including an Nscan signal control circuit (103);

the Nscan signal control circuit (103) is connected to the third clock signal line CK3 and the fourth clock signal line CK4, respectively, and outputs a row scanning signal Nscan.

8. The gate driving circuit according to claim 7, wherein the data writing control signal Pscan of each stage is connected to the pixel driving circuit of the OLED display panel (1000);

the pixel driving circuit comprises a driving transistor T1, a data transistor T2, a compensation transistor T3, a first reset transistor T7, a second reset transistor T4, a first light-emitting control transistor T6, a second light-emitting control transistor T5, a light-emitting device, a first storage capacitor Cst and a second storage capacitor Cboost;

the gate of the data transistor T2 is electrically connected to the current level data writing control signal Pscan (n), the gate of the first reset transistor T7 is electrically connected to the previous level data writing control signal Pscan (n-1), and the first reset transistor T7 is used for resetting the anode of the light emitting device;

the gate of the compensation transistor T3 is electrically connected to the row scan signal Nscan (n), the gate of the second reset transistor T4 is electrically connected to the row scan signal Nscan (n-5) of the fifth row before the second reset transistor T4 is electrically connected to the gate of the driving transistor T1.

9. The gate driving circuit according to claim 7, wherein the second clock signal line unit is provided with a second load adjusting portion for adjusting a second load of the second clock signal line unit, the second load being in negative correlation with a screen temperature of the OLED display panel (1000).

10. An OLED display panel (1000) comprising an array substrate having a display region and a non-display region;

the display area is provided with a pixel array, the pixel array comprises a plurality of pixel units of N rows and M columns, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 2;

the non-display area is provided with a gate driving circuit as claimed in any one of claims 1 to 9 to control data writing of the pixel unit.