CN117475918A

CN117475918A - Pixel driving circuit and display panel

Info

Publication number: CN117475918A
Application number: CN202310350484.1A
Authority: CN
Inventors: 程卫高
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2024-01-30

Abstract

The application discloses a pixel driving circuit and a display panel. The pixel driving circuit comprises a first light emitting control module, a driving transistor, a second light emitting control module, a data writing module and a first initialization module. The driving timing sequence of the pixel driving circuit comprises a writing frame and a holding frame, wherein the writing frame comprises a first reset phase and a data writing phase which are sequentially carried out, and in the first reset phase, the first light emitting control module is used for writing the first power supply signal into a first pole and a second pole of the driving transistor, or the first initialization module and the second light emitting control module are used for writing the first initialization signal into the first pole and the second pole of the driving transistor. The method and the device can reduce the characteristic reset effect difference of the driving transistor between the writing frame and the holding frame, and improve the flicker caused by the brightness difference between the writing frame and the holding frame.

Description

Pixel driving circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a pixel driving circuit and a display panel.

Background

With the continuous development of Active-Matrix organic Light-emission Diode (AMOLED) products in the consumer market, the requirements of people on the optical performance of mobile phone products are higher and higher. Flicker is an important index for evaluating the optical performance of mobile phones, and specifications are becoming more and more strict. While the introduction of low frequency displays also causes flicker to become more severe.

At low frequency display, a frame of display typically includes a write frame and a hold frame, the hold frame including at least one sub-frame. Since there is a difference in characteristic reset of the driving transistor in the first sub-frame of the writing frame and the holding frame, there is a difference in luminance between the writing frame and the first sub-frame of the holding frame, and thus flicker of the picture occurs.

Disclosure of Invention

The application provides a pixel driving circuit and a display panel, which are used for solving the technical problem that a first subframe of a writing frame and a first subframe of a holding frame in the prior art have brightness difference, so that a picture flickers.

In a first aspect, the present application provides a pixel driving circuit, comprising:

a driving transistor;

the control end of the first light-emitting control module is connected with a first enabling signal, the input end of the first light-emitting control module is connected with a first power supply signal, and the output end of the first light-emitting control module is electrically connected with a first pole of the driving transistor;

the control end of the second light-emitting control module is connected with a second enabling signal, and the output end of the second light-emitting control module is electrically connected with a second pole of the driving transistor;

the first control end of the data writing module is connected with a first control signal, the second control end of the data writing module is connected with a second control signal, the input end of the data writing module is connected with a data signal, and the data writing module is further electrically connected with the grid electrode, the first electrode and the second electrode of the driving transistor; and

the control end of the first initialization module is connected with a third control signal, the input end of the first initialization module is connected with a first initialization signal, and the output end of the first initialization module is electrically connected with the input end of the second light-emitting control module;

the driving timing sequence of the pixel driving circuit comprises a writing frame and a holding frame, wherein the writing frame comprises a first reset phase and a data writing phase which are sequentially carried out, and in the first reset phase, the first light emitting control module is used for writing the first power supply signal into a first pole and a second pole of the driving transistor, or the first initialization module and the second light emitting control module are used for writing the first initialization signal into the first pole and the second pole of the driving transistor.

Optionally, in some embodiments of the present application, the holding frame includes at least one subframe, and if the brightness of the writing frame is smaller than the brightness of the first subframe of the holding frame, in the first reset phase, the first light emitting control module responds to the first enable signal, and writes the first power signal to the first pole and the second pole of the driving transistor.

Optionally, in some embodiments of the present application, the first control signal and the third control signal are the same signal.

Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second initialization module, a control end of the second initialization module is connected to a fourth control signal, an input end of the second initialization module is connected to a second initialization signal, and an output end of the second initialization module is electrically connected to a gate of the driving transistor;

in the first reset phase, the second initialization module responds to the fourth control signal and writes the second initialization signal to the grid electrode of the driving transistor.

Optionally, in some embodiments of the present application, the holding frame includes at least one subframe, and if the brightness of the writing frame is greater than the brightness of the first subframe of the holding frame, in the first reset phase, the first initialization module responds to the third control signal to write the first initialization signal to the fourth node; the second light emission control module writes the first initialization signal to the first and second poles of the driving transistor in response to the second enable signal.

the write frame further includes a second reset phase, the second reset phase being located between the first reset phase and the data write phase;

in the second reset phase, the second initialization module responds to the fourth control signal and writes the second initialization signal to the grid electrode of the driving transistor.

Optionally, in some embodiments of the present application, the first control signal and the third control signal are different signals.

Optionally, in some embodiments of the present application, the driving timing of the pixel driving circuit further includes a third reset phase and a light-emitting phase after the data writing phase;

in the data writing stage, the data writing module responds to the first control signal and the second control signal to transmit the compensated data signal to the grid electrode of the driving transistor;

in the third reset phase, the first light emitting control module writes the first power signal to a first pole and a second pole of the driving transistor in response to the first enable signal;

in the light emitting stage, the first light emitting control module responds to the first enabling signal and the second light emitting control module responds to the second enabling signal to control the light emitting device to emit light.

Optionally, in some embodiments of the present application, the data writing module is further configured to write the data signal to the first and second poles of the driving transistor at least once in the holding frame.

In a second aspect, the present application further provides a display panel, where the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a pixel driving circuit as set forth in any one of the above.

The application provides a pixel driving circuit and a display panel. The pixel driving circuit comprises a first light emitting control module, a driving transistor, a second light emitting control module, a data writing module and a first initialization module. According to the method, before a data writing stage, a first power supply signal is written into the first pole and the second pole of the driving transistor through the first light emitting control module, or the first initialization signal is written into the first pole and the second pole of the driving transistor through the first initialization module and the second light emitting control module, the electric potentials of the first pole and the second pole of the driving transistor are reset, so that the gate source voltage of the driving transistor is changed, the reset effect of the driving transistor in a writing frame is adjusted, the difference of the characteristic reset effect of the driving transistor in the writing frame and the holding frame can be reduced, the brightness difference of the writing frame and the holding frame is further reduced, and the picture flicker is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a first circuit structure of a pixel driving circuit provided in the present application;

FIG. 2 is a signal timing diagram of a write frame of the pixel drive circuit shown in FIG. 1;

fig. 3 is a schematic diagram of a second circuit structure of the pixel driving circuit provided in the present application;

FIG. 4 is a signal timing diagram of a write frame of the pixel drive circuit shown in FIG. 3;

fig. 5 is a signal timing diagram of a write frame and a hold frame of the pixel driving circuit shown in fig. 1;

fig. 6 is a schematic structural diagram of a display panel provided in the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be interpreted as indicating or implying a relative importance or number of technical features indicated. Thus, features defining "first" and "second", etc., may explicitly or implicitly include one or more of such features and thus should not be construed as limiting the application. Furthermore, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "connected" should be interpreted broadly, and may be, for example, mechanically connected or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

The present application provides a pixel driving circuit and a display panel, which are described in detail below. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present application.

Referring to fig. 1 to 3, fig. 1 is a schematic diagram of a first circuit structure of a pixel driving circuit provided in the present application, fig. 2 is a signal timing diagram of a writing frame of the pixel driving circuit shown in fig. 1, and fig. 3 is a schematic diagram of a second circuit structure of the pixel driving circuit provided in the present application. In the embodiment of the present application, the pixel driving circuit 100 includes a first light emitting control module 101, a driving transistor TD, a second light emitting control module 102, a data writing module 103, and a first initializing module 105.

The control terminal of the first light emitting control module 101 is connected to the first enable signal em_l. An input terminal of the first light emitting control module 101 is connected to the first power signal ELVDD. The output terminal of the first light emitting control module 101 is electrically connected to the first node a.

Wherein the first light emitting control module 101 includes, but is not limited to, a first transistor T1. The gate of the first transistor T1 is connected to the first enable signal em_l. One of the source and the drain of the first transistor T1 is connected to the first power signal ELVDD. The other of the source and the drain of the first transistor T1 is electrically connected to the first node a.

The first pole of the driving transistor TD is electrically connected to the first node a. The second pole of the driving transistor TD is electrically connected to the second node B. The gate of the driving transistor TD is electrically connected to the third node Q.

Wherein the first electrode is one of the source or the drain of the driving transistor TD, and the second electrode is the other of the source or the drain of the driving transistor TD.

The control terminal of the second light emitting control module 102 is connected to the second enable signal em_r. The input of the second light emitting control module 102 is electrically connected to the second node B. The output terminal of the second light emitting control module 102 is electrically connected to the fourth node C, i.e. to the output terminal of the first initialization module 105.

Wherein the second light emitting control module 102 includes, but is not limited to, a second transistor T2. The gate of the second transistor T2 is connected to the second enable signal em_r. One of the source and the drain of the second transistor T2 is electrically connected to the second node B. The other of the source and the drain of the second transistor T2 is electrically connected to the fourth node C.

The first control terminal of the data writing module 103 is connected to the first control signal PScan (n). A second control terminal of the data writing module 103 is connected to the second control signal nsan (n+10). The input of the Data writing module 103 is connected to the Data signal Data. The data writing module 103 is further electrically connected to the first node a, the second node B, and the third node Q.

The data writing module 103 includes, but is not limited to, a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is connected to the first control signal PScan (n). One of the source and the drain of the third transistor T3 is connected to the Data signal Data. The other of the source and the drain of the third transistor T3 is electrically connected to the first node a. The gate of the fourth transistor T4 is connected to the second control signal nsan (n+10). One of the source and the drain of the fourth transistor T4 is electrically connected to the second node B. The other of the source and the drain of the fourth transistor T4 is electrically connected to the third node Q.

The control terminal of the first initialization module 105 is connected to the third control signal PScan (n)/PScan (n-1). The input of the first initialization module 105 is connected to a first initialization signal Vi1.

Wherein the first initialization module 105 includes, but is not limited to, a sixth transistor T6. The gate of the sixth transistor T6 is connected to the third control signal PScan (n)/PScan (n-1). One of the source and the drain of the sixth transistor T6 is connected to the first initialization signal Vi1. The other of the source and the drain of the sixth transistor T6 is electrically connected to the fourth node C.

In the embodiment of the present application, the driving timing of the pixel driving circuit 100 includes a write frame and a hold frame. The write frame includes a first reset phase M1 and a data write phase M2, which are sequentially performed. In the first reset phase M1, the first and second poles of the driving transistor TD are written with the first power signal ELVDD or the first initialization signal Vi1.

Wherein the write frame comprises one subframe and the hold frame comprises at least one subframe. It is understood that the display panel may include a variety of display frequencies, such as 30Hz, 60Hz, 120Hz, etc. For example, with reference to 120Hz, when the display panel displays at 120Hz, the driving timing of the pixel driving circuit 100 includes only a writing frame including one sub-frame. When the display panel displays at 30Hz, the driving timing of the pixel driving circuit 100 includes a write frame and a hold frame. The write frame includes one subframe, and the hold frame includes 3 subframes. That is, when the display panel is displaying at 120Hz, one frame of the display screen includes one subframe. When the display panel displays at 30Hz, for low frequency display, one frame of display screen includes 3 subframes. The pixel driving circuit 100 writes the compensated Data signal Data to the gate of the driving transistor TD only in the write frame.

According to the embodiment of the application, before the data writing stage M2, the first power supply signal ELVDD is written into the first pole and the second pole of the driving transistor DT through the first light emitting control module 101, or the first initialization signal Vi1 is written into the first pole and the second pole of the driving transistor TD through the first initialization module 105 and the second light emitting control module 102, and the electric potentials of the first pole and the second pole of the driving transistor TD are reset, so that the reset effect of the driving transistor TD in a writing frame is adjusted by changing the gate-source voltage Vgs of the driving transistor TD, the characteristic reset effect difference of the driving transistor TD in the first subframe of the writing frame and the first subframe of the holding frame is reduced, the brightness difference of the first subframe of the writing frame and the first subframe of the holding frame is further reduced, and the picture flicker is improved.

In some embodiments of the present application, the pixel driving circuit 100 further includes a first initialization module 104, a first capacitor Cst, and a light emitting device D.

The control terminal of the first initialization module 104 is connected to the fourth control signal PScan (n)/PScan (n-1). The input of the first initialization module 104 is connected to the second initialization signal Vi2. The output of the first initialization module 104 is connected to the fourth node C.

Wherein the first initialization module 104 includes, but is not limited to, a sixth transistor T6. The gate of the sixth transistor T6 is connected to the fourth control signal PScan (n)/PScan (n-1). One of the source and the drain of the sixth transistor T6 is connected to the second initialization signal Vi2. The other of the source and the drain of the sixth transistor T6 is connected to the fourth node C.

One electrode of the first capacitor Cst is connected to the third node Q. The other electrode plate of the first capacitor Cst is connected to the first power supply signal ELVDD.

One end of the light emitting device D is connected to the fourth node C. The other end of the light emitting device D is connected to the second power signal VSS.

Wherein, the voltage of the first power signal ELVDD is greater than the voltage of the second power signal VSS. The light emitting device D may be a mini light emitting diode, a micro light emitting diode, or an organic light emitting diode, which is not particularly limited in this application.

It should be noted that, the transistors used in all embodiments of the present application may be thin film transistors, field effect transistors, or other devices with the same characteristics, and the source and the drain of the transistors used herein are symmetrical, so the source and the drain of the transistors may be interchanged. In the embodiment of the present application, to distinguish between two electrodes of the transistor except the gate, one electrode is referred to as a source electrode and the other electrode is referred to as a drain electrode. The middle terminal of the switching transistor is defined as a gate, the signal input terminal is a drain, and the output terminal is a source according to the form in the figure. In addition, the transistors used in the embodiments of the present application may include two types of P-type transistors and/or N-type transistors, where the P-type transistors are turned on when the gate is at a low level, turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level, and turned off when the gate is at a low level.

In addition, in order to improve the performance of the pixel driving circuit 100, the transistors provided in the embodiments of the present application are a low-temperature polysilicon thin film transistor and an oxide semiconductor thin film transistor, wherein the oxide semiconductor thin film transistor may be an oxide thin film transistor, such as an indium gallium zinc oxide thin film transistor. In this embodiment, the thin film transistors of the two types are applied to the same pixel driving circuit 100, so that the oxide thin film transistor is used as a device with larger leakage current in the pixel driving circuit 100, so as to effectively prevent the charge at the gate of the corresponding driving transistor TD from leaking away during low-frequency driving, and further prevent the problem of screen flash of the display screen.

Specifically, the following embodiments of the present application will take the first transistor T1, the driving transistor TD, the second transistor T2, the third transistor T3 and the sixth transistor T6 in the pixel driving circuit 100 as P-type low-temperature polycrystalline silicon transistors, and the fourth transistor T4 and the fifth transistor T5 as N-type oxide transistors as examples, but the present application is not limited thereto.

With continued reference to fig. 1 and 2, in some embodiments of the present application, the holding frame includes at least one subframe, and if the brightness of the writing frame is smaller than the brightness of the first subframe of the holding frame, in the first reset phase M1, the first light emitting control module 101 responds to the first enable signal em_l to write the first power signal ELVDD to the first and second poles of the driving transistor TD.

Specifically, in the first reset phase M1, the first enable signal em_l is low, and the first transistor T1 is turned on. The first power signal ELVDD is written to the first and second poles of the driving transistor TD through the first transistor T1 and the driving transistor TD.

Further, in the first reset phase M1, the second initialization module 104 writes the second initialization signal Vi2 to the gate of the driving transistor TD in response to the fourth control signal nsan (n).

Specifically, in the first reset phase M1, the fourth control signal nsan (n) is high, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written to the gate of the driving transistor TD via the fifth transistor T5.

That is, in the embodiment of the present application, both the first light emitting control module 101 and the second initialization module 104 operate in the first reset phase M1. Of course, by controlling the timing of the fourth control signal nsan (n) and the first enable signal em_l, the first light emitting control module 101 and the second initialization module 104 may also be controlled to operate in stages, which is not particularly limited in this application.

It will be appreciated that writing the first power supply signal ELVDD to the first and second poles of the driving transistor TD may cause the gate-source voltage Vgs of the driving transistor TD to be at a fixed value, i.e., vgs=vgd=v2-ELVDD. Since the voltage value of the first power supply signal ELVDD is large, the voltage difference of Vgs/Vgd is increased, that is, the characteristic reset effect of the driving transistor Td is increased, the brightness of the writing frame can be effectively improved, and the flicker caused by the low brightness of the writing frame can be improved.

In the embodiment of the present application, in the Data writing stage M2, the Data writing module 103 transmits the compensated Data signal Data to the third node Q in response to the first control signal PScan (n) and the second control signal NScan (n+10), that is, writes the compensated Data signal into the gate of the driving transistor TD.

Specifically, in the data writing stage M2, the first control signal PScan (n) is at a low level, the second control signal NScan (n+10) is at a high level, and both the third transistor T3 and the fourth transistor T4 are turned on. The data writing phase M2 includes compensation of the threshold voltage of the driving transistor TD. Therefore, the third node Q writes the compensated data signal, specifically vdata+vth. Wherein Vth is a threshold voltage of the driving transistor.

In the embodiment of the present application, the first control signal PScan (n) and the third control signal PScan (n) are the same signal. Then in the data writing phase M2 the first initialization module 105 and the data writing module 103 operate simultaneously. The first initialization module 105 writes the first initialization signal Vi1 into the fourth node C in response to the third control signal PScan (n), thereby realizing the reset of the anode of the light emitting device D and improving the display uniformity.

Specifically, in the data writing stage M2, the third control signal PScan (n) is at a low level, and the sixth transistor T6 is turned on. The first initialization signal Vi1 is written to the fourth node C via the sixth transistor T6.

In the embodiment of the present application, the driving timing of the pixel driving circuit 100 further includes a third reset stage M3 and a light emitting stage M4 after the data writing stage M2.

In the third reset phase M3, the first light emitting control module 101 writes the first power signal ELVDD to the first and second poles of the driving transistor TD in response to the first enable signal em_l.

Specifically, in the third reset phase M3, the first enable signal em_l is low, and the first transistor T1 is turned on. The first power signal ELVDD is written to the first and second poles of the driving transistor TD through the first transistor T1 and the driving transistor TD.

It can be appreciated that in the third reset phase M3, the first power signal ELVDD is transmitted to the first and second poles of the driving transistor TD using the first light emitting control module 101. Thus, the pixel driving circuit 100 can reset the potentials of the first and second poles of the driving transistor TD to the same value under different Data signals Data, reducing the influence on the characteristics of the driving transistor DT.

In the light emitting stage M4, the first light emitting control module 101 responds to the first enable signal em_l and the second light emitting control module 102 responds to the second enable signal em_r to control the light emitting device D to emit light.

Specifically, in the light emitting stage M4, the first enable signal em_l and the second enable signal em_r are both low, and the first transistor T1 and the second transistor T2 are both turned on. The current flows through the first transistor T1, the driving transistor TD, and the second transistor T2 to the light emitting device D, so that the light emitting device D emits light normally.

In some embodiments of the present application, the pixel driving circuit 100 further includes a second capacitor Cboost. One plate of the second capacitor Cboost is electrically connected to the third node Q. The other plate of the second capacitor Cboost is connected to the first control signal PScan (n).

The function of the second capacitor Cboost is to regulate the potential of the third node Q, i.e. the potential of the gate of the drive transistor TD. Thereby changing the variation range of different Data signals Data and improving the phenomenon of picture flickering caused by larger leakage current of the display panel.

Referring to fig. 3 and 4, fig. 4 is a signal timing diagram of a write frame of the pixel driving circuit shown in fig. 3. The pixel driving circuit 100 shown in fig. 3 is different from the pixel driving circuit 100 shown in fig. 1 in that, in the embodiment of the present application, the holding frame includes at least one subframe, and if the brightness of the writing frame is greater than the brightness of the first subframe of the holding frame, in the first reset phase M1, the first initialization module 105 writes the first initialization signal Vi1 to the fourth node C in response to the third control signal PScan (n-1). The second light emission control module 102 writes the first initialization signal Vi1 to the first and second poles of the driving transistor TD in response to the second enable signal em_r.

Specifically, in the first reset phase M1, the third control signal PScan (n-1) and the second enable signal em_r are both low, the sixth transistor T6 and the second transistor T2 are turned on, and the first initialization signal Vi1 is written to the first and second poles of the driving transistor TD through the sixth transistor T6 and the second transistor T2.

In the embodiment of the present application, the write frame further includes a second reset phase M5, where the second reset phase M5 is located between the first reset phase M1 and the data write phase M2.

In the second reset phase M5, the second initialization module 104 writes the second initialization signal Vi2 to the gate of the driving transistor TD in response to the fourth control signal nsan (n), thereby completing the initialization of the gate of the driving transistor TD.

Specifically, in the second reset phase M5, the fourth control signal nsan (n) is high, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written to the gate of the driving transistor TD via the fifth transistor T5.

It will be appreciated that writing the first initialization signal Vi1 to the first and second poles of the drive transistor TD may cause the gate-source voltage Vgs of the drive transistor TD to be at a fixed value vgs=vgd=v2-Vi 1. Since the voltage value of the first initialization signal Vi1 is smaller, the voltage difference of Vgs/Vgd is reduced, that is, the characteristic reset effect of the driving transistor Td is reduced, the brightness of the writing frame can be effectively reduced, and the flicker caused by the higher brightness of the writing frame can be improved.

In the embodiment of the present application, the first control signal PScan (n) and the third control signal PScan (n-1) are different signals.

It can be appreciated that when the first initialization signal Vi1 is written to the first and second poles of the driving transistor TD in the first reset phase M1, the first initialization module 105 and the second light emission control module 102 are required to operate simultaneously. And the data writing phase M2 follows the first reset phase M1. Therefore, the first control signal PScan (n) and the third control signal PScan (n-1) are different signals, thereby ensuring normal operation of the pixel driving circuit 100.

In the embodiment of the present application, the driving timing of the pixel driving circuit 100 further includes a third reset stage M3 and a light emitting stage M4 after the data writing stage M2, and the above embodiments can be referred to, and the details are not repeated here.

In the embodiment of the present application, the Data writing module 103 is further configured to write the Data signal Data to the first and second poles of the driving transistor TD at least once in the hold frame.

Specifically, referring to fig. 3 and 5, fig. 5 is a signal timing diagram of a write frame and a hold frame of the pixel driving circuit shown in fig. 3. The embodiments of the present application are described taking the example that the holding frame includes two subframes, namely, the first subframe and the second subframe.

The signal timing of the first subframe and the second subframe are the same. The difference from the write frame is that the driving timing of the pixel driving circuit 100 does not include the first reset period M1 in the first sub-frame or the second sub-frame. And in the data writing stage M2, the fourth control signal nsan (n) is always maintained at the low level, and the fourth transistor T4 and the fifth transistor T5 are always turned off. When the first control signal PScan (n) is low, the third transistor T3 is turned on, and the Data writing module 103 writes the Data signal Data to the first and second poles of the driving transistor TD, i.e., resets the first and second poles of the driving transistor TD. It is known that the first and second poles of the driving transistor TD are reset in each sub-frame of the sustain frame.

In the first or second sub-frame, the gate of the driving transistor TD holds the Data signal Data written in the writing frame. The Data signal Data written in the write frame and the Data signal Data written in the hold frame are not identical.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment also provides a display panel 1000, which includes a plurality of pixel units 110 arranged in an array. Each pixel unit 110 includes the pixel driving circuit 100 described in any of the above embodiments, and the detailed description is omitted herein.

In the embodiment of the present application, the display panel 1000 may be an OLED (Organic Light-Emitting Diode) display panel, a Mini LED (Mini Light-Emitting Diode) display panel, a Micro LED (Micro Light-Emitting Diode) display panel, or the like.

In the display panel 1000 provided in the embodiment of the present application, the pixel driving circuit 100 includes a first light emitting control module, a driving transistor, a second light emitting control module, a data writing module, a second initializing module, a first capacitor, and a light emitting device. According to the embodiment of the application, before the data writing stage, the first power supply signal or the first initialization signal is written into the first pole and the second pole of the driving transistor in the first resetting stage, the resetting effect of the driving transistor in the writing frame can be adjusted by changing the gate source voltage of the driving transistor, the difference of the characteristic resetting effect of the driving transistor in the writing frame and the holding frame is reduced, the brightness difference of the writing frame and the holding frame is further reduced, and the picture flicker is improved.

The pixel driving circuit and the display panel provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A pixel driving circuit, comprising:

a driving transistor;

2. The pixel driving circuit according to claim 1, wherein the holding frame includes at least one sub-frame, and the first light emitting control module writes the first power signal to the first and second poles of the driving transistor in response to the first enable signal in the first reset phase if the brightness of the writing frame is smaller than the brightness of the first sub-frame of the holding frame.

3. The pixel driving circuit according to claim 2, wherein the first control signal and the third control signal are the same signal.

4. The pixel driving circuit according to claim 2, further comprising a second initialization module, wherein a control terminal of the second initialization module is connected to a fourth control signal, an input terminal of the second initialization module is connected to a second initialization signal, and an output terminal of the second initialization module is electrically connected to a gate of the driving transistor;

5. The pixel driving circuit according to claim 1, wherein the holding frame includes at least one sub-frame, and the first initialization module is responsive to the third control signal and the second light emitting control module is responsive to the second enable signal to write the first initialization signal to the first and second poles of the driving transistor in the first reset phase if the brightness of the writing frame is greater than the brightness of the first sub-frame of the holding frame.

6. The pixel driving circuit according to claim 5, further comprising a second initialization module, wherein a control terminal of the second initialization module is connected to a fourth control signal, an input terminal of the second initialization module is connected to a second initialization signal, and an output terminal of the second initialization module is electrically connected to a gate of the driving transistor;

7. The pixel driving circuit according to claim 5, wherein the first control signal and the third control signal are different signals.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein a driving timing of the pixel driving circuit further includes a third reset phase and a light-emitting phase after the data writing phase;

9. A pixel driving circuit according to any one of claims 1 to 7, wherein the data writing module is further operable to write the data signal to the first and second poles of the driving transistor at least once in the hold frame.

10. A display panel comprising a plurality of pixel cells arranged in an array, each of the pixel cells comprising a pixel driving circuit according to any one of claims 1-9.