CN117475897A - Gate driving circuit and display panel - Google Patents
Gate driving circuit and display panel Download PDFInfo
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- CN117475897A CN117475897A CN202310835862.5A CN202310835862A CN117475897A CN 117475897 A CN117475897 A CN 117475897A CN 202310835862 A CN202310835862 A CN 202310835862A CN 117475897 A CN117475897 A CN 117475897A
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- 239000003990 capacitor Substances 0.000 claims description 16
- 238000012423 maintenance Methods 0.000 claims description 3
- 101100438980 Arabidopsis thaliana CDC2C gene Proteins 0.000 description 8
- 101100274517 Arabidopsis thaliana CKL1 gene Proteins 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- 101100113626 Arabidopsis thaliana CKL2 gene Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a gate driving circuit and a display panel. The first node pull-down module pulls down the potential of the first node according to the first clock signal, the second clock signal and the first voltage; the second node pull-down module pulls down the potential of the second node according to the second clock signal and the pull-down control signal so as to enable the variable at the signal output end of the grid driving circuit to be coupled to the second node; the second node maintaining module maintains the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal; the output module outputs a grid control signal according to the potential control signal output ends of the first node and the second node. The display panel includes a plurality of sub-pixels and a plurality of gate driving circuits.
Description
Technical Field
The invention relates to the technical field of display, in particular to a grid driving circuit and a display panel.
Background
In the conventional gate driving circuit (as shown in fig. 1), the capacitor C3 is often used To maintain the gate potential of the pull-down output transistor To 2. However, when the pull-down output transistor To2 is a P-type transistor, the voltage difference between the source and the gate is smaller than the threshold voltage, so that the voltage loss is caused when the conventional gate driving circuit outputs the gate control signal Scan. That is, when the gate potential of the pull-down output transistor To2 is l+|vth|, and the drain potential is low, the source (i.e., the signal output terminal OUT) of the pull-down output transistor To2 outputs a potential l+2|vth| that satisfies the conduction condition of Vgs < Vth, so that the pull-down output transistor To2 is turned on, and thus the voltage loss of 2|vth| is output and the voltage corresponding To VGL cannot be directly output (i.e., as shown in fig. 2, the output waveform corresponds To the tail with l+2|vth|, and the output waveform can output the voltage corresponding To VGL only when the clock signal XCK is low).
Disclosure of Invention
The embodiment of the invention provides a gate driving circuit and a display panel, which can realize the maintenance of the potential of a second node and improve the problem of voltage loss of a gate control signal output by the gate driving circuit.
The embodiment of the invention provides a gate driving circuit, which comprises a first node pull-down module, a second node maintaining module and an output module.
The first node pull-down module is electrically connected with the first clock signal line, the second clock signal line, the first voltage end and the first node, and is configured to pull down the potential of the first node according to the first clock signal transmitted by the first clock signal line, the second clock signal transmitted by the second clock signal line and the first voltage transmitted by the first voltage end.
The second node pull-down module is electrically connected with the first clock signal line, the pull-down control line and the second node, and is configured to pull down the potential of the second node according to the pull-down control signals transmitted by the first clock signal and the pull-down control line, so that the variable at the signal output end of the gate driving circuit is coupled to the second node.
The second node maintaining module is electrically connected with the first clock signal line, the second clock signal line, the pull-down control line and the second node, and is configured to maintain the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal.
The output module is electrically connected with the first node and the second node, and is configured to control the signal output end to output a gate control signal according to the potentials of the first node and the second node.
Optionally, in some embodiments of the invention, the output module includes a pull-up output transistor, a pull-down output transistor, and a first capacitor. The control end of the pull-up output transistor is electrically connected with the first node, the input end of the pull-up output transistor is electrically connected with the second voltage end, and the output end of the pull-up output transistor is electrically connected with the signal output end; the control end of the pull-down output transistor is electrically connected with the second node, the input end of the pull-down output transistor is electrically connected with the first voltage end, and the output end of the pull-down output transistor is electrically connected with the signal output end; the first capacitor is connected in series between the first node and the second voltage terminal.
Optionally, in some embodiments of the present invention, the second node pull-down module includes a first transistor and a second transistor. The control end of the first transistor is electrically connected with the first clock signal line, and the input end of the first transistor is electrically connected with the pull-down control line; the control end of the second transistor is electrically connected with the first voltage end, the input end of the second transistor is electrically connected with the output end of the first transistor, and the output end of the second transistor is electrically connected with the second node.
Optionally, in some embodiments of the invention, the second node maintaining module includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.
The control end of the third transistor is electrically connected with the first clock signal line, and the input end of the third transistor is electrically connected with the pull-down control line; the control end of the fourth transistor is electrically connected with the first voltage end, and the input end of the fourth transistor is electrically connected with the output end of the third transistor; the control end of the fifth transistor is electrically connected with the output end of the fourth transistor, the input end of the fifth transistor is electrically connected with the control end of the fifth transistor, and the output end of the fifth transistor is electrically connected with the second node; the control end of the sixth transistor is electrically connected with the control end of the fifth transistor, and the input end of the sixth transistor is electrically connected with the second clock signal line; the control end and the input end of the seventh transistor are electrically connected with the output end of the sixth transistor, and the output end of the seventh transistor is electrically connected with the control end of the fifth transistor.
Optionally, in some embodiments of the present invention, the first node pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a second capacitor. The control end of the eighth transistor is electrically connected with the first clock signal line, and the input end of the eighth transistor is electrically connected with the first voltage end; the control end of the ninth transistor is electrically connected with the first voltage end, and the input end of the ninth transistor is electrically connected with the output end of the eighth transistor; the control end of the tenth transistor is electrically connected with the output end of the ninth transistor, and the input end of the tenth transistor is electrically connected with the second clock signal line; the control end of the eleventh transistor is electrically connected with the second clock signal line, the input end of the eleventh transistor is electrically connected with the output end of the tenth transistor, and the output end of the eleventh transistor is electrically connected with the first node; the second capacitor is connected in series between the control end of the tenth transistor and the output end of the tenth transistor.
Optionally, in some embodiments of the present invention, the second node maintaining module further includes a twelfth transistor, a control terminal of the twelfth transistor is electrically connected to the output terminal of the eighth transistor, an input terminal of the twelfth transistor is electrically connected to the second voltage terminal, and an output terminal of the twelfth transistor is electrically connected to the control terminal of the seventh transistor.
Optionally, in some embodiments of the present invention, the gate driving circuit further includes a first node pull-up module, the first node pull-up module includes a thirteenth transistor, a control terminal of the thirteenth transistor is electrically connected to the output terminal of the first transistor, an input terminal of the thirteenth transistor is electrically connected to the second voltage terminal, and an output terminal of the thirteenth transistor is electrically connected to the first node.
Optionally, in some embodiments of the present invention, the first node pull-down module further includes a fourteenth transistor, a control terminal of the fourteenth transistor is electrically connected to the output terminal of the first transistor, an input terminal of the fourteenth transistor is electrically connected to the first clock signal line, and an output terminal of the fourteenth transistor is electrically connected to the output terminal of the eighth transistor.
Optionally, in some embodiments of the present invention, the gate driving circuit further includes a reset module, the reset module includes a reset transistor, a control terminal of the reset transistor is electrically connected to the reset control line, an input terminal of the reset transistor is electrically connected to the second voltage terminal, and an output terminal of the reset transistor is electrically connected to the output terminal of the first transistor.
The invention also provides a display panel, which comprises a plurality of any grid driving circuits; and a plurality of sub-pixels electrically connected with the gate driving circuits.
The invention provides a gate driving circuit and a display panel. The first node pull-down module pulls down the potential of the first node according to the first clock signal, the second clock signal and the first voltage; the second node pull-down module pulls down the potential of the second node according to the second clock signal and the pull-down control signal so as to enable the variable at the signal output end of the grid driving circuit to be coupled to the second node; the second node maintaining module maintains the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal; the output module outputs a grid control signal according to the potential control signal output ends of the first node and the second node. By enabling the gate driving circuit to comprise the second node pull-down module, when the second node potential is pulled down, the variable of the signal output end can be coupled to the second node, so that the second node potential is pulled down further, and the voltage loss of the gate control signal output by the output module is reduced. By providing the second node maintaining module, the potential of the second node can be maintained at a low potential after being pulled down. The display panel includes a plurality of sub-pixels and a plurality of gate driving circuits.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a conventional gate driving circuit;
FIG. 2 is a timing diagram corresponding to FIG. 1;
fig. 3 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 4 is a timing chart corresponding to the gate driving circuit shown in fig. 3 according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a display panel according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the invention. In the present invention, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
Specifically, as shown in fig. 3, a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention is shown; the embodiment of the invention provides a gate driving circuit, which comprises a first node pull-down module 100, a second node pull-down module 200, a second node maintaining module 300 and an output module 400.
The first node pull-down module 100 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first voltage terminal VGL, and the first node N1, and the first node pull-down module 100 is configured to pull down the potential of the first node N1 according to the first clock signal CK transmitted by the first clock signal line CKL1, the second clock signal XCK transmitted by the second clock signal line CKL2, and the first voltage transmitted by the first voltage terminal VGL.
The second node pull-down module 200 is electrically connected to the first clock signal line CKL1, the pull-down control line InL, and the second node N2, and the second node pull-down module 200 is configured to pull down the potential of the second node N2 according to the pull-down control signal In transmitted by the first clock signal CK and the pull-down control line InL, so that the variable of the signal output end Out of the gate driving circuit is coupled to the second node N2.
The second node maintaining module 300 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the pull-down control line InL and the second node N2, and the second node maintaining module 300 is configured to maintain the potential of the second node N2 according to the first clock signal CK, the second clock signal XCK and the pull-down control signal In.
The output module 400 is electrically connected to the first node N1 and the second node N2, and the output module 400 is configured to control the signal output terminal Out to output the gate control signal Scan according to the potentials of the first node N1 and the second node N2.
By setting the second node pull-down module 200 to enable the variable of the signal output terminal Out to be coupled to the second node N2 when the potential of the second node N2 is pulled down, so as to further pull down the potential of the second node N2, the output module 400 can quickly transmit the first voltage to the signal output terminal Out according to the potential of the second node N2, so as to shorten the period of time for changing the gate control signal Scan from high level to low level, and avoid the voltage loss of 2|vth| of the gate control signal Scan from high level to low level. Where Vth is the threshold voltage of the pull-down output transistor To2 included in the output module 400.
Optionally, referring To fig. 3, the output module 400 includes a pull-up output transistor To1, a pull-down output transistor To2, and a first capacitor C1.
The control end of the pull-up output transistor To1 is electrically connected with the first node N1, the input end of the pull-up output transistor To1 is electrically connected with the second voltage end VGH, and the output end of the pull-up output transistor To1 is electrically connected with the signal output end Out; the pull-up output transistor To1 transmits the second voltage output from the second voltage terminal VGH To the signal output terminal Out according To the potential of the first node N1.
The control end of the pull-down output transistor To2 is electrically connected with the second node N2, the input end of the pull-down output transistor To2 is electrically connected with the first voltage end VGL, and the output end of the pull-down output transistor To2 is electrically connected with the signal output end Out; the pull-down output transistor To2 transmits the first voltage output from the first voltage terminal VGL To the signal output terminal Out according To the potential of the second node N2.
The first capacitor C1 is connected in series between the first node N1 and the second voltage terminal VGH, and the first capacitor C1 is configured to maintain the potential of the first node N1.
Optionally, the first voltage is smaller than the second voltage, so that when the pull-down output transistor To2 is turned on, the gate control signal Scan output by the gate driving circuit is pulled down from the first voltage To the second voltage.
Optionally, referring to fig. 3, the second node pull-down module 200 includes a first transistor T1 and a second transistor T2.
The control end of the first transistor T1 is electrically connected to the first clock signal line CKL1, the input end of the first transistor T1 is electrically connected to the pull-down control line InL, and the output end of the first transistor T1 is electrically connected to the input end of the second transistor T2. The first transistor T1 transmits a pull-down control signal In to an input terminal of the second transistor T2 according to the first clock signal CK.
The control end of the second transistor T2 is electrically connected to the first voltage end VGL, the output end of the second transistor T2 is electrically connected to the second node N2, and the second transistor T2 is configured to make the potential of the second node N2 be the sum of the first voltage and the threshold voltage of the second transistor T2 when the pull-down control signal In is transmitted to the input end of the second transistor T2.
Optionally, referring to fig. 3, the second node maintaining module 300 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
The control end of the third transistor T3 is electrically connected to the first clock signal line CKL1, the input end of the third transistor T3 is electrically connected to the pull-down control line InL, and the output end of the third transistor T3 is electrically connected to the input end of the fourth transistor T4; the third transistor T3 transmits a pull-down control signal In to the input terminal of the fourth transistor T4 according to the first clock signal CK.
The control end of the fourth transistor T4 is electrically connected to the first voltage end VGL, and the output end of the fourth transistor T4 is electrically connected to the control end of the fifth transistor T5; the fourth transistor T4 is configured to transmit a pull-down control signal In to the control terminal of the fifth transistor T5 to control on and off of the fifth transistor T5.
The input end of the fifth transistor T5 is electrically connected to the control end of the fifth transistor T5, and the output end of the fifth transistor T5 is electrically connected to the second node N2; the fifth transistor T5 is configured to make the potential of the second node N2 be a sum of the first voltage and a threshold voltage of the fifth transistor T5 when the pull-down control signal In is transmitted to the input terminal of the fifth transistor T5.
The control end of the sixth transistor T6 is electrically connected to the control end of the fifth transistor T5, the input end of the sixth transistor T6 is electrically connected to the second clock signal line CKL2, the output end of the sixth transistor T6 is electrically connected to the control end and the input end of the seventh transistor T7, and the output end of the seventh transistor T7 is electrically connected to the control end of the fifth transistor T5; the sixth transistor T6 transmits the second clock signal XCK to the control terminals of the seventh transistor T7 and the fifth transistor T5 according to the pull-down control signal In.
Optionally, referring to fig. 3, the first node pull-down module 100 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2.
The control end of the eighth transistor T8 is electrically connected to the first clock signal line CKL1, the input end of the eighth transistor T8 is electrically connected to the first voltage end VGL, and the output end of the eighth transistor T8 is electrically connected to the input end of the ninth transistor T9.
The control end of the ninth transistor T9 is electrically connected to the first voltage end VGL, and the output end of the ninth transistor T9 is electrically connected to the control end of the tenth transistor T10.
An input terminal of the tenth transistor T10 is electrically connected to the second clock signal line CKL2, and an output terminal of the tenth transistor T10 is electrically connected to an input terminal of the eleventh transistor T11.
The control end of the eleventh transistor T11 is electrically connected to the second clock signal line CKL2, and the output end of the eleventh transistor T11 is electrically connected to the first node N1.
The second capacitor C2 is connected in series between the control terminal of the tenth transistor T10 and the output terminal of the tenth transistor T10.
Optionally, referring to fig. 3, the second node maintaining module 300 further includes a twelfth transistor T12, a control terminal of the twelfth transistor T12 is electrically connected to the output terminal of the eighth transistor T8, an input terminal of the twelfth transistor T12 is electrically connected to the second voltage terminal VGH, and an output terminal of the twelfth transistor T12 is electrically connected to the control terminal of the seventh transistor T7; the twelfth transistor T12 controls on or off of the seventh transistor T7 by a second voltage.
Optionally, referring to fig. 3, the gate driving circuit further includes a first node pull-up module 500, where the first node pull-up module 500 includes a thirteenth transistor T13, a control end of the thirteenth transistor T13 is electrically connected to the output end of the first transistor T1, an input end of the thirteenth transistor T13 is electrically connected to the second voltage end VGH, and an output end of the thirteenth transistor T13 is electrically connected to the first node N1; the thirteenth transistor T13 pulls up the potential of the first node N1 by a second voltage.
Optionally, referring to fig. 3, the first node pull-down module 100 further includes a fourteenth transistor T14, a control terminal of the fourteenth transistor T14 is electrically connected to the output terminal of the first transistor T1, an input terminal of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1, and an output terminal of the fourteenth transistor T14 is electrically connected to the output terminal of the eighth transistor T8.
Optionally, the fourteenth transistor is a dual gate transistor to reduce leakage current.
Optionally, referring to fig. 3, the gate driving circuit further includes a reset module 600, the reset module 600 includes a reset transistor Tin, a control terminal of the reset transistor Tin is electrically connected to the reset control line RL, an input terminal of the reset transistor Tin is electrically connected to the second voltage terminal VGH, and an output terminal of the reset transistor Tin is electrically connected to the output terminal of the first transistor T1; the reset transistor Tin resets the potential of the output terminal of the first transistor T1 according to the reset control signal Rst transmitted by the reset control line RL.
Fig. 4 is a timing chart corresponding to the gate driving circuit shown in fig. 3 according to an embodiment of the present invention, and an operation principle of the gate driving circuit is described below by taking P-type transistors as examples of transistors included in the gate driving circuit.
First stage t1: the second clock signal XCK and the pull-down control signal In are low, and the first clock signal CK and the reset control signal Rst are high.
The eleventh transistor T11 is turned on according To the second clock signal XCK, the control terminal of the tenth transistor T10 is turned on by maintaining the previous stage at the low level, the input terminal of the tenth transistor T10 transmits the second clock signal XCK To the first node N1 To turn on the pull-up output transistor To1, and the second voltage is output To the signal output terminal Out through the pull-up output transistor To 1. The second clock signal XCK is coupled to the control terminal of the twelfth transistor T12 via the second capacitor C2 to turn on the twelfth transistor T12, and the second voltage is transmitted to the control terminal of the seventh transistor T7 via the twelfth transistor T12 to turn off the seventh transistor T7. The reset transistor Tin is turned off according To the reset control signal Rst, the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned off according To the first clock signal CK, and the control terminals of the fifth transistor T5, the sixth transistor T6, the thirteenth transistor T13, the fourteenth transistor T14 and the pull-down output transistor To2 are turned off by maintaining a high level of a previous stage.
Second stage t2: the pull-down control signal In is low, and the first clock signal CK, the second clock signal XCK, and the reset control signal Rst are high.
The eleventh transistor T11 is turned off according To the second clock signal XCK, the first capacitor C1 maintains the pull-up output transistor To1 To be turned on, and the second voltage is output To the signal output terminal Out through the pull-up output transistor To 1. The reset transistor Tin is turned off according To the reset control signal Rst, the first transistor T1, the third transistor T3, and the eighth transistor T8 are turned off according To the first clock signal CK, and the fifth transistor T5, the sixth transistor T6, the double gate seventh transistor T7, the thirteenth transistor T13, the fourteenth transistor T14, and the pull-down output transistor To2 remain turned off.
Third stage t3: the first clock signal CK and the pull-down control signal In are low, and the second clock signal XCK and the reset control signal Rst are high.
The first transistor T1, the third transistor T3 and the eighth transistor T8 are turned on, and the pull-down control signal In is transmitted To the control terminals of the pull-down output transistor To2, the thirteenth transistor T13 and the fourteenth transistor T14 through the first transistor T1, so that the potential of the control terminal of the pull-down output transistor To2 becomes the sum of the first voltage and the threshold voltage of the third transistor T3 (i.e., l+|vth_t3|). The third transistor T3 is turned on to turn on the fifth transistor T5 and the sixth transistor T6, and the potential of the control terminal of the fifth transistor T5 becomes the sum of the first voltage and the threshold voltage of the fourth transistor T4. Since the P-type transistor needs To be turned on under the condition that the gate-source voltage difference is smaller than the threshold voltage, when the potential of the control terminal of the pull-down output transistor To2 is the sum of the first voltage and the threshold voltage of the third transistor T3, the potential of the signal output terminal Out needs To be 2 times the sum of the first voltage and the threshold voltage of the third transistor T3 (i.e., l+2|vth_t3|). The signal output Out is thus changed from the second voltage of the second phase t2 to l+2|vth_t3| of the third phase t3, so that the signal output Out has a voltage variation of l+2|vth_t3| -H. The signal output terminal Out has a voltage variation amount coupled To the control terminal of the pull-down output transistor To2 through parasitic capacitance between the gate and source of the pull-down output transistor To2, so that the potential of the control terminal of the pull-down output transistor To2 is pulled down To a lower potential from l+|vth_t3|, thereby making the pull-down output transistor To2 fully turned on, and the first voltage can be output To the signal output terminal Out through the pull-down output transistor To2, so that the gate control signal Scan output by the gate driving circuit bypasses the voltage loss of 2|vth| when being converted from the second voltage To the output of the first voltage. The fourteenth transistor T14 and the eighth transistor T8 are turned on, so that the tenth transistor T10 and the twelfth transistor T12 are turned on. The twelfth transistor T12 and the sixth transistor T6 are turned on such that the seventh transistor T7 is turned off. The thirteenth transistor T13 is turned on such that the second voltage is transmitted To the control terminal of the pull-up output transistor To1 To control the pull-up output transistor To1 To be turned off. Where H represents a voltage value corresponding to the first voltage, L represents a voltage value corresponding to the second voltage, and vth_t3 represents a threshold voltage of the third transistor T3.
Fourth stage t4: the pull-down control signal In is low, and the first clock signal CK, the second clock signal XCK, and the reset control signal Rst are high.
The first transistor T1, the third transistor T3, and the eighth transistor T8 are turned off according to the first clock signal CK, and the eleventh transistor T11 is turned off according to the second clock signal XCK. The first capacitor C1 maintains the pull-up output transistor To1 To be turned off, the thirteenth transistor T13 and the pull-down output transistor To2 To be turned on, the first voltage is transmitted To the signal output terminal Out, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the fourteenth transistor T14 To be turned on, the first clock signal CK charges the second capacitor C2 To raise the potentials of the control terminals of the tenth transistor T10 and the twelfth transistor T12, and the second clock signal XCK is transmitted To the control terminal of the seventh transistor T7 via the sixth transistor T6 To turn off the seventh transistor T7. The reset transistor Tin is turned off according to the reset control signal Rst.
In the fifth stage t5, the second clock signal XCK and the pull-down control signal In are low, and the first clock signal CK and the reset control signal Rst are high.
The fifth transistor T5 and the sixth transistor T6 are kept on (i.e., the potential of the control terminal of the fifth transistor T5 and the sixth transistor T6 is the sum l+|vth_t4|) of the first voltage and the threshold voltage of the fourth transistor T4), so the second clock signal XCK makes the potential of the control terminal of the seventh transistor T7 become l+2|vth_t4| through the sixth transistor T6, and thus the voltage variation amount of the control terminal of the seventh transistor T7 generated by the high level H1 of the fourth stage T4 becomes l+|vth_t4| of the fifth stage T5 becomes l+2|vth_t4| -H1. The voltage variation of the control terminal of the seventh transistor T7 couples the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 through the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the seventh transistor T7, so that the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 are changed from the original l+|vth_t4 to a lower potential, and then the potential of the control terminal of the seventh transistor T7 is further reduced from l+2|vth_t4|, and then the potentials of the control terminals of the fifth transistor T5 and the sixth transistor T6 are further reduced again through the coupling of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the seventh transistor T7. Since the control terminal and the input terminal of the fifth transistor are shorted, the control terminal and the input terminal of the fifth transistor T5 are equipotential, and the potential of the control terminal of the pull-down output transistor To2 can be coupled through the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the fifth transistor T5, so that the potential of the control terminal of the pull-down output transistor To2 is further reduced, thereby ensuring that the signal output terminal Out can stably output a low level for a long time.
Fig. 5 is a schematic diagram of a display panel according to an embodiment of the invention. The invention also provides a display panel, which comprises a plurality of any grid driving circuits; and a plurality of sub-pixels electrically connected with the gate driving circuits.
Optionally, the plurality of gate driving circuits are arranged in cascade, and the plurality of sub-pixels are electrically connected with the plurality of gate driving circuits through a plurality of gate control lines.
It is understood that the display panel includes a liquid crystal display panel, a self-luminous display panel (including a light emitting device of an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.), and the like.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (10)
1. A gate driving circuit, comprising:
the first node pull-down module is electrically connected with the first clock signal line, the second clock signal line, the first voltage end and the first node and is configured to pull down the potential of the first node according to the first clock signal transmitted by the first clock signal line, the second clock signal transmitted by the second clock signal line and the first voltage transmitted by the first voltage end;
the second node pull-down module is electrically connected with the first clock signal line, the pull-down control line and the second node and is configured to pull down the potential of the second node according to the pull-down control signals transmitted by the first clock signal line and the pull-down control line so as to enable the variable of the signal output end of the grid driving circuit to be coupled to the second node;
the second node maintaining module is electrically connected with the first clock signal line, the second clock signal line, the pull-down control line and the second node and is configured to maintain the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal; and
and the output module is electrically connected with the first node and the second node and is configured to control the signal output end to output a grid control signal according to the potentials of the first node and the second node.
2. The gate drive circuit of claim 1, wherein the output module comprises:
the control end of the pull-up output transistor is electrically connected with the first node, the input end of the pull-up output transistor is electrically connected with the second voltage end, and the output end of the pull-up output transistor is electrically connected with the signal output end;
the control end of the pull-down output transistor is electrically connected with the second node, the input end of the pull-down output transistor is electrically connected with the first voltage end, and the output end of the pull-down output transistor is electrically connected with the signal output end; and
the first capacitor is connected in series between the first node and the second voltage terminal.
3. The gate driving circuit of claim 1, wherein the second node pull-down module comprises:
the control end of the first transistor is electrically connected with the first clock signal line, and the input end of the first transistor is electrically connected with the pull-down control line;
the control end of the second transistor is electrically connected with the first voltage end, the input end of the second transistor is electrically connected with the output end of the first transistor, and the output end of the second transistor is electrically connected with the second node.
4. The gate drive circuit of claim 3, wherein the second node maintenance module comprises:
a third transistor, a control end of which is electrically connected with the first clock signal line, and an input end of which is electrically connected with the pull-down control line;
a control end of the fourth transistor is electrically connected with the first voltage end, and an input end of the fourth transistor is electrically connected with an output end of the third transistor;
a fifth transistor, wherein a control end of the fifth transistor is electrically connected with an output end of the fourth transistor, an input end of the fifth transistor is electrically connected with the control end of the fifth transistor, and an output end of the fifth transistor is electrically connected with the second node;
a sixth transistor, wherein a control end of the sixth transistor is electrically connected with the control end of the fifth transistor, and an input end of the sixth transistor is electrically connected with the second clock signal line;
and the control end and the input end of the seventh transistor are electrically connected with the output end of the sixth transistor, and the output end of the seventh transistor is electrically connected with the control end of the fifth transistor.
5. The gate driving circuit of claim 4, wherein the first node pull-down module comprises:
an eighth transistor, wherein a control end of the eighth transistor is electrically connected with the first clock signal line, and an input end of the eighth transistor is electrically connected with the first voltage end;
a ninth transistor, wherein a control end of the ninth transistor is electrically connected with the first voltage end, and an input end of the ninth transistor is electrically connected with an output end of the eighth transistor;
a tenth transistor, wherein a control end of the tenth transistor is electrically connected with an output end of the ninth transistor, and an input end of the tenth transistor is electrically connected with the second clock signal line;
an eleventh transistor, wherein a control terminal of the eleventh transistor is electrically connected to the second clock signal line, an input terminal of the eleventh transistor is electrically connected to the output terminal of the tenth transistor, and an output terminal of the eleventh transistor is electrically connected to the first node; and
and the second capacitor is connected in series between the control end of the tenth transistor and the output end of the tenth transistor.
6. The gate drive circuit of claim 5, wherein the second node maintenance module further comprises:
and a twelfth transistor, wherein the control end of the twelfth transistor is electrically connected with the output end of the eighth transistor, the input end of the twelfth transistor is electrically connected with the second voltage end, and the output end of the twelfth transistor is electrically connected with the control end of the seventh transistor.
7. The gate drive circuit of claim 5, further comprising:
the first node pull-up module comprises a thirteenth transistor, wherein the control end of the thirteenth transistor is electrically connected with the output end of the first transistor, the input end of the thirteenth transistor is electrically connected with the second voltage end, and the output end of the thirteenth transistor is electrically connected with the first node.
8. The gate drive circuit of claim 5, wherein the first node pull-down module further comprises:
a fourteenth transistor, wherein a control end of the fourteenth transistor is electrically connected with the output end of the first transistor, an input end of the fourteenth transistor is electrically connected with the first clock signal line, and an output end of the fourteenth transistor is electrically connected with the output end of the eighth transistor.
9. The gate drive circuit of claim 8, wherein the gate drive circuit further comprises:
the reset module comprises a reset transistor, wherein the control end of the reset transistor is electrically connected with a reset control line, the input end of the reset transistor is electrically connected with a second voltage end, and the output end of the reset transistor is electrically connected with the output end of the first transistor.
10. A display panel, comprising:
a plurality of gate driving circuits according to any one of claims 1 to 9; and
the sub-pixels are electrically connected with the gate driving circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310835862.5A CN117475897A (en) | 2023-07-07 | 2023-07-07 | Gate driving circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310835862.5A CN117475897A (en) | 2023-07-07 | 2023-07-07 | Gate driving circuit and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN117475897A true CN117475897A (en) | 2024-01-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310835862.5A Pending CN117475897A (en) | 2023-07-07 | 2023-07-07 | Gate driving circuit and display panel |
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| Country | Link |
|---|---|
| CN (1) | CN117475897A (en) |
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2023
- 2023-07-07 CN CN202310835862.5A patent/CN117475897A/en active Pending
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