CN117460245A - Multi-port memory cell structure with read-write separation and layout structure - Google Patents
Multi-port memory cell structure with read-write separation and layout structure Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
The invention provides a read-write separated semiconductor multiport memory cell structure and a layout structure; wherein the storage unit includes: the reading area is provided with M reading subunits which are in one-to-one correspondence with the reading ports, and a first port circuit is arranged in the reading subunits; the writing area is provided with a latch subunit and N writing subunits which are in one-to-one correspondence with the writing ports, and a second port circuit is arranged in the writing subunits; the latch subunit comprises latch circuits which are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunit and the reading subunit; the invention not only improves the parallel processing performance of the device, but also greatly improves the integration level of the memory unit.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a multi-port memory cell structure with read-write separation and a layout structure.
Background
With the development of integrated circuit manufacturing processes, static Random-Access Memory (SRAM) is increasingly used in a central processing unit (Central Processing Unit, CPU). Particularly in a multi-core and real-time signal processing system, each module of the CPU can perform read-write operation on the same memory. However, most of the conventional commonly used SRAMs are 1R1W (1 read 1 write) or 2R1W (2 read 1 write), and the number of read/write ports is relatively small, so that the read/write efficiency is low; when the number of the read ports is increased by a multiple, metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) transistors of the read ports are multiplied, bit Lines (BL) and Word Lines (WL) are correspondingly increased by multiple, for example, an 8R6W (8 read 6 write) memory, the number of MOS transistors of the read ports is increased by about 7 times than that of 1R1W (the number of the read ports is increased by 8 times, the number of the write ports is increased by 6 times, and the average number of the write ports is increased by about 7 times), and the Bit lines BL and the Word lines WL are correspondingly increased by multiple.
In a semiconductor memory device, a memory cell is the most basic cell structure for realizing a data storage function in a memory; for a semiconductor memory with multiple read-write ports, how to realize the layout of multiple read-write ports in a memory cell, so that the memory cell has small area and better performance, and the technical problem to be solved in the field is urgent.
Disclosure of Invention
In view of the above drawbacks in the prior art, an object of the present invention is to provide a read-write separated multiport memory cell structure and layout structure, which are used for solving the problems that the layout of multiport memories cannot be realized or the performance effects of small area and better performance cannot be achieved based on the existing semiconductor multiport memory cell structure.
To achieve the above and other related objects, the present invention provides, in a first aspect, a structure of a multi-port memory cell with separate read and write, which is suitable for a semiconductor memory device having a total number of read and write ports not less than 2; the memory array of the memory device comprises a plurality of memory units which are arranged in parallel, and a read-write control circuit connected with each memory unit; wherein, in the single storage unit, it includes:
the reading area is provided with M reading subunits which are in one-to-one correspondence with the reading ports; a first port circuit is arranged in the reading subunit and used for reading the data in the storage unit to the corresponding reading port;
the writing area is provided with latch subunits and N writing subunits which are in one-to-one correspondence with the writing ports; a second port circuit is arranged in the writing subunit and used for storing data input by a corresponding port into the storage unit; the latch subunit comprises latch circuits which are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunit and the reading subunit;
wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component;
the read-write control circuit comprises a read control circuit and a write control circuit; the reading control circuit is connected with the first port circuits in the reading subunits and is used for reading the data stored in the storage units through the first port circuits; the write control circuit is connected with the second port circuits in the write subunits and is used for writing data into the storage units through the second port circuits.
In an embodiment of the first aspect of the present application, each of the read control circuit and the write control circuit is disposed in a different metal layer of the memory cell; wherein the metal width of the lower layer of the wiring is larger than that of the higher layer.
In an embodiment of the first aspect of the present application, the writing area and the reading area are adjacent to each other and are arranged in parallel; wherein, each writing subunit is adjacent to each other and is arranged in parallel along a first direction; the reading subunits are adjacent to each other and are arranged in parallel along the first direction.
In an embodiment of the first aspect of the present application, the read control circuit includes a read bit line RBL and N read word lines RWL; the write control circuit comprises a write bit line WBL and M write word lines WWL;
wherein, each read word line RWL is connected with a corresponding first port circuit; the write word line WWL is connected to a corresponding second port circuit.
In an embodiment of the first aspect of the present application, each read word line RWL is disposed along the second direction and is connected to a corresponding first port circuit in an adjacent memory cell in the second direction; each write word line is arranged along a second direction and is connected with a corresponding second port circuit in the adjacent memory cells in the second direction;
the read bit line RBL penetrates through the write area along a first direction and is connected with the read bit line RBL in the adjacent memory cells; the writing bit line WBL penetrates through the reading area and is connected with the writing bit line WBL in the adjacent storage unit; wherein the second direction is perpendicular to the first direction.
In an embodiment of the first aspect of the present application, a layout height of each of the reading subunits in the memory cell is the same; the layout heights of the writing subunits in the storage units are the same, so that the second port circuits in the writing subunits are connected with each other; and in each storage unit of the same storage array, the layout heights of the reading subunits are the same, and the layout heights of the writing subunits are the same.
Secondly, the invention provides a layout structure of a multiport memory cell in a second aspect, which is suitable for semiconductor memory devices with the total number of read-write ports not lower than 2; the memory array of the memory device comprises a plurality of memory units which are arranged in parallel, and a read-write control circuit connected with each memory unit; the layout structure of the storage unit comprises the following components;
the reading area layout comprises M reading subunit layouts which are in one-to-one correspondence with the reading ports and are used for arranging corresponding first port circuits, wherein the first port circuits are used for reading data in the storage units to the corresponding reading ports;
the writing area layout comprises a latch circuit layout and N writing subunit layouts which are in one-to-one correspondence with writing ports, wherein the writing subunit layouts are used for arranging corresponding second port circuits, and the second port circuits are used for storing data input by corresponding ports into the storage units; the latch subunit layout is used for arranging latch circuits, and the latch circuits are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunits and the reading subunits;
wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component;
the read-write control circuit layout is used for arranging a read control circuit and a write control circuit; the reading control circuit is connected with the first port circuits in the reading subunits and is used for reading the data stored in the storage units through the first port circuits; the write control circuit is connected with the second port circuits in the write subunits and is used for writing data into the storage units through the second port circuits.
In an embodiment of the second aspect of the present application, the writing area layout and the reading area layout are adjacent to each other and are arranged in parallel; wherein, each writing subunit layout is adjacent to each other and is arranged in parallel along the first direction; the reading subunit layouts are mutually adjacent and are arranged in parallel along the first direction.
In an embodiment of the second aspect of the present application, the read-write control circuit layout includes: the read word line layout is distributed along the second direction and is connected with the corresponding read subunit layout in the adjacent storage units in the second direction; each writing word line layout is distributed along the second direction and is connected with the corresponding writing subunit layout in the adjacent storage units in the second direction; reading a bit line layout, which penetrates through the writing area layout along a first direction and is connected with the reading bit line layout in the adjacent storage unit; writing a bit line layout which penetrates through the read area layout along a first direction and is connected with the writing bit line layout in the adjacent storage unit; wherein the second direction is perpendicular to the first direction.
The present invention provides in a third aspect a semiconductor memory having a total number of read/write ports of not less than 2; the semiconductor memory includes: the device comprises a read-write port, a storage array and a read-write control circuit; wherein each memory cell in the memory array has a multi-port memory cell structure with read-write separation as described above.
As described above, according to the multi-port memory cell structure and layout structure with separate reading and writing, the number of reading and writing ports in a memory cell can be increased by arranging the writing area and the reading area which are mutually separated in a single memory cell, and corresponding the writing area to the writing port and the reading area to the reading port; the area of the memory unit is not multiplied while the number of ports is multiplied, so that the parallel processing performance of the device is improved, and the integration level of the memory unit is greatly improved; meanwhile, the processing technology is simplified, the processing area is saved, and the yield of the product is improved.
Drawings
FIG. 1 is a schematic diagram (third direction) of a read-write separated multi-port memory cell structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram (first direction) of a read-write separated multi-port memory cell structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of an SRAM basic cell in an embodiment of the present invention when the SRAM basic cell is an 8T SRAM basic cell;
FIG. 4 is a schematic diagram of a memory cell according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a layout height of each structural layer in the memory cell according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a memory array in a semiconductor memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a read word line layout and a write word line layout according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a read bit line layout and a write bit line layout according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Aiming at the traditional semiconductor memory unit structure, the layout of the multiport memory can not be realized in a smaller area, and the effects of small area and better performance can not be achieved; the application provides a read-write separated multiport memory cell structure and a layout structure, which aim to solve the problems faced by the layout of memory cells in multiport memories and achieve the effects of small area and better performance.
Wherein the total number of read-write ports of the semiconductor memory device is not less than 2; the read-write port comprises a write port and a read port; illustratively, the semiconductor memory device is an 8R6W SRAM having 8 read ports and 6 write ports.
The memory array of the memory device comprises a plurality of memory units which are arranged in parallel; the memory cell is a basic memory cell for storing unit data (1 bit).
Referring to fig. 1 and 2, schematic structural diagrams of an embodiment of the read-write separated multi-port memory cell structure according to the present invention are shown; fig. 1 is a schematic structural diagram of the memory unit along a third direction (a Z-axis direction in fig. 1); fig. 2 is a schematic structural diagram of the memory cell along a first direction (X-axis direction in fig. 1).
As shown in fig. 1, the storage unit includes, in a third direction: the device comprises a device layer, an insulating layer and a plurality of metal layers;
each metal layer is arranged above the device layer and distributed in a superposition way and is used for arranging a read/write control circuit in the memory cell; the metal layers are M respectively from bottom to top 0 、M 1 … … to M L L is the total number of the metal layers.
The insulating layer is arranged between two adjacent metal layers and between the metal layers and the device layer.
The device layer is used for distributing semiconductor components of the storage unit.
For a single memory cell, as shown in FIG. 2, the memory cell 100 includes a read region 110 and a write region 120; the memory cell 100 includes M read subunits 111 disposed in the read area 110, and the memory cell 100 includes N write subunits 121 and a latch subunit 130 disposed in the write area 120.
Wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component.
Specifically, each of the reading subunits 111 corresponds to a reading port of the semiconductor device one by one, that is, a single reading subunit 111 corresponds to a single writing port; a first port circuit 111a is disposed in the reading subunit 111, and is configured to read the data in the storage unit to the corresponding reading port.
Each writing subunit 121 corresponds to a writing port of the semiconductor device one by one, that is, a single writing subunit 121 corresponds to a single writing port; a second port circuit 121a is disposed in a single writing subunit 121, and is configured to store data input by a corresponding port into the storage unit.
The latch subunit 130 includes a latch circuit 131, where the latch circuit 131 is connected to each of the first port circuits 111a and each of the second port circuits 121a, respectively, and is configured to implement data reading according to a first control signal of each of the first port circuits, and to implement data storage according to a second control signal of each of the second port circuits, so that the latch circuit is commonly used for each of the write subunit and each of the read subunits.
In a specific embodiment, the circuit structure of the first port circuit is the same as the structure of the read control switch in the SRAM basic storage unit, and the circuit structure of the second port circuit is the same as the structure of the write control switch in the SRAM basic storage unit; the latch circuit has the same structure as a latch in the SRAM basic storage unit;
the SRAM basic storage unit is a 6T SRAM basic storage unit, an 8TSRAM basic storage unit or other existing basic storage units.
Illustratively, when the SRAM basic memory cell is an 8T SRAM basic memory cell as shown in fig. 3, the first port circuit 111a is a circuit formed by an M5 pipe and an M6 pipe; the second port circuit 121a is a circuit formed by an M7 pipe and an M8 pipe; the latch circuit 131 is a circuit formed by an M1 pipe, an M2 pipe, an M3 pipe and an M4 pipe.
In a specific embodiment, each writing subunit is uniformly distributed above the latching subunit, and each device in the latching subunit is uniformly distributed below each writing subunit, so that the distances between each writing subunit and the latching unit are similar, the data storage efficiency of each writing port is similar, and the process difficulty of the semiconductor device is reduced.
As will be appreciated by those skilled in the art, the individual storage units are obtained by:
performing combination optimization on M+N SRAM basic storage units; the read control switches in M SRAM basic storage units are respectively used as first port circuits in all the read subunits; the write control switches in the N SRAM basic storage units are respectively used as a second port circuit in each write subunit, and any latch in the M+N SRAM basic storage units is used as a common latch circuit in the storage units.
In this embodiment, as shown in fig. 2, the read/write control circuit 200 includes a read control circuit 201 and a write control circuit 202.
Wherein, the read control circuit 201 is connected to the first port circuit 111a in each read subunit, and is configured to read the data stored in the storage unit through each first port circuit 111 a; the write control circuit 202 is connected to the second port circuits 121a in the write sub-units, and is configured to write data into the memory units through the second port circuits 121 a.
In one embodiment, for a single memory cell, the read control circuit to which it is connected includes a read bit line RBL and N read word lines RWL; the write control circuit connected with the memory cell comprises a write bit line WBL and M write word lines WWL;
wherein, each read word line RWL corresponds to the read sub-unit one by one, and the read word line RWL is connected with the corresponding first port circuit; and each write word line WWL corresponds to the read subunit one by one, and the write word lines WWL are connected with the corresponding second port circuits.
The read control circuit and the write control circuit are respectively arranged in different metal layers of the memory cell, so that the layout area of the read/write control circuit is reduced, and the layout and the wiring are reasonably arranged.
In one embodiment, when the semiconductor memory device has 8 read ports and 6 write ports, the number of the metal layers is not less than 7; the internal wiring between the latch circuit and the second port circuit in each of the read subcells uses M0 layer and M1 layer metal layers, the read bitline RBL uses M1 layer, M3 layer and M5 layer metal layers, and the write bitline WBL uses M2 layer, M4 layer and M6 layer.
It should be noted that, because of the different thickness of each layer of metal in the process, in order to achieve the balance of RC parameters of each port, the metal of the lower layer needs to be wider than the width of the upper layer during wiring so as to reduce the gap caused by the thickness; the specific proportion can be calculated by a tool according to different processes, and is not particularly limited.
It should be noted that, when the total number of the read/write ports is small (e.g., less than 4), the read control circuit and the write control circuit may be disposed in the same metal layer according to specific requirements.
According to the multi-port memory cell structure with separate reading and writing, the reading sub-cells corresponding to the reading interfaces and the writing sub-cells corresponding to the writing interfaces are respectively arranged in the memory cells, so that separation of the reading and writing functional areas is realized in a single memory cell; compared with the existing memory cell structure, the read function area is integrated, and the read-write separated multiport memory cell structure provided by the application can realize the increase of the number of read-write ports in the memory cell by separating the read function area in a single memory cell; the area of the memory unit is not multiplied while the number of ports is multiplied, so that the memory capacity of the device is improved, and the integration level of the memory unit is greatly improved; meanwhile, the processing technology is simplified, the processing area is saved, and the yield of the product is improved.
Referring to fig. 4, a schematic diagram of the memory cell structure in one embodiment is shown.
As shown in fig. 4, in the single memory cell, the writing sub-units 121 are adjacent to each other and are arranged in parallel along a first direction (X-axis direction in the figure), so as to form the writing area 120 of the memory cell; similarly, the reading subunits 111 are adjacent to each other and are arranged in parallel along the first direction to form the reading area 110 of the memory cell; and, the writing area 120 and the reading area 110 are adjacent to each other and are arranged in parallel, so that the utilization rate of the area in the memory cell can be improved, and the integration level of the semiconductor device can be improved.
For a single memory cell, each read word line RWL is arranged along the second direction to connect the first port circuits of the same write sub-unit 121 in the adjacent memory cells in the second direction (Y-axis direction in the figure); similarly, each of the write word lines is arranged along the second direction to connect the second port circuits of the same read subunit 111 in the adjacent memory cells in the second direction;
the second direction is perpendicular to the first direction and the third direction.
And, the read bit line RBL penetrates the write region 120 along a first direction and is connected to the read bit line RBL in an adjacent memory cell; similarly, the write bit line WBL penetrates the read region 110 and is connected to the write bit line WBL in the adjacent memory cells, so that the connection mode between the read control circuit and the write control circuit in different memory cells is optimized, and the difficulty of the wiring process between the memory cells is reduced.
It can be understood by those skilled in the art that a first through connection line is pre-arranged in the read area, and the setting position and setting height of the first through connection line in the read area are adapted to the setting position and setting height of the write bit line WBL in the write area, so as to connect the write bit lines WBL in two adjacent memory cells respectively by using the first through connection line; and a second through connection line is pre-arranged in the writing area, and the setting position and the setting height of the second through connection line in the writing area are matched with the setting position and the setting height of the reading bit line RBL in the reading area so as to be respectively connected with the reading bit lines RBL in two adjacent storage units.
In a preferred embodiment, in a single memory cell, the layout heights of the read subunits in the memory cell are the same, so as to facilitate interconnection of the first port circuits; the layout heights of the writing subunits in the storage units are the same, so that the second port circuits in the writing subunits are connected with each other;
and in each memory cell of the same memory array, the layout heights of the read subunits are the same, and the layout heights of the write subunits are the same, so that the first port circuits among different memory cells are connected with each other, and the second port circuits among different memory cells are connected with each other.
It should be noted that, because the first port circuit in the read area subunit and the second port circuit in the write area subunit have different circuit functions, the circuit types and the number of MOS transistors of the two are inconsistent, and when the two subareas are arranged, the two subareas need to be ensured to be at the same height (the widths of the two subareas can be different); as shown in fig. 5, the heights of the PW junction and the NW junction are also consistent, so as to ensure that when the write area and the read area are spliced, there is no drc error between the two, thereby further reducing the area size of the memory cell and improving the integration level of the device.
In one embodiment, referring to fig. 6, a schematic diagram of a memory array in a semiconductor memory is shown; as shown in fig. 6, the memory array is arranged in parallel in M rows and N columns, and includes m×n memory cells, m×8 read bit lines, m×6 write bit lines, n×8 read word lines, and n×6 write word lines.
As shown in fig. 6, each of the memory cells 100 includes a read area 110 and a write area 120 arranged in parallel; each of the read areas 110 includes 1 st to 8 th read sub-units (not shown) arranged in parallel, and each of the write areas includes 1 st to 6 th write sub-units (not shown) arranged in parallel.
For each read/write bit line, each read bit line is connected to each first port circuit in the corresponding row of memory cells, and each write bit line is connected to each first port circuit in the corresponding row of memory cells; for example, for the 1 st write bit line WBL [0], it is connected to the first port circuit in each write subunit in the first row and first column of memory cells, respectively, the first port circuit in each write subunit in the first row and second column of memory cells, and so on, until the first port circuit in each write subunit in the first row and N column of memory cells is connected; similarly, for the 1 st read bit line RBL [0], it is respectively connected with the second port circuit in each read subunit in the first row and first column of memory units, and so on until the second port circuit in each read subunit in the first row and the N column of memory units is connected;
for each read/write word line, each read word line is connected to each second port circuit in the corresponding column of memory cells, and each write bit line is connected to each first port circuit in the corresponding row of memory cells; for example, for a first read word line, it is connected sequentially along a second direction to the second port circuits of each first read subunit in the first column of memory cells; for a second sub-word line in the second read word line, it is sequentially connected to the second port circuits of each second read sub-cell in the first column of memory cells along the second direction, and so on.
In an alternative embodiment, in the memory array, at least 2 groups of power control lines and bottom control lines are correspondingly arranged for the memory cells arranged in each row, and each power control line and bottom control line penetrate through each transverse/longitudinal metal layer to form a grid-shaped power supply structure so as to provide power for each memory cell.
Further, a power supply unit for supplying power is arranged between two adjacent storage units or in the internal gap of a single storage unit; furthermore, a power tap cell is inserted between two adjacent memory cells or in an internal gap of a single memory cell, so as to improve the layout compactness of the semiconductor device.
In order to solve the technical problems in the prior art, based on the same inventive concept, the application also provides a multi-port memory cell layout structure which is suitable for a semiconductor memory device with 2 or more read-write ports; the memory device comprises a plurality of memory cells in a memory array;
in this embodiment, the layout structure includes; reading a region layout, writing a region layout and a read-write control circuit layout;
the reading area layout comprises M reading subunit layouts which are in one-to-one correspondence with the reading ports and are used for arranging corresponding first port circuits; the first port circuit is used for reading the data in the storage unit to the corresponding reading port;
the writing area layout comprises a latch circuit layout and N writing subunit layouts which are in one-to-one correspondence with the writing ports, wherein the writing subunit layouts are used for arranging corresponding second port circuits; the second port circuit is used for storing data input by a corresponding port into the storage unit; the latch subunit layout is used for arranging latch circuits, and the latch circuits are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunits and the reading subunits;
wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component;
the read-write control circuit layout is used for arranging a read control circuit and a write control circuit; the reading control circuit is connected with the first port circuits in the reading subunits and is used for reading the data stored in the storage units through the first port circuits; the write control circuit is connected with the second port circuits in the write subunits and is used for writing data into the storage units through the second port circuits.
In an alternative embodiment, the writing subunit layouts are adjacent to each other and are arranged in parallel along the first direction to form the writing area layout of the memory unit; the read subunit layouts are mutually adjacent and are arranged in parallel along a first direction to form the read area layout of the storage unit; and the writing area layout and the reading area layout are mutually adjacent and are arranged in parallel.
In an alternative embodiment, the read-write control circuit layout includes: reading a word line layout, writing a word line layout, reading a bit line layout and writing a bit line layout;
referring to fig. 7 and 8, fig. 7 is a schematic diagram showing the distribution of the read word line layout and the write word line layout in a specific embodiment; FIG. 8 illustrates a distribution diagram of the read bit line layout and the write bit line layout in a particular embodiment.
As shown in fig. 7, each read word line layout 10 is arranged along the second direction and is connected to a corresponding read subunit layout 61 in the adjacent memory cells in the second direction; each of the write word line layouts 20 is arranged along the second direction and connects with the corresponding write sub-cell layout 71 in the adjacent memory cells in the second direction.
As shown in fig. 8, the read bit line layout 30 extends through the write area layout 70 in a first direction and is connected to the read bit line layout in an adjacent memory cell; the write bit line layout 40 extends through the read region layout 60 in a first direction and is connected to the write bit line layout in adjacent memory cells.
Wherein the second direction is perpendicular to the first direction. It should be noted that, in the actual layout, each read word line and each write word line are laid out in different metal layers, so that there is an overlap between the actual layout positions of part of the word lines, and similarly, each read bit line and each write bit line are laid out in different metal layers, so that there is an overlap between the actual layout positions of part of the bit lines, which is not shown in fig. 5 and 6.
In order to solve the technical problems existing in the prior art, the application also provides a semiconductor memory, wherein the total number of read-write ports is not less than 2; illustratively, the semiconductor memory device is an 8R6W SRAM having 8 read ports and 6 write ports.
The semiconductor memory, as shown in fig. 9, includes: the device comprises a read-write port, a storage array and a read-write control circuit; the read-write control circuit is connected between the read-write port and the storage array.
Specifically, each memory cell in the memory array has a multi-port memory cell structure with read-write separation as described above, which is not described herein.
In summary, according to the multi-port memory cell structure and layout structure with separate reading and writing, the number of reading and writing ports in a memory cell can be increased by arranging the writing area and the reading area which are mutually separated in a single memory cell, and corresponding the writing area to the writing port and the reading area to the reading port; the area of the memory unit is not multiplied while the number of ports is multiplied, so that the parallel processing performance of the device is improved, and the integration level of the memory unit is greatly improved; meanwhile, the processing technology is simplified, the processing area is saved, and the yield of the product is improved; in addition, the heights of the writing layers are set to be the same, the heights of the reading layers are set to be the same, and the heights of the first storage layer and the second storage layer are set to be the same, so that the internal connection is convenient, and the process difficulty is further reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A multi-port memory cell structure with separated read and write is characterized in that the structure is suitable for semiconductor memory devices with the total number of read and write ports not lower than 2; the memory array of the memory device comprises a plurality of memory units which are arranged in parallel, and a read-write control circuit connected with each memory unit; wherein,
in a single said memory cell, comprising:
the reading area is provided with M reading subunits which are in one-to-one correspondence with the reading ports; a first port circuit is arranged in each reading subunit and used for reading the data in the storage unit to the corresponding reading port;
the writing area is provided with latch subunits and N writing subunits which are in one-to-one correspondence with the writing ports; a second port circuit is arranged in the writing subunit and used for storing data input by a corresponding port into the storage unit; the latch subunit comprises latch circuits which are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunit and the reading subunit;
wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component;
the read-write control circuit comprises a read control circuit and a write control circuit; the reading control circuit is connected with the first port circuits in the reading subunits and is used for reading the data stored in the storage units through the first port circuits; the write control circuit is connected with the second port circuits in the write subunits and is used for writing data into the storage units through the second port circuits.
2. The structure of claim 1, wherein each of the read control circuit and the write control circuit is disposed in a different metal layer of the memory cell; wherein the metal width of the lower layer of the wiring is larger than that of the higher layer.
3. The structure of claim 1, wherein the writing area and the reading area are adjacent to each other and are arranged in parallel; wherein,
the writing subunits are mutually adjacent and are arranged in parallel along a first direction; the reading subunits are adjacent to each other and are arranged in parallel along the first direction.
4. The multi-port memory cell structure of claim 3, wherein the read control circuit comprises a read bit line RBL and N read word lines RWL; the write control circuit comprises a write bit line WBL and M write word lines WWL;
wherein, each read word line RWL is connected with a corresponding first port circuit; the write word line WWL is connected to a corresponding second port circuit.
5. The structure of claim 4, wherein each read word line RWL is arranged along a second direction and is connected to a corresponding first port circuit in an adjacent memory cell in the second direction; each write word line is arranged along a second direction and is connected with a corresponding second port circuit in the adjacent memory cells in the second direction;
the read bit line RBL penetrates through the write area along a first direction and is connected with the read bit line RBL in the adjacent memory cells; the writing bit line WBL penetrates through the reading area and is connected with the writing bit line WBL in the adjacent storage unit; wherein the second direction is perpendicular to the first direction.
6. The structure of claim 1, wherein the layout height of each of the read sub-units in the memory unit is the same; the layout heights of the writing subunits in the storage units are the same, so that the second port circuits in the writing subunits are connected with each other; the method comprises the steps of,
in each memory cell of the same memory array, the layout heights of each read subunit are the same, and the layout heights of each write subunit are the same.
7. The layout structure of the multiport memory cell is characterized by being suitable for semiconductor memory devices with the total number of read-write ports not lower than 2; the memory array of the memory device comprises a plurality of memory units which are arranged in parallel, and a read-write control circuit connected with each memory unit;
the layout structure of the storage unit comprises the following components;
the reading area layout comprises M reading subunit layouts which are in one-to-one correspondence with the reading ports and are used for arranging corresponding first port circuits, wherein the first port circuits are used for reading data in the storage units to the corresponding reading ports;
the writing area layout comprises a latch circuit layout and N writing subunit layouts which are in one-to-one correspondence with writing ports, wherein the writing subunit layouts are used for arranging corresponding second port circuits, and the second port circuits are used for storing data input by corresponding ports into the storage units; the latch subunit layout is used for arranging latch circuits, and the latch circuits are respectively connected with the first port circuits and the second port circuits, so that the latch circuits are shared by the writing subunits and the reading subunits;
wherein M is the number of read ports of the semiconductor component, and N is the number of write ports of the semiconductor component;
the read-write control circuit layout is used for arranging a read control circuit and a write control circuit; the reading control circuit is connected with the first port circuits in the reading subunits and is used for reading the data stored in the storage units through the first port circuits; the write control circuit is connected with the second port circuits in the write subunits and is used for writing data into the storage units through the second port circuits.
8. The multi-port memory cell layout structure of claim 7 wherein the write area layout and the read area layout are adjacent to each other and arranged side-by-side;
wherein, each writing subunit layout is adjacent to each other and is arranged in parallel along the first direction; the reading subunit layouts are mutually adjacent and are arranged in parallel along the first direction.
9. The multi-port memory cell layout structure of claim 7, wherein the read-write control circuit layout comprises:
reading a word line layout, which is arranged along a second direction and is connected with the corresponding reading subunit layout in the adjacent storage units in the second direction;
writing a word line layout which is arranged along a second direction and is connected with the corresponding writing subunit layout in the adjacent storage units in the second direction;
reading a bit line layout, which penetrates through the writing area layout along a first direction and is connected with the reading bit line layout in the adjacent storage unit;
writing a bit line layout which penetrates through the read area layout along a first direction and is connected with the writing bit line layout in the adjacent storage unit;
wherein the second direction is perpendicular to the first direction.
10. A semiconductor memory is characterized in that the total number of read-write ports is not less than 2; the semiconductor memory includes:
the device comprises a read-write port, a storage array and a read-write control circuit; wherein,
each of the memory cells in the memory array has a read-write separated multiport memory cell structure as in any of claims 1 to 6.
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| US8913455B1 (en) * | 2013-07-29 | 2014-12-16 | Xilinx, Inc. | Dual port memory cell |
| US20150310909A1 (en) * | 2014-04-25 | 2015-10-29 | Broadcom Corporation | Optimization of circuit layout area of a memory device |
| CN114496027A (en) * | 2020-10-26 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | Hybrid port memory and working method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8913455B1 (en) * | 2013-07-29 | 2014-12-16 | Xilinx, Inc. | Dual port memory cell |
| US20150310909A1 (en) * | 2014-04-25 | 2015-10-29 | Broadcom Corporation | Optimization of circuit layout area of a memory device |
| CN114496027A (en) * | 2020-10-26 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | Hybrid port memory and working method thereof |
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