CN117460159A - Circuit board patch packaging technology - Google Patents
Circuit board patch packaging technology Download PDFInfo
- Publication number
- CN117460159A CN117460159A CN202311399871.0A CN202311399871A CN117460159A CN 117460159 A CN117460159 A CN 117460159A CN 202311399871 A CN202311399871 A CN 202311399871A CN 117460159 A CN117460159 A CN 117460159A
- Authority
- CN
- China
- Prior art keywords
- pcb substrate
- pcb
- workbench
- reprocessing
- conveyor belt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012536 packaging technology Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 198
- 238000007689 inspection Methods 0.000 claims abstract description 29
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 239000002994 raw material Substances 0.000 claims abstract description 16
- 238000004064 recycling Methods 0.000 claims abstract description 16
- 238000012858 packaging process Methods 0.000 claims abstract description 14
- 230000002950 deficient Effects 0.000 claims abstract description 7
- 238000007599 discharging Methods 0.000 claims abstract description 6
- 238000012958 reprocessing Methods 0.000 claims description 44
- 239000010410 layer Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 26
- 238000013102 re-test Methods 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000003344 environmental pollutant Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 7
- 231100000719 pollutant Toxicity 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 7
- 238000012546 transfer Methods 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 abstract description 9
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C7/00—Sorting by hand only e.g. of mail
- B07C7/04—Apparatus or accessories for hand picking
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
- B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
- B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
- B07C5/34—Sorting according to other particular properties
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8803—Visual inspection
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N2021/95638—Inspecting patterns on the surface of objects for PCB's
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02W—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO WASTEWATER TREATMENT OR WASTE MANAGEMENT
- Y02W30/00—Technologies for solid waste management
- Y02W30/50—Reuse, recycling or recovery technologies
- Y02W30/82—Recycling of waste of electrical or electronic equipment [WEEE]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
The invention discloses a circuit board patch packaging process, in particular to the technical field of circuit board patches, which comprises the following steps: (a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt; (b) The quality inspection personnel visually inspect the PCB substrate sent by the conveyor belt on the quality inspection workbench, find the PCB substrate with the notch, and collect the PCB substrate into the recycling basket for recycling. The invention can detect the quality of the PCB substrate by double quality inspection, detect whether the PCB substrate has a notch and burrs, can be recycled with the notch, can be manually repaired with the burrs, is convenient for the normal operation of subsequent processing, ensures the service life and durability of the processed PCB, and ensures that the defective rate of the product produced by the invention is lower.
Description
Technical Field
The invention relates to the technical field of circuit board surface mounting, in particular to a circuit board surface mounting packaging process.
Background
The circuit board patch package is mainly used for packaging electronic components, the common circuit board package type is SOP (solid oxide fuel cell) or small-outline package, is a common surface-mounted component package form, is mainly applied to surface-mounted components, and also is DIP package, is a plug-in package type, leads are led out from two sides of the package, and the package materials comprise plastic and ceramic, PLCC package, TQFP package and the like.
Although the circuit board patch packaging process in the prior art can be normally applied, in actual use, there are still more disadvantages, such as that after the circuit board patch packaging process in the prior art is used for cutting a board, only the surface of the cut PCB is cleaned basically, then subsequent processing is performed, in the board cutting process, the edge of the PCB can possibly have the problems of notch, burr and the like, the PCB cannot be normally used even if the subsequent processing is completed, the service life of the PCB is shorter than that of a normal PCB, and the PCB is easy to damage, so that the defective rate of the product of the circuit board patch packaging process in the prior art is higher.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, an embodiment of the present invention provides a circuit board patch packaging process to solve the above-mentioned problems set forth in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a circuit board patch packaging process comprises the following steps:
(a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt;
(b) The quality inspector visually inspects the PCB substrate sent by the conveyor on the quality inspection workbench, discovers the PCB substrate with the notch, receives the PCB substrate into a recycling basket for recycling, discovers the PCB substrate with the burr, places the PCB substrate on the reprocessing conveyor to the reprocessing workbench, places the qualified PCB substrate on the reprocessing conveyor, and sends the PCB substrate to the rechecking workbench for rechecking;
(c) The reprocessing operator receives the PCB substrate with burrs sent by the reprocessing conveyor belt, manually cleans the burrs of the PCB substrate by using pliers and tweezers on the reprocessing workbench, and after the burrs are cleaned, places the processed PCB substrate on the conveying and returning conveyor belt, and sends the processed PCB substrate to the rechecking workbench for rechecking;
(d) On a retest workbench, retests use a magnifying glass to carry out detailed retest on the sent PCB substrate, and observe whether the PCB substrate is defective or not;
(e) Cleaning the PCB substrate subjected to the rechecking to remove pollutants on the surface of the PCB substrate;
(f) Preparing a cleaned PCB substrate, and then attaching a dry film on the surface layer of the PCB substrate to prepare for image transfer;
(g) Exposing the film-covered PCB substrate by using ultraviolet light by using an exposure machine, and transferring an image of the substrate onto a dry film;
(h) Developing the exposed PCB substrate by a developing machine, removing the unexposed part and forming a required circuit pattern;
(i) Etching the PCB substrate after the development treatment by an etching machine, transferring the exposed circuit pattern to the PCB, and etching away the unnecessary copper layer;
(j) Removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, and then completing the manufacture of the inner layer plate;
(k) And comparing the image of the inner layer plate with the data of the well-recorded good product plate through AO I optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected through AOI to VRS, and overhauling by technicians.
In a preferred embodiment, the spacing between every two adjacent PCB substrates in the step (a) is 4-6cm.
In a preferred embodiment, the developing machine in step (h) is of the type MV-60.
In a preferred embodiment, the etching machine in step (i) is model ES-2.
The invention has the technical effects and advantages that:
the invention prepares the PCB substrate raw material, then uses the mechanical cutting machine to cut the PCB substrate raw material, then discharges the cut PCB substrate on the conveyor belt, and sends out the cut PCB substrate to the quality inspection workbench through the conveyor belt, the quality inspection personnel visually inspect the PCB substrate sent by the conveyor belt on the quality inspection workbench, find the PCB substrate with the notch, the quality inspection personnel collect the PCB substrate into the recycling basket for recycling, find the PCB substrate with the burr, the quality inspection personnel place the PCB substrate on the reprocessing conveyor belt to the reprocessing workbench, the qualified PCB substrate quality inspection personnel place the PCB substrate on the reprocessing conveyor belt to the reprocessing workbench for the rechecking, the reprocessing operator receives the PCB substrate with the burr sent by the reprocessing conveyor belt, the forceps and the tweezers are used for manually cleaning the burr of the PCB substrate on the reprocessing workbench after the burr is cleaned, placing the processed PCB substrate on a conveying and returning belt, conveying to a rechecking workbench for rechecking, rechecking personnel on the rechecking workbench in detail by using a magnifying glass to check whether the conveyed PCB substrate is residual or not, cleaning the rechecked PCB substrate, removing pollutants on the surface of the PCB substrate, preparing the cleaned PCB substrate, pasting a dry film on the surface layer of the PCB substrate for image transfer, using an exposure machine to expose the film-covered PCB substrate by ultraviolet light, transferring the image of the substrate onto the dry film, developing the exposed PCB substrate by a developing machine, removing the unexposed part, forming a required circuit pattern, etching the developed PCB substrate by an etching machine, transferring the exposed circuit pattern onto the PCB, and etching away an unnecessary copper layer, removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, then finishing the manufacture of an inner layer plate, comparing the image of the inner layer plate with the data of the well-recorded good product plate by AOI optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected by AOI to VRS, and overhauling by technicians.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The invention provides a circuit board patch packaging process, which comprises the following steps:
(a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt;
(b) The quality inspector visually inspects the PCB substrate sent by the conveyor on the quality inspection workbench, discovers the PCB substrate with the notch, receives the PCB substrate into a recycling basket for recycling, discovers the PCB substrate with the burr, places the PCB substrate on the reprocessing conveyor to the reprocessing workbench, places the qualified PCB substrate on the reprocessing conveyor, and sends the PCB substrate to the rechecking workbench for rechecking;
(c) The reprocessing operator receives the PCB substrate with burrs sent by the reprocessing conveyor belt, manually cleans the burrs of the PCB substrate by using pliers and tweezers on the reprocessing workbench, and after the burrs are cleaned, places the processed PCB substrate on the conveying and returning conveyor belt, and sends the processed PCB substrate to the rechecking workbench for rechecking;
(d) On a retest workbench, retests use a magnifying glass to carry out detailed retest on the sent PCB substrate, and observe whether the PCB substrate is defective or not;
(e) Cleaning the PCB substrate subjected to the rechecking to remove pollutants on the surface of the PCB substrate;
(f) Preparing a cleaned PCB substrate, and then attaching a dry film on the surface layer of the PCB substrate to prepare for image transfer;
(g) Exposing the film-covered PCB substrate by using ultraviolet light by using an exposure machine, and transferring an image of the substrate onto a dry film;
(h) Developing the exposed PCB substrate by a developing machine, removing the unexposed part and forming a required circuit pattern;
(i) Etching the PCB substrate after the development treatment by an etching machine, transferring the exposed circuit pattern to the PCB, and etching away the unnecessary copper layer;
(j) Removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, and then completing the manufacture of the inner layer plate;
(k) And comparing the image of the inner layer plate with the data of the well-recorded good product plate through AO I optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected through AO I to VRS, and overhauling by technicians.
The interval between every two adjacent PCB substrates in the step (a) is 4cm.
The model of the developing machine in the step (h) is MV-60.
The model of the etching machine in the step (i) is ES-2.
In this embodiment, the interval between every two adjacent PCB substrates in step (a) is 4cm, and compared with the prior art, this embodiment can detect the quality of PCB substrates through double quality inspection, detects whether it has opening and deckle edge, has the recoverable recycle of opening, has the deckle edge and can be artifical restoration, the normal clear of follow-up processing of being convenient for has guaranteed the life and the durability of the PCB board that processing was accomplished.
Example 2
The invention provides a circuit board patch packaging process, which comprises the following steps:
(a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt;
(b) The quality inspector visually inspects the PCB substrate sent by the conveyor on the quality inspection workbench, discovers the PCB substrate with the notch, receives the PCB substrate into a recycling basket for recycling, discovers the PCB substrate with the burr, places the PCB substrate on the reprocessing conveyor to the reprocessing workbench, places the qualified PCB substrate on the reprocessing conveyor, and sends the PCB substrate to the rechecking workbench for rechecking;
(c) The reprocessing operator receives the PCB substrate with burrs sent by the reprocessing conveyor belt, manually cleans the burrs of the PCB substrate by using pliers and tweezers on the reprocessing workbench, and after the burrs are cleaned, places the processed PCB substrate on the conveying and returning conveyor belt, and sends the processed PCB substrate to the rechecking workbench for rechecking;
(d) On a retest workbench, retests use a magnifying glass to carry out detailed retest on the sent PCB substrate, and observe whether the PCB substrate is defective or not;
(e) Cleaning the PCB substrate subjected to the rechecking to remove pollutants on the surface of the PCB substrate;
(f) Preparing a cleaned PCB substrate, and then attaching a dry film on the surface layer of the PCB substrate to prepare for image transfer;
(g) Exposing the film-covered PCB substrate by using ultraviolet light by using an exposure machine, and transferring an image of the substrate onto a dry film;
(h) Developing the exposed PCB substrate by a developing machine, removing the unexposed part and forming a required circuit pattern;
(i) Etching the PCB substrate after the development treatment by an etching machine, transferring the exposed circuit pattern to the PCB, and etching away the unnecessary copper layer;
(j) Removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, and then completing the manufacture of the inner layer plate;
(k) And comparing the image of the inner layer plate with the data of the well-recorded good product plate through AO I optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected through AO I to VRS, and overhauling by technicians.
The distance between every two adjacent PCB substrates in the step (a) is 5cm.
The model of the developing machine in the step (h) is MV-60.
The model of the etching machine in the step (i) is ES-2.
In this embodiment, the interval between every two adjacent PCB substrates in step (a) is 5cm, and compared with the prior art, this embodiment can detect the quality of PCB substrates through double quality inspection, detects whether it has opening and deckle edge, has the recoverable recycle of opening, has the deckle edge and can be artifical restoration, the normal clear of follow-up processing of being convenient for has guaranteed the life and the durability of the PCB board that processing was accomplished.
Example 3
The invention provides a circuit board patch packaging process, which comprises the following steps:
(a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt;
(b) The quality inspector visually inspects the PCB substrate sent by the conveyor on the quality inspection workbench, discovers the PCB substrate with the notch, receives the PCB substrate into a recycling basket for recycling, discovers the PCB substrate with the burr, places the PCB substrate on the reprocessing conveyor to the reprocessing workbench, places the qualified PCB substrate on the reprocessing conveyor, and sends the PCB substrate to the rechecking workbench for rechecking;
(c) The reprocessing operator receives the PCB substrate with burrs sent by the reprocessing conveyor belt, manually cleans the burrs of the PCB substrate by using pliers and tweezers on the reprocessing workbench, and after the burrs are cleaned, places the processed PCB substrate on the conveying and returning conveyor belt, and sends the processed PCB substrate to the rechecking workbench for rechecking;
(d) On a retest workbench, retests use a magnifying glass to carry out detailed retest on the sent PCB substrate, and observe whether the PCB substrate is defective or not;
(e) Cleaning the PCB substrate subjected to the rechecking to remove pollutants on the surface of the PCB substrate;
(f) Preparing a cleaned PCB substrate, and then attaching a dry film on the surface layer of the PCB substrate to prepare for image transfer;
(g) Exposing the film-covered PCB substrate by using ultraviolet light by using an exposure machine, and transferring an image of the substrate onto a dry film;
(h) Developing the exposed PCB substrate by a developing machine, removing the unexposed part and forming a required circuit pattern;
(i) Etching the PCB substrate after the development treatment by an etching machine, transferring the exposed circuit pattern to the PCB, and etching away the unnecessary copper layer;
(j) Removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, and then completing the manufacture of the inner layer plate;
(k) And comparing the image of the inner layer plate with the data of the well-recorded good product plate through AO I optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected through AO I to VRS, and overhauling by technicians.
The interval between every two adjacent PCB substrates in the step (a) is 6cm.
The model of the developing machine in the step (h) is MV-60.
The model of the etching machine in the step (i) is ES-2.
In this embodiment, the interval between every two adjacent PCB substrates in step (a) is 6cm, and compared with the prior art, this embodiment can detect the quality of PCB substrates through double quality inspection, detects whether it has opening and deckle edge, has the recoverable recycle of opening, has the deckle edge and can be artifical restoration, the normal clear of follow-up processing of being convenient for has guaranteed the life and the durability of the PCB board that processing was accomplished.
The invention prepares the PCB substrate raw material, then uses the mechanical cutting machine to cut the PCB substrate raw material, then discharges the cut PCB substrate on the conveyor belt, and sends out the cut PCB substrate to the quality inspection workbench through the conveyor belt, the quality inspection personnel visually inspect the PCB substrate sent by the conveyor belt on the quality inspection workbench, find the PCB substrate with the notch, the quality inspection personnel collect the PCB substrate into the recycling basket for recycling, find the PCB substrate with the burr, the quality inspection personnel place the PCB substrate on the reprocessing conveyor belt to the reprocessing workbench, the qualified PCB substrate quality inspection personnel place the PCB substrate on the reprocessing conveyor belt to the reprocessing workbench for the rechecking, the reprocessing operator receives the PCB substrate with the burr sent by the reprocessing conveyor belt, the forceps and the tweezers are used for manually cleaning the burr of the PCB substrate on the reprocessing workbench after the burr is cleaned, placing the processed PCB substrate on a conveying and returning belt, conveying to a rechecking workbench for rechecking, rechecking personnel on the rechecking workbench in detail by using a magnifying glass to check whether the conveyed PCB substrate is residual or not, cleaning the rechecked PCB substrate, removing pollutants on the surface of the PCB substrate, preparing the cleaned PCB substrate, pasting a dry film on the surface layer of the PCB substrate for image transfer, using an exposure machine to expose the film-covered PCB substrate by ultraviolet light, transferring the image of the substrate onto the dry film, developing the exposed PCB substrate by a developing machine, removing the unexposed part, forming a required circuit pattern, etching the developed PCB substrate by an etching machine, transferring the exposed circuit pattern onto the PCB, and etching away an unnecessary copper layer, removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, then finishing the manufacture of an inner layer plate, comparing the image of the inner layer plate with the data of the well-recorded good product plate by AO I optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected by AO I to VRS, and overhauling by technicians.
Finally: the foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (4)
1. The circuit board patch packaging process is characterized by comprising the following steps of:
(a) Preparing a PCB substrate raw material, cutting the PCB substrate raw material by using a mechanical board cutting machine, discharging the cut PCB substrate on a conveyor belt, and sending the PCB substrate onto a quality inspection workbench through the conveyor belt;
(b) The quality inspector visually inspects the PCB substrate sent by the conveyor on the quality inspection workbench, discovers the PCB substrate with the notch, receives the PCB substrate into a recycling basket for recycling, discovers the PCB substrate with the burr, places the PCB substrate on the reprocessing conveyor to the reprocessing workbench, places the qualified PCB substrate on the reprocessing conveyor, and sends the PCB substrate to the rechecking workbench for rechecking;
(c) The reprocessing operator receives the PCB substrate with burrs sent by the reprocessing conveyor belt, manually cleans the burrs of the PCB substrate by using pliers and tweezers on the reprocessing workbench, and after the burrs are cleaned, places the processed PCB substrate on the conveying and returning conveyor belt, and sends the processed PCB substrate to the rechecking workbench for rechecking;
(d) On a retest workbench, retests use a magnifying glass to carry out detailed retest on the sent PCB substrate, and observe whether the PCB substrate is defective or not;
(e) Cleaning the PCB substrate subjected to the rechecking to remove pollutants on the surface of the PCB substrate;
(f) Preparing a cleaned PCB substrate, and then attaching a dry film on the surface layer of the PCB substrate to prepare for image transfer;
(g) Exposing the film-covered PCB substrate by using ultraviolet light by using an exposure machine, and transferring an image of the substrate onto a dry film;
(h) Developing the exposed PCB substrate by a developing machine, removing the unexposed part and forming a required circuit pattern;
(i) Etching the PCB substrate after the development treatment by an etching machine, transferring the exposed circuit pattern to the PCB, and etching away the unnecessary copper layer;
(j) Removing the film of the etched PCB substrate by film removing equipment, removing a dry film attached to the PCB, exposing a circuit pattern, and then completing the manufacture of the inner layer plate;
(k) And comparing the image of the inner layer plate with the data of the well-recorded good product plate through AOI optical scanning, determining the bad phenomenon of the inner layer plate, transmitting the bad image data detected through AOI to VRS, and overhauling by technicians.
2. The circuit board chip packaging process according to claim 1, wherein: the interval between every two adjacent PCB substrates in the step (a) is 4-6cm.
3. The circuit board chip packaging process according to claim 1, wherein: the model of the developing machine in the step (h) is MV-60.
4. The circuit board chip packaging process according to claim 1, wherein: the model of the etching machine in the step (i) is ES-2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311399871.0A CN117460159A (en) | 2023-10-26 | 2023-10-26 | Circuit board patch packaging technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311399871.0A CN117460159A (en) | 2023-10-26 | 2023-10-26 | Circuit board patch packaging technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117460159A true CN117460159A (en) | 2024-01-26 |
Family
ID=89586763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311399871.0A Pending CN117460159A (en) | 2023-10-26 | 2023-10-26 | Circuit board patch packaging technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117460159A (en) |
-
2023
- 2023-10-26 CN CN202311399871.0A patent/CN117460159A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100915418B1 (en) | Method for marking wafer, method for marking failed die, method for aligning wafer and wafer test equipment | |
| CN105842253B (en) | A kind of automation pcb board optical detecting method | |
| JP4583317B2 (en) | Method for inspecting and repairing defects in photoresist, and printed circuit board manufacturing process | |
| CN114126245A (en) | Circuit board pattern electroplating sandwiched film remover and pattern electroplating sandwiched film removing process | |
| CN114615814B (en) | Manufacturing process of circuit pattern of outer-layer flexible rigid-flex circuit board | |
| CN117460159A (en) | Circuit board patch packaging technology | |
| CN111385977A (en) | PCB (printed circuit board) blind hole layer negative film process | |
| CN114449765A (en) | HDI board manufacturing method for manufacturing blind hole instead of laser | |
| CN112714555A (en) | Method for manufacturing bare copper PCB | |
| CN112654159A (en) | Method for automatically supplementing and correcting film | |
| CN109298594B (en) | Glass recycling method, recycled glass substrate, and photomask blank and photomask using same | |
| JP2006165106A (en) | Electronic component mounting method | |
| CN112230511A (en) | Method for removing contamination particles on surface of photomask protective film | |
| CN111323082A (en) | Printed circuit board production quality detection method | |
| CN114760769A (en) | UV (ultraviolet) line repairing method for reducing scrappage of positioning open circuit notch | |
| KR100852294B1 (en) | Method of restoring printed circuit boards | |
| CN112261784A (en) | Processing technology for manufacturing silicon nitride ceramic circuit substrate | |
| CN117682161B (en) | Film attaching method, device, terminal equipment and storage medium | |
| JP4446845B2 (en) | Printed circuit board manufacturing method and manufacturing apparatus | |
| KR102455560B1 (en) | Cell-unit Ultra thin-film glass manufacturing and quality selection method | |
| JPH06202128A (en) | Thin film working method | |
| WO2016153052A1 (en) | Photomask manufacturing method and inspection apparatus | |
| CN112859513A (en) | Method for manufacturing photomask by using expired blank material coated with photoresist | |
| CN116634683A (en) | Glass-based Mini LED circuit board and preparation method thereof | |
| US20030044699A1 (en) | Check board replacement systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |