CN117459065A

CN117459065A - Method and device for converting PDM signal into PCM signal and electronic equipment

Info

Publication number: CN117459065A
Application number: CN202311799737.XA
Authority: CN
Inventors: 赵希敏
Original assignee: Shenzhen Jiutian Ruixin Technology Co ltd
Current assignee: Shenzhen Jiutian Ruixin Technology Co ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-01-26
Anticipated expiration: 2043-12-26
Also published as: CN117459065B

Abstract

The invention relates to a method for converting a PDM signal into a PCM signal, comprising: acquiring a PDM signal; performing downsampling processing on the obtained PDM signals through a downsampling filter to obtain a plurality of downsampled signal sets, wherein the downsampling processing is used for reducing the sampling rate of the PDM signals and reducing the calculated amount of the PDM signals; and carrying out low-pass filtering and high-pass filtering on the plurality of down-sampling signal sets through a memory and calculation integrated module to obtain PCM signals. The method can reduce the power consumption of converting the PDM signal into the PCM signal, and simplify the conversion and structure of converting the PDM signal into the PCM signal.

Description

Method and device for converting PDM signal into PCM signal and electronic equipment

Technical Field

The present invention relates to the field of PDM decoding technologies, and in particular, to a method and an apparatus for converting a PDM signal into a PCM signal, and an electronic device.

Background

With the increasing development of information technology, the proportion of digital circuits in various electronic systems is increasing, and higher requirements are put on the input quality of sound signals and the capability of resisting various external interferences. These requirements have been difficult to meet with only improvements in the acoustic properties of the analog microphone itself. Compared with an analog microphone, the digital microphone has strong anti-interference capability, and a high-frequency filter capacitor and a filter circuit are not needed to be built in as the analog microphone. The digital microphone is not interfered and influenced by computer, network and RF magnetic field signal source because the audio signal is in the form of digital signal transmission. Therefore, when the digital microphone is connected to the digital microphone, a shielding wire is not required, and the limited space of related products can be effectively utilized. Digital microphones are widely used in the field of audio acquisition by virtue of their own numerous advantages.

In modern audio processing, digital signal audio devices gradually replace analog signal audio devices due to the advantages of easy transmission, better accuracy, and the like. Digital microphones classified by output signals mainly include pulse code modulation (Pulse Code Modulation, PCM) microphones and pulse density modulation (Pulse Density Modulation, PDM) microphones. PDM microphones have the advantage of low noise and low cost due to their particular modulation scheme. Therefore, PDM microphones are used in a large number of application scenarios. However, in most modern digital audio systems, PCM microphones are also employed, requiring the use of multi-bit data to characterize the audio signal. PCM microphones are advantageous for simplifying the processing of audio signals so that the processing of audio signals can be done on an audio stream, for example, the audio signals can be subjected to mixing, filtering and equalization processes on the audio stream.

The PCM microphone outputs a PCM signal and the PDM microphone outputs a PDM signal. PCM signals are often used in various audio and video processing, and by encoding the level values to characterize the signal amplitude, the PCM signals can be further transmitted in channels, and various complex processing in modern audio devices, such as endpoint detection, compression encoding and the like, are facilitated. The PDM signal represents an analog signal with a one-bit binary number, whose output is not 0, i.e., 1, which characterizes the analog signal amplitude by density. Fig. 1 is a schematic diagram of an analog signal and a PCM signal and a PDM signal corresponding thereto, where (a) in fig. 1 is an analog signal, (b) in fig. 1 is a PCM signal corresponding to the analog signal, and (c) in fig. 1 is a PDM signal corresponding to the analog signal. It can be seen from fig. 1 that the coding quantization ideas of the PDM signal and the PCM signal are greatly different, the PCM signal represents the original analog signal, and still approximates to the sine wave form of the original analog signal, and the density of the PDM signal shows periodic variation; the binary sequence of the PDM signal corresponds to the level value of the original analog signal, each bit has only two states of 0 and 1, and the PCM signal stores the amplitude information of the original signal by adopting multi-bit quantization coding. Accordingly, the PCM signal may be widely applied to various audio devices, for example, the PCM signal is used in a microphone. As digital microphones become more and more popular, there are many places where it is necessary to convert PDM signals into PCM signals in order to process and analyze the PCM signals. However, the current process of converting PDM signals into PCM signals is generally power consuming and complex in structure.

Disclosure of Invention

The embodiment of the application can at least solve the technical problems by providing a method, a device and electronic equipment for converting a PDM signal into a PCM signal.

In a first aspect, an embodiment of the present invention provides a method for converting a PDM signal into a PCM signal, including:

acquiring a PDM signal;

performing downsampling processing on the obtained PDM signals through a downsampling filter to obtain a plurality of downsampled signal sets, wherein the downsampling processing is used for reducing the sampling rate of the PDM signals and reducing the calculated amount of the PDM signals;

and carrying out low-pass filtering and high-pass filtering on the plurality of down-sampling signal sets through a memory and calculation integrated module to obtain PCM signals.

Preferably, the number of the integrative storage and calculation modules is at least two, and the at least two integrative storage and calculation modules comprise a first integrative storage and calculation module and a second integrative storage and calculation module;

the first calculation integrated module comprises a plurality of first buffers and a plurality of first storage units, wherein the output ends of the first buffers are connected with the input ends of the first storage units, the first buffers are in a matrix shape to form a first buffer matrix, and the first storage units are in a matrix shape to form a first storage matrix;

The second calculation integrated module comprises a plurality of second buffers and a plurality of second storage units, wherein the output ends of the second buffers are connected with the input ends of the second storage units, the second buffers are in a matrix shape to form a second buffer matrix, and the second storage units are in a matrix state to form a second storage matrix.

Preferably, the performing low-pass filtering and high-pass filtering on the plurality of down-sampled signal sets by the integrated memory module to obtain PCM signals includes:

the method comprises the steps of adjusting a weight coefficient of each first storage unit in the first storage matrix to be a first filter coefficient, and adjusting a weight coefficient of each second storage unit in the second storage matrix to be a second filter coefficient, wherein if the first filter coefficient is a low-pass filter coefficient, the second filter coefficient is a high-pass filter coefficient, if the first filter coefficient is the high-pass filter coefficient, the second filter coefficient is the low-pass filter coefficient, the low-pass filter coefficient is the weight coefficient of each storage unit in the low-pass filter process, and the high-pass filter coefficient is the weight coefficient of each storage unit in the high-pass filter process;

Performing first filtering processing on each downsampled signal set through the first calculation integrated module to obtain a first calculation signal subset, and further obtaining a plurality of first calculation signal sets; each downsampled signal set comprises a plurality of downsampled signal subsets, wherein in each downsampled signal set, the number of the downsampled signal subsets is the number of rows of the first buffer matrix, and the number of the downsampled signals in each downsampled signal subset is the number of columns of the first buffer matrix; each first storage signal set comprises a plurality of first storage signal subsets, wherein in each first storage signal set, the number of the plurality of first storage signal subsets is the number of columns of the second buffer matrix, and the number of the first storage signals in each first storage signal subset is the number of columns of the second buffer matrix;

and performing second filtering processing on the plurality of first calculation signal sets through the second calculation integrated module to obtain the PCM signal, wherein if the first filtering coefficient is a low-pass filtering coefficient, the first filtering processing is the low-pass filtering processing, the second filtering processing is a high-pass filtering processing, and if the first filtering coefficient is the high-pass filtering coefficient, the first filtering processing is the high-pass filtering processing, and the second filtering processing is the low-pass filtering processing.

Preferably, the performing, by the first calculation integral module, a first filtering process on each downsampled signal set to obtain a first calculation signal subset, and further obtain a plurality of first calculation signal sets, including:

loading each down-sampled signal subset in parallel into one row of first buffers of the first buffer matrix in each down-sampled signal set, and loading each down-sampled signal of each down-sampled signal subset into one of the first buffers of the row of first buffer matrix in sequence;

performing multiply-accumulate operation on the downsampled signals of each row of the first buffer matrix and the low-pass filter coefficients of the first storage units of the corresponding column of the first storage matrix to obtain a first calculation signal of each column of the first storage units, and further obtaining a first calculation signal subset;

and after each downsampled signal set is subjected to multiply-accumulate operation of the first calculation integrated module, a plurality of first calculation signal subsets are obtained, and the plurality of first calculation signal subsets are sequentially divided, so that the plurality of first calculation signal sets are obtained.

Preferably, the performing, by the second integrating module, second filtering processing on the plurality of first computing signal sets to obtain the PCM signal includes:

in each first calculation signal set, loading the plurality of first calculation signal subsets into a row of second buffers of the second buffer matrix in parallel, and loading each first calculation signal of each first calculation signal subset into one of the row of second buffers of the second buffer matrix in sequence;

performing multiply-accumulate operation on the first calculation signals of each row of the second buffer matrix and the high-pass filter coefficients of the second storage units of the corresponding columns of the second storage matrix to obtain a second calculation signal of each column of the second storage units, and further obtaining a second calculation signal subset;

and after each first storage signal set executes multiply-accumulate operation of the second storage integrated module, obtaining a plurality of second storage signal subsets, and taking each second storage signal in the plurality of second storage signal subsets as the PCM signal.

Preferably, the number of the integrated storage modules is one, the integrated storage modules are third integrated storage modules, the third integrated storage modules comprise a plurality of third buffers and a plurality of third storage units, the output ends of the third buffers are connected with the input ends of the third storage units, the third buffers are in a matrix shape to form a third buffer matrix, and the third storage units are in a matrix shape to form a third storage matrix;

The method comprises the steps of performing low-pass filtering and high-pass filtering on the plurality of down-sampling signal sets through a memory integrated module to obtain PCM signals, and comprises the following two steps:

firstly, adjusting a weight coefficient of each storage unit of the third storage matrix into a first filter coefficient, and performing first filtering processing on a preset number of downsampled signal sets through the third integrated storage module to obtain a first stored signal set, wherein the preset number is the number of columns of the third buffer matrix;

the first filter coefficient of each storage unit of the third storage matrix is adjusted to be a second filter coefficient, the third integrated storage module carries out second filter processing on the first storage signal set to obtain a plurality of second storage signals, and each second storage signal is used as the PCM signal;

repeatedly executing the two steps to obtain a plurality of PCM signals;

if the first filter coefficient is a low-pass filter coefficient, the second filter coefficient is a high-pass filter coefficient, the first filter process is the low-pass filter process, and the second filter process is a high-pass filter process;

if the first filter coefficient is the high-pass filter coefficient, the second filter coefficient is the low-pass filter coefficient, the first filter process is the high-pass filter process, and the second filter process is the low-pass filter process;

The low-pass filter coefficient is a weight coefficient of each storage unit in the low-pass filter process, and the high-pass filter coefficient is a weight coefficient of each storage unit in the high-pass filter process.

Preferably, the step of performing downsampling processing on the obtained PDM signal by using a downsampling filter to obtain a plurality of downsampled signal sets includes:

and carrying out downsampling processing on the PDM signals through a CIC filter to obtain a plurality of downsampled signal sets.

Preferably, the Z-domain transfer function of the CIC filter is:

；

wherein H is ^N_cic (Z) is a Z-domain transfer function of a CIC filter, N_ CIC is the number of stages of the CIC filter, R is a downsampling multiple, and M is a differential time delay;

the amplitude-frequency characteristic of the CIC filter is as follows:

；

wherein,and omega is normalized frequency, and j is complex unit for the amplitude-frequency characteristic of the CIC filter.

Preferably, after obtaining the PCM signal, the method further comprises:

and carrying out format processing on the PCM signal to obtain a processed PCM signal.

Based on the same inventive concept, the present invention also provides an apparatus for converting a PDM signal into a PCM signal, including:

the acquisition module is used for acquiring the PDM signal;

the downsampling filter is used for performing downsampling processing on the acquired PDM signals to obtain a plurality of downsampled signal sets, wherein the downsampling processing is used for reducing the sampling rate of the PDM signals and reducing the calculated amount of the PDM signals;

And the integrated memory module is used for carrying out low-pass filtering processing and high-pass filtering processing on the plurality of down-sampling signal sets to obtain PCM signals.

Based on the same inventive concept, in a third aspect, the present invention provides an electronic device, including the apparatus for converting a PDM signal into a PCM signal according to the second aspect.

One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:

in the embodiment of the invention, after acquiring a PDM signal, the PDM signal is subjected to downsampling processing through a downsampling filter to obtain a plurality of downsampled signal sets. The down-sampling processing can down-sample and extract the PDM signal, so that the sampling rate of the PDM signal is reduced, the down-sampled PDM signal can be conveniently processed later, the calculated amount of the PDM signal is reduced, and the power consumption is saved. After a plurality of down-sampling signal sets are obtained, the down-sampling signal sets are subjected to low-pass filtering processing and high-pass filtering processing through the memory integrated module, so that the down-sampling signal sets are directly processed through the memory integrated module, unnecessary data carrying is reduced, power consumption is further reduced, and the conversion efficiency of the PDM signals is improved. And the low-pass filtering processing and the high-pass filtering processing on a plurality of down-sampling signal sets are realized through the integrated memory module, and the memory unit of the integrated memory module directly participates in logic calculation to improve the calculation power, which is equivalent to increasing the calculation core number in a large scale under the condition of unchanged chip area, saving the chip area occupied by a large number of devices used for multiplication and addition, reducing the hardware occupation ratio and leading the whole hardware structure to be simpler. The PCM signals obtained by processing the plurality of down-sampling signal sets through the memory and calculation integrated module have higher PCM signal precision and are easy to be accurately processed and analyzed by related digital devices such as audio frequency and the like. In addition, the present embodiment only completes the process of converting the PDM signal into the PCM signal by using the downsampling filter and the memory module in a matching manner, so as to simplify the conversion structure of converting the PDM signal into the PCM signal and avoid the complex conversion structure.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also throughout the drawings, like reference numerals are used to designate like parts. In the drawings:

fig. 1 shows a schematic diagram of an analog signal, a PCM signal and a PDM signal corresponding thereto in the background art;

FIG. 2 is a flow chart showing the steps of a method for converting a PDM signal into a PCM signal in an embodiment of the present invention;

FIG. 3 is a process diagram of a method for converting a PDM signal into a PCM signal in an embodiment of the present invention;

fig. 4 is a schematic process diagram of a method for converting a PDM signal into a PCM signal by performing low-pass filtering processing by a first integrated memory module and performing high-pass filtering processing by a second integrated memory module according to an embodiment of the present invention;

FIG. 5a is a schematic diagram of a plurality of buffers of a unified module according to an embodiment of the present invention;

FIG. 5b is a schematic diagram illustrating a plurality of memory units of a memory module according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of the amplitude-frequency response of a low-pass filtering process with a cut-off frequency of 20KHz for the applied low-pass filter principle in an embodiment of the present invention;

FIG. 7 shows a schematic diagram of the amplitude-frequency response of a high-pass filtering process with a cut-off frequency of 20Hz for the applied high-pass filter principle in an embodiment of the present invention;

fig. 8 is a schematic diagram showing a structure of an apparatus for converting a PDM signal into a PCM signal according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Embodiment one: a first embodiment of the present invention provides a method for converting a PDM signal into a PCM signal, as shown in fig. 2, including:

s101, acquiring a PDM signal;

s102, performing downsampling processing on the acquired PDM signals through a downsampling filter to obtain a plurality of downsampled signal sets, wherein the downsampling processing is used for reducing the sampling rate of the PDM signals and reducing the calculated amount of the PDM signals;

s103, performing low-pass filtering and high-pass filtering on the plurality of down-sampling signal sets through the integrated memory module to obtain PCM signals.

The PDM signal is bit stream data of 0 or 1. The integrated memory module is a fusion module integrating the memory unit and the computing unit. Fig. 3 is a process schematic diagram of a method for converting a PDM signal into a PCM signal according to this embodiment, and as shown in fig. 3, the PDM signal is sequentially subjected to a down-sampling process, a low-pass filtering process, and a high-pass filtering process by the conversion method according to this embodiment, so as to obtain the PCM signal. The low-pass filtering processing is a processing mode for realizing a low-pass filter principle through a memory integrated module, and the high-pass filtering processing is a processing mode for realizing a high-pass filter principle through a memory integrated module.

After the PDM signal is obtained, the PDM signal is subjected to downsampling processing through a downsampling filter, so that a plurality of downsampled signal sets are obtained. The down-sampling processing can down-sample and extract the PDM signal, so that the sampling rate of the PDM signal is reduced, the down-sampled PDM signal can be conveniently processed later, the calculated amount of the PDM signal is reduced, and the power consumption is saved. After a plurality of down-sampling signal sets are obtained, the down-sampling signal sets are subjected to low-pass filtering processing and high-pass filtering processing through the memory integrated module, so that the down-sampling signal sets are directly processed through the memory integrated module, unnecessary data carrying is reduced, power consumption is further reduced, and the conversion efficiency of the PDM signals is improved. And the low-pass filtering processing and the high-pass filtering processing on a plurality of down-sampling signal sets are realized through the integrated memory module, and the memory unit of the integrated memory module directly participates in logic calculation to improve the calculation power, which is equivalent to increasing the calculation core number in a large scale under the condition of unchanged chip area, saving the chip area occupied by a large number of devices used for multiplication and addition, reducing the hardware occupation ratio and leading the whole hardware structure to be simpler. The PCM signals obtained by processing the plurality of down-sampling signal sets through the memory and calculation integrated module have higher PCM signal precision and are easy to be accurately processed and analyzed by related digital devices such as audio frequency and the like. In addition, the present embodiment only completes the process of converting the PDM signal into the PCM signal by using the downsampling filter and the memory module in a matching manner, so as to simplify the conversion structure of converting the PDM signal into the PCM signal and avoid the complex conversion structure.

The following describes in detail the specific implementation steps of the PDM signal conversion method provided in this embodiment with reference to fig. 2 and 3:

first, step S101 is performed to acquire a PDM signal. Specifically, a PDM signal is generally obtained by a sound absorbing device such as a microphone.

Next, step S102 is executed to perform a downsampling process on the obtained PDM signal by a downsampling filter, so as to obtain a plurality of downsampled signal sets, where the downsampling process is used to reduce the sampling rate of the PDM signal and reduce the computation amount of the PDM signal.

Specifically, the PDM signal is subjected to a downsampling process by a downsampling filter, resulting in a plurality of downsampled signal sets. And the down-sampling processing is performed on the PDM signals to obtain down-sampled data, namely a plurality of down-sampled signal sets, so that the down-sampled PDM signals can be conveniently processed subsequently, the calculated amount of the PDM signals is reduced, and the power consumption is saved.

The downsampling filter of the present embodiment preferably employs a CIC (Cascaded integrator-comb filter) filter. And carrying out downsampling processing on the PDM signals through the CIC filter to obtain a plurality of downsampled signal sets. In a specific application process, as shown in fig. 3, the input frequency of the CIC filter is 3072khz,64/128 is the downsampling rate, and the input frequency and the downsampling rate of the CIC filter can be set according to practical requirements.

The Z-domain transfer function of the CIC filter is:

（1）；

wherein H is ^N_cic (Z) is a Z-domain transfer function of the CIC filter, N_ CIC is the number of stages of the CIC filter, R is a downsampling multiple, and M is a differential time delay.

The amplitude-frequency characteristics of the CIC filter are:

（2）；

wherein,the amplitude-frequency characteristic of the CIC filter is that omega is normalized frequency and j is complex unit.

The working principle of the CIC filter for carrying out downsampling processing on the PDM signal is as follows: the CIC filter firstly accumulates the PDM signals through an integrator of the CIC filter, and then extracts the accumulated PDM signals through a dressing filter of the CIC filter to obtain a plurality of groups of down-sampling signal sets. The whole CIC filter has a simple structure, does not involve any multiplier, only performs addition and subtraction operations, namely utilizes an adder and a subtracter, and is suitable for working at a high sampling rate. The CIC filter reduces the high sample rate signal to a lower sample rate, reducing the consumption of memory and computing resources. And the CIC filter is mainly used for sampling rate extraction, has the function of low-pass filtering, has good out-of-band filtering effect, realizes high-quality filtering effect and downsampling effect with lower cost, and is excellent in downsampling filtering system.

Of course, the downsampling filter may also employ an anti-aliasing filter. The specific parameters of the downsampling filter can be set according to actual requirements.

In the process of obtaining a plurality of down-sampling signal sets, in order for the integrated module to rapidly process the plurality of down-sampling signal sets, each down-sampling signal in each down-sampling signal set needs to be preprocessed. The preprocessing is to perform format adjustment on each downsampled signal to match the format of the data processed by the memory module. For example, the CIC filter downsamples the PDM signal to 40bit signed numbers per downsampled signal, wherein each downsampled signal is within a threshold range of [ -1,1 ]. If the format of the processing number of the integrated memory module is 32 bits, each downsampling signal is shifted to the right by 8 bits to be adjusted to be 0, the 32 bits are obtained, namely, each preprocessed downsampling signal is obtained, and each preprocessed downsampling signal is used as a downsampling signal input to the integrated memory module. Specifically, a certain down-sampled signal obtained by down-sampling the PDM signal by the CIC filter is + 0.8542395479454..25, the down-sampled signal needs to be preprocessed to obtain + 0.0000000079454..25, and the preprocessed down-sampled signal is used as the down-sampled signal input to the integrated memory module.

Then, step S103 is executed, where the integrated memory module performs low-pass filtering and high-pass filtering on the plurality of down-sampled signal sets to obtain PCM signals.

Specifically, the process of obtaining PCM signals by performing low-pass filtering processing and high-pass filtering processing on a plurality of down-sampled signal sets by the integrated memory module is divided into two cases. In the first case, the process of obtaining the PCM signal by performing low-pass filtering processing and high-pass filtering processing on the plurality of down-sampled signal sets is implemented by at least two integrated memory modules. In the second case, the process of obtaining the PCM signal by performing low-pass filtering processing and high-pass filtering processing on the plurality of down-sampled signal sets is implemented by only one memory integrated module. Each integrated storage module comprises a plurality of buffers and a plurality of storage units, and the output ends of the buffers are connected with the input ends of the storage units. As shown in fig. 5a, the plurality of buffers are in a matrix form to form a first buffer matrix. As shown in fig. 5b, a plurality of memory cells are in a matrix state to form a memory matrix. Each storage unit of the integrated storage and calculation module not only realizes the storage function, but also can carry out operation on the storage unit, and integrates the storage function and the calculation function. Therefore, the storage integrated module and the storage unit thereof have the advantages of high calculation power, low power consumption, low delay and high cost performance.

For the first case, as shown in fig. 4, taking two integrative modules shown in fig. 3 as an example, the two integrative modules are a first integrative module and a second integrative module respectively. The output end of the downsampling filter is connected with the input end of the first memory integrated module, the output end of the first memory integrated module is connected with the input end of the second memory integrated module, and the output end of the second memory integrated module outputs PCM signals. The first memory integrated module comprises a plurality of first buffers and a plurality of first memory units, wherein the output ends of the first buffers are connected with the input ends of the first memory units, the first buffers are in a matrix shape to form a first buffer matrix, and the first memory units are in a matrix shape to form a first memory matrix. The second integrated memory module comprises a plurality of second buffers and a plurality of second memory units, wherein the output ends of the second buffers are connected with the input ends of the second memory units, the second buffers are in a matrix shape to form a second buffer matrix, and the second memory units are in a matrix state to form a second memory matrix.

The specific implementation procedure of the first case is: a. and adjusting the weight coefficient of each first storage unit in the first storage matrix to be a first filter coefficient, and adjusting the weight coefficient of each second storage unit in the second storage matrix to be a second filter coefficient. Wherein the first filter coefficients of each first memory cell in the first memory matrix are different and the second filter coefficients of each second memory cell in the second memory matrix are different. The weight coefficient of each storage unit in the integrated storage and calculation module is essentially the conductivity of each storage unit, and the conductivity of each storage unit can be set according to actual requirements. b. And performing first filtering processing on each downsampled signal set through the first calculation integrated module to obtain a first calculation signal subset, and further obtaining a plurality of first calculation signal sets. Each of the downsampled signal sets includes a plurality of downsampled signal subsets, wherein in each of the downsampled signal sets, a number of the plurality of downsampled signal subsets is a number of rows of the first buffer matrix, and a number of the downsampled signals in each of the downsampled signal subsets is a number of columns of the first buffer matrix, such that a number of the downsampled signals in each of the downsampled signal sets is consistent with a number of the first buffers in the first buffer matrix. Each first calculation signal set comprises a plurality of first calculation signal subsets, the number of the first calculation signal subsets in each first calculation signal set is the number of columns of the second buffer matrix, and the number of the first calculation signals in each first calculation signal subset is the number of rows of the second buffer matrix, so that the number of the calculation signals in each first calculation signal set is consistent with the number of the second buffers in the second buffer matrix. c. And performing second filtering processing on the plurality of first calculation signal sets through a second calculation integrated module to obtain PCM signals.

If the first filter coefficient is a low-pass filter coefficient, the second filter coefficient is a high-pass filter coefficient, the first filter process is a low-pass filter process, and the second filter process is a high-pass filter process. If the first filter coefficient is a high-pass filter coefficient, the second filter coefficient is a low-pass filter coefficient, the first filter process is a high-pass filter process, and the second filter process is a low-pass filter process. Therefore, in the low-pass filtering process, the weight coefficient of the memory matrix of the integrated module is adjusted to the low-pass filter coefficient. In the high-pass filtering process, the weight coefficient of the storage matrix of the integrated module is adjusted to be a high-pass filter coefficient. The low-pass filter coefficient is a weight coefficient of each memory cell in the low-pass filter process, and is essentially a filter coefficient of the low-pass filter principle to which the low-pass filter process is applied. The high-pass filter coefficient is a weight coefficient of each memory cell in the high-pass filter process, and is essentially a filter coefficient of the high-pass filter principle applied by the high-pass filter process.

It should be noted that the cutoff frequency of the low-pass filter principle applied by the low-pass filter process is larger than the cutoff frequency of the high-pass filter principle applied by the high-pass filter process. For example, the cut-off frequency of the applied low-pass filter principle is 20KHz and the cut-off frequency of the applied high-pass filter principle is 20Hz. Therefore, the low-pass filter coefficient can enable the signal to obtain a storage signal meeting the requirements after the low-pass filter processing, and the high-pass filter coefficient can enable the signal to obtain a storage signal meeting the requirements after the high-pass filter processing, so that a PCM signal is obtained, and the error signal calculated by the storage and calculation integrated module is avoided. In addition, the process of obtaining the PCM signal by performing low-pass filtering processing and high-pass filtering processing on the plurality of downsampled signal sets is implemented for at least two integrative modules, and the implementation principle of at least two integrative modules is consistent with that of two integrative modules, and is not described herein.

In the first case, the two sequentially connected integrated memory modules are used for respectively performing low-pass filtering processing and high-pass filtering processing, and a plurality of down-sampling signal sets are directly operated, so that unnecessary data carrying is reduced, power consumption is further reduced, and conversion efficiency of converting PDM signals into PCM signals is improved. And the low-pass filtering processing and the high-pass filtering processing of a plurality of down-sampling signal sets are realized through the integrated memory module, and the memory unit parameter of the integrated memory module directly and logically calculates to improve the calculation power, which is equivalent to increasing the calculation core number in a large scale under the condition of unchanged chip area, saving the chip area occupied by a large number of triggers, reducing the hardware occupation ratio, greatly reducing the cost and having the characteristic of high cost performance. The PCM signals obtained by processing the plurality of down-sampling signal sets through the integrated memory module have higher precision, and are easy to be accurately processed and analyzed by related digital devices. In addition, through the matching use of the down-sampling filter and the two storage and calculation integrated modules, the process of converting the PDM signal into the PCM signal is completed, and the conversion structure of converting the PDM signal into the PCM signal is simplified.

As shown in fig. 4, the first case is described in detail by taking the first integrative module as the low-pass filtering process and the second integrative module as the high-pass filtering process, and the first memory matrix of the first integrative module is 64×16 memory cells. The second memory matrix of the second memory module is 64×16 memory cells. Thus, the first memory matrix and the second memory matrix are each a matrix of 64 x 16 as shown in fig. 5 b. The first buffer matrix of the first integrative module and the second buffer matrix of the second integrative module are both 16×64 arrays as shown in fig. 5 a.

According to step a, the weight coefficient of each memory cell of the first memory matrix of the first memory module is adjusted to a low pass filter coefficient, and the weight coefficient of each memory cell of the second memory matrix of the second memory module is adjusted to a high pass filter coefficient. As shown in fig. 5b, h0-h63 of each column of the memory matrix is the weight coefficient of each memory cell of each column of the memory matrix of the memory module, respectively. For example, assume that the memory matrix shown in fig. 5b is a first memory matrix of the first memory module, where h0 of the 64 th row and 1 st column is a weight coefficient of a memory cell of the 64 th row and 1 st column of the first memory matrix of the first memory module, and is a corresponding low-pass filter coefficient.

According to step b, each of the sub-sets of downsampled signals is loaded in parallel into one of the first buffers of the first buffer matrix in each of the downsampled signal sets, and each of the downsampled signals of each of the sub-sets of downsampled signals is loaded in sequence into one of the first buffers of the first buffer matrix in one of the first buffers. The sequence can be set according to actual requirements. And performing multiply-accumulate operation on the downsampled signals of the first buffers of each row of the first buffer matrix and the low-pass filter coefficients of the first storage units of the corresponding columns of the first storage matrix to obtain a first calculation signal of each column of the first storage units, and further obtaining a first calculation signal subset. And after each downsampled signal set is subjected to multiply-accumulate operation of the first integral storage module, a plurality of first storage signal subsets are obtained, and the plurality of first storage signal subsets are sequentially divided to obtain a plurality of first storage signal sets.

Specifically, each downsampled signal set includes a plurality of downsampled signal subsets, the number of the plurality of downsampled signal subsets is the number of rows of the first buffer matrix of the first memory integrated module, and the number of the downsampled signals in each downsampled signal subset is the number of columns of the first buffer matrix. As shown in fig. 5a, the first buffer matrix is an array of 16×64, and one set of downsampled signals includes 16 downsampled signal subsets, and the number of downsampled signals in each downsampled signal subset is 64. As shown in fig. 5a, each row x0-x63 of the buffer matrix is a signal corresponding to each buffer of each row in the buffer matrix of the memory module. For example, assume that the buffer matrix shown in fig. 5a is a first buffer matrix of the first memory module, where x0 of the 1 st row and 1 st column is a downsampled signal corresponding to the first buffer of the 1 st row and 1 st column of the first buffer matrix of the first memory module.

For each down-sampled signal set, loading 16 down-sampled signal subsets in parallel into one row of the first buffers of the first buffer matrix, and loading each down-sampled signal in each down-sampled signal subset into one first buffer of one row in sequence during loading of each row of the first buffers of the first buffer matrix. And performing matrix multiplication operation on the first buffer matrix and the first storage matrix, namely performing multiplication accumulation operation on the downsampled signals of the first buffers in each row of the first buffer matrix and the low-pass filter coefficients of the storage units in the corresponding columns of the first storage matrix to obtain first calculation signals of the storage units in each column of the first storage matrix. As shown in fig. 5a and 5b, y1=x0×h63+x1×h62+ … … +x63×h0, and y1 is a first calculation signal of a memory cell of a first column of the first memory matrix. Y1 is obtained by multiply-accumulate-ing the downsampled signal of the first buffer of the first row of the first buffer matrix with the low-pass filter coefficients of the memory cells of the first column of the first memory matrix. Pushing y2-y16 in this manner. After y1-y16 is obtained, { y1, y2,..y 16} gets a first subset of the stored signals of the first storage matrix, i.e., { y1, y2,..y 16} is a first subset of the stored signals of the first storage matrix. The number of first calculation signals in one first calculation signal subset is the number of columns of the first calculation matrix, namely 16.

In this way, the plurality of downsampled signal sets are low pass filtered through the first computationally intensive module to obtain a plurality of first computationally intensive signal subsets. The whole low-pass filtering processing process has the characteristics of high speed, high calculation power, low power consumption and the like, and the obtained first calculation signal set of each group has high precision and is convenient for the next calculation integrated module to process.

According to step c, in each first stored signal set, a plurality of first stored signal subsets are loaded in parallel into a column of second buffers of the second buffer matrix, and each first stored signal of each first stored signal subset is loaded in sequence into one of the column of second buffers of the second buffer matrix. And multiplying and accumulating the first calculation signals of each row of the second buffer matrix and the high-pass filter coefficients of the second storage units of the corresponding columns of the second storage matrix to obtain a second calculation signal of each column of the second storage units, and further obtaining a second calculation signal subset. After each first storage signal set executes multiply-accumulate operation of the second storage integrated module, a plurality of second storage signal subsets are obtained, and each second storage signal in the plurality of second storage signal subsets is used as a PCM signal.

Specifically, each first calculation signal set includes a plurality of first calculation signal subsets, the number of the plurality of first calculation signal subsets is the number of columns of the second buffer matrix of the second calculation integrated module, and the number of the first calculation signals in each first calculation signal subset is the number of columns of the second buffer matrix. As shown in fig. 5a, the second buffer matrix is an array of 16×64, and one first storage signal set includes 64 first storage signal subsets, and the number of first storage signals in each first storage signal subset is 16.

For each first calculation signal set, 64 first calculation signal subsets are loaded in parallel to each column of second buffers of a second buffer matrix of a second calculation integrated module, and in the process of loading each column of second buffers of the second buffer matrix, each first calculation signal in each first calculation signal set is sequentially loaded into one storage unit of one column. And performing matrix multiplication operation on the second buffer matrix and the second storage matrix, namely performing multiplication accumulation operation on the first storage signals of each row of the second buffer matrix and the high-pass filter coefficients of the storage units of the corresponding columns of the second storage matrix to obtain second storage signals of the storage units of each column of the second storage matrix. At this time, as shown in fig. 5a and 5b, y1=x0×h63+x1×h62+ … … +x63×h0, and y1 is the second calculation signal of the memory cells in the first column of the second memory matrix. Y1 is obtained by multiply-accumulate operation of the first calculation signal of the first buffer of the first row of the second buffer matrix with the high-pass filter coefficient of the calculation unit of the first column of the second memory matrix. Pushing y2-y16 in this manner. After y1-y16 is obtained, a second subset of the stored signals of the second memory matrix is obtained, i.e., { y1, y2,. }, y16} is a first subset of the stored signals of the first memory matrix. The number of second storage signals in one second storage signal subset is the number of columns of the second storage matrix, namely 16.

And after each first calculation signal set is subjected to multiply-accumulate operation of the second calculation integrated module, a plurality of second calculation signal subsets are obtained. And each second stored signal in each second stored signal subset is used as a PCM signal. In this way, the second calculation integrated module performs high-pass filtering processing on the plurality of first calculation signal sets to obtain a plurality of second calculation signal subsets, so as to obtain PCM signals, and the PDM signals are converted into the PCM signals. The whole high-pass filtering processing process has the characteristics of rapidness, high calculation power, low power consumption and the like, and each obtained second calculation signal subset has high precision and is convenient for subsequent digital devices to process.

Aiming at the second condition, if the number of the integrated storage and calculation modules is one, the integrated storage and calculation modules are recorded as third integrated storage and calculation modules, the third integrated storage and calculation modules comprise a plurality of third buffers and a plurality of third storage units, the output ends of the third buffers are connected with the input ends of the third storage units, the third buffers are in a matrix shape to form a third buffer matrix, and the third storage units are in a matrix shape to form a third storage matrix.

The specific implementation procedure of the second case is: A. and adjusting the weight coefficient of each storage unit of the third storage matrix into a first filter coefficient, and performing first filtering processing on a preset number of downsampled signal sets through a third storage integrated module to obtain a first stored signal set, wherein the preset number is the number of columns of the third buffer matrix. B. And then the first filter coefficient of each storage unit of the third storage matrix is adjusted to be a second filter coefficient, the second filter processing is carried out on the first storage signal set through the third storage integrated module, a plurality of second storage signals are obtained, and each second storage signal is used as a PCM signal. C. And repeatedly executing the steps A and B to obtain a plurality of PCM signals.

If the first filter coefficient is a low-pass filter coefficient, the second filter coefficient is a high-pass filter coefficient, the first filter process is a low-pass filter process, and the second filter process is a high-pass filter process. If the first filter coefficient is a high-pass filter coefficient, the second filter coefficient is a low-pass filter coefficient, the first filter process is a high-pass filter process, and the second filter process is a low-pass filter process.

The low-pass filter processing principle and the high-pass filter processing principle in the second case are the same as those in the first case. The low-pass filtering and the high-pass filtering of the plurality of down-sampled signal sets by one integral memory module are required to be switched and adjusted to adjust the weight coefficient of the memory matrix of the integral memory module. The method comprises the steps that a storage matrix of a storage and calculation integrated module is required to be controlled, and in low-pass filtering processing, the weight coefficient of the storage matrix of the storage and calculation integrated module is adjusted to be a low-pass filter coefficient; in the high-pass filtering process, the weight coefficient of the storage matrix of the integrated module is adjusted to be a high-pass filter coefficient.

In the second case, the low-pass filtering process and the high-pass filtering process are performed by only one integral memory module, and the plurality of down-sampling signal sets are directly operated, so that unnecessary data carrying is reduced, and power consumption is reduced. Compared with the first case, in the process of completing the processing of a plurality of down-sampling signal sets, the number of the integrated modules is reduced, so that the power consumption is further reduced, and the conversion efficiency of the PDM signals is improved. And the low-pass filtering processing and the high-pass filtering processing of a plurality of down-sampling signal sets are realized through the integrated memory module, and the memory unit parameter of the integrated memory module directly and logically calculates to improve the calculation power, which is equivalent to increasing the calculation core number in a large scale under the condition of unchanged chip area, saving the chip area occupied by a large number of triggers, reducing the hardware occupation ratio, greatly reducing the cost and having the characteristic of high cost performance. The PCM signals obtained by processing the plurality of down-sampling signal sets through the integrated memory module have higher precision, and are easy to be accurately processed and analyzed by related digital devices. In addition, through the matching use of the down-sampling filter and one memory integrated module, the process of converting the PDM signal into the PCM signal is completed, and the conversion structure of converting the PDM signal into the PCM signal is further simplified.

The second case is described in detail by taking the third integrated module as an example of performing the low-pass filtering process and then performing the high-pass filtering process. And B, after the third integrated memory module is initialized, according to the step A, adjusting the weight coefficient of each memory cell of a third memory matrix of the third integrated memory module into a low-pass filter coefficient. As shown in fig. 5a, the third buffer matrix of the third integrating module is an array of 16×64, and one set of downsampled signals includes 16 downsampled signal subsets, and the number of downsampled signals in each downsampled signal subset is 64. According to the low-pass filtering process of the first case, the down-sampled signal of the third buffer matrix and the low-pass filter coefficient of the third storage matrix perform a multiplication and accumulation operation to obtain a first stored signal subset. Then, the third integrated storage module performs low-pass filtering processing on the preset 64 downsampled signal sets to obtain a first stored signal set. One first set of stored signals includes 16 first subsets of stored signals.

According to step B, after obtaining a first stored signal set, the low-pass filter coefficient of each storage unit of the third storage matrix of the third integrated storage module is adjusted to be a high-pass filter coefficient. And then, carrying out high-pass filtering processing on the first storage signal set through a third storage integrated module, namely carrying out multiply-accumulate operation on the first storage signals of each row of third filters of a third buffer matrix of the third storage integrated module and the high-pass filter coefficients of storage units of corresponding columns of the third storage matrix to obtain second storage signals of each column of storage units in the third storage matrix of the third storage integrated module, and further obtaining a plurality of second storage signals, namely 16 second storage signals. And each of the second stored signals is used as a PCM signal.

According to the step C, the high-pass filter coefficient of each storage unit of the third storage matrix of the third integrated storage module is adjusted to be a low-pass filter coefficient, and the steps A and B are executed to be circularly executed.

After the PCM signal is obtained, in order to match the data processing format of the subsequent related digital signal processing device, format processing needs to be performed on the PCM signal, so as to obtain a processed PCM signal. For example, if each PCM signal obtained in the example shown in fig. 4 is a 32-bit number and the data processing format of the subsequent related digital signal processing device is a 24-bit number, each PCM signal is shifted rightward by a corresponding bit number, and the corresponding bit number is adjusted to 0, so as to obtain a 24-bit number, that is, each processed PCM signal is obtained, and each processed PCM signal is transmitted as an input signal to the subsequent device. Therefore, the subsequent devices can rapidly process the PCM signal and match with the format of the PCM signal, and the processing efficiency of the PCM signal is improved.

In addition, the low-pass filter coefficient and the high-pass filter coefficient are explained taking the case where the cutoff frequency of the low-pass filter principle applied by the low-pass filter process is 20KHz and the cutoff frequency of the high-pass filter principle applied by the high-pass filter process is 20 Hz:

The weight coefficient of each memory cell of the memory matrix of the memory module is rewritable. In the low-pass filtering process, the weight coefficient of the storage unit of the storage matrix of the integrated storage module is adjusted to be a low-pass filtering coefficient so as to achieve the effect of adjusting the filtering frequency. The low-pass filtering process adjusts the weight coefficients of the memory matrix of the memory module shown in fig. 5b to low-pass filter coefficients as follows:

{30100173，17045778，-17236132，18472633，-18944795，17296544，-12818444，5584837，3518864，-12917804，20639411，-24746951，23764648，-17077721，5264812，9895149，-25559199，38287613，-44648645，41950071，-28899112，6099126，23726915，-55859468，83994798，-100955097，99103084，-70810455，6517859，112237611，-351658386，1331167822，1331167822，-351658386，112237611，6517859，-70810455，99103084，-100955097，83994798，-55859468，23726915，6099126，-28899112，41950071，-44648645，38287613，-25559199，9895149，5264812，-17077721，23764648，-24746951，20639411，-12917804，3518864，5584837，-12818444，17296544，-18944795，18472633，-17236132，17045778，30100173}。

the amplitude-frequency response diagram corresponding to the low-pass filtering process is shown in fig. 6, the abscissa of fig. 6 represents the frequency, and the ordinate of fig. 6 represents the amplitude. As can be seen from fig. 6, the low pass filtering process can filter out frequency signals below 20KHZ, resulting in corresponding stored signals.

In the high-pass filtering process, the weight coefficient of the storage unit of the storage matrix of the integrated storage module is adjusted to be a high-pass filter coefficient so as to achieve the effect of adjusting the filter frequency. The high-pass filtering process adjusts the weight coefficients of the memory matrix of the memory integrated module shown in fig. 5b to the high-pass filter coefficients as follows:

{-1731512，-1839771，-2060556，-2404148，-2881216，-3502912，-4281010，-5228084，-6357751，-7684979，-9226506，-11001379，-13031676，-15343474，-17968150，-20944166，-24319552，-28155415，-32531020，-37551293，-43358251，-50148949，-58204755，-67941271，-79998172，-95411949，-115977054，-145088529，-190029066，-269744902，-453725123，-1367431971，1367431971，453725123，269744902，190029066，145088529，115977054，95411949，79998172，67941271，58204755，50148949，43358251，37551293，32531020，28155415，24319552，20944166，17968150，15343474，13031676，11001379，9226506，7684979，6357751，5228084，4281010，3502912，2881216，2404148，2060556，1839771，1731512}

the amplitude-frequency response diagram corresponding to the high-pass filtering process is shown in fig. 7, the abscissa of fig. 7 represents the frequency, and the ordinate of fig. 7 represents the amplitude. As can be seen from fig. 7, the high-pass filtering process can filter out the frequency signal higher than 20HZ, thereby obtaining a corresponding stored signal.

Compared with the prior method and device for converting the PDM signal into the PCM signal, the method and device for converting the PDM signal into the PCM signal are compared with the prior method and device for converting the PDM signal into the PCM signal:

existing methods and apparatus implement the conversion of PDM signals to PCM signals through digital downsampling filters and FIR filters. The order of the digital downsampling filter represents the number of filtered harmonics, and the higher the order is, the better the filtering performance is, but the multiplier and the adder are greatly increased, which means that the filter needs more hardware cost. The basic components of the FIR filter comprise a delay unit, an adder, a multiplier and the like, the adder and the delay unit are generally used for realizing an integrating or differentiating function, multiplication operation with coefficients is completed through the multiplier, and the multiplier is often the component with the largest power consumption occupation ratio and the largest hardware realization area occupation ratio in digital operation. In addition, the power consumption of the existing method and device is increased due to the increase of hardware cost.

However, the down-sampling filter and the memory module are matched for use in the embodiment of the invention, so that the process of converting the PDM signal into the PCM signal is realized, and the conversion structure of converting the PDM signal into the PCM signal is simplified. The storage unit of the integrated storage and calculation module directly participates in logic calculation to improve calculation force, which is equivalent to increasing the number of calculation cores in a large scale under the condition of unchanged chip area, saves a large amount of chip area occupied by devices used for multiplication and addition, reduces the hardware occupation ratio, and ensures that the whole hardware structure is simpler. In addition, the method and the device are realized through the integrated storage and calculation module, so that the number of multipliers and adders is effectively reduced, and the power consumption is reduced.

Thus, the method and apparatus of the present invention first performs a downsampling process on the bit stream of the PDM signal and converts the PDM signal into a plurality of downsampled signals, such as 32bit signed numbers. And then the low-pass filtering processing and the high-pass filtering processing are carried out on the plurality of down-sampling signals through the integrated memory module. Finally, the PCM signal is output, the noise point of the PCM signal is less, the high-quality original data can be restored, and the problems of complex structure and higher power consumption of the traditional method for converting the PDM signal into the PCM signal are solved.

Embodiment two: based on the same inventive concept, the second embodiment of the present invention further provides an apparatus for converting a PDM signal into a PCM signal, as shown in fig. 8, including:

an acquisition module 201, configured to acquire a PDM signal;

a downsampling filter 202, configured to downsample the obtained PDM signal to obtain a plurality of downsampled signal sets, where the downsampling process is configured to reduce a sampling rate of the PDM signal and reduce a calculation amount of the PDM signal;

the integrated memory module 203 is configured to perform low-pass filtering and high-pass filtering on the plurality of downsampled signal sets to obtain PCM signals.

The apparatus of this embodiment includes, but is not limited to, a memory integrated chip.

Embodiment III: based on the same inventive concept, a third embodiment of the present invention further provides an electronic device, which includes the apparatus for converting a PDM signal into a PCM signal according to the second embodiment. Electronic devices include, but are not limited to: digital microphone, digital loudspeaker, electronic device with audio decoding module applied to autopilot, AR (Augmented Reality ), VR (Virtual Reality).

For example, the PCM microphone internally integrates a PDM modulation circuit and a digital filter circuit, and the digital filter circuit further converts the PDM signal into a PCM signal, and then processes the PCM signal. MEMS microphones, which are PDM microphones, are often employed due to the size of the microphone and the complexity of the process. The MEMS microphone is internally integrated with only a PDM modulator to output PDM signals, and a digital downsampling filter circuit with larger area is integrated in an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or a digital signal processing chip (Digital Signal Processing, DSP), so that the high cost performance of digitally transmitting audio signals can be ensured, and the volume and the integration level of the MEMS microphone are ensured. Research into the generation and conversion of PDM signals and PCM signals has become an important point of attention in modern audio processing.

The basic components of the digital filter circuit of the PCM microphone comprise a delay unit, an adder, a multiplier and the like. Usually, an adder and a delay unit are used for realizing an integrating or differentiating function, multiplication operation with coefficients is completed through a multiplier, the multiplier is often the component with the largest power consumption and the largest area occupation in digital operation, and the hardware is used for realizing the component with the largest area occupation. The order of the digital downsampling filter of the PDM microphone represents the number of filtering harmonic waves, and the higher the order is, the better the filtering performance is, but the larger the number of multipliers and adders is, which means that the more hardware cost is needed for the filter.

The PCM microphone formed by the method and the device for converting the PDM signal into the PCM signal only completes the process of converting the PDM signal into the PCM signal through the matching use of the down-sampling filter and the memory integrated module, simplifies the conversion structure of converting the PDM signal into the PCM signal, and avoids the complex conversion structure. And performing downsampling processing on the PDM signals through a downsampling filter to obtain a plurality of downsampled signal sets. The down-sampling processing can down-sample and extract the PDM signal, so that the sampling rate of the PDM signal is reduced, the down-sampled PDM signal can be conveniently processed later, the calculated amount of the PDM signal is reduced, and the power consumption is saved. And the low-pass filtering processing and the high-pass filtering processing are carried out on the plurality of down-sampling signal sets through the integrated memory module, so that the plurality of down-sampling signal sets are directly processed through the integrated memory module, unnecessary data carrying is reduced, power consumption is further reduced, and the conversion efficiency of the PDM signals is improved. The storage unit of the integrated storage and calculation module directly participates in logic calculation to improve calculation force, which is equivalent to increasing the number of calculation cores in a large scale under the condition of unchanged chip area, saving the chip area occupied by a large number of triggers and reducing the hardware occupation ratio. Regarding the PCM signals obtained by processing the plurality of down-sampling signal sets through the integrated memory module, the PCM signals have higher precision and are easier to be accurately processed and analyzed by related digital devices such as audio in a microphone.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of converting a PDM signal to a PCM signal, comprising:

acquiring a PDM signal;

2. The method of claim 1, wherein the number of the integrative modules is at least two, the at least two integrative modules comprising a first integrative module and a second integrative module;

3. The method of claim 2, wherein the performing, by the memory module, the low-pass filtering and the high-pass filtering on the plurality of down-sampled signal sets to obtain PCM signals comprises:

4. The method of claim 3, wherein said performing, by said first computation block, a first filtering process on each of said downsampled signal sets to obtain a first subset of computed signals, and further obtaining a plurality of first sets of computed signals, comprises:

5. The method of claim 4, wherein said performing, by said second computation block, a second filtering process on said plurality of first computation signal sets to obtain said PCM signal, comprises:

6. The method of claim 1, wherein the number of the integrative storage modules is one, the integrative storage modules are third integrative storage modules, the third integrative storage modules comprise a plurality of third buffers and a plurality of third storage units, the output ends of the third buffers are connected with the input ends of the third storage units, the third buffers are in a matrix shape to form a third buffer matrix, and the third storage units are in a matrix state to form a third storage matrix;

Repeatedly executing the two steps to obtain a plurality of PCM signals;

7. The method of claim 1, wherein the downsampling the acquired PDM signal with the downsampling filter to obtain a plurality of downsampled signal sets, comprising:

8. The method of claim 7, wherein a Z-domain transfer function of the CIC filter is:

；

the amplitude-frequency characteristic of the CIC filter is as follows:

；

9. An apparatus for converting a PDM signal to a PCM signal, comprising:

the acquisition module is used for acquiring the PDM signal;

10. An electronic device comprising the apparatus for converting a PDM signal according to claim 9 into a PCM signal.