JP5540211B2 - Equalizer for 1-bit audio signal - Google Patents

Description

  The present invention relates to an improvement in an apparatus having a function of performing equalization on a 1-bit audio signal.

  A method of performing equalizing processing on a 1-bit audio signal has been proposed. For example, after a 1-bit audio signal is converted into a multi-bit by an FIR filter that suppresses high-frequency noise, a plurality of noise shapers and dither generators are built in. An apparatus that performs equalizing processing (EQ processing) through the IIR filter of the above and then outputs the signal back to a 1-bit audio signal by a delta-sigma modulator (ΔΣ modulator) provided in the final stage has been proposed (for example, (Refer nonpatent literature 1.).

P. Eastty et al., “DSD-Wide a Practical Implementation for Professional Audio”, Convention Paper 5377, UK, “Audio Engineering Society”, May 12-15, 2001 in the Netherlands Amsterdam, p7-p11

  However, according to the above-described conventional apparatus, the amount of calculation is enormous and the calculation cost is high. Also, since the processing system is unsuitable for parallelization within the same channel, real-time processing is extremely difficult to realize.

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide an apparatus capable of performing equalization on a 1-bit audio signal in real time with high quality.

  In order to achieve the above-mentioned object, the present inventor, as a result of earnest research, inserts a delay device for one sample between each cascade-connected biquad filter, for example, SIMD operation (Single After constructing a configuration suitable for Instruction / Multiple Data calculation, it was considered to use the last-stage biquad filter as a DSD filter (Direct Stream Digital Filter) that suppresses out-of-band noise.

That is, in order to achieve the above object, the present invention is an apparatus for performing equalization on a bit stream that is a 1-bit audio signal sequence sampled at a predetermined cycle,
1-bit audio signal processing means for sequentially receiving a given bit stream and outputting a positive specific value when the digital value is “1”, and outputting the negative specific value when the digital value is “0” When,
A plurality of filters are connected in cascade, and the filter at the front stage receives the output from the 1-bit audio signal processing means, and performs a filtering operation, which is an operation for filtering, on each filter in parallel. Filter processing means for outputting the filtering results of all filters,
A delta-sigma converter that receives an output signal from the filter processing means and converts the output signal into a 1-bit audio signal;
A delay device is provided between the filters in the plurality of filters.

  According to the present invention, the filter processing means accepts the output from the 1-bit audio signal processing means by the filter at the front stage of the filter processing means, and performs the filtering operation on each filter in parallel so that all the filters are used. The filtering result is output, and a 1-bit audio signal finally equalized by the delta-sigma modulator is output. Since a delay device is provided between the plurality of filters, it is possible to perform the filtering operation with the subsequent filter without waiting for the completion of the previous filtering operation. As a result, the filtering result of all the filters, in other words, equalization can be performed very quickly, and equalization for a 1-bit audio signal can be performed in real time without degrading sound quality.

  More specifically, the delay device is preferably a delay device having a delay corresponding to the predetermined period in terms of processing speed and simplification of the configuration. Each of the plurality of filters has a simple configuration and can realize an equalizing function if it is a biquad filter in which the denominator and numerator of the transfer function H (z) in the Z conversion region are second-order filters. More specifically, a first delay unit (530) and a second delay unit (525) connected in series, and first and second multipliers that multiply the output of the first delay unit (530) by a given coefficient. A second multiplier (510, 515); third and fourth multipliers (500, 505) for multiplying the output of the second delay unit (525) by a given coefficient; and the first multiplication. A first adder (540) for adding the output of the multiplier (510) and the output of the third multiplier (500), the output of the second multiplier (515) and the third multiplier (505) ) And the output of the fifth multiplier (520), and a second adder (545) that adds the output of the fifth multiplier (520), the fifth multiplier (520) being the first adder (540) Of the first to fifth multipliers (510, 5 and 5). The coefficient of 5,500,505,520) can be capable of setting independently.

  According to the present invention, it is possible to perform an equalizing process on a 1-bit audio signal in real time with high quality.

1 is a configuration diagram of a 1-bit audio signal equalizing apparatus 1. FIG. It is a block diagram of the filter process part 200 of embodiment of this invention. It is a block diagram of the conventional filter process part. 2 is a configuration diagram of a delta-sigma modulator 300. FIG. It is a block diagram of a biquad filter. It is explanatory drawing of the example of a characteristic of a biquad filter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the embodiment of the present invention will be described, and then an effort will be made to facilitate understanding by explaining the difference in operation from the prior art.

(Constitution)
FIG. 1 is a block diagram of a 1-bit audio signal equalizing apparatus 1 according to an embodiment of the present invention. The apparatus 1 includes a 1-bit audio signal processing unit 100, a filter processing unit 200 having an equalizing function, a delta-sigma modulator 300 (ΔΣ modulator 300) that outputs a given signal as a 1-bit audio signal sequence, and It is comprised.

(1-bit signal processing unit 100)
The 1-bit signal processing unit 100 receives a sequentially supplied 1-bit audio signal sequence (bit stream), and outputs a value “−1.0” when the received signal is a digital value “0”. When the received signal is a digital value “1”, a value “+1.0” is output. That is, the given bit stream is converted into “−1.0” and “+1.0” signal sequences, and these signal sequences are input to the filter processing unit 200 in the next stage. In this example, the values “−1.0” and “+1.0” are output for the digital values “0” and “1”, respectively, but the output value is not limited to this. . For example, “−2.0” and “+2.0” may be output. More generally, if “X” is a positive real number, “−X” and “+ X” may be output for digital values “0” and “1”, respectively.

(Delta Sigma Modulator 300)
FIG. 4 is a configuration diagram of an example of the delta-sigma modulator (ΔΣ modulator) 300 in FIG. As shown in FIG. 4, the delta-sigma modulator 300 includes an adder 340, an integrator 310 that inputs the addition result of the adder 340, and a quantization that quantizes the integration result of the integrator 310 with one bit. 320, and the output of the quantizer 320 is returned to one terminal of the adder 340 via the delay unit 330. The integrator 310 is configured to return the adder 312 and the addition result of the adder 312 to one terminal of the adder 312 via the delay unit 314. The adder 340 is configured to subtract the 1-bit audio output signal that has passed through the delay unit 330 from the signal output from the filter processing unit 200, and the adder 312 is output from the adder 340. And the signal that has passed through the delay unit 314 are added. By providing the delta-sigma modulator 300 having such a configuration in the final stage, the apparatus 1 outputs a 1-bit audio signal that has been equalized by the filter processing unit 200. The delta sigma modulator 300 itself is well known, and not only the first order delta sigma modulation shown in FIG. 4 but also a second or higher order delta sigma modulator (not shown) may be adopted.

(Filter processing unit 200)
FIG. 2 is an explanatory diagram of a configuration example of the filter processing unit 200. The filter processing unit 200 has a configuration in which four biquad filters 210, 230, 250, and 270 are connected in series. In order to describe the configuration of the filter processing unit 200, first, the configuration and function of a biquad filter will be described with reference to FIG.

  FIG. 5 is a configuration diagram of an example of a biquad filter employed in the present embodiment. The biquad filter refers to a second-order filter having both a denominator and a numerator of the transfer function in the Z-transform region. The biquad filter of FIG. 5 includes a multiplier 500 having a coefficient b2, a multiplier 505 having a coefficient a2, a multiplier 510 having a coefficient b1, a multiplier 515 having a coefficient a1, and a multiplier having a coefficient a0. 520. Further, an adder 540 that adds the outputs of the multiplier 500 and the multiplier 505 and an adder 545 that adds the outputs of the multiplier 505 and the multiplier 515 are provided. An input signal is also added to the adder 540, and the addition result obtained by multiplying the addition result in the adder 540 by the multiplier 520 is also added to the adder 545. It has become. Further, the addition result in the adder 540 is delayed by the delay unit 530 and supplied as an input of the multiplier 510 and the multiplier 515, and the signal delayed by the delay unit 530 is further delayed by the delay unit 525. Thus, it is configured to be supplied as an input to the multiplier 500 and the multiplier 505.

  That is, the biquad filter shown in FIG. 5 multiplies the first delay device 530 and the second delay device 525 connected in series and the output of the first delay device 530 by given coefficients (b1, a1). First and second multipliers 510 and 515; third and fourth multipliers 500 and 505 for multiplying the output of the second delay unit 525 by a given coefficient (b2, a2); and a first multiplication A first adder 540 that adds the output of the multiplier 510 and the output of the third multiplier 500, the output of the second multiplier 515, the output of the third multiplier 505, and the fifth multiplier 520. A second adder 545 for adding the output, and the fifth multiplier 520 is connected to multiply the addition result of the first adder 540 by a given coefficient (a0), and First to fifth multipliers 510, 515, 500, 505, 52 It is configured to be set to the coefficients independently.

  In the biquad filter having the configuration shown in FIG. 5, the transfer function H (z) in the Z conversion region is “H (z) = (a0 + a1 · z∥−1 + a2 · z∥−2) / (1−b1 · z∧-1−b2 · z∧-2) ”(∧ represents a power. In this case, z∧-1 means the negative first power of z, and ∧-2 indicates the negative second power of z. Meaning). That is, the denominator of the transfer function H (z) is obtained by adding the coefficient a0, the coefficient a1 multiplied by z minus 1 and the coefficient a2 multiplied by z minus square, The denominator of the transfer function H (z) is obtained by subtracting the constant 1 from the coefficient b1 multiplied by the negative first power of z and the coefficient b2 multiplied by the second power of z. Incidentally, the coefficients a0, a1, a2, b1, b2 are set to “a0 = 1.0011066, a1 = −1.9976525, a2 = 0.99666971, b1 = 1.9976525, b2 = −0.99777627 (however, the sampling frequency of the 1-bit audio signal: 2.844200 (Hz) ””, The frequency amplitude characteristic as shown in FIG. 6 is obtained. In FIG. 6, the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dB). The frequency amplitude characteristic of FIG. 6 has a peaking filter characteristic in which the amplitude gain has a peak in the vicinity of 5000 (Hz). Depending on how the coefficients are set, the peak position in the frequency amplitude characteristic can be set to a desired one, or the desired equalizing function can be realized by setting the frequency characteristic to low pass, high pass, or the like.

  Now, the filter processing unit 200 shown in FIG. 2 connects the four biquad filters 210, 230, 250, and 270 in a column as described above. More specifically, the biquad filter 210 is composed of five multipliers 211, 212, 213, 214, 215, two delay units 216, 217, and two adders 218, 219. Yes. Similarly, the biquad filter 230 includes five multipliers 231, 232, 233, 234, 235, two delay devices 236, 237, and two adders 238, 239, The biquad filter 250 includes five multipliers 251, 252, 253, 254, and 255, two delay units 256 and 257, and two adders 258 and 259, and further includes a biquad filter. 270 includes five multipliers 271, 272, 273, 274 and 275, two delay units 276 and 277, and two adders 278 and 279.

  A delay device is provided between each biquad filter. In the configuration example of FIG. 2, a delay device 290 is provided between the biquad filter 210 and the biquad filter 230, and similarly, a delay device 291 is provided between the biquad filter 230 and the biquad filter 250. In addition, a delay 292 is provided between the biquad filter 250 and the biquad filter 270. More specifically, a signal from the 1-bit signal processing unit 100 is input to the adder 218 constituting the biquad filter 210, while a filtering result in the biquad filter 210 is output from the adder 219. The output of the first-stage biquad filter 210 is delayed by the delay unit 290 and input to the adder 238 of the second-stage biquad filter 230. Similarly, the filtering result of the biquad filter 230 is output from the adder 239 constituting the biquad filter 230. The output of the second biquad filter 230 is delayed by the delay unit 291 to form a three-stage filter. It is configured to be input to the adder 258 of the eye biquad filter 250. Then, the adder 259 constituting the bi-quad filter 250 outputs the filtering result of the bi-quad filter 250. The output of the third bi-quad filter 250 is delayed by the delay unit 292, and the fourth-stage filter is output. The biquad filter 270 is input to the adder 278. The delay amounts of the three delay units 290, 291 and 292 are times corresponding to one sample when a 1-bit audio signal is sampled at a predetermined period.

  Thus, this embodiment is characterized in that the delay devices 290, 291 and 292 are provided between the filters. In addition, the part shown with a dotted line in FIG. 2 has shown the range which can calculate the filtering calculation which is a calculation for filtering in parallel by the parallel calculation control part 280 so that it may demonstrate later. In the case of FIG. 2, since each biquad filter 210, 230, 250, 270 is entirely surrounded by a dotted line, as will be described later, parallel operations for all filtering operations in each biquad filter 210, 230, 250, 270 are performed. This is because the delay devices 290, 291 and 292 are provided between the biquad filters.

(Operation)
Next, the operation will be described. When a bit stream that is a 1-bit audio signal sequence is sequentially supplied to the 1-bit signal processing unit 100, the 1-bit signal processing unit 100 receives the sequentially supplied bit stream. When the received signal is a digital value “0”, the value “−1.0” is output, and when the received signal is “1”, the value “+1.0” is output. Then, the signal sequence composed of “−1.0” and “+1.0” is supplied to the filter processing unit 200.

  The filter processing unit 200 receives the supplied signal sequence, performs filtering by filtering operation in the four biquad filters 210, 230, 250, and 270 connected in cascade, performs a desired equalizing process, and performs delta processing. This is supplied to the sigma modulator 300. Then, the delta-sigma modulator 300 converts the signal supplied from the filter processing unit 200 into a 1-bit audio signal and outputs it.

  By the way, the filtering operation (parallel operation processing of filtering operation) performed by the four biquad filters 210, 230, 250, and 270 is characterized in this embodiment. This will be described in comparison with the conventional example shown in FIG. In FIG. 3 as well, a portion indicated by a dotted line indicates a range in which parallel operation can be performed by the parallel operation control unit 281. In FIG. 3, first, the parallel arithmetic control unit 281 sets the outputs of the delay units 216, 236, 256, and 276 for each biquad filter as indicated by “(1)”. Multipliers 211, 231, 251, 271 having coefficients multiply the coefficients and output. Next, as indicated by “(2)”, in each biquad filter, the outputs of the delay units 216, 236, 256, and 276 are multiplied by multipliers 212, 232, having coefficients set for the respective ones. At 252 and 272, the coefficient is multiplied and output. Next, as indicated by “(3)”, in each biquad filter, the outputs of the delay units 217, 237, 257, and 277 are multiplied by multipliers 213, 233, and 253 having coefficients set for the respective filters. In 273, the coefficient is multiplied and output. Then, as indicated by “(4)”, in each biquad filter, the outputs of the delay units 217, 237, 257, and 277 are multiplied by multipliers 214, 234, and 254 having coefficients set for the respective filters. In 274, the coefficient is multiplied and output. Thus, the filtering operations indicated by “(1)” to “(4)” are performed in parallel with respect to each biquad filter.

  However, as shown by “(5)”, the adder 218 of the first-stage biquad filter 210 adds the output of the multiplier 211 and the output of the multiplier 213, and this addition result is sent to the multiplier 215. The set coefficient is multiplied, and this is added by the adder 219 together with the output of the multiplier 212 and the output of the multiplier 214 (see (6)). However, for the addition by the adder 238 shown in the next “(7)”, the adder 238 of the second-stage filter must perform addition processing using the addition result of the previous-stage adder 219. At this point, filtering operations must be performed sequentially. Similarly, the addition processing by the adder 258 of the third-stage filter indicated by “(9)” is performed using the addition result of the adder 239 of the preceding-stage filter indicated by “(8)”. Therefore, the filtering operation cannot be performed quickly. Thereafter, all filtering operations indicated by “(10)”, “(11)”, and “(12)” are sequentially performed. As described above, in the conventional example shown in FIG. 3, only a part of the filtering calculation process of each filter (the parts (1) to (4) surrounded by a dotted line) can be performed in parallel.

  On the other hand, in the filter processing unit 200 according to the embodiment of the present invention shown in FIG. 2, the parallel calculation control unit 280 performs the filtering calculation indicated by “(1)” to “(6)” for each filter. Run in parallel. First, the filtering operations from “(1)” to “(4)” are not different from those in FIG. Next, in the arithmetic processing indicated by “(5)”, the addition processing of the adders 218, 238, 258, and 278 on the front side (left side of the drawing) in each filter is performed in parallel. Even if the adder 238 on the front side of the second-stage filter does not wait for the addition result of the adder 219 of the previous-stage filter to be output, the delay unit 290 holds the data one sample before. This makes it possible to perform addition in the adder 238 by using. Similarly, if the data before one sample held by the delay device 291 is used, the adder 258 on the filter front side of the third stage does not have to wait for the addition result of the adder 239 of the previous filter to be output, Further, if the data before one sample held by the delay unit 292 is used, the adder 278 on the filter front side of the fourth stage (the last stage) does not have to wait for the addition result of the adder 259 of the preceding filter to be output. It will be over.

  As described above, according to the present embodiment, the filter processing unit 200 receives the output from the 1-bit audio signal processing unit 100 by the frontmost filter of the filter processing unit 200, and performs a filtering operation on each filter. Are performed in parallel to output the filtering result of all the filters, and the 1-bit audio signal finally equalized by the delta-sigma modulator 300 is output. Since the delay devices 290, 291 and 292 are provided between the plurality of filters, it is possible to perform the filtering operation with the subsequent filter without waiting for the end of the previous filtering operation. As a result, the filtering result of all the filters, in other words, equalization can be performed very quickly, and equalization for a 1-bit audio signal can be performed in real time without degrading sound quality.

  In FIG. 2, the same delay devices 290, 291 and 292 for delaying one sample are provided between the biquad filters. However, the delay amounts of the three delay devices are not necessarily the same. Further, the delay amount in the delay unit may be two samples or more. However, in order to simplify the configuration and prevent the delay time from being too long, it is preferable to use the configuration of FIG. 2 in which a delay device having the same delay amount for one sample is provided.

  In addition, although FIG. 2 demonstrated the example which comprised the filter process part 200 like hardware, it is also possible to implement | achieve the filter process part 200 with software. For example, by executing a program recorded on a recording medium such as a ROM by a CPU or DSP, a multiplier, a delay unit, an adder, or a biquad filter constituting each biquad filter 210, 230, 250, 270 It is possible to realize the delay devices 290, 291 and 292 provided in FIG. The parallel processing of the filter calculation performed by the parallel calculation control unit 280 can be realized by a calculation program of SIMD calculation (Single Instruction / Multiple Data calculation). For example, it is possible to implement parallel filtering operations using vector type addition, vector type multiplication, etc. in a high-level language.

  As described above, the present invention can be used for a music apparatus that performs equalizing processing on a 1-bit audio input signal.

1 Equalizer for 1-bit audio signal 100 1-bit audio signal processor
200 Filter processing unit 210 Biquad filter 230 Biquad filter 250 Biquad filter 270 Biquad filter 290 Delay unit 291 Delay unit 292 Delay unit 300 Delta-sigma modulator 310 Integrator 320 Quantizer 330 Delay unit 340 Adder 500 Multiplier 505 Multiplier 510 Multiplier 515 Multiplier 520 Multiplier 525 Delay 530 Delay 540 Adder 545 Adder

Claims (4)

An apparatus for performing equalization on a bit stream that is a 1-bit audio signal sequence sampled at a predetermined cycle,
1-bit audio signal processing means for sequentially receiving a given bit stream and outputting a positive specific value when the digital value is “1”, and outputting the negative specific value when the digital value is “0” When,
A plurality of filters are connected in cascade, and the filter at the front stage receives the output from the 1-bit audio signal processing means, and performs a filtering operation, which is an operation for filtering, on each filter in parallel. Filter processing means for outputting the filtering results of all filters,
A delta-sigma converter that receives an output signal from the filter processing means and converts the output signal into a 1-bit audio signal;
An equalizer for 1-bit audio signal, wherein a delay device is provided between the filters in the plurality of filters. The equalization apparatus for 1-bit audio signals according to claim 1,
The equalizing apparatus for 1-bit audio signal, wherein the delay unit is a delay unit having a delay of the predetermined period. In the equalization apparatus for 1-bit audio signals according to any one of claims 1 and 2,
Each of the plurality of filters is a biquad filter in which a denominator and a numerator of a transfer function H (z) in a Z conversion region are second-order filters, and an equalizer for 1-bit audio signal, The equalization apparatus for 1-bit audio signals according to claim 3,
Each of the plurality of filters is
A first delay unit (530) and a second delay unit (525) connected in series, and first and second multipliers (multipliers) for multiplying the output of the first delay unit (530) by a given coefficient ( 510, 515), third and fourth multipliers (500, 505) for multiplying the output of the second delay unit (525) by a given coefficient, and the output of the first multiplier (510) And the output of the third multiplier (500), the output of the second multiplier (515), the output of the third multiplier (505), and the fifth A second adder (545) for adding the output of the first multiplier (520), and the fifth multiplier (520) is provided with the addition result of the first adder (540). And the first to fifth multipliers (510, 515, 500, 5 1-bit audio signal equalizing apparatus characterized by being capable of setting a coefficient of 5,520) independently.

Images