CN117457663A - Display panel - Google Patents
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- CN117457663A CN117457663A CN202310162468.XA CN202310162468A CN117457663A CN 117457663 A CN117457663 A CN 117457663A CN 202310162468 A CN202310162468 A CN 202310162468A CN 117457663 A CN117457663 A CN 117457663A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
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- 239000000758 substrate Substances 0.000 claims description 97
- 230000004888 barrier function Effects 0.000 claims description 42
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 21
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 229910052814 silicon oxide Inorganic materials 0.000 description 21
- 239000000463 material Substances 0.000 description 17
- 229910004205 SiNX Inorganic materials 0.000 description 11
- 229910052750 molybdenum Inorganic materials 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 9
- 229920000139 polyethylene terephthalate Polymers 0.000 description 9
- 239000005020 polyethylene terephthalate Substances 0.000 description 9
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 4
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
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- 239000010409 thin film Substances 0.000 description 4
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
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- ZXVONLUNISGICL-UHFFFAOYSA-N 4,6-dinitro-o-cresol Chemical compound CC1=CC([N+]([O-])=O)=CC([N+]([O-])=O)=C1O ZXVONLUNISGICL-UHFFFAOYSA-N 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention relates to a display panel. According to the invention, at least one pixel circuit module is integrated on each driving circuit module, so that the frame position where the driving circuit layer is positioned in the prior art has a display function to form a frame display area, and the frame-free effect of the display panel is realized. In the main display area, the pixel circuit layer is electrically connected with the first signal transfer pad, the first signal transfer pad is electrically connected with the signal wire, the pixel circuit layer is electrically connected with the first signal transfer pad, the first signal transfer pad is electrically connected with the second signal transfer pad, the second signal transfer pad is electrically connected with the third signal transfer pad, and the third signal transfer pad is electrically connected with the signal wire, so that the signal wire can be prepared through a thick metal process, the thickness of the signal wire is increased, the square resistance of the signal wire is reduced, the voltage drop is further reduced, the display brightness of the display panel is improved, and the display uniformity of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
Currently, the main-stream sub-millimeter light emitting diode (Mini LED) backlight products, the Mini LED direct display products and the Micro light emitting diode (Micro LED) direct display products are basically thin film transistor (English full name: thin Film Transistor, TFT) back plates based on low-temperature polysilicon (English full name: low Temperature Poly-Silicon, LTPS) or indium gallium zinc oxide (English full name: indium Gallium Zinc Oxide, IGZO). After the back plate process is finished, anodes and cathodes for driving Light Emitting Diodes (LEDs) in the pixel circuit layers are exposed on the surface of the back plate, and then anodes and cathodes of Mini LEDs or Micro LEDs are electrically connected with the anodes and cathodes in the pixel circuit layers through a piece-bonding process or a mass transfer and metal bonding or other bonding processes, so that the Mini LEDs or Micro LEDs can be driven by an Active Matrix through the pixel circuit layers in the back plate.
In current backplane technology, the signal wire material is typically copper, molybdenum/aluminum/molybdenum, or titanium/aluminum/titanium. On one hand, the thickness of the signal wire manufactured by sputtering processes such as physical vapor deposition (English full name: physical Vapor Deposition, PVD for short) and the like is very limited, and the thickness is at most about 1um at present, so that the square resistance of the signal wire is larger; on the other hand, in the case of a large-sized display panel, or in the case where the transparency requirement is relatively high and the width of the signal line on the display panel is required to be compressed as much as possible to improve the transmittance, the resistance of the signal line may be large; the large resistance of the signal line may cause an increase in voltage drop in the display panel, resulting in a decrease in display brightness of the display panel, and eventually, a non-uniformity in display brightness of the display panel.
Disclosure of Invention
The invention aims to provide a display panel which can solve the problems of uneven display brightness and the like of the display panel caused by large resistance of a signal wire in the existing display panel.
In order to solve the above problems, the present invention provides a display panel including a main display area and a bezel display area; the display panel includes: a substrate; the metal layer is arranged on the substrate and comprises a plurality of signal lines; the driving circuit modules are arranged on one side of the metal layer, which is far away from the substrate, and are positioned in the frame display area and are arranged at intervals; the pixel circuit modules are arranged on one side of the driving circuit module, far away from the substrate, of the frame display area and are arranged at intervals; each of the pixel circuit modules includes: the pixel circuit comprises a first substrate, a pixel circuit layer arranged on the first substrate, a light emitting unit arranged on one side of the pixel circuit layer far away from the first substrate, and a first signal transfer pad arranged on the first substrate far away from the pixel circuit layer; each of the driving circuit modules includes: the circuit comprises a second substrate, a driving circuit layer arranged on the second substrate, a second signal transfer pad arranged on one side of the driving circuit layer far away from the second substrate, and a third signal transfer pad arranged on one side of the second substrate far away from the driving circuit layer; in the frame display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal line.
Further, the first signal transfer pad includes one or more of a first scan signal transfer pad, a first data signal transfer pad, a first high voltage power signal transfer pad, and a first low voltage power signal transfer pad electrically connected to the first scan line, the first data line, the first high voltage power line, and the first low voltage power line of the pixel circuit layer, respectively; the second signal transfer pads are arranged in one-to-one correspondence with the first signal transfer pads.
Further, the main display area is also provided with a plurality of pixel circuit modules, and the pixel circuit modules are arranged at intervals on one side of the metal layer of the main display area, which is far away from the substrate; in the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, and the first signal transfer pad is electrically connected to the signal line of the main display area; the metal layer of the main display area includes: a third data line disposed along a first direction, a fourth scan line disposed parallel to each other along a second direction crossing the first direction, a third high voltage power line, and a third low voltage power line; the first scan signal transfer pad, the first data signal transfer pad, the first high voltage power supply signal transfer pad and the first low voltage power supply signal transfer pad are respectively and electrically connected to the fourth scan line, the third data line, the third high voltage power supply line and the third low voltage power supply line.
Further, the third signal transfer pad includes one or more of a first clock signal transfer pad, a first positive power input pad, a first negative power input line, a second scan line, a third scan line, a second data line, a second high voltage power line, and a first low voltage power line electrically connected to the driving circuit layer, respectively; the metal layer of the frame display region includes: a second clock signal line, a second positive power input line, a second negative power input line, a fourth data line, a fourth high voltage power line, and a fourth low voltage power line disposed in parallel with each other along a first direction, and a fifth scan line and a sixth scan line disposed in parallel with each other along a second direction crossing the first direction; the first clock signal transfer pad, the first positive power input signal transfer pad, the first negative power input signal transfer pad, the second scan signal transfer pad, the third scan signal transfer pad, the second data signal transfer pad, the second high voltage power signal transfer pad, and the second low voltage power signal transfer pad are electrically connected to the second clock signal line, the second positive power input line, the second negative power input line, the fifth scan line, the sixth scan line, the fourth data line, the fourth high voltage power line, and the fourth low voltage power line, respectively.
Further, the first scan signal transfer pad, the first data signal transfer pad, the first high voltage power supply signal transfer pad, and the first low voltage power supply signal transfer pad are respectively and correspondingly electrically connected to the third scan signal transfer pad, the second data signal transfer pad, the second high voltage power supply signal transfer pad, and the second low voltage power supply signal transfer pad.
Further, the first substrate comprises a first buffer layer, a first flexible layer, a first barrier layer, a second flexible layer, a second barrier layer, a first conductive unit and a second buffer layer which are sequentially arranged; the pixel circuit layer includes: a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a second conductive unit, a first planarization layer, a third conductive unit, and a second planarization layer; the first low-voltage power line penetrates through the second flat layer to be electrically connected with the third conductive unit, the third conductive unit penetrates through the first flat layer to be electrically connected with the second conductive unit, the second conductive unit penetrates through the first interlayer insulating layer, the second gate insulating layer, the first gate insulating layer and the second buffer layer to be electrically connected with the first conductive unit, and the first conductive unit penetrates through the second barrier layer, the second flexible layer, the first barrier layer, the first flexible layer and the first buffer layer to be electrically connected with the first signal transfer pad.
Further, the second substrate comprises a third buffer layer, a third flexible layer, a third barrier layer, a fourth flexible layer, a fourth barrier layer, a fourth conductive unit and a fourth buffer layer which are sequentially arranged; the driving circuit layer includes: a third gate insulating layer, a fourth gate insulating layer, a second interlayer insulating layer, a fifth conductive unit, a third planarization layer, a sixth conductive unit, and a fourth planarization layer; the second signal transfer pad penetrates through the fourth flat layer to be electrically connected with the sixth conductive unit, the sixth conductive unit penetrates through the third flat layer to be electrically connected with the fifth conductive unit, the fifth conductive unit penetrates through the second interlayer insulating layer, the fourth gate insulating layer, the third gate insulating layer and the fourth buffer layer to be electrically connected with the fourth conductive unit, and the fourth conductive unit penetrates through the fourth barrier layer, the fourth flexible layer, the third barrier layer, the third flexible layer and the third buffer layer to be electrically connected with the third signal transfer pad.
Further, the distance between the two pixel circuit modules in the main display area is equal to the distance between the two pixel circuit modules in the frame display area.
Further, the display panel further includes: the first packaging body is positioned in the main display area; the first packaging body covers one side of the light emitting unit far away from the first substrate and extends to cover the pixel circuit layer and the first substrate; the bottom surface of the first package body is flush with the bottom surface of the first substrate.
Further, the display panel further includes: the second packaging body is positioned in the frame display area; the second packaging body covers one side of the light emitting unit far away from the first substrate, and extends to cover the pixel circuit layer, the first substrate, the first signal transfer pad, the second signal transfer pad, the driving circuit layer and the second substrate; the bottom surface of the second package body is flush with the bottom surface of the second substrate.
Further, the thickness of the signal line of the metal layer is greater than 10 micrometers.
Further, the light emitting unit is a light emitting diode, the anode of the light emitting diode is electrically connected to the anode of the pixel circuit layer, and the cathode of the light emitting diode is electrically connected to the cathode of the pixel circuit layer; or the light emitting unit is an organic light emitting diode, an anode of the organic light emitting diode is electrically connected to an anode of the pixel circuit layer, and a cathode of the organic light emitting diode is electrically connected to a cathode of the pixel circuit layer.
The invention has the advantages that: according to the invention, at least one pixel circuit module is integrated on each driving circuit module, so that the frame position where the driving circuit layer is positioned in the prior art has a display function to form a frame display area, and the frame-free effect of the display panel is realized.
In the main display area, the pixel circuit layer is electrically connected with the first signal transfer pad, the first signal transfer pad is electrically connected with the signal wire, in the frame display area, the pixel circuit layer is electrically connected with the first signal transfer pad, the first signal transfer pad is electrically connected with the second signal transfer pad, the second signal transfer pad is electrically connected with the third signal transfer pad, and the third signal transfer pad is electrically connected with the signal wire, so that the signal wire can be prepared through a thick metal process, the thickness of the signal wire is increased, the square resistance of the signal wire is reduced, the voltage drop is further reduced, the display brightness of the display panel is improved, and the display uniformity of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic plan view of a display panel of the present invention;
FIG. 2 is a schematic plan view of a substrate and metal layer of the present invention;
FIG. 3 is a schematic view of a display panel of the main display area of the present invention;
FIG. 4 is a schematic diagram of a pixel circuit module according to the present invention;
FIG. 5 is a circuit schematic of the pixel circuit module of the present invention;
FIG. 6 is a schematic diagram of a first signal transfer pad according to the present invention;
FIG. 7 is a schematic diagram of a display panel of a bezel display area according to the present invention;
FIG. 8 is a schematic diagram of a display panel of a bezel display area of the present invention;
FIG. 9 is a schematic diagram of a driving circuit module and a pixel circuit module of a frame display region according to the present invention;
FIG. 10 is a schematic diagram of a third signal transfer pad according to the present invention;
FIG. 11 is a schematic diagram showing the connection between the first signal transfer pad and the signal line in the main display area according to the present invention;
fig. 12 is a schematic diagram illustrating connection between a third signal transfer pad and a signal line in a frame display area according to the present invention.
Reference numerals illustrate:
100. a display panel; 101. a main display area;
102. a frame display area;
1. a substrate; 2. A metal layer;
3. a pixel circuit module; 4. A driving circuit module;
5. A first package; 6. A second package;
21. a signal line;
31. a first substrate; 32. A pixel circuit layer;
33. a light emitting unit; 34. A first signal transfer pad;
3101. a first buffer layer; 3102. A first flexible layer;
3103. a first barrier layer; 3104. A second flexible layer;
3105. a second barrier layer; 3106. A first conductive unit;
3107. a second buffer layer;
3201. an active layer; 3202. A first gate insulating layer;
3203. a first electrode; 3204. A second gate insulating layer;
3205. a second electrode; 3206. A first interlayer insulating layer;
3207. a third electrode; 3208. A fourth electrode;
3209. a second conductive unit; 3210. A first planarization layer;
3211. a fifth electrode; 3212. A third conductive unit;
3213. a second flat layer; 3214. An anode;
3215. a first low voltage power supply line; 3216. A pixel definition layer;
41. A second substrate; 42. A driving circuit layer;
43. a second signal transfer pad; 44. A third signal transfer pad;
4101. a third buffer layer; 4102. A third flexible layer;
4103. a third barrier layer; 4104. A fourth flexible layer;
4105. a fourth barrier layer; 4106. A fourth conductive unit;
4107. a fourth buffer layer;
4201. a third gate insulating layer; 4202. A fourth gate insulating layer;
4203. a second interlayer insulating layer; 4204. A fifth conductive unit;
4205. a third planarization layer; 4206. A sixth conductive unit;
4207. a fourth flat layer.
Detailed Description
The following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, is provided to fully convey the substance of the invention to those skilled in the art, and to illustrate the invention to practice it, so that the technical disclosure of the invention will be made more clear to those skilled in the art to understand how to practice the invention more easily. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as limited to the set forth herein.
The directional terms used herein, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are used for explaining and describing the present invention only in terms of the directions of the drawings and are not intended to limit the scope of the present invention.
In the drawings, like structural elements are referred to by like reference numerals and components having similar structure or function are referred to by like reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.
Example 1
As shown in fig. 1, the present embodiment provides a display panel 100. The display panel 100 includes a main display area 101 and a bezel display area 102. In this embodiment, the frame display area 102 is located at two ends of the main display area 101, and in other embodiments, the frame display area 102 may be located at only one end of the main display area 101 or may be located at four ends of the main display area 101.
Wherein the display panel 100 includes: a substrate 1, a metal layer 2, a plurality of driving circuit modules 4, and a plurality of pixel circuit modules 3.
The substrate 1 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate and polyethylene naphthalate, so that the substrate 1 has better impact resistance and can effectively protect the display panel 100.
As shown in fig. 1 and 2, a metal layer 2 is provided on the substrate 1. Wherein the metal layer 2 comprises a number of signal lines 21.
Wherein the signal line 21 of the metal layer 2 may be formed on the surface of the substrate 1 by a thick metal preparation process such as an electroplating process, a chemical plating process, a printing process, etc. Thus, the thickness of the signal line 21 of the metal layer 2 is greater than 10 micrometers, so that the square resistance of the signal line 21 can be reduced by increasing the thickness of the signal line 21, the voltage drop can be reduced, the display brightness of the display panel 100 can be improved, and the display uniformity of the display panel 100 can be improved.
As shown in fig. 1 and 3, a plurality of pixel circuit modules 3 are disposed on a side of the metal layer 2 of the main display area 101 away from the substrate 1 and are spaced apart from each other.
The pixel circuit module 3 may be mounted to a corresponding position by soldering or Bonding (Bonding) through a surface mount technology (english full name: surface Mounted Technology, abbreviated to SMT) and the like, so as to be electrically connected to the corresponding signal line 21.
As shown in fig. 3, each of the pixel circuit modules 3 includes: a first substrate 31, a pixel circuit layer 32, a light emitting unit 33, and a first signal transfer pad 34.
As shown in fig. 4, the first substrate 31 includes: a first buffer layer 3101, a first flexible layer 3102, a first barrier layer 3103, a second flexible layer 3104, a second barrier layer 3105, a first conductive unit 3106, and a second buffer layer 3107.
The first buffer layer 3101 mainly plays a role of buffering, and may be made of SiOx, siNx, or a combination of SiNx and SiOx.
Wherein the first flexible layer 3102 is disposed on the first buffer layer 3101. In this embodiment, the material of the first flexible layer 3102 is Polyimide (PI). In other embodiments, the material of the first flexible layer 3102 may be a flexible material such as polyethylene terephthalate (PET), so as to increase the flexibility of the first substrate 31.
Wherein the first barrier layer 3103 is disposed on a side of the first flexible layer 3102 remote from the first buffer layer 3101. The first barrier layer 3103 may serve to prevent water oxygen from penetrating through the first flexible layer 3102 to a structure above the first barrier layer 3103, preventing damage to the display panel 100.
Wherein the second flexible layer 3104 is disposed on a side of the first barrier layer 3103 remote from the first buffer layer 3101. In this embodiment, the material of the second flexible layer 3104 is Polyimide (PI). In other embodiments, the second flexible layer 3104 may be made of a flexible material such as polyethylene terephthalate (PET), so as to increase the flexibility of the first substrate 31.
Wherein a second barrier layer 3105 is disposed on a side of the second flexible layer 3104 remote from the first buffer layer 3101. The second barrier layer 3105 may serve to prevent water oxygen from penetrating through the second flexible layer 3104 to a structure above the second barrier layer 3105, preventing damage to the display panel 100.
Wherein, the first conductive unit 3106 is disposed on a side of the second barrier layer 3105 away from the first buffer layer 3101, and is electrically connected to the first signal transfer pad 34.
Wherein the second buffer layer 3107 is disposed on a side of the first conductive unit 3106 remote from the first buffer layer 3101. The second buffer layer 3107 mainly plays a role of buffering, and may be made of SiOx, siNx, or a combination of SiNx and SiOx.
The pixel circuit layer 32 is disposed on the first substrate 31 and electrically connected to the corresponding signal line 21.
The pixel circuit layer 32 includes: an active layer 3201, a first gate insulating layer 3202, a first electrode 3203, a second gate insulating layer 3204, a second electrode 3205, a first interlayer insulating layer 3206, a third electrode 3207, a fourth electrode 3208, a second conductive element 3209, a first planarization layer 3210, a fifth electrode 3211, a third conductive element 3212, a second planarization layer 3213, an anode 3214, a first low-voltage power supply line 3215, and a pixel defining layer 3216.
Wherein an active layer 3201 is disposed on the first substrate 31. Specifically, the active layer 3201 is disposed on a side of the second buffer layer 3107 away from the first buffer layer 3101. The active layer 3201 includes a channel portion 32011 and two conductive portions 32012 respectively located at both ends of the channel portion 32011.
The first gate insulating layer 3202 is disposed on a side of the active layer 3201 away from the first substrate 31, and extends to cover the second buffer layer 3107. The first gate insulating layer 3202 is mainly used for preventing a short circuit phenomenon from occurring in contact between the active layer 3201 and the first electrode 3203. The material of the first gate insulating layer 3202 may be SiOx or SiNx or Al2O3 or a combination structure of SiNx and SiOx or a combination structure of SiOx, siNx and SiOx.
The first electrode 3203 is disposed on a side of the first gate insulating layer 3202 away from the first substrate 31. The first electrode 3203 is disposed corresponding to the channel portion 32011 of the active layer 3201. The material of the first electrode 3203 may be Mo or a combination of Mo and Al or a combination of Mo and Cu or a combination of Mo, cu and IZO or a combination of IZO, cu and IZO or a combination of Mo, cu and ITO or a combination of Ni, cu and Ni or a combination of MoTiNi, cu and MoTiNi or a combination of NiCr, cu and NiCr or CuNb.
The second gate insulating layer 3204 is disposed on a side of the first electrode 3203 away from the first substrate 31, and extends to cover the first gate insulating layer 3202. The second gate insulating layer 3204 is mainly used for preventing a short circuit phenomenon from occurring in contact between the first electrode 3203 and the second electrode 3205. The material of the second gate insulating layer 3204 may be SiOx, siNx, al2O3, a combination structure of SiNx and SiOx, a combination structure of SiOx, siNx and SiOx, or the like.
The second electrode 3205 is disposed on a side of the second gate insulating layer 3204 away from the first substrate 31. The second electrode 3205 is coupled to the first electrode 3203 to form a storage capacitor Cst. The material of the second electrode 3205 may be Mo or a combination of Mo and Al or a combination of Mo and Cu or a combination of Mo, cu and IZO or a combination of IZO, cu and IZO or a combination of Mo, cu and ITO or a combination of Ni, cu and Ni or a combination of MoTiNi, cu and MoTiNi or a combination of NiCr, cu and NiCr or CuNb.
The first interlayer insulating layer 3206 is disposed on a side of the second electrode 3205 away from the first substrate 31, and extends to cover the second gate insulating layer 3204. The interlayer insulating layer 3206 may be made of SiOx, siNx, or SiNOx.
Wherein the third electrode 3207 and the fourth electrode 3208 are arranged on the same layer on one side of the interlayer insulating layer 3206 away from the first substrate 31, and are respectively and electrically connected to two conductive portions 32012 of the active layer 3201. In this embodiment, the third electrode 3207 is a source, and the fourth electrode 3208 is a drain.
Wherein the second conductive unit 3209 is disposed in the same layer as the third electrode 3207 and the fourth electrode 3208.
Wherein, the first flat layer 3210 covers one side of the third electrode 3207 and the fourth electrode 3208 away from the first substrate 31, and extends to cover the first interlayer insulating layer 3206. The material of the first flat layer 3210 may be SiOx or SiNx or a combination structure of SiNx and SiOx.
The fifth electrode 3211 is disposed on a side of the first planarization layer 3210 remote from the first substrate 31. The fifth electrode 3211 is mainly used for electrically connecting the anode 3214 and the fourth electrode 3208.
Wherein, the third conductive unit 3212 is arranged in the same layer as the fifth electrode 3211.
Wherein, the second flat layer 3213 covers one side of the fifth electrode 3211 and the third conductive unit 3212 away from the first substrate 31 and extends over the first flat layer 3210. The material of the second flat layer 3213 may be SiOx or SiNx or a combination structure of SiNx and SiOx.
Wherein the anode 3214 is disposed on a side of the second planar layer 3213 remote from the first substrate 31. The anode 3214 may be made of metal. In this embodiment, the anode 3214 is made of silver (Ag). Thus, the anode 3214 has good electrical conductivity.
Wherein, the first low voltage power line 3215 is arranged at the same layer as the anode 3214. In this embodiment, the material of the first low voltage power line 3215 is the same as that of the anode 3214, so that the low voltage power line 3215 and the anode 3214 may be formed by one process. In this embodiment, the first low voltage power line 3215 is multiplexed as the cathode of the pixel circuit layer 32.
The pixel defining layer 3216 is disposed on a side of the first low voltage power line 3215 and the anode 3214 away from the first substrate 31, and extends over the second flat layer 3213.
Wherein the active layer 3201, the first gate insulating layer 3202, the first electrode 3203, the second gate insulating layer 3204, the second electrode 3205, the first interlayer insulating layer 3206, the third electrode 3207 and the fourth electrode 3208 form a first thin film transistor T 1 。
In the present embodiment, T is as shown in FIG. 5 1 Is electrically connected to the first high voltage power line VDD, T 1 Is electrically connected to the positive electrode 3302, t of the light emitting unit 33 1 Is electrically connected to the first plate of the storage capacitor Cst. The second plate of the storage capacitor Cst is electrically connected to a first high voltage power line VDD. T (T) 2 Is electrically connected to the first Data line Data, T 2 Is electrically connected to T 1 Gate of T 2 Is electrically connected to the first scanAnd (5) tracing Scan. In the present embodiment, the negative electrode 3303 of the light emitting unit 33 is electrically connected to the first low voltage power line VSS.
Wherein the light emitting unit 33 is electrically connected to a side of the pixel circuit layer 32 remote from the first substrate 31.
In the present embodiment, the light emitting unit 33 is a light emitting diode (LED for short). Specifically, the light emitting diode may be a Mini LED or a Micro LED. The light emitting unit 33 includes: a light-emitting functional layer 3301, a positive electrode 3302, and a negative electrode 3303.
In this embodiment, the positive electrode 3302 of the light emitting unit 33 is electrically connected to the anode electrode 3214 of the pixel circuit layer 32, and the negative electrode 3303 of the light emitting unit 33 is electrically connected to the first low voltage power line (cathode electrode) 3215 of the pixel circuit layer 32.
In other embodiments, the Light Emitting unit 33 may also employ an Organic Light Emitting Diode (OLED). The anode of the organic light emitting diode is electrically connected to the anode 3214 of the pixel circuit layer 32, and the cathode of the organic light emitting diode is electrically connected to the first low voltage power line 3215 of the pixel circuit layer 32.
The first signal transfer pad 34 is disposed on a side of the first substrate 31 away from the pixel circuit layer 32. The first signal transfer pad 34 may be obtained by performing a metal patterning process on a surface of the first substrate 31 on a side remote from the pixel circuit layer 32.
As shown in fig. 6, the first signal transfer pad 34 includes: the first Scan line Scan, the first Data line Data, the first high voltage power line VDD, and the first low voltage power line VSS of the pixel circuit layer 32 are electrically connected to one or more of the first Scan signal transfer pad 3401, the first Data signal transfer pad 3402, the first high voltage power signal transfer pad 3403, and the first low voltage power signal transfer pad 3404, respectively. In this embodiment, the first signal transfer pad 34 includes: a first scan signal transfer pad 3401 electrically connected to the first scan line, a first data signal transfer pad 3402 electrically connected to the first data line, a first high voltage power supply signal transfer pad 3403 electrically connected to the first high voltage power supply line, and a first low voltage power supply signal transfer pad 3404 electrically connected to the first low voltage power supply line.
As shown in fig. 11, the metal layer 2 of the main display area 101 includes: a third data line 2102 disposed along a first direction M, a fourth scan line 2101 disposed along a second direction N crossing the first direction M in parallel with each other, a third high voltage power line 2103, and a third low voltage power line 2104; the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high voltage power supply signal transfer pad 3403 and the first low voltage power supply signal transfer pad 3404 are electrically connected to the fourth scan line 2101, the third data line 2102, the third high voltage power supply line 2103 and the third low voltage power supply line 2104, respectively. In fact, the metal layer 2 is provided with a fourth scan signal transfer pad (not shown), a third data signal transfer pad, a third high voltage power signal transfer pad (not shown) and a third low voltage power signal transfer pad (not shown) corresponding to the fourth scan line 2101, the third data line 2102, the third high voltage power line 2103 and the third low voltage power line 2104 respectively, and then the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high voltage power signal transfer pad 3403 and the first low voltage power signal transfer pad 3404 are electrically connected with the fourth scan signal transfer pad (not shown), the third data signal transfer pad, the third high voltage power signal transfer pad (not shown) and the third low voltage power signal transfer pad (not shown) respectively.
As shown in fig. 4, in the present embodiment, a first low voltage power line 3215 penetrates the second flat layer 3213 to be electrically connected to the third conductive unit 3212, the third conductive unit 3212 penetrates the first flat layer 3210 to be electrically connected to the second conductive unit 3209, the second conductive unit 3209 penetrates the first interlayer insulating layer 3206, the second gate insulating layer 3204, the first gate insulating layer 3202 and the second buffer layer 3107 to be electrically connected to the first conductive unit 3106, the first conductive unit 3106 penetrates the second barrier layer 3105, the second flexible layer 3104, the first barrier layer 3103, the first flexible layer 3102 and the first buffer layer 3101 to be electrically connected to the first signal transfer pad 34.
In the main display area 101, the pixel circuit layer 32 is electrically connected to the first signal transfer pad 34, and the first signal transfer pad 34 is electrically connected to the signal line 21, so that the signal line 21 can be prepared by a thick metal process, the thickness of the signal line 21 is increased, the square resistance of the signal line 21 is reduced, the voltage drop is further reduced, the display brightness of the display panel 100 is improved, and the display uniformity of the display panel 100 is improved.
As shown in fig. 3, the display panel 100 further includes: a first package 5. The first package 5 is located in the main display area 101. Specifically, the first package 5 covers a side of the light emitting unit 33 away from the first substrate 31, and extends to cover the pixel circuit layer 32 and the first substrate 31; the bottom surface of the first package 5 is flush with the bottom surface of the first substrate 31. The first package 5 is mainly used to prevent intrusion of water oxygen into the light emitting unit 33, the pixel circuit layer 32, and the first substrate 31.
As shown in fig. 1, 7 and 8, the driving circuit modules 4 are disposed on a side of the metal layer 2 away from the substrate 1, and are located in the frame display area 102 and spaced apart from each other. The driving circuit module 4 may be mounted to a corresponding position by soldering or Bonding (Bonding) through a surface mount technology (english full name: surface Mounted Technology, abbreviated to SMT) and the like, so as to be electrically connected to the corresponding signal line 21.
As shown in fig. 1, 7 and 8, the plurality of pixel circuit modules 3 are further disposed on a side of the frame display area 102, which is far from the substrate 1, and are spaced apart from each other. Wherein the interval between the pixel circuit modules 3 located in the main display area 101 is equal to the interval between the pixel circuit modules 3 located in the bezel display area 102, whereby the display uniformity of the display panel 100 can be improved. In this embodiment, the pixel circuit module 3 located in the main display area 101 and the pixel circuit module 3 located in the frame display area 102 have the same structure. In other embodiments, the structures of the pixel circuit module 3 located in the main display area 101 and the pixel circuit module 3 located in the frame display area 102 may also be different.
As shown in fig. 8, each of the driving circuit modules 4 is provided corresponding to at least one of the pixel circuit modules 3. In this embodiment, each of the driving circuit modules 4 is disposed corresponding to three of the pixel circuit modules 3.
In this embodiment, at least one pixel circuit module 3 is integrated on each driving circuit module 4, so that the frame position where the driving circuit layer is located in the prior art has a display function to form the frame display area 102, which is beneficial to realizing the borderless effect of the display panel 100.
As shown in fig. 9, each of the driving circuit modules 4 includes: a second substrate 41, a driving circuit layer 42, a second signal transfer pad 43 and a third signal transfer pad 44.
Wherein the second substrate 41 includes: third buffer layer 4101, third flex layer 4102, third barrier layer 4103, fourth flex layer 4104, fourth barrier layer 4105, fourth conductive element 4106, and fourth buffer layer 4107.
The third buffer layer 4101 mainly plays a role of buffering, and may be made of SiOx, siNx, or a combination structure of SiNx and SiOx.
Wherein, the third flexible layer 4102 is disposed on the third buffer layer 4101. In this embodiment, the material of the third flexible layer 4102 is Polyimide (PI). In other embodiments, the third flexible layer 4102 may be made of a flexible material such as polyethylene terephthalate (PET), so as to increase the flexibility of the second substrate 41.
Wherein a third barrier layer 4103 is disposed on a side of the third flex layer 4102 remote from the first buffer layer 3101. The third barrier layer 4103 may be used to prevent water oxygen from penetrating through the third flexible layer 4102 to structures above the third barrier layer 4103, preventing damage to the display panel 100.
Wherein the fourth flexible layer 4104 is disposed on a side of the third barrier layer 4103 remote from the third buffer layer 4101. In this embodiment, the material of the fourth flexible layer 4104 is Polyimide (PI). In other embodiments, the fourth flexible layer 4104 may be made of a flexible material such as polyethylene terephthalate (PET), so as to increase the flexibility of the second substrate 41.
Wherein a fourth barrier layer 4105 is disposed on a side of the fourth flex layer 4104 remote from the third buffer layer 4101. The fourth barrier layer 4105 may be used to prevent water oxygen from penetrating through the fourth flexible layer 4104 to structures above the fourth barrier layer 4105, preventing damage to the display panel 100.
Wherein the fourth conductive unit 4106 is disposed on a side of the second barrier layer 3105 away from the third buffer layer 4101.
Wherein, the fourth buffer layer 4107 is disposed on a side of the fourth conductive unit 4106 away from the third buffer layer 4101. The fourth buffer layer 4107 mainly plays a role of buffering, and may be made of SiOx, siNx, or a combination structure of SiNx and SiOx.
Wherein, the driving circuit layer 42 is disposed on the second substrate 41 and electrically connected to the corresponding signal line 21.
Wherein the driving circuit layer 42 includes: third gate insulating layer 4201, fourth gate insulating layer 4202, second interlayer insulating layer 4203, fifth conductive unit 4204, third planar layer 4205, sixth conductive unit 4206, and fourth planar layer 4207. The driving circuit layer 42 and the first thin film transistor T of the pixel circuit layer 32 1 The same structure is not described in detail herein.
The second signal transfer pad 43 is disposed on a side of the driving circuit layer 42 near the second substrate 41. The third signal transfer pad 44 is disposed on a side of the second substrate 41 away from the driving circuit layer 42. The second signal transfer pads 43 are disposed in one-to-one correspondence with the first signal transfer pads 34.
As shown in fig. 10, the third signal transfer pad 44 includes: in one or more embodiments of the first clock signal line (not shown), the first positive power input line (not shown), the first negative power input line (not shown), the second Scan line (Scan (n-1)), the third Scan line (Scan (n)), the second data line, the second high voltage power line, and the first clock signal pad 4401, the first positive power input signal pad 4402, the first negative power input signal pad 4403, the second Scan signal pad 4404, the third Scan signal pad 4405, the second data signal pad 4406, the second high voltage power signal pad 4407, and the second low voltage power signal pad 4408, which are electrically connected to the driving circuit layer 42, the third signal pad 44 comprises: the first clock signal transfer pad 4401, the first positive power input signal transfer pad 4402, the first negative power input signal transfer pad 4403, the second scan signal transfer pad 4404, the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high voltage power signal transfer pad 4407, and the second low voltage power signal transfer pad 4408.
Specifically, the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high voltage power signal transfer pad 3403 and the first low voltage power signal transfer pad 3404 are electrically connected to the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high voltage power signal transfer pad 4407 and the second low voltage power signal transfer pad 4408, respectively.
As shown in fig. 12, the metal layer 2 of the frame display area 102 includes: a second clock signal line 2105, a second positive power input line 2106, a second negative power input line 2107, a fourth data line 2110, a fourth high-voltage power line 2111, and a fourth low-voltage power line 2112, which are arranged parallel to each other, along a first direction M, and a fifth scan line 2108 and a sixth scan line 2109, which are arranged parallel to each other, along a second direction N crossing the first direction M; the first clock signal transfer pad 4401, the first positive power input signal transfer pad 4402, the first negative power input signal transfer pad 4403, the second scan signal transfer pad 4404, the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high voltage power signal transfer pad 4407 and the second low voltage power signal transfer pad 4408 are electrically connected to the second clock signal line 2105, the second positive power input line 2106, the second negative power input line 2107, the fifth scan line 2108, the sixth scan line 2109, the fourth data line 2110, the fourth high voltage power line 2111 and the fourth low voltage power line 2112, respectively. In other embodiments, the fifth scan line 2108 and the sixth scan line 2109 may be arranged along the first direction M.
Similarly, the metal layer 2 is provided with a second clock signal switching pad (not shown), a second positive power input signal switching pad (not shown), a second negative power input signal switching pad (not shown), a fifth scanning signal switching pad (not shown), a sixth scanning signal switching pad (not shown), a fourth data signal switching pad (not shown), a fourth high voltage power signal switching pad (not shown) and a fourth low voltage power signal switching pad (not shown) corresponding to the second clock signal line 2105, the second positive power input line 2106, the second negative power input line 2107, the fifth scanning line 2108, the sixth scanning line 2109, the fourth data line 2110, the fourth high voltage power supply line 2111 and the fourth low voltage power supply line 2112, respectively, and then the first clock signal switching pad 4401, the first positive power input signal switching pad 4403, the second scanning signal switching pad 4404, the third scanning signal switching pad 5, the second negative power input signal switching pad 4406, the second data signal switching pad (not shown), the fourth high voltage power supply signal switching pad (not shown), the fourth voltage power supply signal switching pad (not shown) and the fourth low voltage power supply signal switching pad (not shown) respectively, A fourth high voltage power signal transfer pad (not shown) and a fourth low voltage power signal transfer pad (not shown).
As shown in fig. 10, in the present embodiment, the second signal pad 43 is electrically connected to the sixth conductive unit 4206 through the fourth flat layer 4207, the sixth conductive unit 4206 is electrically connected to the fifth conductive unit 4204 through the third flat layer 4205, the fifth conductive unit 4204 is electrically connected to the fourth conductive unit 4106 through the second interlayer insulating layer 4203, the fourth gate insulating layer 4202, the third gate insulating layer 4201 and the fourth buffer layer 4107, and the fourth conductive unit 4106 is electrically connected to the third signal pad 44 through the fourth barrier layer 4105, the fourth flexible layer 4104, the third barrier layer 4103, the third flexible layer 4102 and the third buffer layer 4101.
As shown in fig. 10, in the frame display area 102, the pixel circuit layer 32 is electrically connected to the first signal transfer pad 34, the first signal transfer pad 34 is electrically connected to the second signal transfer pad 43, the second signal transfer pad 43 is electrically connected to the third signal transfer pad 44, and the third signal transfer pad 44 is electrically connected to the signal line 21, so that the signal line 21 can be prepared by a thick metal process, the thickness of the signal line 21 is increased, the square resistance of the signal line 21 is reduced, the voltage drop is further reduced, the display brightness of the display panel 100 is improved, and the display uniformity of the display panel 100 is improved.
As shown in fig. 8 and 9, the display panel 100 further includes a second package 6. The second package 6 is located in the frame display area 102, and the second package 6 covers a side of the light emitting unit 33 away from the first substrate 31 and extends to cover the pixel circuit layer 32, the first substrate 31, the first signal transfer pad 34, the second signal transfer pad 43, the driving circuit layer 42 and the second substrate 41; the bottom surface of the second package 6 is flush with the bottom surface of the second substrate 41. The second package 6 is mainly used for preventing the intrusion of water and oxygen into the pixel circuit module 3, the second signal transfer pad 43, the driving circuit layer 42 and the second substrate 41.
The embodiment also provides a preparation method of the display panel. A pixel circuit layer 32 is prepared on the first substrate 31. Specifically, the pixel circuit layer 32 includes a plurality of pixel circuit units, and a scribe line is reserved between adjacent pixel circuit units. Signals such as Scan, data, VDD, VSS required for the pixel circuit layer 32 are conducted to the first signal transfer pad 34 on the side of the first substrate 31 remote from the pixel circuit layer 32 by a laser drilling and silver (Ag) filling process in the holes. The anode 3214 and the first low voltage power line (cathode) 3215 of the pixel circuit layer 32 are exposed on the surface layer of the pixel circuit layer 32, and then the anode 3302 and the cathode 3303 of the light emitting unit 33 are electrically connected with the anode 3214 and the first low voltage power line (cathode) 3215 of the pixel circuit layer 32 through a bonding process, or a mass transfer bonding metal bonding or other bonding processes. Next, the first package 5 is prepared in the scribe lines between the light emitting unit 33, the pixel circuit layer 32, the first substrate 31, and the pixel circuit units to form a first semi-finished product. The first semi-finished product is separated by a dicing process to form a plurality of pixel circuit modules 3 packaged with the first package 5.
Bonding the pixel circuit module 3 which is not packaged on the driving circuit module 4, and then conducting signals required by the pixel circuit module 3 to a third signal transfer pad 44 on one side of the second substrate 41 far away from the driving circuit layer 42 through a process of laser drilling and filling Ag in holes or a process of filling metal after deep holes are etched; meanwhile, the signals required by the driving circuit module 4 are conducted to the third signal transfer pad 44 on one side of the second substrate 41 far away from the driving circuit layer 42 by the process of laser drilling and filling Ag in the holes or the process of filling metal after deep holes are etched and dug, and then the second packaging body 6 is prepared on the driving circuit module 4 and the pixel circuit module 3 for packaging.
Further, the foregoing has outlined a detailed description of a display panel provided herein, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, and the above examples are provided to assist in understanding the methods and core ideas of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (12)
1. The display panel is characterized by comprising a main display area and a frame display area;
the display panel includes:
a substrate;
the metal layer is arranged on the substrate and comprises a plurality of signal lines;
the driving circuit modules are arranged on one side of the metal layer, which is far away from the substrate, and are positioned in the frame display area and are arranged at intervals; and
the pixel circuit modules are arranged on one side, away from the substrate, of the driving circuit module of the frame display area and are arranged at intervals;
each of the pixel circuit modules includes: the pixel circuit comprises a first substrate, a pixel circuit layer arranged on the first substrate, a light emitting unit arranged on one side of the pixel circuit layer far away from the first substrate, and a first signal transfer pad arranged on the first substrate far away from the pixel circuit layer;
each of the driving circuit modules includes: the circuit comprises a second substrate, a driving circuit layer arranged on the second substrate, a second signal transfer pad arranged on one side of the driving circuit layer far away from the second substrate, and a third signal transfer pad arranged on one side of the second substrate far away from the driving circuit layer;
In the frame display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal line.
2. The display panel of claim 1, wherein the first signal transfer pad comprises one or more of a first scan signal transfer pad, a first data signal transfer pad, a first high voltage power signal transfer pad, and a first low voltage power signal transfer pad electrically connected to the first scan line, the first data line, the first high voltage power line, and the first low voltage power line of the pixel circuit layer, respectively;
the second signal transfer pads are arranged in one-to-one correspondence with the first signal transfer pads.
3. The display panel according to claim 2, wherein the main display area is also provided with a plurality of the pixel circuit modules, and the plurality of the pixel circuit modules are arranged at a side of the metal layer of the main display area away from the substrate at intervals;
in the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, and the first signal transfer pad is electrically connected to the signal line of the main display area;
The metal layer of the main display area includes: a third data line disposed along a first direction, a fourth scan line disposed parallel to each other along a second direction crossing the first direction, a third high voltage power line, and a third low voltage power line;
the first scan signal transfer pad, the first data signal transfer pad, the first high voltage power supply signal transfer pad and the first low voltage power supply signal transfer pad are respectively and electrically connected to the fourth scan line, the third data line, the third high voltage power supply line and the third low voltage power supply line.
4. The display panel of claim 2, wherein the third signal transfer pad comprises one or more of a first clock signal transfer pad, a first positive power input pad, a first negative power input line, a second scan line, a third scan line, a second data line, a second high voltage power line, and a second low voltage power line electrically connected to the driving circuit layer, respectively;
The metal layer of the frame display region includes: a second clock signal line, a second positive power input line, a second negative power input line, a fourth data line, a fourth high voltage power line, and a fourth low voltage power line disposed in parallel with each other along a first direction, and a fifth scan line and a sixth scan line disposed in parallel with each other along a second direction crossing the first direction;
the first clock signal transfer pad, the first positive power input signal transfer pad, the first negative power input signal transfer pad, the second scan signal transfer pad, the third scan signal transfer pad, the second data signal transfer pad, the second high voltage power signal transfer pad, and the second low voltage power signal transfer pad are electrically connected to the second clock signal line, the second positive power input line, the second negative power input line, the fifth scan line, the sixth scan line, the fourth data line, the fourth high voltage power line, and the fourth low voltage power line, respectively.
5. The display panel of claim 4, wherein the first scan signal transfer pad, the first data signal transfer pad, the first high voltage power signal transfer pad, and the first low voltage power signal transfer pad are electrically connected to the third scan signal transfer pad, the second data signal transfer pad, the second high voltage power signal transfer pad, and the second low voltage power signal transfer pad, respectively.
6. The display panel of claim 4, wherein the display panel comprises,
the first substrate comprises a first buffer layer, a first flexible layer, a first blocking layer, a second flexible layer, a second blocking layer, a first conductive unit and a second buffer layer which are sequentially arranged;
the pixel circuit layer includes: a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a second conductive unit, a first planarization layer, a third conductive unit, and a second planarization layer;
the first low-voltage power line penetrates through the second flat layer to be electrically connected with the third conductive unit, the third conductive unit penetrates through the first flat layer to be electrically connected with the second conductive unit, the second conductive unit penetrates through the first interlayer insulating layer, the second gate insulating layer, the first gate insulating layer and the second buffer layer to be electrically connected with the first conductive unit, and the first conductive unit penetrates through the second barrier layer, the second flexible layer, the first barrier layer, the first flexible layer and the first buffer layer to be electrically connected with the first signal transfer pad.
7. The display panel of claim 6, wherein the second substrate comprises a third buffer layer, a third flexible layer, a third barrier layer, a fourth flexible layer, a fourth barrier layer, a fourth conductive unit, and a fourth buffer layer disposed in that order;
The driving circuit layer includes: a third gate insulating layer, a fourth gate insulating layer, a second interlayer insulating layer, a fifth conductive unit, a third planarization layer, a sixth conductive unit, and a fourth planarization layer;
the second signal transfer pad penetrates through the fourth flat layer to be electrically connected with the sixth conductive unit, the sixth conductive unit penetrates through the third flat layer to be electrically connected with the fifth conductive unit, the fifth conductive unit penetrates through the second interlayer insulating layer, the fourth gate insulating layer, the third gate insulating layer and the fourth buffer layer to be electrically connected with the fourth conductive unit, and the fourth conductive unit penetrates through the fourth barrier layer, the fourth flexible layer, the third barrier layer, the third flexible layer and the third buffer layer to be electrically connected with the third signal transfer pad.
8. The display panel of claim 1, wherein a pitch between the two pixel circuit modules located in the main display area is equal to a pitch between the pixel circuit modules located in the bezel display area.
9. The display panel of claim 1, further comprising:
the first packaging body is positioned in the main display area;
The first packaging body covers one side of the light emitting unit far away from the first substrate and extends to cover the pixel circuit layer and the first substrate;
the bottom surface of the first package body is flush with the bottom surface of the first substrate.
10. The display panel of claim 1, further comprising:
the second packaging body is positioned in the frame display area;
the second packaging body covers one side of the light emitting unit far away from the first substrate, and extends to cover the pixel circuit layer, the first substrate, the first signal transfer pad, the second signal transfer pad, the driving circuit layer and the second substrate;
the bottom surface of the second package body is flush with the bottom surface of the second substrate.
11. The display panel of claim 1, wherein the thickness of the signal lines of the metal layer is greater than 10 microns.
12. The display panel according to claim 1, wherein the light emitting unit is a light emitting diode, an anode of the light emitting diode is electrically connected to an anode of the pixel circuit layer, and a cathode of the light emitting diode is electrically connected to a cathode of the pixel circuit layer; or alternatively
The light emitting unit is an organic light emitting diode, an anode of the organic light emitting diode is electrically connected to an anode of the pixel circuit layer, and a cathode of the organic light emitting diode is electrically connected to a cathode of the pixel circuit layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310162468.XA CN117457663A (en) | 2023-02-22 | 2023-02-22 | Display panel |
| PCT/CN2023/087932 WO2024174360A1 (en) | 2023-02-22 | 2023-04-12 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310162468.XA CN117457663A (en) | 2023-02-22 | 2023-02-22 | Display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112885847B (en) * | 2021-01-27 | 2023-02-07 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
| KR20230006735A (en) * | 2021-07-02 | 2023-01-11 | 삼성디스플레이 주식회사 | Electronic device and display panel included therein |
| KR20230019313A (en) * | 2021-07-29 | 2023-02-08 | 삼성디스플레이 주식회사 | Display panel and display apparatus including the same |
| CN114171563B (en) * | 2021-11-30 | 2023-07-04 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114975403A (en) * | 2022-05-24 | 2022-08-30 | Tcl华星光电技术有限公司 | Display panel, preparation method thereof and splicing display device |
| CN115064115A (en) * | 2022-07-01 | 2022-09-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN115311975A (en) * | 2022-08-09 | 2022-11-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN115632053A (en) * | 2022-09-26 | 2023-01-20 | 京东方科技集团股份有限公司 | Driving backboard, display panel and display device |
-
2023
- 2023-02-22 CN CN202310162468.XA patent/CN117457663A/en active Pending
- 2023-04-12 WO PCT/CN2023/087932 patent/WO2024174360A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024174360A1 (en) | 2024-08-29 |
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