CN117457656A - Manufacturing method of semiconductor structure and structure thereof - Google Patents
Manufacturing method of semiconductor structure and structure thereof Download PDFInfo
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- CN117457656A CN117457656A CN202210827394.2A CN202210827394A CN117457656A CN 117457656 A CN117457656 A CN 117457656A CN 202210827394 A CN202210827394 A CN 202210827394A CN 117457656 A CN117457656 A CN 117457656A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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Abstract
The embodiment of the disclosure relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure and the structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming an active region, wherein the active region is arranged at intervals along a first direction, a second direction and a third direction, and the active region comprises a first doped region, a channel region and a second doped region which are arranged along the second direction; forming word lines, wherein the word lines extend along a first direction and comprise a first word line and a second word line, the first word line is positioned on the top surface of the channel region, and the second word line is positioned on the bottom surface of the channel region; forming bit lines, wherein the bit lines are positioned between adjacent active areas arranged along the second direction, extend along the third direction and cover the side walls of the second doped areas far away from the channel areas; and forming a capacitor, wherein the capacitor extends along the second direction, is stacked and arranged along the third direction, and covers the side wall of the first doped region, which is far away from the channel region. The space utilization of the semiconductor structure can be improved.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the structure thereof.
Background
With the continuous development of semiconductor structures, the critical dimensions of the semiconductor structures are continuously reduced, but due to the limitation of the photoetching machine, the critical dimensions are limited to be reduced, so that how to manufacture chips with higher storage density on a wafer is the research direction of numerous scientific researchers and semiconductor practitioners.
In the two-dimensional or planar semiconductor device, memory cells are arranged in the horizontal direction, and thus, the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by unit memory cells, and the integration density of the two-dimensional or planar semiconductor device is greatly affected by the technology of forming fine patterns, so that there is a limit in continuously increasing the integration density of the two-dimensional or planar semiconductor device. Thus, it is highly desirable to design a semiconductor structure in which memory cells can be stacked in three dimensions.
Disclosure of Invention
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure and a structure thereof, which can at least provide a semiconductor structure stacked in a three-dimensional direction, thereby being beneficial to improving the space utilization rate of the semiconductor structure.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming an active region, wherein the active region is arranged at intervals along a first direction, a second direction and a third direction, and comprises a first doped region, a channel region and a second doped region which are arranged along the second direction; forming word lines extending along the first direction, wherein the word lines comprise a first word line and a second word line, the first word line is positioned on the top surface of the channel region, and the second word line is positioned on the bottom surface of the channel region; forming bit lines between adjacent active regions arranged in the second direction, the bit lines extending in the third direction, the bit lines covering sidewalls of the second doped regions remote from the channel region; and forming a capacitor, wherein the capacitor extends along the second direction, is stacked and arranged along the third direction, and covers the side wall of the first doped region, which is far away from the channel region.
In some embodiments, a method of forming an active region includes: forming a first stacking structure on the surface of the substrate, wherein the first stacking structure comprises a first interlayer dielectric layer, an initial active region, a first interlayer dielectric layer and a first isolation layer which are sequentially arranged along the third direction; the initial active region is etched to form the active region.
In some embodiments, the step of etching the initial active region includes: a first etching process, the first etching process comprising: etching the first stacked structure to form the first stacked structures which are arranged at intervals along the first direction; forming a second stacking structure, wherein the second stacking structure is positioned between adjacent first stacking structures, the second stacking structure comprises second interlayer dielectric layers and second isolation layers which are sequentially arranged along the third direction, the second interlayer dielectric layers are in contact connection with the first interlayer dielectric layers, and the second isolation layers are in contact connection with the initial active area or the first isolation layers; a second etching process, the second etching process comprising: and etching the first stacking structure and the second stacking structure to form the active areas which are arranged at intervals along the second direction.
In some embodiments, the material of the first interlayer dielectric layer is the same as the material of the second interlayer dielectric layer.
In some embodiments, the step of forming the word line includes: etching the first interlayer dielectric layer along the second direction to form a first groove, wherein the first groove exposes the surface of the channel region of the active region; forming an initial word line, wherein the initial word line is positioned on the surfaces of the channel region and the second doped region; and patterning the initial word line to expose the surface of the second doped region, and taking the remaining initial word line as the word line, wherein the word line positioned on the top surface of the channel region is taken as the first word line, and the word line positioned on the bottom surface of the channel region is taken as the second word line.
In some embodiments, the step of forming the bit line includes: forming a third isolation layer which is positioned between the active regions arranged at intervals along the second direction and covers the surface of the second doped region; patterning the third isolation layer to form a second groove, wherein the second groove exposes the side wall of the second doping region away from the channel region; and forming the bit line, wherein the bit line fills the second groove.
In some embodiments, the step of forming the capacitor comprises: etching the active region to form a third groove; forming a lower polar plate, wherein the lower polar plate covers the side wall of the third groove; forming a capacitance medium layer, wherein the capacitance medium layer covers the surface of the lower polar plate; and forming an upper polar plate, wherein the upper polar plate covers the surface of the capacitance medium layer and fills the third groove.
In some embodiments, etching the active region includes: patterning the first stack structure to expose a side surface of the active region away from the word line; and etching the active region to form the third groove.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: a substrate; the active region is arranged at intervals along a first direction, a second direction and a third direction, and comprises a first doped region, a channel region and a second doped region which are arranged along the second direction; a word line extending in the first direction, stacked in the third direction, and comprising: a first word line and a second word line, the first word line being located on a top surface of the channel region, the second word line being located on a bottom surface of the channel region; the bit line is positioned between the adjacent active areas arranged along the second direction, the same bit line is in contact connection with the two adjacent active areas, the bit line extends along the third direction, and the bit line covers the side wall of the second doped area far away from the channel area; and the capacitor extends along the second direction, is stacked and arranged along the third direction, and covers the side wall of the first doped region, which is far away from the channel region.
In some embodiments, in the second direction, the bit line has a width that is less than a spacing between adjacent word lines.
In some embodiments, the active regions spaced apart along the third direction share the same bit line.
In some embodiments, the active regions spaced apart along the first direction share the same word line.
In some embodiments, further comprising: and the first interlayer dielectric layer is positioned on the top surface and the bottom surface of the capacitor and the active region.
In some embodiments, further comprising: the first isolation layer, the capacitor, the active area electrically connected with the capacitor and the first interlayer dielectric layers positioned on the top surfaces and the bottom surfaces of the capacitor and the active area form a repeating unit, and the repeating unit and the first isolation layer are alternately arranged in the third direction.
In some embodiments, the capacitor comprises: the lower polar plate comprises a bottom surface in contact with the first doping region and a side surface surrounding the edge of the bottom surface and extending along the second direction, and an accommodating space is formed by the bottom surface and the side surface in a surrounding manner; the capacitive medium layer covers the inner wall of the accommodating space; and the upper polar plate covers the inner wall of the capacitance medium layer and fills the accommodating space.
In some embodiments, the capacitors arranged along the third direction share the capacitor dielectric layer and the upper plate.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the first word line positioned on the top surface of the channel region of the active region and the second word line positioned on the bottom surface of the channel region are formed to form the word line, the bit line positioned on the second doped region and far away from the side wall of the channel region is formed, and the capacitor positioned on the first doped region and far away from the side wall of the channel region is formed to realize the function of the semiconductor structure.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 to 10 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 12 is a schematic structural diagram of another semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
As known in the art, the integration density of memory cells in semiconductor structures is increasing.
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which is characterized in that a first word line positioned on the top surface of a channel region of an active region and a second word line positioned on the bottom surface of the channel region are formed to form the word line, a bit line positioned on a second doped region far away from the side wall of the channel region is formed, a capacitor positioned on the first doped region far away from the side wall of the channel region is formed to realize the function of the semiconductor structure, and the active region which is arranged at intervals along a first direction, a second direction and a third direction is formed, and corresponding capacitors, word lines and bit lines are respectively formed in the first doped region, the channel region and the second doped region of the active region, so that the semiconductor structure is stacked in the three-dimensional direction, thereby improving the space utilization rate of the semiconductor structure and further improving the stacking density of the semiconductor structure.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Referring to fig. 1 to 10, fig. 1 to 10 are schematic structural diagrams corresponding to steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure, wherein fig. 7 is a cross-sectional view of fig. 6 along a dotted line direction, and fig. 8 to 10 are schematic structural diagrams corresponding to a subsequent fabrication method performed on the basis of fig. 7.
Referring to fig. 1 to 10, the method for fabricating a semiconductor structure includes: providing a substrate 100; forming an active region 110, wherein the active region 110 is arranged at intervals along a first direction X, a second direction Y and a third direction Z, and the active region 110 comprises a first doped region 111, a channel region 112 and a second doped region 113 which are arranged along the second direction X; forming a word line 120, wherein the word line 120 extends along a first direction X, the word line 120 includes a first word line 121 and a second word line 122, the first word line 121 is located on a top surface of the channel region 112, and the second word line 122 is located on a bottom surface of the channel region 112; forming bit lines 130, wherein the bit lines 130 are positioned between adjacent active regions 110 arranged along the second direction Y, the bit lines 130 extend along the third direction Z, and the bit lines 130 cover the side walls of the second doped regions 113 away from the channel regions 112; the capacitor 140 is formed, the capacitor 140 extends along the second direction Y, is stacked along the third direction Z, and the capacitor 140 covers the sidewall of the first doped region 111 away from the channel region 112. The word line 120 is arranged on the surface of the channel region 112 of the active region 110, the capacitor 140 is arranged on the side wall of the first doped region 111 away from the channel region 112, the bit line 130 is arranged on the side wall of the second doped region 113 away from the channel region 112, so that the storage of the semiconductor structure is realized, the active region is arranged at intervals along the first direction X, the second direction Y and the third direction Z, the bit line 130 extends along the third direction Z, and the word line 120 extends along the first direction X, so that the stacking of the semiconductor structure is realized, and the space utilization rate of the semiconductor structure can be improved.
Referring to fig. 1 to 4, a method of forming an active region 110 includes: forming a first stacked structure 150 on the surface of the substrate 100, where the first stacked structure 150 includes a first interlayer dielectric layer 160, an initial active region 114, a first interlayer dielectric layer 160, and a first isolation layer 180 sequentially arranged along a third direction Z; the initial active region 114 is etched to form the active region 110.
The first interlayer dielectric layer 160 is formed to be used for forming a supporting structure of a capacitor subsequently, so that the capacitor 140 can be prevented from being suspended in the semiconductor structure, the capacitor is supported by the first interlayer dielectric layer 160 to be prevented from being broken or deformed, the reliability of the semiconductor structure can be improved, the first interlayer dielectric layer 160 is formed to guide the flow of etching liquid in the subsequent etching process, the flow path of the etching liquid is fixed when the subsequent etching liquid flows, the etching direction can be fixed, and the situation of over etching or etching deviation is avoided. Thereby improving the reliability of the semiconductor structure.
Specifically, referring to fig. 1, in some embodiments, in the second direction Y, the substrate 100 may include a substrate 101 and an isolation layer 102 stacked in sequence, where the isolation layer 102 is used to achieve insulation between the substrate 101 and the first stacked structure 150, so as to avoid electric leakage between the active region 110 in the first stacked structure 150 and the substrate 101, which is beneficial to improving electrical performance of the semiconductor structure.
In some embodiments, the material of the substrate 101 may be a silicon material, and the material of the isolation layer 102 may be an insulating material such as silicon oxide or silicon nitride.
Referring to fig. 2, the step of etching the initial active region 114 includes: a first etching process, the first etching process comprising: the first stack structures 150 are etched to form first stack structures 150 arranged at intervals along the first direction X. The initial active regions 114 arranged in the first direction X may be formed by etching to form the first stack structures 150 arranged at intervals in the first direction X.
Referring to fig. 3, a second stack structure 210 is formed, the second stack structure 210 is located between adjacent first stack structures 150, the second stack structure 210 includes second interlayer dielectric layers 190 sequentially arranged along a third direction Z, a second isolation layer 200, the second interlayer dielectric layers 190 are in contact with the first interlayer dielectric layers 160, and the second isolation layer 200 is in contact with the initial active region 114 or the first isolation layer 180. The second stack structure 210 is formed to fill the gap formed by etching the first stack structure 150, and the second stack structure 210 is used as a supporting structure for forming the word line subsequently, so that the word line is prevented from being deformed, and the reliability of the semiconductor structure is improved.
In some embodiments, the material of the second interlayer dielectric layer 190 may be the same as the material of the first interlayer dielectric layer 160, and the material of the second isolation layer 200 may be the same as the material of the first isolation layer 180, so that the first interlayer dielectric layer 160 and the second interlayer dielectric layer 190 may be etched simultaneously in the same step in the subsequent etching process, and the second isolation layer 200 and the first isolation layer 180 may be etched simultaneously in the same step, thereby reducing the process steps of the method for forming a semiconductor structure. In the disclosed embodiment, the second spacer 200 is illustrated using the same fill as the first spacer 180.
In some embodiments, in the third direction Z, the thickness of the second interlayer dielectric layer 190 is equal to the thickness of the first interlayer dielectric layer 160, that is, the top surface of the second interlayer dielectric layer 190 is flush with the top surface of the first interlayer dielectric layer 160; the thickness of the second isolation layer 200 is equal to that of the first isolation layer 180, that is, the top surface of the second isolation layer 200 is flush with the top surface of the first isolation layer 180, so that a semiconductor structure having a regular shape can be formed. In some embodiments, the thickness of the second interlayer dielectric layer may be different from the thickness of the first interlayer dielectric layer, and the thickness of the second isolation layer may be different from the thickness of the first isolation layer, which may be adjusted according to actual production requirements.
In some embodiments, in the third direction Z, the thicknesses of the adjacent first interlayer dielectric layers 160 are equal, so that only the same deposition speed and the same deposition time are required to be controlled in the process of forming the first stacked structure, so that the first interlayer dielectric layers 160 with equal thickness can be formed, and the same process parameters can be adopted in the process of forming the second interlayer dielectric layers 190 of the second stacked structure 210, so that the parameters formed in the process of forming the first interlayer dielectric layers 160 and the second interlayer dielectric layers 190 can not be adjusted, thereby facilitating the whole production process; in other embodiments, the thicknesses of the adjacent first interlayer dielectric layers 160 may be different, and the thicknesses of the adjacent second interlayer dielectric layers 190 may be different, which may be adjusted according to actual production requirements.
In some embodiments, the thickness of the initial active region 114 may be greater than the thickness of the first interlayer dielectric layer 160 in the third direction Z, and in other embodiments, the thickness of the initial active region may be equal to the thickness of the first interlayer dielectric layer; in still other embodiments, the thickness of the initial active region may also be less than the thickness of the first interlayer dielectric layer. Can be adjusted according to actual production conditions. The thickness of the initial active region 114 is controlled to be greater than that of the first interlayer dielectric layer 160, so that more carriers can be contained in the initial active region 114, and the transmission rate of the initial active region 114 can be improved; the thickness of the initial active layer is equal to that of the first interlayer dielectric layer, so that the process complexity of the semiconductor structure can be reduced in the production process; the insulation between adjacent initial active regions can be improved by forming the initial active regions to have a thickness smaller than that of the first interlayer dielectric layer.
In some embodiments, the thickness of the initial active region 114 is greater than the thickness of the first isolation layer 180, that is, the thickness of the second isolation layer 200 in contact with the initial active region 114 is greater than the thickness of the second isolation layer 200 in contact with the first isolation layer 180 in the subsequent process of forming the second isolation layer 200, the number of carriers within the initial active region 114 may be increased by forming the initial active region 114 to have a thickness greater than the thickness of the first isolation layer 180, and thus the transmission rate of the initial active region 114 may be increased; in other embodiments, the thickness of the initial active region 114 is equal to the thickness of the first isolation layer 180, such that the formation parameters of the second isolation layer 200 may not need to be changed during the subsequent formation of the second isolation layer 200; in still other embodiments, the thickness of the initial active region may be smaller than the thickness of the first isolation layer, and may be adjusted according to practical situations, and the present disclosure is not limited to the thickness of the initial active region 114 and the first isolation layer 180.
It is understood that the thickness of the initial active region 114, the thickness between the first interlayer dielectric layer 160 and the first isolation layer may be equal or different, and may be adjusted according to practical situations, where the thickness of the illustrated portion of the disclosure is different only for convenience of distinguishing different film layers, and the thickness relationship between the film layers is not limited.
Referring to fig. 4, the step of etching the initial active region 114 may further include: and a second etching process including: the first stacked structure 150 and the second stacked structure 210 are etched to form active regions 110 arranged at intervals along the second direction Y, and the active regions 110 arranged at intervals along the second direction Y can be formed by the second etching, and a process basis can be provided for the subsequent formation of word lines. It can be understood that the active regions 110 spaced apart along the second direction Y are formed by etching the same initial active region 114, so that the formed active regions 110 are symmetrically distributed, that is, adjacent active regions 110, wherein one active region 110 includes the first doped region 111, the channel region 112 and the second doped region 113 arranged along the second direction, and the other active region 110 includes: a second doped region 113, a channel region 112 and a first doped region 111 arranged along the second direction Y.
Referring to fig. 4 and 5, the step of forming the word line 120 may include: etching the first interlayer dielectric layer 160 in the second direction Y to form a first recess 220, the first recess 220 exposing a surface of the channel region 112 of the active region 110; forming an initial word line on the surfaces of the channel region 112 and the second doped region 113; the initial word lines are patterned to expose the surface of the second doped region 113, with the remaining initial word lines being the word lines 120, wherein the word lines 120 located on the top surface of the channel region 112 are the first word lines 121, and the word lines 120 located on the bottom surface of the channel region 112 are the second word lines 122.
It will be appreciated that the etching of the first interlayer dielectric layer 160 further includes etching the second interlayer dielectric layer 190 in contact with the first interlayer dielectric layer 160 together, that is, the first recess 220 also exposes the top surface of the second isolation layer 200 in contact with the active region 110 during the formation of the first recess 220, such that the word lines 120 are formed continuously in the second direction, that is, the active region 110 arranged in the second direction shares the word lines 120, subsequently during the formation of the word lines 120.
It can be appreciated that, since the first interlayer dielectric layer 160 located above the active region 110 is the same as the first interlayer dielectric layer 160 located below the active region 110, the top and bottom surfaces of the channel region 112 of the active region 110 are simultaneously exposed when the first interlayer dielectric layer 160 is etched, the word line 120 is formed to cover the top and bottom surfaces of the channel region 112 at the same time during the process of depositing the conductive material of the word line 120, the word line 120 located on the top surface of the channel region 112 serves as the first word line 121, the word line 120 located on the bottom surface of the channel region 112 serves as the second word line 122, and the facing area between the word line 120 and the active region 110 can be increased by forming the first word line 121 and the second word line 122, so that the capability of the word line 120 to control the channel region 112 can be improved, and the performance of the semiconductor structure can be improved.
In some embodiments, after forming the first recess 220, before forming the word line 120, further includes: a gate dielectric layer (not shown) is formed to cover the surface of the active region 110, so that the word line 120 can be prevented from being directly connected to the active region 110.
In some embodiments, the material of the gate dielectric layer may be an insulating material such as silicon oxide or silicon nitride.
Referring to fig. 5 to 7, the step of forming the bit line 130 includes: forming a third isolation layer 230, wherein the third isolation layer 230 is positioned between the active regions 110 which are arranged at intervals along the second direction and covers the surface of the second doped region 113; patterning the third isolation layer 230 to form a second recess 240, the second recess 240 exposing the sidewalls of the second doped region 113 away from the channel region 112; the bit line 130 is formed, and the bit line 130 fills the second recess 240.
Referring to fig. 5, a third isolation layer 230 is formed, and in some embodiments, the third isolation layer 230 further covers the top surface of the semiconductor structure, so that by forming the third isolation layer 230 on the top surface of the semiconductor structure, the semiconductor structure can be protected when the mask layer on the top surface of the third isolation layer 230 is removed later, and the contact between the mask layer removing agent and the internal structure of the semiconductor structure can be avoided, so that the reliability of the semiconductor structure can be improved.
The material of the third isolation layer 230 may be an insulating material, such as silicon oxide or silicon nitride.
Referring to fig. 6, a mask layer is formed on the top surface of the semiconductor structure, the pattern of the mask layer exposes a portion of the top surface of the third isolation layer 230, the second recess 240 is formed by etching the third isolation layer 230 using the mask layer as a mask, the accuracy of the pattern of the second recess 240 may be improved by forming the mask layer first and forming the second recess 240 by means of mask etching, so that the reliability of the semiconductor structure may be improved, and in some embodiments, removing the mask layer is further included after forming the second recess 240.
Referring to fig. 7, in some embodiments, during the formation of the second recess 240 (refer to fig. 6), a portion of the third isolation layer 230 located on the top surface of the first isolation layer 180 may be etched first to expose the sidewall of the first isolation layer 180, and then the third isolation layer 230 is etched with the first isolation layer 180 as a mask, that is, the width of the pattern opening of the mask layer may be greater than the gap between the adjacent active regions 110 in the second direction Y. The second groove 240 with a larger opening is formed on the part of the third isolation layer 230 located on the top surface of the first isolation layer 180, so that the first isolation layer 180 with a space can be conveniently located, and then the first isolation layer 180 is used as a mask to etch the third isolation layer 230, so that etching deviation in the etching process can be avoided, and the situation that part of the bit line 130 is not in contact connection with the second doped region 113 of the active region 110 in the subsequent process of forming the bit line 130 is avoided, so that the reliability of the manufacturing process of the semiconductor structure can be improved. In other words, by etching a portion of the third isolation layer 230 located on the top surface of the first isolation layer 180, and then continuing to etch the third isolation layer 230 with the first isolation layer 180 as a mask, it is ensured that the second recess 240 formed exposes the sidewall of the adjacent active region 110 during the formation of the second recess 240, so that the electrical connection between the bit line and the active region 110 can be ensured during the subsequent formation of the bit line.
With continued reference to fig. 7, the bit lines 130 are formed, and it can be appreciated that the active regions 110 adjacent in the second direction Y and the active regions 110 spaced apart in the third direction Z share the same bit line 130.
In some embodiments, a portion of the third isolation layer 230 that is in contact with the sidewall of the word line 120 is also reserved in the process of etching the third isolation layer 230, so that the word line 120 and the bit line 130 can be isolated by the reserved portion of the third isolation layer 230, thereby avoiding the word line 120 from being in contact with the bit line 130, avoiding the occurrence of an abnormality in the semiconductor structure, and improving the reliability of the semiconductor structure.
Referring to fig. 8 to 10, the step of forming the capacitor 140 includes: etching the active region 110 to form a third recess 250; forming a lower plate 141, the lower plate 141 covering a sidewall of the third recess 250; forming a capacitance dielectric layer 142, wherein the capacitance dielectric layer 142 covers the surface of the lower electrode plate 141; an upper plate 143 is formed, the upper plate 143 covers the surface of the capacitor dielectric layer 142 and fills the third recess 250.
Specifically, referring to fig. 8, the first stack structure 150 is patterned to expose a side surface of the active region 110 away from the word line 120; by patterning the first stack structure 150 to form the fourth recess 260, the active region 110 may be etched by forming the fourth recess 260 through the exposed surface of the active region 110 of the fourth recess 260, thereby providing a process basis for the subsequent formation of the capacitor 140.
In some embodiments, the fourth groove 260 may be formed by means of mask etching, that is, a mask may be formed on the surface of the third isolation layer 230, the pattern of the fourth groove 260 may be defined by the mask, the fourth groove 260 may be formed by means of mask etching, and removing the mask on the top surface of the third isolation layer 230 may be further included after forming the fourth groove 260.
Referring to fig. 9, the active region is etched to form a third recess 250, and a process basis may be provided for the subsequent formation of a capacitor by forming the third recess 250.
Referring to fig. 10, a capacitor 140 is formed, and in some embodiments, in the third direction Z, the capacitor 140 shares the capacitor dielectric layer 142 and the upper plate 143, the capacitance of the shared capacitor dielectric layer 142 and the upper plate 143 determines the capacitance of the capacitor 140 through the non-shared lower plate 141, and the capacitor 140 with the shared capacitor dielectric layer 142 and the upper plate 143 can facilitate the manufacturing process.
In some embodiments, the material of the lower plate 141 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper, or tungsten; the materials of the capacitive dielectric layer 142 may include: zrO, alO, zrNbO, zrHfO, zrAlO or any combination thereof; the material of the upper plate 143 may include one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride or other conductive materials, or the material of the upper plate 143 may be a conductive semiconductor material, such as polysilicon, silicon germanium, etc.
It is understood that the relative area between the lower plate 141 and the upper plate 143 of the capacitor 140, the distance between the lower plate 141 and the upper plate 143, and the material of the capacitor dielectric layer 142 may affect the capacity of the capacitor 140, so the relative area between the lower plate 141 and the upper plate 143 of the capacitor 140, the distance between the lower plate 141 and the upper plate 143, and the material of the capacitor dielectric layer 142 may be set according to practical requirements.
In other embodiments, during the process of forming the capacitor dielectric layer and the upper electrode plate, the capacitor dielectric layer and the upper electrode plate only located in the third groove may be formed, that is, the capacitor not sharing the upper capacitor dielectric layer and the upper electrode plate in the third direction may be formed by first forming the capacitor dielectric layer and the upper electrode plate filling the third groove and the fourth groove, and then etching to expose the fourth groove to form the capacitor not sharing the capacitor dielectric layer and the upper electrode plate in the third direction.
In some embodiments, before forming the upper plate 143 after forming the capacitive dielectric layer 142, further comprises: a diffusion barrier layer (not shown in the figure) is formed, and the diffusion barrier layer covers the surface of the capacitor dielectric layer 142 away from the lower electrode plate 141, that is, the upper electrode plate 143 covers the surface of the diffusion barrier layer away from the capacitor dielectric layer 142, and the conductive element in the upper electrode plate 143 is blocked from diffusing into the capacitor dielectric layer 142 by the diffusion barrier layer, so that the conductivity of the upper electrode plate 143 is prevented from being reduced, and the insulating property of the capacitor dielectric layer 142 is prevented from being affected by the upper electrode plate 143.
In some embodiments, the material of the diffusion barrier layer may be a metal compound such as titanium nitride.
In the embodiment of the disclosure, by forming the word line 120 on the surface of the channel region 112 of the active region 110, forming the capacitor 140 on the sidewall of the first doped region 111 away from the channel region 112, forming the bit line 130 on the sidewall of the second doped region 113 away from the channel region 112, thereby realizing the storage of the semiconductor structure, and by arranging the active region at intervals along the first direction X, the second direction Y and the third direction Z, arranging the bit line 130 to extend along the third direction Z, and arranging the word line 120 to extend along the first direction X, the stack of the semiconductor structure is formed, and the space utilization of the semiconductor structure can be improved.
Another embodiment of the present disclosure further provides a semiconductor structure, which may be formed by the above-mentioned part or all of the process steps, and the semiconductor structure provided in another embodiment of the present disclosure will be described with reference to the drawings, where the same or corresponding parts as those of the previous embodiment may be referred to, and the description thereof will not be repeated.
Referring to fig. 11, 12 and 10, fig. 11 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure, and fig. 12 is a schematic diagram of an internal structure of a semiconductor structure according to an embodiment of the disclosure.
Referring to fig. 11, 12 and 10, the semiconductor structure includes: a substrate 100; the active region 110, the active region 110 is arranged at intervals along the first direction X, the second direction Y and the third direction Z, and the active region 110 includes a first doped region 111, a channel region 112 and a second doped region 113 arranged along the second direction Y; the word lines 120, the word lines 120 extend along a first direction X, are stacked and arranged along a third direction Z, and the word lines 120 include: a first word line 121 and a second word line 122, wherein the first word line 121 is located on the top surface of the channel region 112, and the second word line 122 is located on the bottom surface of the channel region 112; the bit line 130, the bit line 130 is located between adjacent active regions 110 arranged along the second direction Y, and the same bit line 130 is in contact connection with two adjacent active regions 110, the bit line 130 extends along the third direction Z, and the bit line 130 covers the sidewall of the second doped region 113 away from the channel region 112; the capacitor 140 extends along the second direction Y, is stacked along the third direction Z, and the capacitor 140 covers the sidewall of the first doped region 111 away from the channel region 112.
In some embodiments, the active regions 110 arranged at intervals along the first direction X share the same word line 120, and by setting that the active regions 110 arranged at intervals along the first direction X share the same word line 120, the space required for arranging the word line 120 can be reduced, so that the space utilization of the semiconductor structure can be improved, and the stacking density of the semiconductor structure can be improved.
By providing the first word line 121 on the top surface of the channel region 112 and the second word line 122 on the bottom surface of the channel region 112, the contact area between the word line 120 and the active region 110 can be increased, thereby improving the ability of the word line 120 to control the channel region 112 and improving the performance of the semiconductor structure.
In some embodiments, the active regions 110 spaced apart along the third direction Z share the same bit line 130. By providing active regions 110 arranged at intervals along the third direction Z to share the same bit line 130, a space required for laying out the bit line 130 can be reduced, so that space utilization of the semiconductor structure can be improved, thereby improving a stacking density of the semiconductor structure.
In some embodiments, the active regions 110 adjacent along the second direction Y share the same bit line 130, as shown in fig. 12, and 6 active regions 110 share the same bit line 130, by setting that the active regions adjacent along the second direction Y share the same bit line 130, the space required for laying out the bit line 130 can be reduced, so that the space utilization of the semiconductor structure can be improved, and the stacking density of the semiconductor structure can be improved, and correspondingly, the area of the bit line 130 can be also improved, so that the resistance of the bit line 130 can be reduced, and thus the transmission rate of the bit line 130 can be improved.
In some embodiments, the active regions 110 adjacent along the second direction Y are axisymmetrically distributed along the bit line 130 between the adjacent active regions 110, that is, the active region 110 on one side of the bit line 130 includes the first doped region 111, the channel region 112, and the second doped region 113 arranged along the second direction, and the active region 110 on the other side of the bit line 130 includes the second doped region 113, the channel region 112, and the first doped region 111 arranged along the second direction Y.
In some embodiments, the width of the bit line 130 is less than the spacing between adjacent word lines 120 in the second direction Y. By setting the width of the bit line 130 smaller than the pitch between adjacent word lines 120, the bit line 130 can be isolated from the word lines 120.
In some embodiments, a third isolation layer 230 is further included between the bit line 130 and the word line 120, and the word line 120 and the bit line 130 are isolated by the third isolation layer 230, so that the word line 120 and the bit line 130 are prevented from being connected in a contact manner, and the semiconductor structure is prevented from being abnormal, so that the reliability of the semiconductor structure is improved.
In some embodiments, the capacitor 140 includes: a lower electrode plate 141, wherein the lower electrode plate 141 comprises a bottom surface contacted with the first doped region 111 and a side surface surrounding the edge of the bottom surface and extending along the second direction Y, and an accommodating space is defined by the bottom surface and the side surface; a capacitance medium layer 142, the capacitance medium layer 142 covering the inner wall of the accommodation space; the upper electrode plate 143, the upper electrode plate 143 covers the inner wall of the capacitance medium layer 142, and the upper electrode plate 143 fills the accommodating space. In other words, the lower electrode plate 141 covers the active region 110 and the sidewall of the space surrounded by the first interlayer dielectric layer 160 on the top and bottom surfaces of the active region 110, the capacitor dielectric layer 142 covers the inner wall of the lower electrode plate 141, and the upper electrode plate 143 covers the inner wall of the capacitor dielectric layer 142.
In some embodiments, the capacitors 140 arranged in the third direction Z share the capacitor dielectric layer 142 and the upper plate 143. The capacitance of the common capacitor dielectric layer 142 and the upper electrode plate 143 determines the capacitance of the capacitor 140 by the lower electrode plate 141 which is not in common, and the capacitor 140 provided with the common capacitor dielectric layer 142 and the upper electrode plate 143 can facilitate the production process and increase the number of the capacitors 140.
In some embodiments, referring to fig. 12, the capacitors 140 distributed along the first direction X, the second direction and the third direction Z share the upper plate 143, the capacitors 140 distributed along the first direction X and the third direction Z share the capacitor dielectric layer 142, the three capacitors 140 distributed along the first direction X share the capacitor dielectric layer 142 and the upper plate 143, the two capacitors 140 distributed along the second direction Y share the upper plate 143 and do not share the capacitor dielectric layer 142, (the connection of one capacitor 140 to the active region 110 is illustrated, the connection of the other capacitor 140 to the active region 110 is not illustrated), and the three capacitors 140 distributed along the third direction Z share the capacitor dielectric layer 142 and the upper plate 143, that is, the 18 capacitors 140 distributed along the second direction Y share the same upper plate 143, and the nine capacitors 140 distributed along the second direction Y share the same capacitor dielectric layer 142.
In other embodiments, the upper electrode plate and the capacitor dielectric layer may be disposed at intervals along the first direction, that is, six capacitors arranged along the second direction share the same upper electrode plate, and three capacitors arranged along the second direction share the same capacitor dielectric layer; in still other embodiments, the top plate and the capacitor dielectric layer may be disposed at intervals along the first direction and the third direction, that is, the top plate and the capacitor dielectric layer are not shared between the capacitors.
It should be noted that, the number of the capacitors 140 sharing the upper electrode plate 143 and the capacitor dielectric layer 142 depends on the number of the capacitors 140 arranged along the first direction X, the second direction Y and the third direction Z, in other words, the number of the capacitors 140 arranged in different directions can be controlled by controlling the number of the capacitors sharing the upper electrode plate 143 and the capacitor dielectric layer 142, which is not limited by the embodiment of the disclosure, and the number and arrangement of the capacitors 140 can be adjusted according to actual requirements.
In some embodiments, a diffusion barrier layer (not shown) is further included between the upper plate 143 and the capacitor dielectric layer 142, and the diffusion barrier layer is used to block the conductive element in the upper plate 143 from diffusing into the capacitor dielectric layer 142, so that the conductive performance of the upper plate 143 is prevented from being reduced, and the insulating performance of the capacitor dielectric layer 142 is prevented from being affected by the upper plate 143.
In some embodiments, the first interlayer dielectric layer 160 is further included, and the first interlayer dielectric layer 160 is located on top and bottom surfaces of the capacitor 140 and the active region 110. The first interlayer dielectric layer 160 can serve as a support for the capacitor 140 and the active region 110, so that the capacitor 140 and the active region 110 are prevented from being suspended, deformation of the capacitor 140 and the active region 110 is prevented, and reliability of the semiconductor structure can be improved.
In some embodiments, further comprising: the first isolation layer 180, the capacitor 140, the active region 110 electrically connected to the capacitor 140, and the first interlayer dielectric layer 160 located on the top and bottom surfaces of the capacitor 140 and the active region 110 form a repeating unit, and the repeating unit and the first isolation layer 180 are alternately arranged in the third direction Z. In the third direction Z, the insulation between adjacent active regions 110 may be improved by providing the first isolation layer 180, and different repeating units may be spaced apart, thereby facilitating process production.
In some embodiments, further comprising: the second stack structure 210 includes a second interlayer dielectric layer 190 and a second isolation layer 200 sequentially stacked in the third direction Z, and the second interlayer dielectric layer 190 is in contact with the first interlayer dielectric layer 160, and the second isolation layer 200 is in contact with the initial active region 114 or the first isolation layer 180, and the semiconductor structure can be filled in the process of forming the active region 110 by forming the second stack structure 210.
The material of the second interlayer dielectric layer 190 may be the same as that of the first interlayer dielectric layer 160, and the material of the second isolation layer 200 may be the same as that of the first isolation layer 180. By providing the second interlayer dielectric layer 190 with the same material as the first interlayer dielectric layer 160, the second isolation layer 200 with the same material as the first isolation layer 180, the kind of etching agent can be reduced in the manufacturing process.
According to the embodiment of the disclosure, the capability of the word line 120 to control the channel region 112 can be improved by arranging the word line 120 on the top surface and the bottom surface of the active region 110, the space utilization rate of the semiconductor structure can be improved by arranging the bit line 130 between two adjacent active regions 110 arranged along the two directions Y, and the same bit line 130 is in contact connection with the two adjacent active regions 110, so that the adjacent active regions 110 along the second direction Y share the same bit line 130, and the capacitor 140 extends along the second direction Y and covers the side wall of the first doped region 111 far away from the channel region 112 by arranging the capacitor 140, so that the stacking of the semiconductor structure is realized, the space utilization rate of the semiconductor structure can be improved, the stacking density of the semiconductor structure is improved, and the number of the capacitors 140 is increased.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming an active region, wherein the active region is arranged at intervals along a first direction, a second direction and a third direction, and comprises a first doped region, a channel region and a second doped region which are arranged along the second direction;
forming word lines extending along the first direction, wherein the word lines comprise a first word line and a second word line, the first word line is positioned on the top surface of the channel region, and the second word line is positioned on the bottom surface of the channel region;
forming bit lines between adjacent active regions arranged in the second direction, the bit lines extending in the third direction, the bit lines covering sidewalls of the second doped regions remote from the channel region;
and forming a capacitor, wherein the capacitor extends along the second direction, is stacked and arranged along the third direction, and covers the side wall of the first doped region, which is far away from the channel region.
2. The method of fabricating a semiconductor structure of claim 1, wherein the method of forming the active region comprises: forming a first stacking structure on the surface of the substrate, wherein the first stacking structure comprises a first interlayer dielectric layer, an initial active region, a first interlayer dielectric layer and a first isolation layer which are sequentially arranged along the third direction;
The initial active region is etched to form the active region.
3. The method of claim 2, wherein etching the initial active region comprises: a first etching process, the first etching process comprising: etching the first stacked structure to form the first stacked structures which are arranged at intervals along the first direction;
forming a second stacking structure, wherein the second stacking structure is positioned between adjacent first stacking structures, the second stacking structure comprises second interlayer dielectric layers and second isolation layers which are sequentially arranged along the third direction, the second interlayer dielectric layers are in contact connection with the first interlayer dielectric layers, and the second isolation layers are in contact connection with the initial active area or the first isolation layers;
a second etching process, the second etching process comprising: and etching the first stacking structure and the second stacking structure to form the active areas which are arranged at intervals along the second direction.
4. The method of claim 3, wherein the material of the first interlayer dielectric layer is the same as the material of the second interlayer dielectric layer.
5. The method of fabricating a semiconductor structure of claim 2, wherein the step of forming the word line comprises: etching the first interlayer dielectric layer along the second direction to form a first groove, wherein the first groove exposes the surface of the channel region of the active region;
forming an initial word line, wherein the initial word line is positioned on the surfaces of the channel region and the second doped region;
and patterning the initial word line to expose the surface of the second doped region, and taking the remaining initial word line as the word line, wherein the word line positioned on the top surface of the channel region is taken as the first word line, and the word line positioned on the bottom surface of the channel region is taken as the second word line.
6. The method of fabricating a semiconductor structure of claim 2, wherein the step of forming the bit line comprises: forming a third isolation layer which is positioned between the active regions arranged at intervals along the second direction and covers the surface of the second doped region;
patterning the third isolation layer to form a second groove, wherein the second groove exposes the side wall of the second doping region away from the channel region;
And forming the bit line, wherein the bit line fills the second groove.
7. The method of fabricating a semiconductor structure of claim 2, wherein the step of forming the capacitor comprises: etching the active region to form a third groove;
forming a lower polar plate, wherein the lower polar plate covers the side wall of the third groove;
forming a capacitance medium layer, wherein the capacitance medium layer covers the surface of the lower polar plate;
and forming an upper polar plate, wherein the upper polar plate covers the surface of the capacitance medium layer and fills the third groove.
8. The method of claim 7, wherein etching the active region comprises: patterning the first stack structure to expose a side surface of the active region away from the word line;
and etching the active region to form the third groove.
9. A semiconductor structure, comprising:
a substrate;
the active region is arranged at intervals along a first direction, a second direction and a third direction, and comprises a first doped region, a channel region and a second doped region which are arranged along the second direction;
a word line extending in the first direction, stacked in the third direction, and comprising: a first word line and a second word line, the first word line being located on a top surface of the channel region, the second word line being located on a bottom surface of the channel region;
The bit line is positioned between the adjacent active areas arranged along the second direction, the same bit line is in contact connection with the two adjacent active areas, the bit line extends along the third direction, and the bit line covers the side wall of the second doped area far away from the channel area;
and the capacitor extends along the second direction, is stacked and arranged along the third direction, and covers the side wall of the first doped region, which is far away from the channel region.
10. The semiconductor structure of claim 9, wherein in the second direction, a width of the bit line is less than a pitch between adjacent word lines.
11. The semiconductor structure of claim 9, wherein the active regions spaced apart along the third direction share the same bit line.
12. The semiconductor structure of claim 9, wherein the active regions spaced apart along the first direction share the same word line.
13. The semiconductor structure of claim 9, further comprising: and the first interlayer dielectric layer is positioned on the top surface and the bottom surface of the capacitor and the active region.
14. The semiconductor structure of claim 13, further comprising: the first isolation layer, the capacitor, the active area electrically connected with the capacitor and the first interlayer dielectric layers positioned on the top surfaces and the bottom surfaces of the capacitor and the active area form a repeating unit, and the repeating unit and the first isolation layer are alternately arranged in the third direction.
15. The semiconductor structure of claim 9, wherein the capacitor comprises:
the lower polar plate comprises a bottom surface in contact with the first doping region and a side surface surrounding the edge of the bottom surface and extending along the second direction, and an accommodating space is formed by the bottom surface and the side surface in a surrounding manner;
the capacitive medium layer covers the inner wall of the accommodating space;
and the upper polar plate covers the inner wall of the capacitance medium layer and fills the accommodating space.
16. The semiconductor structure of claim 15, wherein the capacitors arranged along the third direction share the capacitor dielectric layer and the top plate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210827394.2A CN117457656A (en) | 2022-07-13 | 2022-07-13 | Manufacturing method of semiconductor structure and structure thereof |
| PCT/CN2023/098988 WO2024012104A1 (en) | 2022-07-13 | 2023-06-07 | Semiconductor structure manufacturing method and structure thereof |
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| CN202210827394.2A CN117457656A (en) | 2022-07-13 | 2022-07-13 | Manufacturing method of semiconductor structure and structure thereof |
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| KR20210077098A (en) * | 2019-12-16 | 2021-06-25 | 삼성전자주식회사 | Semiconductor memory device and method for manufacturing the same |
| KR20220003270A (en) * | 2020-07-01 | 2022-01-10 | 에스케이하이닉스 주식회사 | Memory device |
| KR20220049866A (en) * | 2020-10-15 | 2022-04-22 | 에스케이하이닉스 주식회사 | Memory cell and semiconductor dedvice with the same |
| KR20220094592A (en) * | 2020-12-29 | 2022-07-06 | 에스케이하이닉스 주식회사 | Memory cell and memory device |
| CN114023703B (en) * | 2022-01-07 | 2022-04-26 | 长鑫存储技术有限公司 | Semiconductor device forming method and semiconductor device |
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