CN117457536A - Image processing-based intelligent chip pickup method - Google Patents
Image processing-based intelligent chip pickup method Download PDFInfo
- Publication number
- CN117457536A CN117457536A CN202311437150.4A CN202311437150A CN117457536A CN 117457536 A CN117457536 A CN 117457536A CN 202311437150 A CN202311437150 A CN 202311437150A CN 117457536 A CN117457536 A CN 117457536A
- Authority
- CN
- China
- Prior art keywords
- chip
- chips
- image
- wafer
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000001514 detection method Methods 0.000 claims abstract description 31
- 230000003321 amplification Effects 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 55
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003908 quality control method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides an intelligent chip pickup method based on image processing, which comprises the following steps of S1, creating a selection list, S2, obtaining a chip image from the detection range of a camera, and adding a position coordinate into the selection list, wherein the chip image is obtained through shooting by the camera, and a plurality of pieces of chip position information on the wafer are obtained so as to control a suction head to pick up a corresponding chip; s3, selecting the position coordinates of the chip at the optimal position from the selection list through a preference rule, and completing the chip pickup at the position by the suction head; s4, updating a selection list according to a plurality of pieces of chip position information acquired by the chip images of the new array arrangement; s5, when the chipless position information in the selection list is updated, stopping picking, and selecting the most preferred chip picking position through the relative coordinates of the chips in the detection range, so that the picking can be started at the current position of the suction head, and the efficiency of chip picking and the expansibility of different wafers are improved.
Description
Technical Field
The invention relates to a packaging process of a semiconductor discrete device, in particular to an intelligent chip pickup method based on image processing.
Background
In the packaging process of semiconductor discrete devices, the picking up process of chips on a wafer is a critical previous process, which is also called a wafer picking process. A large number of chips are arranged on the wafer according to an array structure, and the wafer taking process is to pick up the chips of the array from the wafer by a precisely controlled manipulator (also called a suction head) and place the chips at PAD points of a designated frame.
The existing chip pickup method generally comprises the steps of firstly carrying out integral pre-scanning on a wafer, establishing a wafer coordinate system through the collected image after integral image collection, determining the specific position of the chip image obtained through scanning in the wafer coordinate system, and then traversing the whole chip array area from head to tail according to a given route by controlling a suction head to move along a Z shape for pickup one by one. However, the Z-shaped routing method needs to traverse all chips one by one in sequence, including passing and failing, and the existing Z-shaped routing method needs to set different routing paths for different types of wafers, so that direct and rapid indiscriminate calling cannot be achieved in the process of picking up chips with different types and different specifications, and preparation works such as resetting and initial position locating need to be performed on the suction head at the beginning of picking up, thereby reducing the chip picking efficiency.
Disclosure of Invention
The invention aims to solve the technical problems that: in the prior art, different types of chips with different specifications need to be customized to different pickup paths, and the pickup efficiency is low, and the invention provides an intelligent chip pickup method based on image processing to solve the problems.
The technical scheme adopted for solving the technical problems is as follows: an intelligent chip pickup method based on image processing, which obtains wafer image by camera shooting and obtains a plurality of chip position information on the wafer to control the suction head to pick up the corresponding chip, comprises the following steps of
S1, creating a selection list,
s2, controlling a camera to shoot the positioned wafer to obtain a chip image, obtaining chip images which cover three rows and three columns of array arrangement by the detection range of the camera, and adding the coordinates of each position of the chips which are arranged in a matrix in the detection range into a selection list respectively;
s3, selecting the position coordinates of the chip at the optimal position from the selection list through a preference rule, transmitting the position coordinates to a suction head, and completing the chip pickup at the position by the suction head;
s4, taking the pick-up position in the step S3 as a center by the camera to obtain a new chip image with array arrangement, and updating a selection list according to a plurality of pieces of chip position information obtained by the chip image with the new array arrangement;
s5, stopping picking up when the chipless position information in the selection list is updated;
the preferred rule is specifically:
firstly, ordering position coordinate information represented by chips arranged in an array in a detection range according to a priority order of a first row X, a second row Y and a third row Z;
and then the position coordinate information represented by the chips arranged in each row is ordered by taking the columns as priority, and the priority order is sequentially a second column B, a first column A and a third column C.
Further: in the chip image which is arranged in an array in the detection range, the array points correspond to chips or empty points, wherein the chips corresponding to the array points are qualified chips or ink point chips, when the chips at the optimal positions in the step S3 are the empty points or the ink point chips, the optimal rule is to skip the empty points or the ink point chips, the next optimal position chip is selected, and when the selected qualified chips or all the array points are selected, the optimal rule selection is ended.
Further: and when no qualified chip exists on the array point in the detection range, the camera performs the operation of the amplification, the amplification is repeated for N times, each time of the operation of the amplification is specifically that the camera translates rightwards by a distance of a chip spacing, then shooting is performed, and the steps S2 to S5 are repeated.
Further: the number of times N of the amplification operation is 2.
The intelligent chip picking method based on image processing does not need to preset a wafer coordinate system for the whole wafer, the picking position of the most preferred chip is selected through the relative coordinates of the chip in the detection range, the chip in the whole wafer area can be picked up from any position, the method is not limited by specific wafer specifications and types, lengthy pre-scanning and image information scanning acquisition preparation work before picking up are abandoned, the chip can be picked up at the current position of the suction head, and the efficiency of chip picking up and expansibility for different wafers are improved.
Drawings
The invention will be further described with reference to the drawings and examples.
FIG. 1 is a flow chart of an intelligent chip pick-up method based on image processing;
FIG. 2 is a schematic diagram of the locations of chips on a wafer corresponding to the preferred rule;
fig. 3 is a sequence diagram of the pick up of chips on a wafer, 1, 2, 3, starting from any one position. . . . . The numbers indicate the order in which the chips were picked up;
FIG. 4 is a schematic diagram of selecting an optimal position chip after skipping null and ink dot chips on a wafer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. On the contrary, the embodiments of the invention include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "connected," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
Referring to fig. 1, the invention provides an intelligent chip pickup method based on image processing, which comprises the following steps of capturing an image of a wafer by a camera, acquiring position information of a plurality of chips on the wafer, and controlling a suction head to pick up a corresponding chip
S1, creating a selection list,
s2, controlling a camera to shoot the positioned wafer to obtain a chip image, obtaining chip images which cover three rows and three columns of array arrangement by the detection range of the camera, and adding the coordinates of each position of the chips which are arranged in a matrix in the detection range into a selection list respectively;
s3, selecting the position coordinates of the chip at the optimal position from the selection list through a preference rule, transmitting the position coordinates to a suction head, and completing the chip pickup at the position by the suction head;
s4, taking the pick-up position in the step S3 as a center by the camera to obtain a new chip image with array arrangement, and updating a selection list according to a plurality of pieces of chip position information obtained by the chip image with the new array arrangement;
s5, stopping picking up when the chipless position information in the selection list is updated;
the preferred rule is specifically:
firstly, ordering position coordinate information represented by chips arranged in an array in a detection range according to a priority order of a first row X, a second row Y and a third row Z;
and then the position coordinate information represented by the chips arranged in each row is ordered by taking the columns as priority, and the priority order is sequentially a second column B, a first column A and a third column C.
The method aims at providing a method which does not need to traverse all chips on a wafer according to a conventional Z-shaped position and can finish chip pickup on the wafer, and particularly, the traditional chip pickup method needs to comprehensively traverse the distribution condition of the chips in the wafer through a camera before pickup aiming at specific parameters such as different wafer sizes, specifications and the like, a wafer coordinate system C (x, y) is established, the chips are controlled to be picked one by one through the established wafer coordinate system, a large amount of early image acquisition preparation is needed in the chip pickup process, and meanwhile, the design of a pickup route based on the wafer coordinate system is needed to be carried out again after the wafer is subjected to the type conversion. In addition, the design of the picking route based on the wafer coordinate system usually takes the first left as a starting point, and Z-shaped walking is adopted to realize picking one by one, so that a series of preparation operations such as suction head reset, starting position locating and the like are required to be carried out on each wafer before the chip is picked up, and the picking process is complex and low in efficiency.
According to the pick-up method, the position coordinates of each chip are obtained through the local relative coordinate system and the coordinate positions generated by the chip images arranged in the array, the relative coordinate positions of the suction head positions and each chip can be obtained through conversion of the camera position coordinates and the suction head position coordinates, and accurate control of suction head position driving can be achieved. Based on the relation between the camera position and the suction head coordinate, the coordinate of each chip position relative to the suction head obtained by conversion from the position of each chip local relative coordinate obtained by shooting by the camera belongs to a more conventional conversion method, and the invention is not repeated.
Because the position coordinate information of the chip is obtained through the chip image in the scheme, the technical scheme provides that the chip image is shot through a camera to obtain three rows and three columns of chip images. The camera shoots the chip image, the shooting image range is obtained, the detection range is obtained in the center of the shooting image range in the obtained shooting image range, the detection range is selected from the area sizes of three rows and three columns, the detection range can be ensured to fall into the central area of the field of view, thus image distortion at the edge of the field of view can be avoided, overlarge errors of the chip position caused by the distortion of target surface image information are prevented, and the pickup precision is ensured.
Referring to fig. 2, unlike the Z-shaped walking traversal pickup in the prior art, in the present solution, lengthy operations such as overall scan image collection, suction head reset, initial position locating, etc. of too many cameras before pickup are not required, after the wafer alignment is completed, the cameras take a photograph and sample at any position of the chip area on the wafer, after the chip positions arranged in array are obtained, the priority order of XB, XA, XC, YB, YA, YC, ZB, ZA, ZC is sequentially passed through at any initial position, the coordinate information is ordered, if the chip is located at the most priority position, the suction head is controlled to suck the chip at the most priority position, and when the optimal rule is selected after each camera shooting, the chip at the most priority in the detection range is always selected.
The priority order of XB, XA, XC, YB, YA, YC, ZB, ZA, ZC, which is the preferred rule disclosed by the invention, can realize that the pick-up range of the suction head gradually moves towards the upper left part of the surface of the wafer in the cycle of continuous suction, displacement, preferred, re-displacement and suction, and the pick-up route of the suction head in any position, moving left upwards and from left to right again is finally realized regardless of the specific position of the chip in the wafer, and the pick-up mode can completely cover all the chip ranges on the wafer, and ensures that the suction head can select the optimal pick-up route design in the current position.
Referring to fig. 3, the existing chip pick-up control method can be applied to wafers with different types and different structural sizes, the technical scheme disclosed by the invention breaks away from the collection of the whole information of the wafer, only pays attention to the chip information in the detection range in each step of optimization rule, ensures that each step is the most priority selection, and cancels the control method of the wafer coordinate system, so that the chip pick-up control method can be directly invoked and applied in the chip pick-up process, simplifies the pick-up process and improves the chip pick-up efficiency.
Referring to fig. 4, in the chip image arranged in an array in the detection range, the array points correspond to the chips or null points, wherein the chips corresponding to the array points are qualified chips or ink point chips, when the optimal position chip in the step S3 is a null point or ink point chip, the optimal rule is to skip the null point or ink point chip, select the next optimal position chip, and when the selected qualified chips or all the array points are selected, finish the optimal rule selection.
In the above scheme, when the chip on the existing pick-up point is removed, null points are generated at the position where the chip is removed in the next detection range, or in practical application, in combination with the actual distribution situation of the chip on the wafer, null point distribution is generated at the edge.
Meanwhile, in the wafer manufacturing process, namely in the previous process of picking up the chips, the wafer detection ring will respectively pass the chips on the wafer or ink dot chips, and the ink dot chips are commonly known by the industry, namely, the unqualified marks are added to the unqualified chips in the wafer detection ring, and ink dots are generally added to the unqualified chips by using ink, so that the unqualified chips are known as ink dot chips.
When the selection rule selects a null point or ink point chip, the selection object is indicated to be unsuitable for picking up the object, and the priority rule skips the unqualified picking up object to select the next optimal position until the qualified chip is selected. If all array points in a detection range are selected to be finished, a qualified chip is not selected, and the probability is that the wafer is picked up completely, the optimization rule is exited, and when no chip position information in the current list is updated, the picking up is stopped.
When no qualified chip exists on the array point in the detection range, the camera performs the operation of the amplification, the amplification is repeated for N times, each time of the operation of the amplification is specifically that the camera translates rightwards by a distance of a chip interval, shooting is performed, the steps S2 to S5 are repeated, and the number of times N of the operation of the amplification is 2.
Ink dot chips are sporadic on a wafer, appear with small probability, and are normally distributed irregularly. In general, the traversing picking of the steps S2 to S5 on the surface of the wafer is not affected, but in consideration of the extreme case, the situation that the picking method cannot be completely covered by the picking method possibly caused by the occurrence of the ink dot chip set is considered, and in consideration of the fact that the picking method is picking from top left to bottom right in the large picking direction, the left area chip of the wafer is covered by a plurality of detection ranges, namely, the area to be picked is covered by the left area chip, in the extreme case, the right-side chip forming ink dot chip blocks the coverage of the detection range, therefore, when the last qualified chip in the detection range is taken, the operation of expanding is performed, the position of one chip interval is shifted to the right by the camera every time, the expansion range is extended to the right by one row, and 3 points can be searched in an expansion mode, so that the qualified chip which is not covered by the detection range is found in time after the ink dot chip interval area is crossed.
Considering the actual quality control condition of wafer production, considering the pick-up efficiency, the number of times of the enlarging and detecting operation is 2, so that 6 points are searched in an expanding way, if the 6 point concentrated areas are isolated by ink point chips, the disqualified chips distributed densely in the previous wafer manufacturing process can be selected and judged to be disqualified products, therefore, the mode can meet the ink point distribution occasions of chips on most wafers, and the requirement of high-efficiency pick-up is met.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
With the above-described preferred embodiments according to the present invention as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (4)
1. The intelligent chip picking method based on image processing is characterized in that a camera shoots and obtains a wafer image, and obtains a plurality of chip position information on the wafer so as to control a suction head to pick up a corresponding chip, and the intelligent chip picking method based on image processing is characterized in that: comprises the following steps of
S1, creating a selection list,
s2, controlling a camera to shoot the positioned wafer to obtain a chip image, obtaining chip images which cover three rows and three columns of array arrangement by the detection range of the camera, and adding the coordinates of each position of the chips which are arranged in a matrix in the detection range into a selection list respectively;
s3, selecting the position coordinates of the chip at the optimal position from the selection list through a preference rule, transmitting the position coordinates to a suction head, and completing the chip pickup at the position by the suction head;
s4, taking the pick-up position in the step S3 as a center by the camera to obtain a new chip image with array arrangement, and updating a selection list according to a plurality of pieces of chip position information obtained by the chip image with the new array arrangement;
s5, stopping picking up when the chipless position information in the selection list is updated;
the preferred rule is specifically:
firstly, ordering position coordinate information represented by chips arranged in an array in a detection range according to a priority order of a first row X, a second row Y and a third row Z;
and then the position coordinate information represented by the chips arranged in each row is ordered by taking the columns as priority, and the priority order is sequentially a second column B, a first column A and a third column C.
2. The intelligent chip pickup method based on image processing as claimed in claim 1, wherein: in the chip image which is arranged in an array in the detection range, the array points correspond to chips or empty points, wherein the chips corresponding to the array points are qualified chips or ink point chips, when the chips at the optimal positions in the step S3 are the empty points or the ink point chips, the optimal rule is to skip the empty points or the ink point chips, the next optimal position chip is selected, and when the selected qualified chips or all the array points are selected, the optimal rule selection is ended.
3. The intelligent chip pickup method based on image processing as claimed in claim 2, wherein: and when no qualified chip exists on the array point in the detection range, the camera performs the operation of the amplification, the amplification is repeated for N times, each time of the operation of the amplification is specifically that the camera translates rightwards by a distance of a chip spacing, then shooting is performed, and the steps S2 to S5 are repeated.
4. The intelligent chip pickup method based on image processing as claimed in claim 3, wherein: the number of times N of the amplification operation is 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311437150.4A CN117457536B (en) | 2023-11-01 | 2023-11-01 | Image processing-based intelligent chip pickup method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311437150.4A CN117457536B (en) | 2023-11-01 | 2023-11-01 | Image processing-based intelligent chip pickup method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117457536A true CN117457536A (en) | 2024-01-26 |
| CN117457536B CN117457536B (en) | 2024-03-26 |
Family
ID=89596231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311437150.4A Active CN117457536B (en) | 2023-11-01 | 2023-11-01 | Image processing-based intelligent chip pickup method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117457536B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004104059A (en) * | 2002-07-17 | 2004-04-02 | Sharp Corp | Method and apparatus for picking up chip |
| US20090014413A1 (en) * | 2007-07-13 | 2009-01-15 | Xerox Corporation | Self-aligned precision datums for array die placement |
| US20100220183A1 (en) * | 2007-06-28 | 2010-09-02 | Yamaha Hatsudoki Kabushiki Kaisha | Component placing apparatus |
| JP2012156240A (en) * | 2011-01-25 | 2012-08-16 | Canon Machinery Inc | Collet position detection method and device |
| CN102834910A (en) * | 2010-04-13 | 2012-12-19 | 日本先锋公司 | Component transfer device and method |
| JP5614825B1 (en) * | 2013-11-29 | 2014-10-29 | 上野精機株式会社 | Classification device, classification method, and classification program |
| CN108807230A (en) * | 2018-06-11 | 2018-11-13 | 皖江新兴产业技术发展中心 | Sorting machine suction nozzle working position accurate calibration method |
| CN111507949A (en) * | 2020-04-08 | 2020-08-07 | 广东九联科技股份有限公司 | Chip identification method based on vision |
| US20220414360A1 (en) * | 2021-01-08 | 2022-12-29 | Changxin Memory Technologies, Inc. | Method for chip collection and method for chip positioning |
| CN116342694A (en) * | 2023-05-19 | 2023-06-27 | 恩纳基智能科技无锡有限公司 | High-efficiency wafer pre-scanning method based on image processing |
| CN116433604A (en) * | 2023-03-15 | 2023-07-14 | 华南理工大学 | Chip identification method and pickup system |
-
2023
- 2023-11-01 CN CN202311437150.4A patent/CN117457536B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004104059A (en) * | 2002-07-17 | 2004-04-02 | Sharp Corp | Method and apparatus for picking up chip |
| US20100220183A1 (en) * | 2007-06-28 | 2010-09-02 | Yamaha Hatsudoki Kabushiki Kaisha | Component placing apparatus |
| US20090014413A1 (en) * | 2007-07-13 | 2009-01-15 | Xerox Corporation | Self-aligned precision datums for array die placement |
| CN102834910A (en) * | 2010-04-13 | 2012-12-19 | 日本先锋公司 | Component transfer device and method |
| JP2012156240A (en) * | 2011-01-25 | 2012-08-16 | Canon Machinery Inc | Collet position detection method and device |
| JP5614825B1 (en) * | 2013-11-29 | 2014-10-29 | 上野精機株式会社 | Classification device, classification method, and classification program |
| CN108807230A (en) * | 2018-06-11 | 2018-11-13 | 皖江新兴产业技术发展中心 | Sorting machine suction nozzle working position accurate calibration method |
| CN111507949A (en) * | 2020-04-08 | 2020-08-07 | 广东九联科技股份有限公司 | Chip identification method based on vision |
| US20220414360A1 (en) * | 2021-01-08 | 2022-12-29 | Changxin Memory Technologies, Inc. | Method for chip collection and method for chip positioning |
| CN116433604A (en) * | 2023-03-15 | 2023-07-14 | 华南理工大学 | Chip identification method and pickup system |
| CN116342694A (en) * | 2023-05-19 | 2023-06-27 | 恩纳基智能科技无锡有限公司 | High-efficiency wafer pre-scanning method based on image processing |
Non-Patent Citations (1)
| Title |
|---|
| 彭昀鹏;张景文;侯洵;: "平板电封装工程中的凸点实现及其在紫外焦平面成像阵列中的应用", 红外, no. 02, 10 February 2008 (2008-02-10) * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117457536B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4543659A (en) | Method for recognizing a pellet pattern | |
| JP3371764B2 (en) | Imaging method and apparatus | |
| CN111256662A (en) | Position information acquisition device, position information acquisition method, recording medium, and position information acquisition system | |
| US20100253814A1 (en) | Image pickup apparatus | |
| WO2017057279A1 (en) | Imaging device, image processing device and display device | |
| CN117457536B (en) | Image processing-based intelligent chip pickup method | |
| KR20150135431A (en) | High-speed image capture method and high-speed image capture device | |
| CN116342694B (en) | High-efficiency wafer pre-scanning method based on image processing | |
| JP2003194881A (en) | Working position confirming device for element conveyor of test handler of semiconductor element, and working position confirming method using the same | |
| US7817846B2 (en) | Method of correcting bonding coordinates using reference bond pads | |
| EP2280539A2 (en) | Method and apparatus for detecting traveling characteristics of shutter | |
| JP3684799B2 (en) | Device for detecting displacement amount of stop position of moving object | |
| JP2004140084A (en) | Pick-up method and device for picking up semiconductor chip | |
| US5946408A (en) | Pick-up apparatus and method for semiconductor chips | |
| JP2005032827A (en) | Pickup method and pickup equipment of semiconductor chip | |
| CN108989690B (en) | Multi-mark-point focusing method, device, equipment and storage medium for linear array camera | |
| JP4101618B2 (en) | Chip pickup method and chip pickup device | |
| US20150369588A1 (en) | Optical measurement apparatus and method of controlling the same | |
| US6380000B1 (en) | Automatic recovery for die bonder wafer table wafermap operations | |
| CN109151319A (en) | A kind of processing method and processing device of multiple labeling point target substance markers point focusing sequence | |
| JP2008014646A (en) | Substrate inspection method | |
| JP2018056944A (en) | Imaging device and imaging element | |
| JPH0821601B2 (en) | Die bonding method for semiconductor pellets | |
| TW202135642A (en) | Manufacturing method for die bonding device and semiconductor device characterized by improving the uniformity of photographic conditions of photographed objects | |
| CN116313939A (en) | High-speed intelligent chip pickup method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |