CN117453474A - Verification method, device, equipment and storage medium of external memory controller - Google Patents
Verification method, device, equipment and storage medium of external memory controller Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The application provides a verification method, a device, equipment and a storage medium of an external memory controller, wherein the method comprises the following steps: configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller; controlling the configured AHB VIP, and performing write operation based on excitation; controlling the configured AHB VIP to perform read operation so as to read the result of the write operation; the results of the write operation and the results of the read operation are compared. According to the method, the AHB VIP is configured according to the AHB transmission mode supported by the internal memory in the external memory controller, the configured AHB VIP is further controlled to perform writing operation and reading operation, verification of the external memory controller is achieved according to comparison of the writing operation result and the reading operation result, and the configuration behavior is not written to a specific design, so that multiplexing of the verification method is achieved.
Description
Technical Field
The present disclosure relates to the field of digital integrated circuit verification, and in particular, to a method, an apparatus, a device, and a storage medium for verifying an external memory controller.
Background
Digital integrated circuit verification is an important element in the design process of integrated circuits to verify that the design meets the intended goals and specifications. The method is mainly used for verifying the correctness, functional consistency, performance, time sequence correctness and the like of the design of the integrated circuit chip. With the increasing cost of manufacturing chips at present, the role played by verification is also becoming important, which is an important link for guaranteeing the quality and reliability of the final product of the integrated circuit.
An Advanced High-performance Bus (AHB) is a High-performance and low-power system Bus proposed by an ARM company, and is used for connecting various hardware modules such as a processor, a memory, a peripheral device and the like. The AHB bus adopts a distributed arbitration mechanism, supports multiple master devices to access the bus simultaneously, and has the characteristics of high efficiency, flexibility, expandability and the like. The AHB VIP (Verification Intellectual Property) is a tool for validating the AHB bus protocol, and may simulate various operations of the AHB bus, including read and write operations, arbitration mechanisms, error handling, etc., to ensure that the design complies with the AHB bus protocol specification. The AHB bus VIP is typically written in a hardware description language and used in conjunction with simulation tools to perform simulation verification.
EXMC (External Memory Controller ) for accessing various off-chip memories, through configuration registers, EXMC can convert AMBA (Advanced Microcontroller Bus Architecture ) protocol into dedicated off-chip Memory communication protocol including SRAM (Static Random-Access Memory), ROM (Read-Only Memory), NOR Flash (nonvolatile Memory), NAND Flash (nonvolatile Memory based on NAND technology), PC Card and SDRAM (Synchronous Dynamic Random-Access Memory). The user may also adjust the relevant time parameters to improve communication efficiency. The access space of the EXMC is divided into a number of blocks (banks), each supporting a specific memory type, the user can control the external memory by configuring the control registers of the banks, and the EXMC external bus interface is an AHB bus.
UVM (Universal Verification Methodology ) is a Systemverilog-based verification methodology that provides a standardized, reusable verification framework for testing environments, test cases, and results analysis in design verification. The goal of UVM is to improve verification efficiency and reusability, reducing verification time and cost.
For the verification of the AHB-EXMC module, a traditional verification method uses a verification platform written by Verilog (hardware description language) to write a directional incentive case for verification. The traditional write AHB bus model simulates the AHB bus behavior.
In the method, the test cases of the Verilog test platform are usually written for specific designs, and other designs are difficult to multiplex.
Disclosure of Invention
In order to solve one of the technical defects, the application provides a verification method, a verification device and a verification storage medium of an external memory controller.
In a first aspect of the present application, there is provided a method of verifying an external memory controller, the method comprising:
configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller;
controlling the configured AHB VIP, and performing write operation based on excitation;
controlling the configured AHB VIP to perform read operation so as to read the result of the write operation;
the results of the write operation and the results of the read operation are compared.
Optionally, the memory is one or more of: nonvolatile memory, synchronous dynamic random access memory, pseudo static random access memory, nonvolatile memory based on NAND technology.
Optionally, controlling the configured AHB VIP to perform a write operation based on the stimulus, including:
the configured AHB VIP is controlled to input stimulus to the design DUT by test based on the AHB _vip_input agent class component, and meanwhile, the behavior of the DUT is simulated based on the stimulus.
Optionally, controlling the configured AHB VIP to perform a read operation, including:
and controlling the configured AHB VIP, and reading the output of the DUT based on the AHB _vip_out agent type component.
Optionally, comparing the result of the write operation with the result of the read operation includes:
taking the result of simulating the behavior of the DUT as the result of the writing operation;
taking the output of the DUT as the result of the read operation;
and comparing whether the result of the write operation is consistent with the result of the read operation.
Optionally, the bit width of the AHB VIP includes one or more of: 4 bit,8bit,16bit,32bit.
Optionally, the transmission manner of the AHB VIP includes one or more of the following: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
In a second aspect of the present application, there is provided an authentication apparatus of an external memory controller, the apparatus comprising:
the configuration module is used for configuring the AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in the external memory controller;
the first control module is used for controlling the configured AHB VIP and performing writing operation based on excitation;
the second control module is used for controlling the configured AHB VIP to perform read operation so as to read the result of the write operation;
and the comparison module is used for comparing the result of the writing operation and the result of the reading operation.
In a third aspect of the present application, there is provided an electronic device, including:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method as described in the first aspect above.
In a fourth aspect of the present application, there is provided a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the method as described in the first aspect above.
The application provides a verification method, a device, equipment and a storage medium of an external memory controller, wherein the method comprises the following steps: configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller; controlling the configured AHB VIP, and performing write operation based on excitation; controlling the configured AHB VIP to perform read operation so as to read the result of the write operation; the results of the write operation and the results of the read operation are compared. According to the method, the AHB VIP is configured according to the AHB transmission mode supported by the internal memory in the external memory controller, the configured AHB VIP is further controlled to perform writing operation and reading operation, verification of the external memory controller is achieved according to comparison of the writing operation result and the reading operation result, and the configuration behavior is not written to a specific design, so that multiplexing of the verification method is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a flow chart of a verification method of an external memory controller according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another method for verifying an external memory controller according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an external memory controller verification device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
In the process of implementing the application, the inventor finds that for the verification of the AHB-EXMC module, a traditional verification method uses a verification platform written by Verilog (hardware description language) to write a directional motivation case for verification. The traditional write AHB bus model simulates the AHB bus behavior. In the method, the test cases of the Verilog test platform are usually written for specific designs, and other designs are difficult to multiplex.
In view of the foregoing, embodiments of the present application provide a method, an apparatus, a device, and a storage medium for verifying an external memory controller, where the method includes: configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller; controlling the configured AHB VIP, and performing write operation based on excitation; controlling the configured AHB VIP to perform read operation so as to read the result of the write operation; the results of the write operation and the results of the read operation are compared. According to the method, the AHB VIP is configured according to the AHB transmission mode supported by the internal memory in the external memory controller, the configured AHB VIP is further controlled to perform writing operation and reading operation, verification of the external memory controller is achieved according to comparison of the writing operation result and the reading operation result, and the configuration behavior is not written to a specific design, so that multiplexing of the verification method is achieved.
The verification method of the external memory controller provided by the embodiment can be realized based on a UVM (Universal Verification Methodology ) verification platform, and an Advanced High-performance Bus (AHB) VIP (Verification Intellectual Property) is adopted to perform function verification on an EXMC (External Memory Controller) module, so that verification can be performed by a variety of construction excitation cases, a basic framework of test cases can be automatically written, and coverage rate can be conveniently collected. The adoption of the AHB bus VIP can save time for writing the bus mode, improve efficiency, avoid insufficient understanding of a protocol and reduce verification risk.
The verification platform for implementing the verification method of the external memory controller provided in this embodiment may be composed of the following parts:
ahb _vip_input agent class component: and (3) inputting excitation into the DUT by using standard protocols of different modes through configuration of different modes of the AHB VIP in a case, and performing write operation of the AHB.
ahb _vip_output agent class component: and reading data of the corresponding address from the DUT by using standard protocols of different modes through configuration of different modes of the AHB VIP in the case, and performing AHB reading operation.
A checker class component: the component is used for realizing data comparison work and is an automatic verification platform
And detecting key components of the result. The verification platform has 1 scoreboard, and data sent by the reference model and data of the DUT are respectively received and compared with each other.
env component: the creation and interconnection work of the components are realized, and a complete verification platform aiming at a specific module is constructed.
Specifically, referring to fig. 1, the implementation procedure of the verification method of the external memory controller provided in this embodiment is as follows:
101, configuring an AHB VIP according to an AHB transmission mode supported by an internal memory in the EXMC.
The method can configure the AHB VIP according to the AHB transmission mode supported by the internal memory in the EXMC of the test point scene, so that the internal memory in the EXMC is traversed according to the corresponding time sequence specified by the AHB-VIP protocol, and the AHB transmission mode supported by the traversed memory is provided for other components in the verification environment to be called, so that verification is completed.
Wherein the internal memory includes, but is not limited to, one or more of the following: NOR Flash (nonvolatile Memory), SDRAM (Synchronous Dynamic Random-Access Memory), PSRAM (Pseudo Static Random Access Memory ), NAND Flash (nonvolatile Memory based on NAND technology).
In addition, the bit width of the AHB VIP includes one or more of the following: 4 bit,8bit,16bit,32bit. The transmission mode of the AHB VIP comprises one or more of the following: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
That is, the AHB VIP is classified into:
single transmission 1.4, 8, 16, 32bit wide;
2.4, 8, 16, 32bit wide burst4 transmissions;
3.4, 8, 16, 32bit wide burst8 transmissions;
4.4, 8, 16, 32bit wide burst16 transmissions;
burst32 transmissions 5.4, 8, 16, 32bit wide;
an unlimited burst transmission of 6.4, 8, 16, 32bit wide.
102, controlling the configured AHB VIP, and performing write operation based on the excitation.
The memory is currently traversed, such as NOR Flash, SDRAM, PSRAM or NAND Flash.
In addition, when writing, the writing is performed simultaneously through two paths. The first path is for writing through the DUT (Design Under Test, by design for testing) according to the configuration of step 101, and the second path is for writing for simulating the DUT.
That is, in this step, the configured AHB VIP is controlled to input stimulus (i.e., the first path) to the DUT by the design under test based on the AHB _vip_input agent class component, and at the same time, simulate the behavior of the DUT (i.e., the second path) based on the stimulus.
As shown in FIG. 2, for the first path, the configured AHB VIP is controlled to traverse the memory (e.g., NOR Flash, SDRAM, PSRAM, NAND Flash) according to a time sequence, and stimulus is input from the AHB _vip_input agent class component to the traversed memory in the DUT so that the DUT performs a write operation through the traversed memory. The DUT internal registers may also be configured. For the second path, the same stimulus in the first path is sent to the reference model to simulate DUT behavior, and the resulting data is sent to the scoreboard.
103, controlling the configured AHB VIP, and performing a read operation so as to read the result of the write operation.
After performing the write operation in step 102, the read operation is performed in step 103, and the result of the write operation is read.
The read operation process is as follows: and controlling the configured AHB VIP, and reading the output of the DUT based on the AHB _vip_out agent type component.
Referring to fig. 2, after input stimulus is given in step 101 and step 102 according to the scene requirement, in step 103, a memory currently traversed by an AHB VIP time sequence is configured in a AHB _vip_out agent component, an AHB read operation is initiated by a protocol configuration method corresponding to the memory, data of an output port of a DUT is collected, and then the collected data is sent to a soundboard, wherein a transmission mode of the AHB VIP read operation is consistent with a transmission mode of a write operation.
That is, the result of the first path in step 102 is read here.
104, comparing the result of the write operation with the result of the read operation.
1. The result of simulating the behavior of the DUT is taken as the result of the write operation.
That is, the result of the write operation is the result of the second path in step 102.
2. The output of the DUT is taken as the result of the read operation.
The result of the read operation is the result of the first path in step 102.
3. And comparing whether the result of the write operation is consistent with the result of the read operation.
The comparison is whether the result of the second path in the step 102 is consistent with the result of the first path in the step 102, and then the EXMC verification is performed according to the comparison result.
Referring to fig. 2, the comparison may be implemented in a software board, because, in step 102, data generated by the behavior of the analog DUT in the second path reference model is sent to the software board, and in step 103, the collected data of the output port of the DUT is sent to the software board, so, in step 104, the software board compares the two data, and compares whether the data input through the write operation is consistent with the data obtained through the read operation.
The verification method of the external memory controller provided by the embodiment can be realized based on a UVM verification platform, compared with a verification platform built by Verilog, the UVM verification environment has higher level abstraction, the UVM provides a series of powerful functions such as things-level modeling and things-level checking, the verification is easier and higher, the UVM adopts an object-oriented method, so that the verification environment can be better reused and expanded, is easy to manage, has the characteristic of high expansion, supports the distributed verification environment, can run in parallel in the process of multiple simulation, and can better utilize system resources and accelerate the verification speed. In addition, the AHB_VIP can better cope with complex application scenes of the EXMC, can automatically generate standard protocol time sequences of different AHB modes, and reduces verification risks compared with manual writing of an AHB bus model.
In addition, the verification method of the external memory controller provided by the embodiment can realize verification of different memory protocols of the EXMC not by manually writing a bus model but by an AHB_VIP mode.
In a specific implementation, the method for verifying the external memory controller provided by the embodiment can integrate the ahb_vip into the UVM environment to verify the function of the EXMC module, and the corresponding UVM environment is built by using only three components, namely the ahb_vip, the reference model and the score board, which is different from the method using the AHB bus model, at least four components are needed, so that the method is convenient for supporting the environment migration of the AHB protocol module verification. Meanwhile, the AHB_VIP can be very conveniently adapted to complex scenes of different EXMC memories, which need to meet different AHB protocol requirements, and verification risks are reduced.
The embodiment provides a verification method of an external memory controller, which includes: configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller; controlling the configured AHB VIP, and performing write operation based on excitation; controlling the configured AHB VIP to perform read operation so as to read the result of the write operation; the results of the write operation and the results of the read operation are compared.
According to the method provided by the embodiment, the AHB VIP is configured according to the AHB transmission mode supported by the internal memory in the external memory controller, so that the configured AHB VIP is controlled to perform writing operation and reading operation, and verification of the external memory controller is realized according to the comparison result of the writing operation and the reading operation.
Based on the same inventive concept of the external memory controller verification method, the present embodiment provides an external memory controller verification apparatus, which can verify the function of an EXMC module in an ahb_vip integrated UVM environment.
Referring to fig. 3, the apparatus includes:
a configuration module 301, configured to configure an AHB VIP according to an advanced high performance bus AHB transmission mode supported by an internal memory in the external memory controller;
a first control module 302, configured to control the configured AHB VIP, and perform a write operation based on the stimulus;
a second control module 303, configured to control the configured AHB VIP, and perform a read operation, so as to read a result of the write operation;
the comparison module 304 is used for comparing the result of the write operation and the result of the read operation.
In particular, the comparison module 304 may control the comparison of the result of the write operation and the result of the read operation of the scoreboard shown in fig. 2.
Wherein the memory is one or more of the following: nonvolatile memory, synchronous dynamic random access memory, pseudo static random access memory, nonvolatile memory based on NAND technology.
The first control module 302 is configured to control the configured AHB VIP, input stimulus to the DUT by the design under test based on the AHB _vip_input agent component, and simulate the behavior of the DUT based on the stimulus.
The second control module 303 is configured to control the configured AHB VIP, and read the output of the DUT based on the AHB _vip_out agent component.
Wherein the comparison module 304 is configured to take a result of simulating the behavior of the DUT as a result of the write operation. The output of the DUT is taken as the result of the read operation. And comparing whether the result of the write operation is consistent with the result of the read operation.
Wherein the bit width of the AHB VIP comprises one or more of the following: 4 bit,8bit,16bit,32bit.
The transmission mode of the AHB VIP comprises one or more of the following: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
The device provided by the embodiment configures the AHB VIP according to the AHB transmission mode supported by the internal memory in the external memory controller, further controls the configured AHB VIP to perform writing operation and reading operation, and realizes verification of the external memory controller according to the comparison result of the writing operation and the reading operation.
Based on the same inventive concept of the verification method of the external memory controller, the present embodiment provides an electronic device including: memory, processor, and computer program.
Wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of verifying the external memory controller described above.
In particular, the method comprises the steps of,
and configuring the AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in the external memory controller.
And controlling the configured AHB VIP, and performing write operation based on the excitation.
And controlling the configured AHB VIP to perform read operation so as to read the result of the write operation.
The results of the write operation and the results of the read operation are compared.
Optionally, the memory is one or more of: nonvolatile memory, synchronous dynamic random access memory, pseudo static random access memory, nonvolatile memory based on NAND technology.
Optionally, controlling the configured AHB VIP to perform a write operation based on the stimulus, including:
the configured AHB VIP is controlled to input stimulus to the design DUT by test based on the AHB _vip_input agent class component, and meanwhile, the behavior of the DUT is simulated based on the stimulus.
Optionally, controlling the configured AHB VIP to perform a read operation, including:
and controlling the configured AHB VIP, and reading the output of the DUT based on the AHB _vip_out agent type component.
Optionally, comparing the result of the write operation with the result of the read operation includes:
the result of simulating the behavior of the DUT is taken as the result of the write operation.
The output of the DUT is taken as the result of the read operation.
And comparing whether the result of the write operation is consistent with the result of the read operation.
Optionally, the bit width of the AHB VIP includes one or more of: 4 bit,8bit,16bit,32bit.
Optionally, the transmission manner of the AHB VIP includes one or more of the following: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
In the electronic device provided in this embodiment, the computer program is executed by the processor to configure the AHB VIP according to the AHB transmission mode supported by the internal memory in the external memory controller, so as to control the configured AHB VIP to perform the writing operation and the reading operation, and the verification of the external memory controller is implemented according to the comparison result of the writing operation and the reading operation.
Based on the same inventive concept of the verification method of the external memory controller, the present embodiment provides a computer-readable storage medium, and a computer program stored thereon. The computer program is executed by the processor to implement the method of verifying the external memory controller described above.
In particular, the method comprises the steps of,
and configuring the AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in the external memory controller.
And controlling the configured AHB VIP, and performing write operation based on the excitation.
And controlling the configured AHB VIP to perform read operation so as to read the result of the write operation.
The results of the write operation and the results of the read operation are compared.
Optionally, the memory is one or more of: nonvolatile memory, synchronous dynamic random access memory, pseudo static random access memory, nonvolatile memory based on NAND technology.
Optionally, controlling the configured AHB VIP to perform a write operation based on the stimulus, including:
the configured AHB VIP is controlled to input stimulus to the design DUT by test based on the AHB _vip_input agent class component, and meanwhile, the behavior of the DUT is simulated based on the stimulus.
Optionally, controlling the configured AHB VIP to perform a read operation, including:
and controlling the configured AHB VIP, and reading the output of the DUT based on the AHB _vip_out agent type component.
Optionally, comparing the result of the write operation with the result of the read operation includes:
the result of simulating the behavior of the DUT is taken as the result of the write operation.
The output of the DUT is taken as the result of the read operation.
And comparing whether the result of the write operation is consistent with the result of the read operation.
Optionally, the bit width of the AHB VIP includes one or more of: 4 bit,8bit,16bit,32bit.
Optionally, the transmission manner of the AHB VIP includes one or more of the following: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
The computer readable storage medium provided in this embodiment, on which a computer program is executed by a processor to configure an AHB VIP according to an AHB transmission manner supported by an internal memory in an external memory controller, further control the configured AHB VIP to perform a write operation and a read operation, and implement verification of the external memory controller according to a result of comparing the write operation and a result of the read operation.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The solutions in the embodiments of the present application may be implemented in various computer languages, for example, object-oriented programming language Java, and an transliterated scripting language JavaScript, etc.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. A method of verifying an external memory controller, the method comprising:
configuring an AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in an external memory controller;
controlling the configured AHB VIP, and performing write operation based on excitation;
controlling the configured AHB VIP to perform a read operation so as to read the result of the write operation;
comparing the result of the write operation with the result of the read operation.
2. The method of claim 1, wherein the memory is one or more of the following: nonvolatile memory, synchronous dynamic random access memory, pseudo static random access memory, nonvolatile memory based on NAND technology.
3. The method of claim 1, wherein controlling the configured AHB VIP to perform a write operation based on the stimulus comprises:
and controlling the configured AHB VIP, inputting stimulus to the design DUT by testing based on the AHB _vip_input agent component, and simulating the behavior of the DUT based on the stimulus.
4. The method of claim 3, wherein controlling the configured AHB VIP to perform a read operation comprises:
and controlling the configured AHB VIP, and reading the output of the DUT based on the AHB _vip_out agent component.
5. The method of claim 4, wherein the comparing the results of the write operation and the results of the read operation comprises:
taking the result of simulating the behavior of the DUT as the result of the writing operation;
taking the output of the DUT as a result of a read operation;
and comparing whether the result of the write operation is consistent with the result of the read operation.
6. The method of claim 1, wherein the bit width of the AHB VIP comprises one or more of: 4 bit,8bit,16bit,32bit.
7. The method of claim 1, wherein the transmission of the AHB VIP comprises one or more of: single transmission, burst4 transmission, burst8 transmission, burst16 transmission, burst32 transmission, and not limited to burst transmission.
8. An authentication apparatus for an external memory controller, the apparatus comprising:
the configuration module is used for configuring the AHB VIP according to an advanced high-performance bus AHB transmission mode supported by an internal memory in the external memory controller;
the first control module is used for controlling the configured AHB VIP and performing writing operation based on excitation;
the second control module is used for controlling the configured AHB VIP to perform read operation so as to read the result of the write operation;
and the comparison module is used for comparing the result of the writing operation with the result of the reading operation.
9. An electronic device, comprising:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any of claims 1-7.
10. A computer-readable storage medium, characterized in that a computer program is stored thereon; the computer program being executed by a processor to implement the method of any of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311453449.9A CN117453474A (en) | 2023-11-03 | 2023-11-03 | Verification method, device, equipment and storage medium of external memory controller |
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| CN202311453449.9A CN117453474A (en) | 2023-11-03 | 2023-11-03 | Verification method, device, equipment and storage medium of external memory controller |
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