CN117452178A - Integrated circuit testing method, integrated circuit testing device, electronic equipment and storage medium - Google Patents
Integrated circuit testing method, integrated circuit testing device, electronic equipment and storage medium Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The application provides an integrated circuit testing method, an integrated circuit testing device, electronic equipment and a storage medium. The integrated circuit testing method comprises the following steps: acquiring a target test item of an integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item; running the input code based on the test stimulus code to generate waveform data; and responding to the waveform data to meet the preset standard corresponding to the target test item, and converting the waveform data into a test vector corresponding to the target test item so as to test the integrated circuit to be tested according to the test vector. According to the integrated circuit testing method, the integrated circuit testing device, the electronic equipment and the storage medium, the waveform data are utilized to directly generate the test vector, so that the generation efficiency and the accuracy of the test vector are effectively improved, and the testing efficiency and the accuracy of the integrated circuit are further effectively improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to an integrated circuit testing method, an integrated circuit testing device, an electronic device, and a storage medium.
Background
An integrated circuit (FPGA, field Programmable Gate Array) needs to generate test vectors at the time of testing. In the prior art, test vectors are usually written row by row manually by a tester, and the number of pins of an FPGA device is usually numerous, and the structure is complex, so that the number of rows and columns of the test vectors to be written is also numerous, and the test vectors need to be manually checked after being written, and the process has low efficiency and is easy to make mistakes, thereby influencing the test efficiency and the test result of an integrated circuit.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide an integrated circuit testing method, an integrated circuit testing device, an electronic device and a storage medium.
Based on the above objects, the present application provides an integrated circuit testing method, comprising:
acquiring a target test item of an integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item;
running the input code based on the test stimulus code to generate waveform data;
and responding to the waveform data to meet the preset standard corresponding to the target test item, and converting the waveform data into a test vector corresponding to the target test item so as to test the integrated circuit to be tested according to the test vector.
Further, the method further comprises:
and modifying the input code in response to the waveform data not conforming to the preset standard corresponding to the target test item, and regenerating the waveform data based on the test excitation code and the modified input code until the regenerated waveform data conforms to the preset standard corresponding to the target test item.
Further, the test excitation code comprises input signal definition information, output signal definition information, instantiation information, an excitation command and a waveform generation command;
wherein the instantiation information is instantiation data applied to the input code.
Further, the test stimulus code and/or the input code are written using integrated circuit functional configuration software.
Further, the input code is written using Verilog language.
Further, before the generating waveform data based on the running the input code of the test excitation code, the method further includes:
and performing static code analysis on the test excitation code and/or the input code.
Further, the waveform data is generated using integrated circuit waveform simulation software.
Based on the same inventive concept, the present disclosure also provides an integrated circuit testing apparatus, including:
the code writing module is used for obtaining a target test item of the integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item;
a waveform generation module to run the input code based on the test stimulus code to generate waveform data;
and the vector generation module is used for responding to the waveform data to accord with the preset standard corresponding to the target test item, converting the waveform data into a test vector corresponding to the target test item and testing the integrated circuit to be tested according to the test vector.
Based on the same inventive concept, the present disclosure also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing an integrated circuit testing method as described above when executing the program.
Based on the same inventive concept, the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform an integrated circuit test method as described above.
From the above, it can be seen that, according to the integrated circuit testing method, the device, the electronic equipment and the storage medium provided by the application, an input code and a test excitation code are written based on a target test item of an integrated circuit to be tested, the input code contains circuit logic corresponding to the target test item, then the input code is operated based on the test excitation code, waveform simulation is performed, and a simulation file containing waveform data is obtained. When the waveform data of the simulation file accords with the preset standard corresponding to the target test item, the input code and the test excitation code are correctly written, the waveform data at the moment is the normal operation result of the integrated circuit to be tested, so the waveform data at the moment is converted into a test vector, the test vector is input into the integrated circuit tester to trigger the integrated circuit to be tested to operate, the integrated circuit tester collects the actual response result of the integrated circuit to be tested, if the actual response result of the integrated circuit to be tested is the same as the standard response in the test vector, the function of the integrated circuit to be tested is normal, and if the actual response result of the integrated circuit to be tested is different from the standard response in the test vector, the integrated circuit to be tested is required to be regulated or redesigned. In the process, the test vectors are not required to be written line by line according to the target test items, the test vectors are obtained through direct conversion of waveform data, the generation efficiency of the test vectors is improved, meanwhile, the waveform data accords with the preset standard corresponding to the target test items, and therefore the accuracy of the obtained test vectors is high, and the test efficiency and accuracy of the integrated circuit are further effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of an integrated circuit testing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an integrated circuit testing apparatus according to an embodiment of the present application;
fig. 3 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
FPGA (Field Programmable Gate Array) is an integrated circuit with programmable characteristics designed and realized in advance on a silicon chip, and can be configured into a specified circuit structure according to the requirements of a designer, so that a user does not need to rely on an ASIC (Application Specific Integrated Circuit ) chip designed and manufactured by a chip manufacturer, and the integrated circuit is widely applied to the fields of prototype verification, communication, automobile electronics, industrial control, aerospace, data centers and the like.
After the FPGA is produced, it needs to test its functional parameters, so as to ensure that the obtained integrated circuit meets the design requirement, and usually, an integrated circuit tester is used to test its functional parameters. When the integrated circuit tester is used for testing the integrated circuit, firstly, a test vector is required to be generated, the test vector generally comprises input excitation and expected storage response, the test vector is input to the integrated circuit tester, the input excitation is used as an input signal to trigger the integrated circuit, the expected storage response is a standard response corresponding to the input excitation, the integrated circuit tester collects an actual response result of the integrated circuit, and the response result is compared with the expected storage response in the test vector, so that whether the functional parameters of the integrated circuit to be tested are normal or not can be measured.
In the prior art, test vectors are usually written row by row manually by a tester, and the number of pins of an FPGA device is usually numerous, and the structure is complex, so that the number of rows and columns of the test vectors to be written is also numerous, and the test vectors need to be manually checked after being written, and the process has low efficiency and is easy to make mistakes, thereby influencing the test efficiency and the test result of an integrated circuit.
Based on the above situation, the present application provides an integrated circuit testing method, as shown in fig. 1, capable of automatically generating a test vector for an integrated circuit tester, so as to effectively improve the test efficiency, and the method includes:
s11: acquiring a target test item of an integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item;
s12: running the input code based on the test stimulus code to generate waveform data;
s13: and responding to the waveform data to meet the preset standard corresponding to the target test item, and converting the waveform data into a test vector corresponding to the target test item so as to test the integrated circuit to be tested according to the test vector.
In the application, input codes and test excitation codes are written based on target test items of an integrated circuit to be tested, the input codes comprise circuit logic corresponding to the target test items, then the input codes are operated based on the test excitation codes, waveform simulation is carried out, and a simulation file containing waveform data is obtained. When the waveform data of the simulation file accords with the preset standard corresponding to the target test item, the input code and the test excitation code are correctly written, the waveform data at the moment is the normal operation result of the integrated circuit to be tested, so the waveform data at the moment is converted into a test vector, the test vector is input into the integrated circuit tester to trigger the integrated circuit to be tested to operate, the integrated circuit tester collects the actual response result of the integrated circuit to be tested, if the actual response result of the integrated circuit to be tested is the same as the standard response in the test vector, the function of the integrated circuit to be tested is normal, and if the actual response result of the integrated circuit to be tested is different from the standard response in the test vector, the integrated circuit to be tested is required to be regulated or redesigned. In the process, the test vectors are not required to be written line by line according to the target test items, the test vectors are obtained through direct conversion of waveform data, the generation efficiency of the test vectors is improved, meanwhile, the waveform data accords with the preset standard corresponding to the target test items, and therefore the accuracy of the obtained test vectors is high, and the test efficiency and accuracy of the integrated circuit are further effectively improved. Specifically, the preset standard of the target test item is the standard response of the target test item of the integrated circuit to be tested when the target test item is normal, and the standard response can be obtained through files such as a product manual, a design instruction, a functional parameter standard and the like of the integrated circuit to be tested.
In some embodiments, the method further comprises:
s14: and modifying the input code in response to the waveform data not conforming to the preset standard corresponding to the target test item, and regenerating the waveform data based on the test excitation code and the modified input code until the regenerated waveform data conforms to the preset standard corresponding to the target test item.
When the waveform data does not meet the preset standard corresponding to the target test item, a certain error exists in the written circuit logic in the input code, and the written circuit logic does not meet the circuit logic when the integrated circuit to be tested normally operates, so that the input code needs to be adjusted, the regenerated waveform data meets the preset standard corresponding to the target test item, a test vector with normal functional parameters is obtained, and then whether the functional parameters corresponding to the integrated circuit to be tested are normal is detected by taking the test vector as the standard, so that the test of the integrated circuit is realized. Specifically, the test excitation code may also have a writing error, so that the test excitation code may be modified appropriately, and then waveform data is regenerated based on the modified test excitation code and the input code until the regenerated waveform data meets a preset standard corresponding to the target test item.
In some embodiments, for an integrated circuit to be tested, a plurality of target test items may be disassembled, and then, for each target test item, steps S11 to S14 are separately executed to obtain a test vector corresponding to each target test item. Specifically, the splitting may be performed according to a module of the integrated circuit to be tested, or the splitting may be performed according to a function of the integrated circuit to be tested, for example, a plurality of target test items obtained by splitting according to a test function are respectively a look-up table test (LUT test), an input/output test (IO test), a memory test, a phase-locked loop test (PLL test), or the like, or one target test item may be established without splitting into a plurality of target test items, to complete the detection of all functions or modules of the integrated circuit to be tested, which is not particularly limited.
When the integrated circuit to be tested is split into a plurality of target test items according to modules or functions, a certain module of the integrated circuit to be tested runs or a certain function is realized, and is generally not applied to all pins, but only partial pins are involved, so that the input codes written comprise relevant circuit logic of the pins involved in the module or the function, namely, the input codes comprise the circuit logic corresponding to the target test items, thereby effectively reducing the workload of input code writing tasks and improving the working efficiency.
In some embodiments, the test stimulus code includes input signal definition information, output signal definition information, instantiation information, a stimulus command, and a waveform generation command;
wherein the instantiation information is instantiation data applied to the input code.
The input signal definition information is used to define the signal type of the pin of the integrated circuit to be tested, which is related to the target test item, for example, whether the signal type is stored in the register of the integrated circuit to be tested first, then the corresponding pin is triggered, or the corresponding pin is triggered directly, etc. The output signal definition information is used for defining the signal type of the pin of the integrated circuit to be tested which is related to the target test item. The instantiation information is actually instantiation data given to the input code, namely, the instantiation data is used for assigning value to the circuit logic, and the circuit logic in the input code is operated on the basis of the instantiation data, so that a specific operation result can be output and obtained. The excitation command comprises operation instructions of all pins of the integrated circuit to be tested related to the target test project. And the waveform generation command is used for triggering the generation of waveform data.
In some embodiments, the test stimulus code and/or the input code is written using integrated circuit functional configuration software. Specifically, the integrated circuit function configuration software may employ a quatus II software. The Quartz II is comprehensive FPGA development software, and has the characteristics of multiple design input forms, high running speed, unified interface, centralized functions and the like. Other integrated circuit function configuration software capable of implementing test stimulus code writing and input code writing may also be applied to the present application, and is not particularly limited.
In some embodiments, the input code is written using Verilog language. The Verilog language, collectively referred to as Verilog HDL (HDL: hardware Description Language), is a hardware description language that describes the structure and behavior of digital system hardware in textual form, and may represent logic diagrams, logic expressions, and logic functions performed by a digital logic system. The Verilog language is used as a standard hardware design language, adopts a standard text format, has the characteristics of simplicity, intuitiveness, high efficiency and the like, and can improve the logic design efficiency of a circuit and shorten the design period, thereby improving the generation efficiency of waveform data, and further effectively improving the generation efficiency of test vectors and the test efficiency of an integrated circuit by writing input codes by using the language.
In some embodiments, before performing step 102, further comprises: and performing static code analysis on the test excitation code and/or the input code.
The static code analysis is to analyze the code semantics and behaviors, discover and correct errors in the test excitation code or the input code in time, and improve the code writing efficiency, so that the generating efficiency of waveform data is improved, and the generating efficiency of test vectors and the testing efficiency of integrated circuits are effectively improved. When using the quatus II software as integrated circuit function configuration software to write test stimulus code and input code, analysis and Synthesis tools (i.e., start Analysis & Synthesis tools) of the quatus II software can be utilized to implement static code Analysis, and the technology finds writing errors in the code.
In some embodiments, the waveform data is generated using integrated circuit waveform simulation software. In particular, the integrated circuit functional configuration software may employ Modelsim software. The Modelsim software is hardware description language simulation software, has high compiling simulation speed, and generates waveform data by using the Modelsim software, and has high speed and high efficiency, thereby improving the generation efficiency of the waveform data, and further effectively improving the generation efficiency of test vectors and the test efficiency of integrated circuits. Other integrated circuit waveform simulation software capable of generating waveform data may be applied to the present application, and is not particularly limited. The integrated circuit function configuration software and the integrated circuit waveform simulation software can adopt the same software or different software, and are not particularly limited.
In some embodiments, the waveform data is converted into test vectors using integrated circuit waveform conversion software. Specifically, the integrated circuit waveform conversion software may employ Wavewizard software. The wave wizard software provides an optimization and synthesis tool, can realize rapid design and rapid execution, and is high in speed and efficiency when being used for converting waveform data into test vectors.
It should be noted that, the method of the embodiments of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of embodiments of the present application, and the devices may interact with each other to complete the methods.
It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Based on the same inventive concept, the application also provides an integrated circuit testing device corresponding to the method of any embodiment, which is used for automatically generating a test vector for an integrated circuit tester to realize the function parameter test of the integrated circuit.
Referring to fig. 2, the integrated circuit testing apparatus includes:
a code writing module 21, configured to obtain a target test item of an integrated circuit to be tested, write an input code and a test excitation code triggering the input code based on the target test item, where the input code includes circuit logic corresponding to the target test item;
a waveform generation module 22 to run the input code based on the test stimulus code to generate waveform data;
the vector generation module 23 is configured to convert the waveform data into a test vector corresponding to the target test item in response to the waveform data meeting a preset standard corresponding to the target test item, so as to test the integrated circuit under test according to the test vector.
In some embodiments, the apparatus further comprises:
and the code modification module is used for modifying the input code according to the fact that the waveform data does not accord with the preset standard corresponding to the target test item, and regenerating the waveform data based on the test excitation code and the modified input code until the regenerated waveform data accord with the preset standard corresponding to the target test item.
In some embodiments, the test stimulus code includes input signal definition information, output signal definition information, instantiation information, a stimulus command, and a waveform generation command;
wherein the instantiation information is instantiation data applied to the input code.
In some embodiments, the test stimulus code and/or the input code is written using integrated circuit functional configuration software.
In some embodiments, the input code is written using Verilog language.
In some embodiments, further comprising:
and the code analysis module is used for carrying out static code analysis on the test excitation code and/or the input code before the input code is operated based on the test excitation code to generate waveform data.
In some embodiments, the waveform data is generated using integrated circuit waveform simulation software.
For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, the functions of each module may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.
The device of the foregoing embodiment is configured to implement a corresponding method for testing an integrated circuit in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
Based on the same inventive concept, the application also provides an electronic device corresponding to the method of any embodiment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor implements the method for testing an integrated circuit according to any embodiment when executing the program.
Fig. 3 shows a more specific hardware architecture of an electronic device according to this embodiment, where the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.
The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.
The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).
It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The electronic device of the foregoing embodiment is configured to implement a corresponding method for testing an integrated circuit in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
Based on the same inventive concept, corresponding to any of the above embodiments, the present application further provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform an integrated circuit testing method as described in any of the above embodiments.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiments stores computer instructions for causing the computer to execute an integrated circuit testing method as described in any one of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
It should be noted that, the embodiments of the present application may be further described in the following manner:
and testing the function of the lookup table of the integrated circuit to be tested by taking the lookup table test of the integrated circuit to be tested as a target test item. The specific method comprises the following steps:
an engineering design file is newly built in the quick II software, a Verilog language is adopted to write an input code corresponding to the lookup table test, and the input code comprises circuit logic corresponding to the lookup table test, namely circuit logic when the lookup table function of the integrated circuit to be tested operates normally. And (3) carrying out static code Analysis on the input codes by using a Start Analysis and Synthesis tool in the quick II software, searching errors in the input codes, and when errors are found, modifying corresponding contents in the input codes. Writing a test excitation code by using the Quartz II software or the Modelsim software, definitely inputting signal definition information, output signal definition information, instantiation information, excitation commands and waveform generation commands into the test excitation code, then carrying out static code analysis on the test excitation code, searching for errors in the test excitation code, and when errors are found, modifying corresponding contents in the test excitation code.
And operating an input code based on the test excitation code by using Modelsim software, testing corresponding circuit logic by using a lookup table in the input code, and outputting a simulation response signal of a waveform after receiving the corresponding test excitation code to obtain waveform data. If the waveform data accords with the preset standard corresponding to the lookup table test of the integrated circuit to be tested, the preset standard at the moment is the standard response when the lookup table test of the integrated circuit to be tested is normal, the written circuit logic corresponding to the lookup table test accords with the design requirement of the integrated circuit to be tested, the waveform data is converted into the corresponding test vector, if the waveform data does not accord with the design requirement, the input code is modified, and the waveform data is regenerated based on the modified input code until the waveform data which accords with the preset standard corresponding to the lookup table test is obtained. The normal operation result of the lookup table function of the integrated circuit to be tested is simulated through the corresponding waveform data, then the waveform data is converted into a test vector by using Wavewizard software, and the test vector contains standard response (namely expected storage response) for comparison with actual response data of the integrated circuit to be tested, so that the functional parameter setting of the integrated circuit to be tested is realized.
And finally, inputting the test vector into the integrated circuit tester to test the function of the lookup table of the integrated circuit to be tested, wherein the test vector triggers the integrated circuit to be tested to operate, the integrated circuit tester collects actual response data of pins related to the function of the lookup table of the integrated circuit to be tested, if the actual response data accords with the standard response in the test vector, the function of the lookup table of the integrated circuit to be tested is normal, if the actual response data does not accord with the standard response in the test vector, the function of the lookup table is abnormal, and therefore the function test result of the lookup table of the integrated circuit to be tested is obtained, and the lookup table test of the integrated circuit to be tested is completed.
It will be appreciated that before using the technical solutions of the various embodiments in the disclosure, the user may be informed of the type of personal information involved, the range of use, the use scenario, etc. in an appropriate manner, and obtain the authorization of the user.
For example, in response to receiving an active request from a user, a prompt is sent to the user to explicitly prompt the user that the operation it is requesting to perform will require personal information to be obtained and used with the user. Therefore, the user can select whether to provide personal information to the software or hardware such as the electronic equipment, the application program, the server or the storage medium for executing the operation of the technical scheme according to the prompt information.
As an alternative but non-limiting implementation, in response to receiving an active request from a user, the manner in which the prompt information is sent to the user may be, for example, a popup, in which the prompt information may be presented in a text manner. In addition, a selection control for the user to select to provide personal information to the electronic device in a 'consent' or 'disagreement' manner can be carried in the popup window.
It will be appreciated that the above-described notification and user authorization process is merely illustrative, and not limiting of the implementations of the present disclosure, and that other ways of satisfying relevant legal regulations may be applied to the implementations of the present disclosure.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and/or the like which are within the spirit and principles of the embodiments are intended to be included within the scope of the present application.
Claims (10)
1. A method of testing an integrated circuit, comprising:
acquiring a target test item of an integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item;
running the input code based on the test stimulus code to generate waveform data;
and responding to the waveform data to meet the preset standard corresponding to the target test item, and converting the waveform data into a test vector corresponding to the target test item so as to test the integrated circuit to be tested according to the test vector.
2. The integrated circuit testing method of claim 1, further comprising:
and modifying the input code in response to the waveform data not conforming to the preset standard corresponding to the target test item, and regenerating the waveform data based on the test excitation code and the modified input code until the regenerated waveform data conforms to the preset standard corresponding to the target test item.
3. The method of claim 1, wherein the test stimulus code comprises input signal definition information, output signal definition information, instantiation information, stimulus commands, and waveform generation commands;
wherein the instantiation information is instantiation data applied to the input code.
4. An integrated circuit testing method according to claim 1, characterized in that the test stimulus code and/or the input code are written using integrated circuit function configuration software.
5. The method of claim 1, wherein the input code is written in Verilog language.
6. The method of claim 1, wherein prior to running the input code to generate waveform data based on the test stimulus code, further comprising:
and performing static code analysis on the test excitation code and/or the input code.
7. The method of claim 1, wherein the waveform data is generated using integrated circuit waveform simulation software.
8. An integrated circuit testing apparatus, comprising:
the code writing module is used for obtaining a target test item of the integrated circuit to be tested, writing an input code and a test excitation code triggering the input code based on the target test item, wherein the input code comprises circuit logic corresponding to the target test item;
a waveform generation module to run the input code based on the test stimulus code to generate waveform data;
and the vector generation module is used for responding to the waveform data to accord with the preset standard corresponding to the target test item, converting the waveform data into a test vector corresponding to the target test item and testing the integrated circuit to be tested according to the test vector.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the integrated circuit testing method of any one of claims 1 to 7 when the program is executed by the processor.
10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the integrated circuit testing method of any one of claims 1 to 7.
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| CN202311182629.8A CN117452178A (en) | 2023-09-13 | 2023-09-13 | Integrated circuit testing method, integrated circuit testing device, electronic equipment and storage medium |
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