CN117439584A - Input/output port circuit and chip thereof - Google Patents

Input/output port circuit and chip thereof Download PDF

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Publication number
CN117439584A
CN117439584A CN202210825318.8A CN202210825318A CN117439584A CN 117439584 A CN117439584 A CN 117439584A CN 202210825318 A CN202210825318 A CN 202210825318A CN 117439584 A CN117439584 A CN 117439584A
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CN
China
Prior art keywords
winding
transistor
input
winding portion
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210825318.8A
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Chinese (zh)
Inventor
游思颖
古辰宣
林尚宏
戴昆育
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to CN202210825318.8A priority Critical patent/CN117439584A/en
Publication of CN117439584A publication Critical patent/CN117439584A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present disclosure relates to input/output port circuits and chips thereof. An input/output port circuit includes an input/output pad, a transistor, and a conductive trace. The transistor has a first connection terminal and a second connection terminal. The first connection end of the transistor is electrically connected to the input/output pad through the conductive wiring, and the second connection end is electrically connected to the other transistor. The conductive wire is electrically connected to the first connection terminal of the transistor. The conductive wire is used for providing a series resistance to force the surge current to flow to another transistor when the surge current is input through the input/output pad.

Description

Input/output port circuit and chip thereof
Technical Field
The present disclosure relates to protection technology for surge current, and more particularly to an input/output port circuit and a chip thereof capable of preventing internal transistors from being damaged by breakdown of surge current.
Background
The surge (current) refers to an overload current that appears instantaneously in the circuit, and may cause damage to the circuit. In one circuit, the drain terminal of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is connected to an input/output pad. However, the drain terminal of the mosfet has a low resistance because no additional wiring is connected thereto. Therefore, when a surge current is input through the input/output pad, the large current is concentrated at the drain terminal of the mosfet, so that the mosfet is damaged by breakdown.
Disclosure of Invention
An input/output port circuit is provided. In one embodiment, an input/output port circuit includes an input/output pad, a transistor, and a conductive trace. The transistor has a first connection terminal and a second connection terminal. The first connection end of the transistor is electrically connected to the input/output pad through the conductive wiring, and the second connection end is electrically connected to the other transistor. The conductive wire is electrically connected to the first connection terminal of the transistor. The conductive wire is used for providing a series resistance so as to force the surge current to flow to the other transistor when the surge current is input through the input/output pad.
In some embodiments, the first connection terminal of the transistor is electrically connected only to the input/output pad and the conductive trace.
In some embodiments, the conductive wiring and at least a portion of the conductive routing are located in different metal layers in the layout.
In some embodiments, the conductive wire includes a first connection section, a wire section and a second connection section connected in sequence in the layout. The first connecting section and the second connecting section are respectively and electrically connected to the first connecting end of the transistor, and the first connecting section is not contacted with the second connecting section.
In some embodiments, the conductive wire and the conductive wire are located in the same metal layer in the layout, and the wire segment of the conductive wire does not overlap the conductive wire.
In some embodiments, the wire segments of the conductive wire at least partially overlap the layout of the transistor.
In some embodiments, the wire segments of the conductive wire at least partially overlap the layout of the control terminal of the transistor.
In some embodiments, the wire segments of the conductive wire do not overlap the layout of the second connection terminal of the transistor.
In some embodiments, the first connection section of the conductive wire is opposite and parallel to the second connection section. The winding section of the conductive winding comprises a first winding part, a second winding part, a third winding part, a fourth winding part and a fifth winding part which are sequentially connected. The winding section of the conductive winding is connected to the first connecting section by a first winding part and connected to the second connecting section by a fifth winding part. The second winding part is opposite to the first connecting section. The fourth winding part is opposite to the second connecting section. The first winding part and the fifth winding part are respectively opposite to the third winding part.
In some embodiments, the third winding portion includes a first sub-winding, a second sub-winding, a third sub-winding, a fourth sub-winding, and a fifth sub-winding connected in sequence. The third winding part is connected with the second winding part by the first sub winding and is connected with the fourth winding part by the fifth sub winding. The first sub-winding is opposite to the first winding part. The fifth sub-winding is opposite to the fifth winding part. The second sub-winding is opposite to the fourth sub-winding.
The present disclosure further provides a chip. In one embodiment, the chip includes the input/output port circuitry of any of the embodiments.
The detailed features and advantages of the present invention will be set forth in the detailed description that follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the invention as described herein.
Drawings
FIG. 1 is a block diagram of one embodiment of a chip.
Fig. 2 is a schematic diagram of one embodiment of an input/output port circuit.
FIG. 3 is a schematic top view of one embodiment of a partial layout of an input/output port circuit.
FIG. 4 is a schematic top view of one embodiment of a partial layout of an input/output port circuit.
Fig. 5 is a schematic cross-sectional view of one embodiment of the relative relationship between the wire segments of the conductive wire and the layout of the transistor.
Fig. 6 is a schematic cross-sectional view of one embodiment of the relative relationship between the wire segments of the conductive wire and the layout of the transistor.
Fig. 7 is a schematic cross-sectional view of one embodiment of the relative relationship between the wire segments of the conductive wire and the layout of the transistor.
Detailed Description
The foregoing objects, features and advantages of the embodiments of the present invention will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of one embodiment of a chip. Referring to fig. 1, a chip 10 includes at least one input/output port circuit 100. For brevity, a set of i/o port circuits 100 is taken as an example, but the number is not limited thereto. In addition, the chip 10 may further include other circuits and/or components, which will not be described herein depending on the application of the chip 10.
Fig. 2 is a schematic diagram of one embodiment of an input/output port circuit. Referring to fig. 2, in one embodiment, the input/output port circuit 100 includes an input/output pad (I/O pad) 110, a transistor 120, and a conductive trace 130. The input/output pad 110 may be used to receive input signals from external inputs and/or output internal output signals. In some embodiments, the i/o pad 110 is a wire bond pad and is electrically connected to a corresponding conductive structure (e.g., a pin or a conductive frame on a package substrate) on a package substrate (not shown) through wire bonds. In addition, the I/O pad 110 may be an I/O pad for a network jack.
The transistor 120 has two connection terminals (hereinafter referred to as a first connection terminal 121 and a second connection terminal 122) and a control terminal 123. The first connection 121 of the transistor 120 is electrically connected to the input/output pad 110 through the conductive connection C1 to receive an input signal input through the input/output pad 110 and/or output an internal output signal through the input/output pad 110, and the second connection 122 of the transistor 120 is electrically connected to another transistor (not shown). Wherein the number of further transistors may be at least one. In some embodiments, the control end 123 of the transistor 120 may be electrically connected to other circuits, devices or other input/output pads inside the chip 10, and the second connection end 122 of the transistor 120 may be electrically connected to other circuits, devices or other input/output pads inside the chip 10, but the disclosure is not limited thereto. Further, the number of the transistors 120 may be at least one. For brevity, a single transistor 120 is used as an example, but the number is not limited thereto. In some embodiments, the transistor 120 may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the first connection terminal 121 is a drain terminal, the second connection terminal 122 is a source terminal, and the control terminal 123 is a gate terminal, but the disclosure is not limited thereto. The transistor 120 may also be a bipolar transistor (BJT) or Insulated Gate Bipolar Transistor (IGBT), etc. Since it is known to those skilled in the art how to replace the connection terminals between the mosfet and the bipolar transistor, the igbt, the descriptions thereof will be omitted.
The conductive wire 130 is electrically connected to the first connection terminal 121 of the transistor 120. The conductive wire 130 is used to provide a series resistance at the first connection terminal 121 of the transistor 120, so as to increase the resistance of the first connection terminal 121 of the transistor 120. In some embodiments, the conductive wire 130 is made of a positive temperature coefficient conductive material. In other words, the higher the temperature, the greater the series resistance provided by the conductive wire 130.
When a surge current is input through the input/output pad 110 and flows to the first connection terminal 121 of the transistor 120 through the conductive connection C1, the surge current flows through the conductive wire 130 through the first connection terminal 121 of the transistor 120. Since the surge current is a large current, the temperature of the conductive wire 130 will be raised when the surge current is large, and the resistance of the string resistor provided by the conductive wire 130 will be raised accordingly. In this way, the conductive wire 130 can force the surge current to flow to the drain terminal of another transistor with a relatively low resistance value, so as to achieve the effect of current dispersion, and further avoid the damage of the transistor 120 caused by the penetration of the large current concentrated at the first connection terminal 121 of the transistor 120.
In some embodiments, the first connection terminal 121 of the transistor 120 may be electrically connected to only the conductive wire 130 and the conductive wire C1. Therefore, the resistance at the first connection 121 of the transistor 120 is mainly determined by the conductive wire 130 and the conductive wire C1.
In some embodiments, the chip 10 includes a layout substrate (not shown), and the input/output port circuit 100 may be disposed on the layout substrate through an integrated circuit process. In the layout of the chip 10, since the length of the conductive line C1 is substantially fixed and the resistance provided by the conductive line C1 is also fixed, the resistance at the first connection 121 of the transistor 120 is mainly changed by the series resistance provided by the conductive wire 130. For example, the wire length, wire width, wire spacing, number of contact and/or via holes (via) connected to the conductive wire 130, or any combination of the foregoing, is varied. In some embodiments, the conductive traces 130 may be routed in any pattern (e.g., but not limited to zigzagged, L-shaped, M-shaped, C-shaped, etc.) in the layout of the chip 10. In order to meet the current density (EM) and surge (500V), the series resistance provided by the conductive wire 130 is at least several tens of ohms.
Fig. 3 and 4 are schematic top views of an embodiment of a partial layout of an input/output port circuit, respectively. The layout of the second connection 122 of the transistor 120 is not shown. Referring to fig. 3 and 4, in some embodiments, the conductive wire 130 may include a first connection segment 131, a wire segment 132, and a second connection segment 133 connected in sequence in the layout. The first connection segment 131 and the second connection segment 133 of the conductive wire 130 can be electrically connected to the first connection end 121 of the transistor 120 through the contact window and/or the via hole, respectively, and the first connection segment 131 is not directly contacted with the second connection segment 133.
In some embodiments, the conductive wire C1 and the conductive wire 130 can be formed through a single metal layer, and the conductive wire C1 and the conductive wire 130 can be formed on the same metal layer or different metal layers. In one example, as shown in fig. 3 and 4, when the conductive wire C1 and the conductive wire 130 are located in different Metal layers, the conductive wire C1 may be located in, for example, metal1 Metal layer and electrically connected to the first connection terminal 121 of the transistor 120 through the contact window, the conductive wire 130 may be located in, for example, metal 2 Metal layer, and the first connection section 131 and the second connection section 133 of the conductive wire 130 may be electrically connected to the conductive wire 130 through the via holes, respectively, so as to be electrically connected to the first connection terminal 121 of the transistor 120 through the contact window on the conductive wire 130. In another example, when the conductive wire C1 and the conductive wire 130 are disposed on the same Metal layer, the conductive wire C1 may be disposed on, for example, the Metal1 Metal layer and electrically connected to the first connection terminal 121 of the transistor 120 through the contact window, the conductive wire 130 is also disposed on the Metal1 Metal layer, and the first connection section 131 and the second connection section 133 of the conductive wire 130 may overlap or contact the conductive wire C1 so as to be electrically connected to the first connection terminal 121 of the transistor 120 through the contact window on the conductive wire 130. Here, the wire segment 132 of the conductive wire 130 does not overlap or contact the conductive wire C1.
In some embodiments, the conductive wiring C1 and the conductive wire 130 can be any combination of multiple layers of metals in the layout. For example, the conductive line C1 is a combination of Metal1 and Metal 2, and the conductive wire 130 is a single Metal 3 or a combination of Metal 2 and Metal 3. If the conductive wire C1 and the wire segment 132 of the conductive wire 130 are located on the same metal layer, the wire segment 132 does not overlap or contact the conductive wire C1. Conversely, if the conductive wire C1 and the wire segment 132 of the conductive wire 130 are located in different metal layers, the wire segment 132 of the conductive wire 130 may or may not overlap the conductive wire C1.
In some embodiments, the wire segments 132 of the conductive wire 130 may at least partially overlap the layout of the transistor 120 in the layout.
In some embodiments, the wire segment 132 of the conductive wire 130 may at least partially overlap the layout of the first connection terminal 121 of the transistor 120. In some embodiments, the winding segments 132 of the conductive winding 130 may be configured to correspond to the layout of the first connection terminal 121 of the transistor 120, such that the winding segments 132 of the conductive winding 130 may fall into the layout of the first connection terminal 121 of the transistor 120, as shown in fig. 3 and 4, but the present invention is not limited thereto. In still other embodiments, the wire segment 132 of the conductive wire 130 may be wire-wound corresponding to the layout of the first connection 121 of the transistor 120, and the wire segment 132 of the conductive wire 130 may extend beyond the layout of the first connection 121 of the transistor 120 but not overlap the layout of the control terminal 123 of the transistor 120, as shown in fig. 5.
In some embodiments, the wire segment 132 of the conductive wire 130 may at least partially overlap the layout of the control terminal 123 of the transistor 120 in addition to at least partially overlapping the layout of the first connection terminal 121 of the transistor 120. In some embodiments, the winding segment 132 of the conductive winding 130 may be configured to correspond to the layout of the first connection terminal 121 and the control terminal 123 of the transistor 120, such that the winding segment 132 of the conductive winding 130 is disposed in the layout of the first connection terminal 121 and the control terminal 123 of the transistor 120, as shown in fig. 3 and 4. In one embodiment, the winding segment 132 of the conductive winding 130 may only partially overlap the layout of the control terminal 123 of the transistor 120, as shown in fig. 6. In another embodiment, the layout of the control end 123 of the transistor 120 is completely covered by the winding segment 132 of the conductive winding 130, as shown in fig. 7, but the present invention is not limited thereto.
In some embodiments, the wire segment 132 of the conductive wire 130 does not overlap the layout of the second connection terminal 122 of the transistor 120, as shown in fig. 5-7.
Please refer to fig. 3. In some embodiments, in the layout, the first connection segment 131 of the conductive wire 130 may be opposite to the second connection segment 133. In addition, the winding section 132 of the conductive winding 130 includes a first winding portion 1321, a second winding portion 1322, a third winding portion 1323, a fourth winding portion 1324 and a fifth winding portion 1325, which are sequentially connected. The winding section 132 of the conductive winding 130 is connected to the first connection section 131 by a first winding portion 1321, and is connected to the second connection section 133 by a fifth winding portion 1325. The second winding portion 1322 is opposite to the first connecting section 131. The fourth winding portion 1324 is opposite to the second connecting section 133. The first winding portion 1321 and the fifth winding portion 1325 are respectively opposite to the third winding portion 1323. Here, the winding section 132 of the conductive winding 130 may have a substantially C-shape. In addition, the conductive wire 130 may substantially fall in the layout of the first connection terminal 121 and the control terminal 123 of the transistor 120.
For example, assume that conductive wire 130 is located in Metal 2 and conductive wire C1 is located in Metal 1. In some embodiments, as shown in fig. 3, the conductive line C1 may be configured corresponding to the center of the layout of the first connection terminal 121 of the transistor 120, and four contact windows may be disposed on the conductive line C1, for example, so that the conductive line C1 may be electrically connected to the first connection terminal 121 of the transistor 120. The extending direction of the conductive wiring C1 is the Y axis on the layout substrate. The first connection segment 131 and the second connection segment 133 of the conductive wire 130 may be configured to correspond to a portion of the conductive wire C1 overlapping the first connection terminal 121 of the transistor 120, respectively. The extending direction of the first connecting section 131 and the second connecting section 133 of the conductive wire 130 is the Y axis on the layout substrate. Four vias may be disposed on the first connection segment 131 of the conductive wire 130, for example, and four contact windows may be disposed on the conductive wire C1 corresponding to the four vias, so that the first connection segment 131 of the conductive wire 130 may be electrically connected to the first connection terminal 121 of the transistor 120. The second connecting section 133 of the conductive wire 130 may be provided with, for example, four vias. The wire segments 132 of the conductive wire 130 are configured to correspond substantially to the outermost periphery of the layout of the first connection terminals 121 of the transistor 120. The extending directions of the second winding portion 1322 and the fourth winding portion 1324 of the winding segment 132 are the Y axis on the layout substrate, the extending directions of the first winding portion 1321, the third winding portion 1323 and the fifth winding portion 1325 are the X axis on the layout substrate, and the first winding portion 1321 and the fifth winding portion 1325 are located on the same extending line. In addition, the second winding portion 1322 and the fourth winding portion 1324 may partially overlap the layout of the control terminal 123 of the transistor 120. The present application is not limited thereto. In other embodiments, the extension lines of the first winding portion 1321 and the fifth winding portion 1325 may be used as mirror rays to mirror the winding sections 132 of the conductive winding 130, compared to the previous embodiments. In addition, the layout of the conductive wire C1, the first winding portion 1321, the second winding portion 1322, the third winding portion 1323, the fourth winding portion 1324 and the fifth winding portion 1325 of the conductive wire 130 may be respectively rectangular, S-shaped bent or any irregular shape.
Please refer to fig. 4. In some embodiments, in the layout, the third winding portion 1323 may include a first sub-winding A1, a second sub-winding A2, a third sub-winding A3, a fourth sub-winding A4, and a fifth sub-winding A5 that are sequentially connected. The third winding portion 1323 is connected to the second winding portion 1322 by a first sub-winding A1, and is connected to the fourth winding portion 1324 by a fifth sub-winding A5. The first sub-winding A1 is opposite to the first winding part 1321. The fifth sub-winding A5 is opposite to the fifth winding part 1325. The second sub-winding A2 is opposite to the second winding part 1322. The fourth sub-winding A4 is opposite to the fourth winding part 1324. Here, the third winding portion 1323 of the winding section 132 may have a substantially Ω -shape. In addition, the conductive wire 130 may substantially fall in the layout of the first connection terminal 121 and the control terminal 123 of the transistor 120.
For example, assume that conductive wire 130 is located in Metal 2 and conductive wire C1 is located in Metal 1. In some embodiments, as shown in fig. 4, the conductive line C1 may be configured corresponding to the center of the layout of the first connection terminal 121 of the transistor 120, and four contact windows may be disposed on the conductive line C1, for example, so that the conductive line C1 may be electrically connected to the first connection terminal 121 of the transistor 120. The extending direction of the conductive wiring C1 is the Y axis on the layout substrate. The first connection segment 131 and the second connection segment 133 of the conductive wire 130 may be configured to correspond to a portion of the conductive wire C1 overlapping the first connection terminal 121 of the transistor 120, respectively. The extending direction of the first connecting section 131 and the second connecting section 133 of the conductive wire 130 is the Y axis on the layout substrate. For example, two vias may be disposed on the first connection segment 131 of the conductive wire 130, and two contact windows may be disposed on the conductive wire C1 corresponding to the two vias, so that the first connection segment 131 of the conductive wire 130 may be electrically connected to the first connection terminal 121 of the transistor 120. The second connection section 133 of the conductive wire 130 may be provided with, for example, two vias. In the winding section 132 of the conductive winding 130, the Ω -shaped opening of the third winding portion 1323 may face upward, and the first winding portion 1321, the second winding portion 1322, the fourth winding portion 1324 and the fifth winding portion 1325 of the winding section 132 are respectively configured corresponding to the outermost periphery of the layout of the first connection terminal 121 of the transistor 120. The extending directions of the second winding portion 1322 and the fourth winding portion 1324 of the winding segment 132 and the second sub-winding A2 and the fourth sub-winding A4 of the third winding portion 1323 are Y axes on the layout substrate, and the extending directions of the first winding portion 1321, the third winding portion 1323 and the fifth winding portion 1325 of the winding segment 132 and the first sub-winding A1, the third sub-winding A3 and the fifth sub-winding A5 of the third winding portion 1323 are X axes on the layout substrate. The first winding portion 1321 and the fifth winding portion 1325 of the winding segment 132 are located on the same extension line, the first sub-winding A1 and the fifth sub-winding A5 of the third winding portion 1323 are located on the same extension line, and the third winding portion 1323 of the third winding portion 1323 is not located on the same extension line as the first sub-winding A1 or the fifth sub-winding A5. In addition, the second winding portion 1322 and the fourth winding portion 1324 of the winding segment 132 may partially overlap the layout of the control terminal 123 of the transistor 120. The present application is not limited thereto. In other embodiments, the third winding portion 1323 may be arranged in a mirrored manner by using the extension line of the first sub-winding A1 and the fifth sub-winding A5 of the third winding portion 1323 as a mirror line, compared to the previous embodiments. In other words, the omega-shaped opening of the third winding portion 1323 may be downward at this time. In still other embodiments, the extension lines of the first winding portion 1321 and the fifth winding portion 1325 of the winding section 132 may be used as mirror rays to mirror the winding section 132 of the conductive winding 130, compared to the previous embodiments.
In summary, the input/output port circuit and the chip thereof according to the embodiments of the present invention provide an additional series resistance through the conductive wire electrically connected to the first connection terminal of the transistor, so that when a surge current is input through the input/output pad, the temperature of the conductive wire increases and the resistance of the provided series resistance also increases accordingly, thereby forcing the surge current to flow to another transistor with a relatively low resistance. Therefore, the effect of current dispersion can be achieved, and the damage of the transistor caused by the penetration of the transistor due to the concentration of large current on a single transistor is avoided.
Although the present disclosure has been described with reference to the preferred embodiments, it should be understood that the invention is not limited thereto, but rather, it should be understood that various changes and modifications can be made by one skilled in the art without departing from the spirit of the disclosure.
Symbol description
10 chip
100 input/output port circuit
110 input/output pad
120 transistor(s)
121 first connecting end
122 second connection end
123 control end
130 conductive winding
131 first connecting section
132, winding section
1321 first winding part
1322 a second winding part
1323 third winding part
1324 fourth winding part
1325 fifth winding part
133 second connecting section
A1 first sub-winding
A2 second sub-winding
A3 third sub-winding
A4 fourth sub-winding
A5 fifth sub-winding
C1 conductive connection

Claims (10)

1. An input/output port circuit comprising:
an input/output pad;
the transistor is provided with a first connecting end and a second connecting end, wherein the first connecting end is electrically connected to the input/output pad through a conductive wiring, and the second connecting end is electrically connected to the other transistor; a kind of electronic device with high-pressure air-conditioning system
The conductive winding is electrically connected to the first connection end of the transistor and is used for providing series resistance so as to force the surge current to flow to the other transistor when the surge current is input through the input/output pad.
2. The i/o port circuit of claim 1, wherein the first connection terminal of the transistor is electrically connected only to the i/o pad and the conductive trace.
3. The input/output port circuit of claim 1, wherein in layout, the conductive wiring is located in a different metal layer than at least a portion of the conductive routing.
4. The input/output port circuit according to claim 1, wherein in the layout, the conductive wire comprises a first connection section, a wire section and a second connection section connected in sequence, the first connection section and the second connection section are electrically connected to the first connection terminal of the transistor respectively, and the first connection section does not contact the second connection section.
5. The input/output port circuit according to claim 4, wherein the conductive wire is in the same metal layer as the conductive wire, and the wire segment of the conductive wire does not overlap the conductive wire.
6. The input/output port circuit of claim 4, wherein the wire segment at least partially overlaps the layout of the transistor.
7. The input/output port circuit of claim 6, wherein the wire segment at least partially overlaps the layout of the control terminal of the transistor.
8. The I/O port circuit of claim 4, wherein the wire segment does not overlap the layout of the second connection terminal of the transistor.
9. The input/output port circuit according to claim 4, wherein the first connection section is opposite to and parallel to the second connection section, the winding section comprises a first winding portion, a second winding portion, a third winding portion, a fourth winding portion and a fifth winding portion connected in sequence, wherein the winding section is connected to the first connection section by the first winding portion and connected to the second connection section by the fifth winding portion, the second winding portion is opposite to the first connection section, the fourth winding portion is opposite to the second connection section, and the first winding portion and the fifth winding portion are respectively opposite to the third winding portion.
10. The input/output port circuit according to claim 9, wherein the third winding portion comprises a first sub-winding, a second sub-winding, a third sub-winding, a fourth sub-winding and a fifth sub-winding connected in sequence, the third winding portion is connected to the second winding portion by the first sub-winding and to the fourth winding portion by the fifth sub-winding, the first sub-winding is opposite to the first winding portion, the fifth sub-winding is opposite to the fifth winding, and the second sub-winding is opposite to the fourth sub-winding.
CN202210825318.8A 2022-07-13 2022-07-13 Input/output port circuit and chip thereof Pending CN117439584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210825318.8A CN117439584A (en) 2022-07-13 2022-07-13 Input/output port circuit and chip thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210825318.8A CN117439584A (en) 2022-07-13 2022-07-13 Input/output port circuit and chip thereof

Publications (1)

Publication Number Publication Date
CN117439584A true CN117439584A (en) 2024-01-23

Family

ID=89546730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210825318.8A Pending CN117439584A (en) 2022-07-13 2022-07-13 Input/output port circuit and chip thereof

Country Status (1)

Country Link
CN (1) CN117439584A (en)

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