CN103094277A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN103094277A CN103094277A CN2012104319746A CN201210431974A CN103094277A CN 103094277 A CN103094277 A CN 103094277A CN 2012104319746 A CN2012104319746 A CN 2012104319746A CN 201210431974 A CN201210431974 A CN 201210431974A CN 103094277 A CN103094277 A CN 103094277A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in Fig. 1 ) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.
Description
The cross reference of related application
With the disclosure (comprising specification, accompanying drawing and summary) of the Japanese patent application No.2011-241938 that submitted on November 4th, 2011 by with reference to all incorporating in this application.
Technical field
The present invention relates to semiconductor device, this semiconductor device comprises be used to the protection component of the destruction that prevents from being caused by overcurrent or overvoltage (such as Electrostatic Discharge) and steady resistance (ballast resistance).
Background technology
Can avoid overcurrent and superpotential protection component arranges steady resistance for the protection internal circuit.Be known that steady resistance has by preventing in protection component that the electric current that flows concentrates in certain part and the uniformity that improves electric current improves the effect of the discharge performance of protection component.
On the other hand, Japanese uncensored Patent Application Publication No.2002-76279 discloses the technology that the following describes.At first, insulation layer is formed in the silicon layer of SOI substrate, and the semiconductor region of island is formed in insulation layer.Semiconductor region has crooked pattern in plane graph.An end of semiconductor region is p
+District and another end are n
+The district.Other zone of semiconductor region is the n district.In other words, semiconductor region is not only as diode, and by this n district coming as resistance.Couple in parallel with a plurality of semiconductor regions of matrix arrangement and semiconductor region.
Summary of the invention
When the overcurrent that is caused by ESD flows in protection component, if a certain amount of or more current flowing, breakdown protection element.This a certain amount of electric current is called as current capacity.Determine current capacity for each in protection component and steady resistance.Than the current capacity of protection component hour, steady resistance may be more Zao more destroyed than protection component when the current capacity of steady resistance.Therefore, preferably the current capacity of steady resistance is set to larger than the current capacity of protection component.The present inventor's research increases current capacity by the width that increases steady resistance.Yet in this case, the area of steady resistance increases.According to this background, inventor's thinking need to increase allowable current in the situation that do not increase the width of steady resistance.
According to an aspect of the present invention, provide a kind of semiconductor device, it comprises: protection component; And the steady resistance that couples with protection component; and be included in comprising at least one resistance in a plurality of resistance in steady resistance upwardly extending a plurality of the first resistive elements of first party and the second resistive element that electric current flows in protection component; this second resistive element and the first resistive element couple in parallel and extend upward in first party, and the second resistive element and the first resistive element extend on the same straight line.
Of the present invention aspect this in, at least one resistance that is included in the resistance in steady resistance has the first resistive element and the second resistive element.The first resistive element and the second resistive element couple with being connected in parallel to each other.Therefore, can increase the current capacity of steady resistance.The first resistive element and the second resistive element extend upward in the first party that electric current flows in protection component.The second resistive element and the first resistive element are located on the same line, and make the width of steady resistance not increase.Therefore, according to this aspect of the present invention, can increase current capacity in the situation that do not increase the width of steady resistance.
According to this aspect of the present invention, can increase current capacity in the situation that do not increase the width of steady resistance.
Description of drawings
Fig. 1 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the first embodiment;
Fig. 2 is the sectional view of the line A-A' intercepting in Fig. 1;
Fig. 3 is the circuit diagram of the semiconductor device shown in Fig. 1;
Fig. 4 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the second embodiment;
Fig. 5 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 3rd embodiment;
Fig. 6 is the sectional view of the line A-A' intercepting in Fig. 5;
Fig. 7 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 4th embodiment;
Fig. 8 is the sectional view of the line A-A' intercepting in Fig. 7;
Fig. 9 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 5th embodiment;
Figure 10 is the sectional view of the line A-A' intercepting in Fig. 9;
Figure 11 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 6th embodiment;
Figure 12 is the sectional view of the line A-A' intercepting in Figure 11;
Figure 13 is the sectional view of the line B-B' intercepting in Figure 11;
Figure 14 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 7th embodiment;
Figure 15 is the plane graph that illustrates according to the configuration that is included in the steady resistance in semiconductor device of the 8th embodiment;
Figure 16 is the sectional view of the line A-A' intercepting in Figure 15;
Figure 17 is the sectional view of the line B-B' intercepting in Figure 15;
Figure 18 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 9th embodiment;
Figure 19 is the sectional view of the line A-A' intercepting in Figure 18;
Figure 20 is the circuit diagram of the semiconductor device shown in Figure 18;
Figure 21 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the tenth embodiment;
Figure 22 is the sectional view of the line A-A' intercepting in Figure 21;
Figure 23 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 11 embodiment;
Figure 24 is the sectional view of the line A-A' intercepting in Figure 23;
Figure 25 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 12 embodiment;
Figure 26 is the sectional view of the line A-A' intercepting in Figure 25;
Figure 27 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 13 embodiment; And
Figure 28 is the sectional view of the line C-C' intercepting in Figure 27.
Embodiment
Hereinafter, embodiments of the invention will be described with reference to the drawings.In institute's drawings attached, give identical assembly and will suitably the descriptions thereof are omitted with identical Reference numeral.
The first embodiment
Fig. 1 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the first embodiment.Fig. 2 is the sectional view of the line A-A' intercepting in Fig. 1.Fig. 3 is the circuit diagram according to the semiconductor device of the present embodiment.Semiconductor device comprises protection component 100 and steady resistance 200.At least one resistance 210 that is included in steady resistance 200 has the first resistance 212 and the second resistance 214.The upper extension of first direction (directions X in Fig. 1) that the first resistance 212 flows in protection component 100 at electric current.The second resistive element 214 and the first resistive element 212 couple in parallel and extend upward in first party.The second resistive element 214 and the first resistive element 212 are located on the same line.Hereinafter, will describe the present embodiment in detail.
As shown in the circuit diagram of Fig. 3, the input side of protection component 100 is couple to wiring 12 by the first wiring 14, and outlet side is couple to wiring 22 by the second wiring 24.Wiring 12 is wirings that the first terminal 10 and internal circuit 400 are coupled, and 22 is wirings that the second terminal 20 and internal circuit 400 are coupled and connect up.That is to say, protection component 100 is that protection internal circuit 400 is avoided overcurrent and superpotential element.Steady resistance 200 is arranged on protection component 100 and connects up between 12.
As depicted in figs. 1 and 2, protection component 100 is the bipolar transistors that comprise collector area 102, base region 104 and emitter region 106.These zones are formed on substrate 1(such as, silicon substrate for example) in.The element (for example, MOS transistor) that forms the internal circuit 400 shown in Fig. 3 also is formed in substrate 1.Collector area 102 has the first conduction type (for example, N-shaped) and is formed in the first trap 112 of the first conduction type.Base region 104 has the second conduction type (for example, p-type) and is formed in the second trap 114 of the second conduction type.The second trap 114 is formed in the first trap 112.Emitter region 106 has the first conduction type and is formed in the second trap 114.First direction (directions X) be along its arrange collector area 102, base region 104 and emitter region 106 and in plane graph electric current in protection component 100 along its direction that flows.In plane graph, the width of collector area 102, base region 104 and emitter region 106 (width on the Y-direction in Fig. 1) is identical.
The collector area 102 of protection component 100 is couple to the first terminal 10 by steady resistance 200, and emitter region 106 and the second terminal 20 couple.The first terminal 10 is power pads of input power current potential for example, and the second terminal 20 is ground pads of input grounding current potential for example.Yet the first terminal 10 and the second terminal 20 are not limited to this.
As shown in Figure 2, the first resistance 212 and the second resistance 214 are positioned on same layer (specifically, the element Disengagement zone 2 that is formed by insulating barrier), and are formed by polysilicon film.As depicted in figs. 1 and 2, the first resistance 212 has identical flat shape and identical thickness, and the second resistance 214 has identical flat shape and identical thickness.In the present embodiment, the first resistance 212 and the second resistance 214 have identical flat shape and identical thickness.In the present embodiment, the flat shape of the first resistance 212 and the second resistance 214 is rectangles.
As shown in Figure 1, when watching on the Y-direction in Fig. 1 (direction vertical with first direction), the first resistance 212 and the second resistance 214 are arranged in the part that collector area 102(electric current flows at protection component 100).The first resistance 212 and the second resistance 214 that are included in same resistance 210 are couple to collector area 102 by same wiring 30.Wiring 30 extends parallel to each other along first direction, each 30 resistance 210 that are couple to separately that connect up.In plane graph, wiring the 30, first resistive element 212 and the second resistive element 214 extend on the same straight line.
The first resistance 212 and the second resistance 214 are couple to the first terminal 10 by the first wiring 14.In the present embodiment, in plane graph, the first wiring 14 was bifurcated into two be couple to the first resistance 212 and the second resistance 214 by contact 44 before.One after fork is routed in the upper extension on the first resistance 212 of the direction vertical with the first resistance 212 (Y-direction in Fig. 1), and another after fork is routed on the direction vertical with the second resistance 214 and extends on the second resistance 214.
As shown in Figure 2, the first wiring 14 wiring layers that are arranged in than the first resistance 212 and second resistance 214 high one decks, and the second wiring 24 and 30 wiring layers that are arranged in than first wiring 14 high one decks that connect up.The first wiring 14 is couple to an end of each the first resistance 212 and each the second resistance 214 by contact 44.Wiring 30 by through hole 52, be formed on the first identical layer of wiring 14 in island conductive pattern and contact 42 another end of being couple to each first resistance 212 and each the second resistance 214.In the present embodiment, the first resistance 212 and the second resistance 214 is arranged in the same side (right side of Fig. 1 and Fig. 2) of all first resistance 212 and the second resistance 214 with the first wiring 14 ends that couple.The first resistance 212 and the second resistance 214 be arranged in the same side (left side of Fig. 1 and Fig. 2) of all first resistance 212 and the second resistance 214 with wiring 30 ends that couple.
Wiring 30 by through hole 56, be formed on the first identical layer of wiring 14 in island conductive pattern and contact 46 be couple to collector area 102.The second wiring 24 is couple to base region 104 and emitter region 106 by wiring 26 and the contact in through hole, identical with the first wiring layer 14 layer.
As shown in Figure 1, a plurality of wirings 26 are set.For example, the quantity of wiring 26 is identical with the quantity of wiring 30.In example shown in Figure 1, wiring 26 and wiring 30 are extended on the same straight line in plane graph.The layout of wiring 26 is not limited to this example.The second wiring width (width on the Y-direction in Fig. 1) of 24 is larger, and the second wiring 24 in plane graph with all wiring 26 crossovers.Yet, second the wiring 24 with the wiring 26 crossovers part in have the broach shape.
Next, will the effect of the present embodiment be described.One of the factor of determining the current capacity of protection component 100 is the width (in the example in Fig. 1, the width of collector area 102, base region 104 and emitter region 106) of the part of current flowing in protection component 110.Therefore, preferably increase the width of the part of current flowing in protection component 100 in order to increase the current capacity of protection component 100.On the other hand, require semiconductor device less.Therefore, determine the width of the part of current flowing in protection component 100 by the necessary ESD tolerance limit of semiconductor device.Therefore, preferably reduce the width of steady resistance 200 on the direction (Y-direction in Fig. 1) of the perpendicular direction that flows with electric current in protection component 100, in order to do not increase the size of the protective circuit that comprises protection component 100 and steady resistance 200.
On the other hand, preferably increase the quantity that is included in the resistance in steady resistance 200, in order to increase the current capacity of steady resistance 200.
In the present embodiment, at least one resistance 210 comprises the first resistance 212 and the second resistance 214.The first resistance 212 and the second resistance 214 couple with being connected in parallel to each other.Therefore, can increase the current capacity of steady resistance 200.
The upper extension of first direction (directions X in Fig. 1) that the first resistance 212 and the second resistance 214 flow in protection component 100 at electric current.The second resistance 214 and the first resistance 212 are located on the same line, and make the width of steady resistance 200 be no more than the width of steady resistance 200 on the direction (Y-direction in Fig. 1) of the perpendicular direction that flows with electric current in protection component 100.
Therefore, according to the present embodiment, can satisfy simultaneously the requirement of two conflicts.
Especially, in the present embodiment, all resistance 210 comprise the first resistance 212 and the second resistance 214.Therefore, can prevent fully the width increase of protective circuit.Therefore, the width on the Y-direction of steady resistance 200 in Fig. 1 can be less than the width of protection component 100.
In the present embodiment, the flat shape of the first resistance 212 is identical, and the flat shape of the second resistance 214 is identical.Therefore, can prevent the resistance change of resistance 210.
In the present embodiment, the flat shape of the first resistance 212 and the second resistance 214 is identical.Therefore, can prevent that electric current from concentrating in one of the first resistance 212 and second resistance 214.
In the present embodiment, the first resistance 212 and the second resistance 214 are formed in same layer.Therefore, can prevent the varied in thickness of the first resistance 212 and the second resistance 214.Therefore, can prevent the resistance change of the first resistance 212 and the second resistance 214.
In the present embodiment, about 200 the current path from the first terminal 10 to steady resistance, exist from the single current path of the first terminal 10 to first wirings 14.This current path is bifurcated into two wirings of the first resistance 212 and the second resistance 214.Thus, the situation that is bifurcated into two with routing path before the first wiring 14 is compared, and can prevent from the cloth line resistance of the first terminal 10 to first resistance 212 and difference occurs from the cloth line resistance of the first terminal 10 to second resistance 214.
The second embodiment
Fig. 4 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the second embodiment.Except the flat shape and layout thereof of the first resistance 212 and the second resistance 214, be identical according to the steady resistance 200 of the present embodiment with steady resistance 200 according to the first embodiment.
In the present embodiment, in the first resistance 212, the part that contacts with contact 42 is thicker than other parts with the part that contacts with contact 44 (that is to say two ends).A plurality of the second resistance 212 are arranged such that the end forms zigzag pattern (zigzag pattern).Specifically, on the directions X in Fig. 4, an end of the first resistance 212 is positioned at the end part (that is, thinner part) in addition of first resistance 212 adjacent with this first resistance 212 and locates.On Y-direction in Fig. 4, the end adjacent one another are of the first resistance 212 is crossover partly each other.
The second resistance 214 has the layout identical with the first resistance 212.
Same by the present embodiment, can obtain the effect identical with the first embodiment.On Y-direction in Fig. 4, the first resistance 212 adjacent one another are is arranged such that its end crossover partly each other, and the second resistance 214 adjacent one another are is arranged such that its end crossover partly each other.Thus, can reduce to arrange width on Y-direction in the required Fig. 4 of the first resistance 212 and the second resistance 214.Therefore, can reduce the area of steady resistance 200.
The 3rd embodiment
Fig. 5 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 3rd embodiment.Fig. 6 is the sectional view of the line A-A' intercepting in Fig. 5.Except resistance 210 comprises the 3rd resistance 216, according to the steady resistance 200 of the present embodiment with identical according to the steady resistance 200 of the first embodiment or the second embodiment.Fig. 5 shows and the similar situation of the situation of the first embodiment.
Couple in parallel the 3rd resistance 216 with the first resistance 212 and the second resistance 214.Form the 3rd resistance 216 in the layer identical with the second resistance 214 with the first resistance 212, and couple in parallel the 3rd resistance 216 with the first resistance 212 and the second resistance 214.The flat shape of the 3rd resistance 216 and thickness are identical with the second resistance 214 with the first resistance 212.In the present embodiment, by the first resistance 212, the second resistance 214 and the 3rd resistance 216 are coupled to form a resistance 210 with being connected in parallel to each other.Although due to the resistance value that the 3rd resistance 216 is set has reduced resistance 210, the reducing of resistance value that can be when needed comes compensating resistance 210 by the length that increases the first resistance 212, the second resistance 214 and the 3rd resistance 216.
The quantity that is included in the resistance in a resistance 210 can further be increased when needed.
Same by the present embodiment, can obtain the effect identical with the first embodiment or the second embodiment.The quantity that is included in the resistance in resistance 210 is increased, and makes the current capacity of steady resistance 200 to be increased.
The 4th embodiment
Fig. 7 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 4th embodiment.Fig. 8 is the sectional view of the line A-A' intercepting in Fig. 7.Except the first and second resistance 212 and the 214 and first wiring 14 couple structure and the first and second resistance 212 and 214 with connect up 30 couple structure, according to the steady resistance 200 of the present embodiment with identical according to the steady resistance 200 of in the first to the 3rd embodiment.Fig. 7 and Fig. 8 show and the similar situation of the situation of the first embodiment.
In the present embodiment, the first resistance 212 and the second resistance 214 with first the wiring 14 ends that couple face with each other.Reciprocally facing with 30 ends that couple of connecting up of the first resistance 212 and the second resistance 214.
Do not have the contact 44 and first of contact at first wiring the 14 and first resistance 212 places of coupling 14 and second resistance 214 that connects up to couple between the contact 44 at place.Therefore, the first wiring 14 needn't be bifurcated into two, and connects up 14 in one first of part place's existence that the first wiring 14 and contact 44 couple.Can increase the width of the first wiring 14.In the example shown in Fig. 7 and Fig. 8, only show a contact 44 in first resistance 212 or second resistance 214.Yet, can in first resistance 212 and second resistance 214, a plurality of contacts 44 be set.
Same by the present embodiment, can obtain the effect identical with the first embodiment.Because the first wiring width of 14 can be increased, therefore the cloth line resistance of the first wiring 14 can be reduced.Thus, can prevent that the amount of electric current is inhomogeneous between a plurality of resistance 210.
The 5th embodiment
Fig. 9 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 5th embodiment.Figure 10 is the sectional view of the line A-A' intercepting in Fig. 9.Except the point that the following describes, identical with steady resistance 200 according to the 4th embodiment according to the steady resistance 200 of the present embodiment.
In the present embodiment, form resistance 210 by a resistance element.When watching, the first wiring 14 and resistance 210 are coupled in together contact 44(input contact on first direction (directions X in Fig. 9)) be couple to the center of resistance 210.Resistance 210 and wiring 30 are coupled in together contact 42(the first output contacts and the second output contacts) be couple to respectively two ends of resistance 210.In resistance 210, the part between contact 44 and contact 42 is the first resistance 212, and the part between contact 44 and another contact 42 is the second resistance 214.In other words, can be considered to have following structure according to the resistance 210 of the present embodiment, in this structure, in the resistance 210 of describing in the 4th embodiment, the first resistance 212 and the second resistance 214 end around contact 44 is coupled to each other.
Same by the present embodiment, can obtain the effect identical with the 4th embodiment.Form the first resistance 212 and the second resistance 214 by a resistance element, make on the directions X of resistance 210(in Fig. 9) length can be shorter than the length in the structure of describing in the 4th embodiment.Thus, can reduce the area of protective circuit.
The 6th embodiment
Figure 11 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 6th embodiment.Figure 12 is the sectional view of the line A-A' intercepting in Figure 11.Figure 13 is the sectional view of the line B-B' intercepting in Figure 11.Except the wire structures that the first wiring 14 is coupled with steady resistance 200, according to the semiconductor device of the present embodiment with identical according to the semiconductor device of the 5th embodiment.
In the present embodiment, the first wiring 14 is arranged in the wiring layer (for example, in wiring layer than resistance 210 Senior Three layers) higher than wiring 30.As Figure 11 and shown in Figure 13, the first wiring 14 is couple to a plurality of resistance 210 by the island conductive pattern 38 in layer identical with wiring 30, wiring 60 and a plurality of contact 44 in the through hole of conductive pattern 38 above and belows, wiring layer between wiring 30 and resistance 210.Specifically, with in the part of resistance 210 and wiring 30 crossovers do not arranging through hole and the conductive pattern 38 of the first wiring 14 together with wiring 60 is coupled in plane graph.In the present embodiment, arranging in each part between a plurality of resistance 210 through hole and the conductive pattern 38 of the first wiring 14 together with wiring 60 is coupled in.Wiring 60 is upward extended, and be couple to resistance 210 by contact 44 separately in the direction (Y-direction in Figure 11) vertical with wiring 30.
Same by the present embodiment, can obtain the effect identical with the 5th embodiment.The first wiring 14 is formed on than in wiring 30 high wiring layers, makes the width of the first wiring 14 can be large fully.Therefore, can further reduce the cloth line resistance of the first wiring 14.Thus, can prevent further that the amount of electric current is inhomogeneous between a plurality of resistance 210.
The 7th embodiment
Figure 14 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 7th embodiment.Except 30 the flat shape of connecting up, according to the semiconductor device of the present embodiment with identical according to the semiconductor device of the 6th embodiment.
In the wiring 30 according to the present embodiment, in the face of the part of conductive pattern 38 width on the direction (Y-direction in Figure 14) of the perpendicular directions that extend with wiring 30 narrower than other parts.When watching on the direction (Y-direction in Figure 14) of the perpendicular directions that extend with wiring 30, the part that does not narrow down of wiring 30 and conductive pattern 38 be crossover partly.
Same by the present embodiment, can obtain the effect identical with the first embodiment.In addition, in the face of the width on the Y-direction of part in Figure 14 of conductive pattern 38 is set to narrowlyer than other parts, and 30 the other parts of connecting up do not narrow down, and make 30 the resistance of can preventing from connecting up too large.
The 8th embodiment
Figure 15 is the plane graph that illustrates according to the configuration that is included in the steady resistance 200 in semiconductor device of the 8th embodiment.Figure 16 is the sectional view of the line A-A' intercepting in Figure 15.Figure 17 is the sectional view of the line B-B' intercepting in Figure 15.Except the wire structures that the first wiring 14 is coupled with steady resistance 200, according to the semiconductor device of the present embodiment with identical according to the semiconductor device of the 6th embodiment.
In the present embodiment, wiring 30 and conductive pattern 38 are formed in wiring layer than resistance 210 high one decks.In the first wiring 14 wiring layers that are formed on than wiring layer 30 high one decks.The first wiring 14 is couple to resistance 210 by through hole, conductive pattern 38 and contact 44.In other words, in the present embodiment, there is no the wiring 60 of describing in the 6th embodiment.In plane graph, with the first wiring 14 through holes that couple, conductive pattern 38 and contact 44 and resistance 210 crossovers.Extending on the straight line different from resistance 210 in the part between two contacts 42 of wiring 30 be not in order to hinder conductive pattern 38.Yet wiring 30 is arranged in protection component 100(referring to Fig. 1 in plane graph) and resistance 210 between part (left end portion of Figure 15) extend on the identical straight line of the straight line that extends thereon with resistance 210.
According to the present embodiment, the first wiring 14 is formed on than in wiring 30 high wiring layers, makes the width of the first wiring 14 can be large fully.Therefore, can further reduce the cloth line resistance of the first wiring 14.Thus, can prevent further that the amount of electric current is inhomogeneous between a plurality of resistance 210.In addition, can the first wiring 14 and resistance 210 be coupled in together by the wiring layer of its quantity than the quantity in the 6th embodiment little one.
The 9th embodiment
Figure 18 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 9th embodiment.Figure 19 is the sectional view of the line A-A' intercepting in Figure 18.Figure 20 is the circuit diagram according to the semiconductor device of the present embodiment.Except semiconductor device comprises steady resistance 200 between protection component 100 and the second wiring 24, semiconductor device has and the configuration identical according to the semiconductor device of the first embodiment.Steady resistance 200 can have the structure of describing in the second to the 8th embodiment.Two steady resistances 200 can have the structure that differs from one another.
In the present embodiment, with the second wiring 24 steady resistances that couple 200 by 26 base region 104 and the emitter regions 106 that are couple to protection component 100 that connect up.For each in a plurality of resistance 210 arranges wiring 26.In the present embodiment, the resistance 210 of each in two steady resistances 200, wiring 30 and connect up and 26 extend on identical direction.
Same by the present embodiment, can obtain the effect identical with the first embodiment.In addition, can prevent in the interior mobile electric current of protection component 100 concentrates on a part due to the outlet side of protection component 100.
The tenth embodiment
Figure 21 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the tenth embodiment.Figure 22 is the sectional view of the line A-A' intercepting in Figure 21.Replace protection component 100 except semiconductor device has protection component 120, have and the configuration identical according to the semiconductor device of the first or the 9th embodiment according to the semiconductor device of the present embodiment.Figure 21 and Figure 22 show and the similar situation of the situation of the first embodiment.Steady resistance 200 can have the structure of describing in the second to the 8th embodiment.
Protection component 120 is thyristors, and this thyristor has therein the configuration of arranging successively the second conductive type layer 122, the first conductive type layer 124, the second conductive type layer 126 and the first conductive type layer 128 along first direction (direction opposite with directions X in Figure 21).The second conductive type layer 122 and the first conductive type layer 124 (for example are formed on the first conduction type, N-shaped) in the first trap 112, and the second conductive type layer 126 and the first conductive type layer 128 are formed in the second trap 114 of the second conduction type (for example, p-type).In the present embodiment, the first trap 112 and the second trap 114 are formed in position adjacent one another are.
The second conductive type layer 122 and the first conductive type layer 124 by connect up 30, steady resistance 200 and the first wiring 14 be couple to the first terminal 10, and the second conductive type layer 126 and the first conductive type layer 128 are couple to the second terminal 20 by 26 and second wiring 24 of connecting up.
Same by the present embodiment, can obtain the effect identical with the first embodiment.Due to the protection component 120 of using as thyristor, therefore can increase the current capacity of protection component 120.
The 11 embodiment
Figure 23 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 11 embodiment.Figure 24 is the sectional view of the line A-A' intercepting in Figure 23.Replace protection component 100 except semiconductor device has protection component 130, have and the configuration identical according to the semiconductor device of the first or the 9th embodiment according to the semiconductor device of the present embodiment.Figure 23 and Figure 24 show and the similar situation of the situation of the first embodiment.Steady resistance 200 can have the structure of describing in the second to the 8th embodiment.
Same by the present embodiment, can obtain the effect identical with the first embodiment.Protection component 130 is MOS transistor, makes to form by the technique identical with internal circuit protection component 130.Therefore, do not need extra technique.
The 12 embodiment
Figure 25 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 12 embodiment.Figure 26 is the sectional view of the line A-A' intercepting in Figure 25.Replace protection component 100 except semiconductor device has protection component 140, have and the configuration identical according to the semiconductor device of the first or the 9th embodiment according to the semiconductor device of the present embodiment.Figure 25 and Figure 26 show and the similar situation of the situation of the first embodiment.Steady resistance 200 can have the structure of describing in the second to the 8th embodiment.
Same by the present embodiment, can obtain the effect identical with the first embodiment.In addition, diode can be used as protection component 140.
The 13 embodiment
Figure 27 is the plane graph that illustrates according to the configuration that is included in the protective circuit in semiconductor device of the 13 embodiment.Figure 28 is the sectional view of the line C-C' intercepting in Figure 27.Comprise protection component 130 and protection component 100 according to the protective circuit of the present embodiment.Steady resistance 200 is arranged between protection component 130 and the first wiring 14 and at protection component 100 and first and connects up between 14.In Figure 27 and Figure 28, steady resistance 200 has the structure shown in Fig. 9 and Figure 10.Yet steady resistance 200 can have above-described any structure.
In the example shown in Figure 27 and Figure 28, the second conductive type layer 152 that arranges in the second trap 114 and the first conductive type layer 154 that arranges in the first trap 112 are surrounded protection component 130.The second conductive type layer 152 is positioned at the first conductive type layer 154 inboards.
Specifically, the second trap 114 of the first trap 112 of the first conduction type and the second conduction type is formed in substrate 1.The first trap 112 is formed and surrounds the second trap 114.Protection component 130 and the second conductive type layer 152 are formed in the second trap 114, and the first conductive type layer 154 is formed in the first trap 112.The first conductive type layer 156 be formed in the zone that is surrounded by the second conductive type layer 152 in the part between protection component 130 and the second conductive type layer 152.The first conductive type layer 156 is extended on the direction vertical with the gate electrode 136 of protection component 130.In the protective circuit according to the present embodiment; the first conductive type layer 156 is added to the protective circuit that comprises protection component 130 and guard ring (the second conductive type layer 152 and the first conductive type layer 154), makes protective circuit according to the present embodiment to be envisioned for to have the structure of adding therein by the protection component 100 that comprises the first conductive type layer 156 as collector electrode, forms as the second conductive type layer 152 of base stage with as the bipolar transistor of the first conductive type layer 154 of emitter.
Same by the present embodiment, can obtain the effect identical with the first embodiment.In addition, can form by the guard ring with protection component 130 another protection component 100.
To consider that the first terminal 10 is for opening the situation of drain electrode (open drain) signal terminal.Opening the drain signal terminal is used to suppose apply lead-out terminal, input terminal or input/output terminal greater than or equal to the voltage of supply voltage to it.For example, when being difficult to due to circuit operation esd protection element (such as diode) is set, can use the drain electrode of opening that utilizes nmos pass transistor between signal terminal and power supply voltage terminal.
On the other hand; in the protective circuit of the structure with the present embodiment; when protection component 130 is nmos pass transistor; the second wiring 24 that couples with protection component 130 is couple to earthed voltage; and be couple to supply voltage with the second wiring 24 that protection component 100 couples; even make when positive overvoltage or negative overvoltage are applied to the first terminal 10, also can overvoltage be discharged by protection component 100 or protection component 130.
Although embodiments of the invention have been described with reference to the drawings, these embodiment are example of the present invention and can utilize various configurations except above-mentioned.
Claims (11)
1. semiconductor device comprises:
Protection component; And
The steady resistance that couples with protection component,
Comprise comprising at least one resistance in a plurality of resistance in steady resistance
Upwardly extending a plurality of the first electric devices of first party that flow in protection component at electric current; And
The second resistive element couples in parallel and extends upward in first party with the first resistive element.
2. semiconductor device according to claim 1, wherein the second resistive element and the first resistive element extend on the same straight line.
3. semiconductor device according to claim 1, comprise the first resistive element and the second resistive element comprising each resistance in steady resistance.
4. semiconductor device according to claim 1, wherein protection component comprises that bipolar transistor and first direction are for arranging the direction of collector electrode, base stage and emitter.
5. semiconductor device according to claim 1, wherein protection component comprises that MOS transistor and first direction are the orientation of MOS transistor.
6. semiconductor device according to claim 1, wherein protection component comprises that thyristor and first direction are for arranging the direction that is included in a plurality of diffusion layers in thyristor.
7. semiconductor device according to claim 3, wherein the flat shape of the first resistive element is identical, and the flat shape of the second resistive element is identical.
8. semiconductor device according to claim 7, wherein the flat shape of the first resistive element and the second resistive element is identical.
9. semiconductor device according to claim 3, wherein the first resistive element and the second resistive element are arranged in same layer.
10. semiconductor device according to claim 3, wherein when watching on the direction vertical with first direction, the first resistive element and the second resistive element are arranged in the part of protection component current flowing.
11. semiconductor device according to claim 1,
Wherein form a resistance element by the first resistive element and the second resistive element, wherein semiconductor device comprises
The input contact couples with part beyond the end of resistance element;
The first output contact couples with the first end of resistance element; And
The second output contact couples with the second end of resistance element,
Wherein the part between input contact and first end of resistance element is the first resistive element, and
Wherein the part between input contact and the second end of resistance element is the second resistive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710263382.0A CN107068677B (en) | 2011-11-04 | 2012-11-02 | Semiconductor device with a plurality of semiconductor chips |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011-241938 | 2011-11-04 | ||
| JP2011241938A JP5864216B2 (en) | 2011-11-04 | 2011-11-04 | Semiconductor device |
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| CN201710263382.0A Division CN107068677B (en) | 2011-11-04 | 2012-11-02 | Semiconductor device with a plurality of semiconductor chips |
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| CN103094277A true CN103094277A (en) | 2013-05-08 |
| CN103094277B CN103094277B (en) | 2017-05-03 |
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| CN201210431974.6A Active CN103094277B (en) | 2011-11-04 | 2012-11-02 | Semiconductor device |
| CN201710263382.0A Active CN107068677B (en) | 2011-11-04 | 2012-11-02 | Semiconductor device with a plurality of semiconductor chips |
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| CN201710263382.0A Active CN107068677B (en) | 2011-11-04 | 2012-11-02 | Semiconductor device with a plurality of semiconductor chips |
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| Country | Link |
|---|---|
| US (1) | US8710589B2 (en) |
| EP (1) | EP2590219A1 (en) |
| JP (1) | JP5864216B2 (en) |
| CN (2) | CN103094277B (en) |
| TW (1) | TWI538153B (en) |
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| JP6311316B2 (en) * | 2014-01-08 | 2018-04-18 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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| WO2001050533A1 (en) * | 2000-01-04 | 2001-07-12 | Sarnoff Corporation | Apparatus for current ballasting esd sensitive devices |
| WO2001097358A1 (en) * | 2000-06-15 | 2001-12-20 | Sarnoff Corporation | Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits |
| JP2002110909A (en) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | Semiconductor device |
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| JP2636804B2 (en) * | 1995-05-30 | 1997-07-30 | 日本電気株式会社 | Semiconductor device |
| US6583972B2 (en) | 2000-06-15 | 2003-06-24 | Sarnoff Corporation | Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits |
| JP2002076279A (en) | 2000-08-29 | 2002-03-15 | Unisia Jecs Corp | Semiconductor device |
| JP2004200486A (en) * | 2002-12-19 | 2004-07-15 | Renesas Technology Corp | Semiconductor device |
| JP3810375B2 (en) * | 2003-03-14 | 2006-08-16 | ローム株式会社 | Semiconductor device |
| JP4519097B2 (en) * | 2006-03-29 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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2011
- 2011-11-04 JP JP2011241938A patent/JP5864216B2/en active Active
-
2012
- 2012-10-22 TW TW101138903A patent/TWI538153B/en not_active IP Right Cessation
- 2012-10-30 EP EP12190535.0A patent/EP2590219A1/en not_active Withdrawn
- 2012-11-02 CN CN201210431974.6A patent/CN103094277B/en active Active
- 2012-11-02 CN CN201710263382.0A patent/CN107068677B/en active Active
- 2012-11-03 US US13/668,266 patent/US8710589B2/en active Active
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| WO2001050533A1 (en) * | 2000-01-04 | 2001-07-12 | Sarnoff Corporation | Apparatus for current ballasting esd sensitive devices |
| WO2001097358A1 (en) * | 2000-06-15 | 2001-12-20 | Sarnoff Corporation | Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits |
| JP2002110909A (en) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | Semiconductor device |
| CN1531083A (en) * | 2003-03-12 | 2004-09-22 | �����ɷ� | Semiconductor protective component, semiconductor device and producing method thereof |
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| JP2011155075A (en) * | 2010-01-26 | 2011-08-11 | Tokai Rika Co Ltd | Offset voltage-adjusting structure of bridge circuit, and electronic component equipped therewith |
Also Published As
| Publication number | Publication date |
|---|---|
| US20130153959A1 (en) | 2013-06-20 |
| CN103094277B (en) | 2017-05-03 |
| EP2590219A1 (en) | 2013-05-08 |
| JP2013098453A (en) | 2013-05-20 |
| CN107068677B (en) | 2021-02-02 |
| JP5864216B2 (en) | 2016-02-17 |
| US8710589B2 (en) | 2014-04-29 |
| TWI538153B (en) | 2016-06-11 |
| CN107068677A (en) | 2017-08-18 |
| TW201332081A (en) | 2013-08-01 |
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