CN117435034A - Integrated circuit and layout method thereof - Google Patents

Integrated circuit and layout method thereof Download PDF

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Publication number
CN117435034A
CN117435034A CN202210831580.3A CN202210831580A CN117435034A CN 117435034 A CN117435034 A CN 117435034A CN 202210831580 A CN202210831580 A CN 202210831580A CN 117435034 A CN117435034 A CN 117435034A
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CN
China
Prior art keywords
circuit
power switch
sub
power
resistance value
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Pending
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CN202210831580.3A
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Chinese (zh)
Inventor
林殿国
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202210831580.3A priority Critical patent/CN117435034A/en
Publication of CN117435034A publication Critical patent/CN117435034A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computing Systems (AREA)
  • Architecture (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit and a layout method thereof are provided, wherein the integrated circuit comprises a functional circuit and a first power switch chain. The first power switch chain comprises a first power switch circuit and a second power switch circuit and is coupled between a power supply and the functional circuit. The first power switch chain is used for receiving a first control signal, and the first control signal is used for controlling whether the first power switch circuit and the second power switch circuit are conducted or not. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.

Description

Integrated circuit and layout method thereof
Technical Field
The present disclosure relates to a power switch chain (power switch chain) technology. And more particularly to an integrated circuit including a non-uniform architecture (non-uniform architecture) power switch chain and a method of layout thereof.
Background
With the development of technology and process, the effect of the power consumption of leakage current on the overall power consumption of the circuit is more and more remarkable. In order to reduce leakage current power consumption, for a specific circuit with higher leakage current power consumption in an integrated circuit, the corresponding power switch circuit can be controlled to stop supplying power to the specific circuit during the idle period.
Disclosure of Invention
Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit comprises a functional circuit and a first power switch chain. The first power switch chain comprises a first power switch circuit and a second power switch circuit and is coupled between a power supply and the functional circuit. The first power switch chain is used for receiving a first control signal, and the first control signal is used for controlling whether the first power switch circuit and the second power switch circuit are conducted or not. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.
Some embodiments of the present disclosure relate to a layout method of an integrated circuit. The layout method comprises the following operations: determining the positions of a first power switch circuit and a second power switch circuit in a first power switch chain through a processor; generating layout information of a functional circuit by the processor, wherein the first power switch circuit and the second power switch circuit are coupled between a power supply and the functional circuit; generating a simulation result according to the layout information of the functional circuit by the processor; and determining, by the processor, a first resistance value of the first power switching circuit and a second resistance value of the second power switching circuit according to the simulation result, wherein the first resistance value is different from the second resistance value.
In summary, in the present disclosure, the power switch chain is composed of at least two power switch circuits with different resistance values to form a non-uniform architecture. Thus, both circuit performance and circuit area can be achieved.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:
FIG. 1 is a schematic diagram of a design system shown in accordance with some embodiments of the present disclosure;
FIG. 2 is a functional block diagram of an integrated circuit shown in accordance with some embodiments of the present disclosure;
FIG. 3 is a flow chart illustrating a layout method according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a predetermined power switch chain and a functional circuit according to some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of a simulation result shown in accordance with some embodiments of the present disclosure;
FIG. 6A is a schematic diagram of different subcircuits shown in accordance with some embodiments of the present disclosure;
FIG. 6B is a schematic diagram of different subcircuits shown in accordance with some embodiments of the present disclosure;
FIG. 6C is a schematic diagram of different subcircuits shown in accordance with some embodiments of the present disclosure;
FIG. 7 is a schematic diagram illustrating different regions of the simulation result of FIG. 5, in accordance with some embodiments of the present disclosure;
FIG. 8 is a schematic diagram of an integrated circuit shown in accordance with some embodiments of the present disclosure; and
fig. 9 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure.
Symbol description
100: design system
110: processor and method for controlling the same
120: memory device
130: input/output interface
200. 800, 900: integrated circuit
210: power supply
220. 220A, 220B, 220C, 220D: power switch chain
230: functional circuit
300: layout method
500: simulation results
PS, PS1, PS2, PS3: power supply switching circuit
DX, DY: distance of
C1, C2, C3, C4, C5, C6, C7, C8, C9: sub-circuit
A. B, C, D: circuit area
CS, CS1, CS2: control signal
S310, S320, S330, S340: operation of
Detailed Description
The term "coupled" as used herein may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of a design system 100 shown in accordance with some embodiments of the present disclosure.
For example, in FIG. 1, design system 100 includes a processor 110, a memory 120, and a plurality of input/output interfaces 130. The processor 110 is coupled to the memory 120 and the plurality of input/output interfaces 130.
In some embodiments, the processor 110 may be a central processing unit (central processing unit, CPU), an application specific integrated circuit (application specific integrated circuit, ASIC), or other circuit having similar functionality.
In some embodiments, the memory 120 may be implemented using a non-transitory computer readable recording medium, such as a read-only memory, a flash memory, a floppy disk, a hard disk, an optical disk, a flash disk, a USB flash disk, a magnetic tape, a database readable from a network, or any recording medium having the same functions as will occur to those of ordinary skill in the art to which the present disclosure pertains. The memory 120 may store a computer program to execute the layout program of the integrated circuit or simulate or verify the layout information of the integrated circuit.
In some embodiments, the input/output interface 130 may be a display panel, a keyboard, a mouse, a touch panel, or other devices with similar functions. The input/output interface 130 is used to receive various inputs or instructions.
During the circuit design process, the user may operate the input-output interface 130. The processor 110 may then receive the corresponding instructions and execute the computer program stored in the memory 120 according to the instructions, thereby performing some corresponding operations (e.g., the layout method 300 of fig. 3).
Reference is made to fig. 2. Fig. 2 is a functional block diagram of an integrated circuit 200 shown in accordance with some embodiments of the present disclosure.
For example, in fig. 2, integrated circuit 200 includes a power supply 210, a power switch chain 220, and a functional circuit 230. Generally, the power source 210 may be coupled to the power switch chain 220 through a power mesh (power mesh). The power switch chain 220 may be coupled to the functional circuit 230 via a metal rail (metal rail). That is, the power switch chain 220 is coupled between the power source 210 and the functional circuit 230. In some embodiments, the power switch chain 220, the functional circuit 230, and the metal tracks therebetween may be disposed in a first metal layer, while the power mesh may be disposed in a second metal layer above the first metal layer.
The power switch chain 220 may receive a control signal (e.g., control signal CS of FIG. 8) from a control circuit (not shown), and the control signal may be used to turn on or off a plurality of power switch circuits (e.g., power switch circuits PS1-PS3 of FIG. 8) in the power switch chain 220 to provide or stop providing power from the power source 210 to the various sub-circuits in the functional circuit 230. In detail, when one power switch circuit in the power switch chain 220 is turned on, the power of the power source 210 can be sequentially transmitted to a corresponding sub-circuit in the functional circuit 230 through the power network, the power switch circuit, and the metal rail. When one of the power switch circuits in the power switch chain 220 is turned off, power from the power source 210 cannot be supplied to a corresponding sub-circuit in the functional circuit 230 through the power switch circuit. In some embodiments, the power switch circuit may be turned off during idle periods of the corresponding sub-circuit to stop providing power from the power supply 210 to the corresponding sub-circuit. Accordingly, the leakage current power consumption of the corresponding sub-circuit can be reduced.
Reference is made to fig. 3. Fig. 3 is a flow chart of a layout method 300 shown in accordance with some embodiments of the present disclosure. For example, in fig. 3, the layout method 300 includes operation S310, operation S320, operation S330, and operation S340.
The following paragraphs describe the layout method 300 in conjunction with fig. 4-8. Fig. 4 is a schematic diagram of a preset power switch chain 220A and a functional circuit 230 according to some embodiments of the present disclosure. Fig. 5 is a schematic diagram of simulation results 500 shown in accordance with some embodiments of the present disclosure. Fig. 6A-6C are schematic diagrams of different sub-circuits C4-C9 shown in accordance with some embodiments of the present disclosure. Fig. 7 is a schematic diagram of different regions in a simulation result 500 shown in accordance with some embodiments of the present disclosure. Fig. 8 is a schematic diagram of an integrated circuit 800 shown in accordance with some embodiments of the present disclosure.
In operation S310, the processor 110 determines the positions of the power switch circuits PS in the preset power switch chain 220A. For example, in fig. 4, the preset power switch chain 220A includes a plurality of power switch circuits PS. The power switch circuits PS are sequentially coupled to form a chain. Each power switching circuit PS may comprise one or more switches. In some embodiments, the switches in each power switch circuit PS may be implemented using Multiple Threshold Complementary Metal Oxide Semiconductor (MTCMOS). Based on the center points of the power switch circuits PS, the processor 110 may determine the positions of the power switch circuits PS in advance by determining the distance between the power switch circuits PS in the direction X (e.g., distance DX) and the distance between the power switch circuits PS in the direction Y perpendicular to the direction X (e.g., distance DY).
In operation S320, layout information of the functional circuit 230 is generated by the processor 110. As described above, the processor 110 can determine the positions of the power switch circuits PS in the preset power switch chain 220A. In addition, the processor 110 may determine the type of the power switch circuit PS in advance. For example, the processor 110 may determine that the power switch circuits PS have the smallest resistance but the largest area (e.g., the power switch circuit PS1 in fig. 7). The resistance value of one power switching circuit PS referred to herein refers to the overall equivalent resistance value of the power switching circuit PS. The area of one power switch circuit PS referred to herein refers to the area occupied by the range of layout (layout) of the power switch circuit PS. Then, the processor 110 may determine the portion that may be occupied by all the power switch circuits PS according to the positions of the power switch circuits PS and the preset areas of the power switch circuits PS. The processor 110 may then layout the functional circuit 230 on other portions not occupied by the power switch circuit PS to generate layout information of the functional circuit 230.
Typically, the functional circuit 230 includes one or more sub-circuits. Some of the sub-circuits are standard cell (standard cell) circuits, and some of the sub-circuits are non-standard cell circuits. The standard cell circuit is referred to herein as a flip-flop (flip-flop), combinational logic (combination logic), buffer (buffer), or inverter (inverter), for example. The nonstandard device circuit referred to herein is, for example, a static random access memory (static random access memory, SRAM), an analog block (analog block), or a digital block (digital block).
For ease of understanding, the functional circuit 230 in FIG. 4 shows only sub-circuits C1-C3 as an example, and other sub-circuits in the functional circuit 230 are omitted. The sub-circuits C1-C3 in fig. 4 (sub-circuits C4-C9 in fig. 6A-6C) may be standard cell circuits, respectively.
In operation S330, the simulation result 500 is generated by the processor 110 according to the layout information of the functional circuit 230. For example, the processor 110 may execute the computer program stored in the memory 120 to perform Voltage drop (IR drop) simulation on the layout information generated in operation S320 to generate the simulation result 500. That is, the simulation result 500 is voltage drop information, and the simulation result 500 may reflect the voltage drop condition of each sub-circuit in the functional circuit 230.
Taking fig. 6A as an example, the distance between the sub-circuit C5 and the power PAD is greater than the distance between the sub-circuit C4 and the power PAD. If the other conditions (e.g., element density, operand) of the sub-circuit C4 and the sub-circuit C5 are the same or substantially similar. Since the distance between the sub-circuit C5 and the power PAD is greater than the distance between the sub-circuit C4 and the power PAD, the voltage drop of the sub-circuit C5 will be greater than the voltage drop of the sub-circuit C4.
In addition, taking fig. 6B as an example, if the element density of the sub-circuit C6 is 90%, the element density of the sub-circuit C7 is 40%, and other conditions (e.g., distance from the power PAD, and operation amount) of the sub-circuit C6 and the sub-circuit C7 are the same or substantially similar. Since the element density of the sub-circuit C6 is greater than that of the sub-circuit C7, the voltage drop of the sub-circuit C6 will be greater than that of the sub-circuit C7.
Further, taking FIG. 6C as an example, if the sub-circuit C8 is a computationally intensive circuit, the sub-circuit C9 is a circuit with a longer idle time, and other conditions (e.g., distance from the power PAD PAD, device density) of the sub-circuit C8 and the sub-circuit C9 are the same or substantially similar. Since the operand of the sub-circuit C8 is larger than that of the sub-circuit C9, the voltage drop of the sub-circuit C8 will be larger than that of the sub-circuit C9.
In the above embodiments, the power PAD may be coupled to a power source or a ground to receive a power voltage or a ground voltage. It is specifically described that, although the above paragraphs are exemplified by a single condition affecting the voltage drop of the sub-circuit, in practical applications, the reason for affecting the voltage drop of the sub-circuit may be a combination of conditions.
In operation S340, the processor 110 determines the types of the power switch circuits PS (e.g. determining the resistance and the area of the power switch circuits PS) according to the simulation result 500. For example, in fig. 5 and 7, the simulation result 500 may be divided into a circuit area a, a circuit area B, a circuit area C, and a circuit area D. The circuit area a is an area without standard element circuits. The circuit region B is a region where the standard element circuit is provided and the voltage drop thereof is less than y%. The circuit region C is a region where the standard element circuit is provided and whose voltage drop is y% or more and less than x%. The circuit region D is a region where the standard element circuit is provided and has a voltage drop of x% or more.
First, since the standard element circuit is not provided in the circuit area a, any power switch circuit PS will not be laid out.
In addition, since the voltage drop of the circuit area D is greater than the voltage drop of the circuit area C, the processor 110 lays out the power switch circuit PS1 at a position corresponding to the circuit area D and lays out the power switch circuit PS2 at a position corresponding to the circuit area C. The resistance value of the power switch circuit PS1 is smaller than the resistance value of the power switch circuit PS2, but the area of the power switch circuit PS1 is larger than the area of the power switch circuit PS2.
Similarly, since the voltage drop of the circuit area C is greater than the voltage drop of the circuit area B, the processor 110 will layout the power switch circuit PS2 at a position corresponding to the circuit area C, and will layout the power switch circuit PS3 at a position corresponding to the circuit area B. The resistance of the power switch circuit PS2 is smaller than that of the power switch circuit PS3, but the area of the power switch circuit PS2 is larger than that of the power switch circuit PS3.
That is, the resistance value of the power switch circuit PS1, the resistance value of the power switch circuit PS2, and the resistance value of the power switch circuit PS3 are different from each other. The area of the power switch circuit PS1, the area of the power switch circuit PS2, and the area of the power switch circuit PS3 are also different from each other.
Based on the above principle, the processor 110 may determine the types of the power switch circuits PS according to the simulation result 500 of fig. 5. For example, in fig. 8, in the power switch chain 220B, the power switch circuit PS1 is set corresponding to the position of the sub-circuit C1 (the position adjacent to the sub-circuit C1), the power switch circuit PS2 is set corresponding to the position of the sub-circuit C2 (the position adjacent to the sub-circuit C2), and the power switch circuit PS3 is set corresponding to the position of the sub-circuit C3 (the position adjacent to the sub-circuit C3).
In some embodiments, after determining the location and type (resistance and area) of the power switch circuits PS, the processor 110 may perform design specification verification (design rule check, DRC), circuit layout verification (layout versus schematic, LVS), or other various verifications on the layout information of the entire integrated circuit 800 (including the power switch chain 220B and the functional circuit 230). After the verification is passed, the integrated circuit 800 may be manufactured based on layout information of the integrated circuit 800 using a semiconductor process.
In some related art, the power switch chain provided with the same has a uniform architecture (uniform architecture). That is, all power switch circuits in the power switch chain are identical (all power switch circuits have the same resistance value and the same area). However, when configuring a power switch circuit having only a single type, the user will select a power switch circuit (e.g., power switch circuit PS 1) having a small resistance value and a large area, so that the overall voltage drop in the maximum voltage drop region can meet the design requirement. Since all power switch circuits are selected power switch circuits with small resistance values and large areas, the whole power switch chain occupies a larger circuit area.
In comparison with the above related art, in the present disclosure, the power switch chain 220B includes different power switch circuits PS1-PS3, and the different power switch circuits PS1-PS3 (having different resistance values and different areas) are appropriately configured at corresponding positions according to the simulation result 500 (e.g., voltage drop information). Thus, not only the overall voltage drop of each circuit region can meet the design requirement, but also the circuit area can be saved.
It is specifically described herein that although three power switch circuits PS1-PS3 are exemplified in fig. 8, the disclosure is not limited to this number.
Refer to fig. 9. Fig. 9 is a schematic diagram of an integrated circuit 900 shown in accordance with some embodiments of the present disclosure.
The integrated circuit 900 in fig. 9 may be, for example, a multi-core system. That is, integrated circuit 900 includes core circuitry 910 and core circuitry 920. The integrated circuit 900 may also include a power switch chain 220C and a power switch chain 220D. The power switch chain 220C is disposed at a position corresponding to (adjacent to the core circuit 910), the power switch chain 220D is disposed at a position corresponding to (adjacent to the core circuit 920), and the power switch chains 220C and 220D are independently controlled. That is, the power switch chains 220C and 220D are controlled by different control signals, respectively. For example, as shown in fig. 9, the control signal CS1 is used to turn on or off the power switches in the power switch chain 220C, and the control signal CS2 is used to turn on or off the power switches in the power switch chain 220C. The control signal CS1 or the control signal CS2 may come from one or more control circuits (not shown). When the core circuit 910 is not operating (during idle period of the core circuit 910), the control signal CS1 may turn off the plurality of power switch circuits in the power switch chain 220C to stop providing power to the core circuit 910. When the core circuit 910 is operating (during operation of the core circuit 910), the control signal CS1 may turn on the plurality of power switch circuits in the power switch chain 220C to provide power to the core circuit 910. Similarly, when the core circuit 920 is not operating (during idle periods of the core circuit 920), the control signal CS2 may turn off the plurality of power switch circuits in the power switch chain 220D to stop providing power to the core circuit 920. When the core circuit 920 is operating (during operation of the core circuit 920), the control signal CS2 may turn on the plurality of power switch circuits in the power switch chain 220D to provide power to the core circuit 920.
The configuration of power switch chain 220C and power switch chain 220D is similar to power switch chain 220B in fig. 8. That is, the power switch chain 220C or 220D includes power switch circuits having different resistance values (different areas), and the power switch circuits are sequentially coupled to form a chain. For the remaining details, please refer to the paragraphs related to the power switch chain 220B, and further description is omitted here.
In summary, in the present disclosure, the power switch chain is composed of at least two power switch circuits with different resistance values to form a non-uniform architecture. Thus, both circuit performance and circuit area can be achieved.
While the present disclosure has been described with reference to the embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present disclosure, and thus the scope of the present disclosure is defined by the appended claims.

Claims (10)

1. An integrated circuit, comprising:
a functional circuit; and
a first power switch chain including a first power switch circuit and a second power switch circuit and coupled between a power source and the functional circuit, wherein the first power switch chain is used for receiving a first control signal, and the first control signal is used for turning on or off the first power switch circuit and the second power switch circuit,
wherein a first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.
2. The integrated circuit of claim 1, wherein the functional circuit comprises a first sub-circuit and a second sub-circuit, the first power switch circuit is located corresponding to the first sub-circuit, the second power switch circuit is located corresponding to the second sub-circuit, a first voltage drop of the first sub-circuit is greater than a second voltage drop of the second sub-circuit, and the first resistance value is less than the second resistance value.
3. The integrated circuit of claim 2, wherein an area of the first power switching circuit is greater than an area of the second power switching circuit.
4. The integrated circuit of claim 2, wherein the functional circuit further comprises a third sub-circuit, the first power switch chain further comprises a third power switch circuit, and the third power switch circuit is positioned corresponding to the third sub-circuit,
the second voltage drop is larger than a third voltage drop of the third sub-circuit, and the second resistance value is smaller than a third resistance value of the third power switch circuit.
5. The integrated circuit of claim 4, wherein an area of the second power switching circuit is greater than an area of the third power switching circuit.
6. The integrated circuit of claim 2, wherein a first distance between the first sub-circuit and a power pad is greater than a second distance between the second sub-circuit and the power pad, a first element density of the first sub-circuit is greater than a second element density of the second sub-circuit, or a first operand of the first sub-circuit is greater than a second operand of the second sub-circuit.
7. The integrated circuit of claim 1, further comprising:
a second power switch chain including a third power switch circuit and a fourth power switch circuit and coupled between the power source and the functional circuit, wherein the second power switch chain is used for receiving a second control signal for controlling whether the third power switch circuit and the fourth power switch circuit are turned on,
wherein a third resistance value of the third power switch circuit is different from a fourth resistance value of the fourth power switch circuit.
8. The integrated circuit of claim 7, wherein the functional circuit comprises a first core circuit and a second core circuit, the first power switch chain being positioned corresponding to the first core circuit and the second power switch chain being positioned corresponding to the second core circuit.
9. A layout method of an integrated circuit, comprising:
determining the positions of a first power switch circuit and a second power switch circuit in a first power switch chain through a processor;
generating a layout information of a functional circuit by the processor, wherein the first power switch circuit and the second power switch circuit are coupled between a power supply and the functional circuit;
generating a simulation result by the processor according to the layout information of the functional circuit; and
determining a first resistance value of the first power switch circuit and a second resistance value of the second power switch circuit according to the simulation result by the processor,
wherein the first resistance value is different from the second resistance value.
10. The layout method according to claim 9, wherein the simulation result is a voltage drop information.
CN202210831580.3A 2022-07-14 2022-07-14 Integrated circuit and layout method thereof Pending CN117435034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210831580.3A CN117435034A (en) 2022-07-14 2022-07-14 Integrated circuit and layout method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210831580.3A CN117435034A (en) 2022-07-14 2022-07-14 Integrated circuit and layout method thereof

Publications (1)

Publication Number Publication Date
CN117435034A true CN117435034A (en) 2024-01-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210831580.3A Pending CN117435034A (en) 2022-07-14 2022-07-14 Integrated circuit and layout method thereof

Country Status (1)

Country Link
CN (1) CN117435034A (en)

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