CN117434861A

CN117434861A - Controller with configurable channel function and air conditioner

Info

Publication number: CN117434861A
Application number: CN202311377021.0A
Authority: CN
Inventors: 唐文; 赵龙生; 阙讯
Original assignee: Trane Air Conditioning Systems China Co Ltd
Current assignee: Trane Air Conditioning Systems China Co Ltd
Priority date: 2023-10-23
Filing date: 2023-10-23
Publication date: 2024-01-23

Abstract

The application provides a controller with a configurable channel function and an air conditioner. The controller comprises a control chip, a channel and a channel configuration circuit. The control chip comprises a PWM output pin, an AD conversion pin and at least one switch control pin. The channel has a first terminal and a second terminal, the second terminal being grounded. The channel configuration circuit is connected between the control chip and the channel and comprises a plurality of switches. The control chip is used for realizing the configuration of the input function or the output function of the first terminal by controlling the combination mode of closing and opening of the plurality of switches, and further realizing the configuration of the input function or the output function of the channel. The method and the device can solve the problem that the channel of the controller is single in function.

Description

Controller with configurable channel function and air conditioner

Technical Field

The application relates to the technical field of controllers, in particular to a controller with a configurable channel function and an air conditioner.

Background

The various controllers of an air conditioner generally include an input channel and an output channel, and the input channel and the output channel can be largely divided into analog and digital according to functions. For example, analog input channels generally include resistance detection, voltage detection, current detection, PWM detection, etc. as a function, and digital input channels generally include high-low voltage/dry-contact detection, pulse counting, etc. as a function; the analog output channel roughly comprises voltage output, current output, PWM output and the like according to functions; the digital output channel generally includes on-off output and the like according to functions.

Currently, the function of each input and output channel of the controller is basically fixed, the function is single, and the number of each channel is also fixed. However, this can be very inconvenient and inflexible for machines having different configurations and/or different applications. If channels with other functions are required, the controller is not applicable, or an expansion board containing the required channel functions needs to be added in the controller again.

Disclosure of Invention

The purpose of the application is to provide a controller with a configurable channel function and an air conditioner, which can solve the problem of single channel function of the controller.

One aspect of the present application provides a controller with configurable channel functionality. The controller comprises a control chip, a channel and a channel configuration circuit. The control chip comprises a PWM output pin, an AD conversion pin and at least one switch control pin. The channel has a first terminal and a second terminal, the second terminal being grounded. The channel configuration circuit is connected between the control chip and the channel and comprises a plurality of switches. The control chip is used for controlling the input function or the output function of the first terminal in a combined mode of controlling the closing and opening of the switches, and further realizing the configuration of the input function or the output function of the channel.

Further, the controller includes a plurality of channels and a plurality of channel configuration circuits, each of the channel configuration circuits is used for performing functional configuration on the corresponding channel, and the plurality of channels includes a plurality of input channels, a plurality of output channels and/or a plurality of input/output channels.

Further, the input functions include functions of resistive input, voltage input, current input, and/or dry-contact input; the output functions include functions of voltage output, PWM output, and/or current output.

Further, the plurality of switches include a first switch, a second left switch, a second right switch, a third left switch, a third right switch, a fourth switch, and a fifth switch, wherein the controller is configured to implement functions of a resistance input, a voltage input, a current input, a voltage output, a PWM output, a current output, and a dry contact input of the first terminal by controlling a combination of closing and opening of the first switch, the second left switch, the second right switch, the third left switch, the third right switch, the fourth switch, and the fifth switch.

Further, the at least one switch control pin includes a first switch control pin, a second switch control pin, a third switch control pin, a fourth switch control pin, and a fifth switch control pin, where the first switch control pin, the fourth switch control pin, and the fifth switch control pin are used to control the first switch, the fourth switch, and the fifth switch, respectively, the second left switch, and the second right switch are exclusive switches, where the second switch control pin is used to control the second left switch, the second right switch, the third left switch, and the third right switch are exclusive switches, and where the third switch control pin is used to control the third left switch, and the third right switch.

Further, the channel configuration circuit comprises a first operational amplifier, a second operational amplifier, a filter circuit, a triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a pull-up resistor, a first voltage detection resistor, a second voltage detection resistor, a first current detection resistor and a second current detection resistor, wherein the negative input end of the first operational amplifier is connected to the PWM output pin through the filter circuit, the negative input end of the first operational amplifier is connected to a first power supply through the third left switch, and the negative input end of the first operational amplifier is further connected between the first resistor and the second resistor; the second left switch, the first resistor, the second resistor, the third resistor and the third right switch are sequentially connected in series between the ground and the first terminal, one end of the second right switch is connected between the second resistor and the third resistor, and the other end of the second right switch is grounded; the base electrode of the triode is connected with the output end of the first operational amplifier, the collector electrode of the triode is connected with a second power supply, and the emitter electrode of the triode is connected between the third resistor and the second right switch through a fourth resistor; the negative input end and the negative input end of the second operational amplifier are connected to the two ends of the fourth resistor, and the negative input end of the second operational amplifier is connected to the ground through the second left switch; one end of the pull-up resistor is connected to a third power supply through the fourth switch, and the other end of the pull-up resistor is connected to the first terminal; the first voltage detection resistor, the second voltage detection resistor and the fifth switch are sequentially connected in series between the first terminal and the ground; the first current detection resistor, the first switch and the second current detection resistor are sequentially connected in series between the first terminal and the ground; and a connection point of the first voltage detection resistor and the second voltage detection resistor is connected to the AD conversion pin.

Further, the first terminal is configured as a resistive input function when the fourth switch is closed, the first switch, the third right switch, and the fifth switch are open.

Further, the first terminal is configured as a voltage input function when the fifth switch is closed, and the first switch, the third right switch, and the fourth switch are open.

Further, the first terminal is configured as a current input function when the first switch is closed, the third right switch, the fourth switch, and the fifth switch are open.

Further, the first terminal is configured as a voltage output function when the second left switch, the third right switch, and the fifth switch are closed, and the first switch, the second right switch, the third left switch, and the fourth switch are open.

Further, when the fifth switch is turned on, the controller has an input voltage detection function, and the control chip detects an output voltage on the first terminal based on an AD value obtained by converting a signal from the first voltage detection resistor and the second voltage detection resistor through the AD conversion pin, and adjusts a duty ratio of a PWM signal output through the PWM pin based on the detected output voltage on the first terminal, thereby adjusting the output voltage.

Further, when the second left switch and the fifth switch are closed, the first switch, the second right switch, and the fourth switch are opened, and the third left switch and the third right switch are periodically alternately opened and closed, the first terminal is configured as a PWM output function.

Further, the first terminal is configured as a current output function when the second right switch, the third right switch, and the fifth switch are closed, and the first switch, the second left switch, the third left switch, and the fourth switch are open.

Further, when the fifth switch is turned on, the controller has an input voltage detection function, and the control chip detects the output voltage on the first terminal based on an AD value obtained by converting the signal from between the first voltage detection resistor and the second voltage detection resistor through the AD conversion pin.

Further, the controller is configured to: before the channel realizes a current output function, setting the channel into a pure PWM mode, and searching for a relation between a pure PWM duty ratio in the pure PWM mode and an output current of a terminal under a preset load, wherein a fifth switch is opened and an input voltage detection function is closed in the pure PWM mode compared with the current output function; and setting the channel back to the current output function, and after connecting a resistor with an unknown resistance value to a terminal of the channel, performing closed-loop feedback control by the control chip based on the set target output current and the relation between the obtained pure PWM duty ratio and the output current of the terminal, and outputting different PWM duty ratios to adjust the output current until the target output current is gradually approximated.

Further, the first terminal is configured as a dry-contact input function when the second right switch, the third right switch, and the fifth switch are closed, and the first switch, the second left switch, the third left switch, and the fourth switch are open.

Further, each of the channel configuration circuits has an access terminal for connection to the AD conversion pin, the access terminals of the plurality of channel configuration circuits being connected to the AD conversion pin through a multiway switch.

Further, each channel configuration circuit further comprises a noise circuit, the noise circuit in each channel configuration circuit is connected between the access end and the multi-way switch, and the control chip further comprises a plurality of noise circuit control pins which are respectively used for controlling a plurality of noise circuits.

Further, the control chip has a function of improving the ADC sampling resolution of the input channels, and is configured to form, in the input channels configured to be input channels, an input channel to be improved in resolution into a circular queue, and for the circular queue, the control chip is configured to sequentially read, through the AD conversion pins, a plurality of AD values of one input channel in the circular queue in turn per noise period, and average the AD value of each input channel in a predetermined time window, where the predetermined time window includes a plurality of the noise periods.

Another aspect of the present application provides an air conditioner. The air conditioner includes a controller having a channel function configurable as described above.

The controller with the configurable channel function and the air conditioner can solve the problem that the channel function of the controller is single, and can flexibly configure the channel function.

In addition, the controller with the configurable channel function and the air conditioner in one or more embodiments of the application can improve the resolution of AD conversion of a certain channel according to actual needs without using a control chip with very high resolution, so that the requirement on the control chip can be reduced, and the controller and the air conditioner have the advantages of high measurement precision, low cost and the like.

Drawings

FIG. 1 is a general block diagram of a controller with configurable channel functions according to one embodiment of the present application.

Fig. 2 is a simplified schematic diagram of a plurality of channels included in a controller 1 with channel function configurable according to one embodiment of the present application.

Fig. 3 is a schematic general structure of a controller with an input/output channel according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a controller with an input-output channel according to an embodiment of the present application when the channel is configured as a resistive input.

Fig. 5 is a schematic diagram of a controller with channel function configurable according to one embodiment of the present application when the channel is configured for voltage input.

Fig. 6 is a schematic diagram of a controller with channel function configurable according to one embodiment of the present application when the channel is configured for current input.

Fig. 7 is a schematic diagram of a controller with a configurable channel function according to an embodiment of the present application when the channel is configured as a voltage output.

Fig. 8 is a schematic diagram of a controller with channel function configurable according to one embodiment of the present application when the channel is configured as a PWM output.

Fig. 9 is a schematic diagram of a controller with channel function configurable according to one embodiment of the present application when the channel is configured for current output.

Fig. 10 is a schematic block diagram of output current employing negative feedback control according to one embodiment of the present application.

Fig. 11 is a schematic diagram of a controller with channel function configurable according to one embodiment of the present application when the channel is configured as a dry-access input.

Fig. 12 is a schematic diagram of a controller with configurable channel function to improve the resolution of AD conversion according to an embodiment of the present application.

FIG. 13 is a schematic diagram of input channels that require resolution enhancement in a circular queue according to one embodiment of the present application.

Fig. 14 is a software processing diagram of the controller 1 with configurable channel function to increase the resolution of AD conversion according to one embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with some aspects of the present application as detailed in the accompanying claims.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The application provides a controller with a configurable channel function. Fig. 1 discloses a general block diagram of a controller 1 with configurable channel functions according to one embodiment of the present application. As shown in fig. 1, a controller 1 with configurable channel function according to one embodiment of the present application includes a control chip 10, a channel 20, and a channel configuration circuit 30. The control chip 10 may include, for example, but is not limited to, an MCU (Microcontroller Unit, micro control unit) chip including a PWM output pin, an AD conversion pin, and at least one individual switch control pin. The channel 20 has a first terminal T1 and a second terminal T2, wherein the second terminal T2 is grounded. The channel configuration circuit 30 is connected between the control chip 10 and the channel 20, and the channel configuration circuit 30 includes a plurality of switches S.

The PWM output pin of the control chip 10 is used for outputting a PWM signal, and the AD conversion pin is used for performing an analog-to-digital conversion on the received voltage signal to convert the voltage signal into an AD value. At least one switch control pin of the control chip 10 may be used to control a plurality of switches S in the channel configuration circuit 30, respectively. The PWM output pin and the AD conversion pin of the control chip 10 are connected to the first terminal T1 of the channel 20 through the channel configuration circuit 30. The control chip 10 can realize the configuration of the input function or the output function of the first terminal T1 by controlling the combination of the closing and opening of the plurality of switches S in the channel configuration circuit 30, thereby realizing the configuration of the input function or the output function of the channel 20, so that the channel 20 of the controller 1 can be configured as an input channel or an output channel according to the actual application requirement.

In some embodiments, the controller 1 may include a plurality of channels 20 and a plurality of channel configuration circuits 30. Each channel configuration circuit 30 may be used to functionally configure a corresponding channel 20, respectively.

As shown in fig. 2, the plurality of channels 20 included in the controller 1 may include a plurality of input channels 21, a plurality of output channels 22, and/or a plurality of input-output channels 23. The input channel 21 refers to a channel 20 having only an input function, the output channel 22 refers to a channel 20 having only an output function, and the input/output channel 23 refers to a channel 20 having both an input function and an output function.

The input function may include, for example, but is not limited to, a function of a resistive input, a voltage input, a current input, and/or a dry-contact input; the output function may include, for example, but is not limited to, a function of voltage output, PWM output, and/or current output.

Fig. 2 discloses a simplified schematic diagram of a plurality of channels 20 comprised by a controller 1 with channel function configurable in one embodiment of the present application. As shown in fig. 2, in one embodiment, the controller 1 may have a plurality of input channels 21, a plurality of output channels 22, and a plurality of input-output channels 23 at the same time.

In practical applications, the corresponding channel configuration circuit 30 may be designed for three different types of channels 20 of the controller 1 configured as an input channel 21, an output channel 22 or an input output channel 23, respectively. The channel configuration circuit 30 that configures the channel 20 as the input channel 21, the channel configuration circuit 30 that configures the channel 20 as the output channel 22, and the channel configuration circuit 30 that configures the channel 20 as the input output channel 23 may be the same or different. In the case where the same channel configuration circuit 30 is used for the input channel 21, the output channel 22, and the input-output channel 23, the channel 20, specifically, the input function or the output function, may be implemented according to different combinations of the closing and opening of the plurality of switches S in the channel configuration circuit 30. It will be appreciated that implementing a channel configuration circuit 30 having both an input function and an output function is relatively complex in internal circuit configuration relative to a channel configuration circuit 30 that implements only an input function or a channel configuration circuit 30 that implements only an output function. Of course, in order to save wiring resources of the circuit board in the controller 1, the input channel 21, the output channel 22, and the input-output channel 23 may also employ different channel configuration circuits 30, respectively.

A schematic description will be given below of how the controller 1 with channel function configuration according to one embodiment of the present application is specifically configured to implement the input and/or output functions of the channel 20, taking the channel configuration circuit 30 employed by the input-output channel 23 as an example.

Fig. 3 discloses a schematic general structure of a controller 1 with input-output channels according to an embodiment of the present application. The controller 1 has a channel 20 and a channel configuration circuit 30. The channel 20 is an input/output channel, and the channel configuration circuit 30 may implement configuration of the channel 20 as a channel having both an input function and an output function, i.e., an input/output channel.

As shown in fig. 3, the channel configuration circuit 30 includes a plurality of switches. The plurality of switches may include a first switch S1, a second left switch S21, a second right switch S22, a third left switch S31, a third right switch S32, a fourth switch S4, and a fifth switch S5. The controller 1 may implement the input function or the output function of the first terminal T1 of the channel 20 by controlling the combination of the closing and opening of the first switch S1, the second left switch S21, the second right switch S22, the third left switch S31, the third right switch S32, the fourth switch S4, and the fifth switch S5, for example, may implement the functions of the resistor input, the voltage input, the current input, the voltage output, the PWM output, the current output, and the dry-contact input of the first terminal T1 of the channel 20.

The control chip 10 may include a PWM output pin, an AD conversion pin, and a plurality of switch control pins. The PWM output pin may output, for example, a PWM signal at a dc voltage of 0-3.3V. In some embodiments, the second left switch S21 and the second right switch S22 in the channel configuration circuit 30 are a pair of exclusive switches, and the third left switch S31 and the third right switch S32 are a pair of exclusive switches. By exclusive switch is meant that one of the switches is closed and the other is open. In this case, the plurality of switch control pins of the control chip 10 may include a first switch control pin CTRL1, a second switch control pin CTRL2, a third switch control pin CTRL3, a fourth switch control pin CTRL4, and a fifth switch control pin CTRL5. The first switch control pin CTRL1, the fourth switch control pin CTRL4, and the fifth switch control pin CTRL5 of the control chip 10 may be used to control the first switch S1, the fourth switch S4, and the fifth switch S5, respectively, the second switch control pin CTRL2 of the control chip 10 may be used to mutually exclusive control the second left switch S21 and the second right switch S22, and the third switch control pin CTRL3 of the control chip 10 may be used to mutually exclusive control the third left switch S31 and the third right switch S32.

Of course, in other embodiments, the second left switch S21 and the second right switch S22 may be controlled by different switch control pins of the control chip 10, and the third left switch S31 and the third right switch S32 may be controlled by different switch control pins of the control chip 10, so that the configuration of the channel configuration circuit 30 for the input function or the output function may be similarly implemented. It can be understood that, if the second left switch S21 and the second right switch S22 are separately controlled and the third left switch S31 and the third right switch S32 are separately controlled, the control chip 10 needs to be increased with two corresponding switch control pins accordingly.

With continued reference to fig. 3, the channel configuration circuit 30 includes a first operational amplifier 311, a second operational amplifier 312, a filter circuit 321, a transistor Q, a first resistor R11, a second resistor R12, a third resistor R13, a fourth resistor R14, a pull-up resistor R2, a first voltage detection resistor R31, a second voltage detection resistor R32, a first current detection resistor R41, and a second current detection resistor R42.

The positive (+) input terminal of the first operational amplifier 311 is connected to the PWM output pin of the control chip 10 through the filter circuit 321, the negative (-) input terminal of the first operational amplifier 311 is connected to a first power source, for example, a 3.5V dc voltage source, through the third left switch S31, and the negative input terminal of the first operational amplifier 311 is also connected between the first resistor R11 and the second resistor R12.

The second left switch S21, the first resistor R11, the second resistor R12, the third resistor R13 and the third right switch S32 are sequentially connected in series between ground and the first terminal T1 of the channel 20, one end of the second right switch S22 is connected between the second resistor R12 and the third resistor R13, and the other end of the second right switch S22 is grounded.

The base of the triode Q is connected with the output end of the first operational amplifier 311, the collector of the triode Q is connected with a second power supply, for example, a 24V direct current voltage source, and the emitter of the triode Q is connected between the third resistor R13 and the second right switch S22 through the fourth resistor R14.

The positive (+) input terminal and the negative (-) input terminal of the second operational amplifier 312 are connected to both ends of the fourth resistor R14, and the output terminal of the second operational amplifier 312 is connected to the ground through the second left switch S21.

One end of the pull-up resistor R2 is connected to a third power source, for example, a 3.3V dc voltage source, through a fourth switch S4, and the other end of the pull-up resistor R2 is connected to the first terminal T1 of the channel 20.

The first voltage detection resistor R31, the second voltage detection resistor R32, and the fifth switch S5 are sequentially connected in series between the first terminal T1 of the channel 20 and ground.

The first current detection resistor R41, the first switch S1, and the second current detection resistor R42 are sequentially connected in series between the first terminal T1 of the channel 20 and ground.

The connection point of the first voltage detection resistor R31 and the second voltage detection resistor R32 is connected to the AD conversion pin of the control chip 10.

In some embodiments, the controller 1 of the present application may also include an output current limiting circuit 331. The output current limiting circuit 331 is located at the output terminal of the first operational amplifier 311 and the base of the transistor Q.

In some embodiments, the controller 1 of the present application may also include a current limiting circuit 332. The current limiting circuit 332 is located between the second current sensing resistor R42 and ground.

In some embodiments, the controller 1 of the present application may further include a fifth resistor R15. The fifth resistor R15 is connected in series between the output terminal of the second operational amplifier 312 and the second left switch S21, and can perform a current limiting function on the output terminal of the second operational amplifier 312.

In some embodiments, the controller 1 of the present application may further include a protection circuit 333 and a second filter circuit 322. The protection circuit 333 and the second filter circuit 322 are located between the third right switch S32 and the first terminal T1 of the channel 20, and may function as protection and filtering, respectively.

In the following, in conjunction with fig. 4 to 11 and table 1, it will be described in detail how the controller 1 with input/output channels according to one embodiment of the present application implements the corresponding channel function configuration by combining different switches in the channel configuration circuit 30.

Table 1 channel functions and respective switch configurations

Fig. 4 discloses a schematic diagram of the structure of the controller 1 with input-output channels according to one embodiment of the present application when the channels 20 are configured as resistive inputs. As shown in fig. 4 and referring to table 1, when the channel 20 needs to be configured as an input channel with a resistive input function, i.e. the first terminal T1 of the channel 20 is configured as a resistive input function, the fourth switch S4 can be controlled to be closed, and the first switch S1, the third right switch S32 and the fifth switch S5 can be controlled to be opened. The fourth switch S4 is closed, the pull-up resistor R2 is enabled, the resistor to be detected and the pull-up resistor R2 form a series connection, and the pull-up resistor is pulled up to 3.3V direct current voltage. The AD conversion pin of the control chip 10 receives the divided voltage, and the fifth switch S5 is turned off, so that the first voltage detection resistor R31 does not participate in the divided voltage at this time.

Fig. 5 discloses a schematic diagram of the configuration of the controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as a voltage input. As shown in fig. 5 and referring to table 1, when the channel 20 needs to be configured as an input channel with a voltage input function, i.e. the first terminal T1 of the channel 20 is configured as a voltage input function, the fifth switch S5 can be controlled to be closed, and the first switch S1, the third right switch S32 and the fourth switch S4 can be controlled to be opened. The fifth switch S5 is closed, and the first voltage detecting resistor R31 and the second voltage detecting resistor R32 form a voltage dividing circuit, so as to reduce the voltage value of the AD conversion pin during the AD conversion, and protect the control chip 10 from being damaged by high voltage.

Fig. 6 discloses a schematic structural diagram of a controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as a current input. As shown in fig. 6 and referring to table 1, when the channel 20 needs to be configured as an input channel with a current input function, i.e. the first terminal T1 of the channel 20 is configured as a current input function, the first switch S1 can be controlled to be closed, and the third right switch S32, the fourth switch S4 and the fifth switch S5 can be controlled to be opened. The first switch S1 is closed, so that the first current detection resistor R41, the second current detection resistor R42 and the current limiting circuit 332 can be enabled, the voltage generated by the current on the resistor is converted by the AD conversion pin of the control chip 10, and the first voltage detection resistor R31 does not participate in voltage division at this time.

Fig. 7 discloses a schematic diagram of the configuration of the controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as a voltage output. As shown in fig. 7 and referring to table 1, when the channel 20 needs to be configured as an output channel with a voltage output function, i.e. the first terminal T1 of the channel 20 is configured as a voltage output function, the second left switch S21, the third right switch S32 and the fifth switch S5 can be controlled to be closed, and the first switch S1, the second right switch S22, the third left switch S31 and the fourth switch S4 can be controlled to be opened.

The control chip 10 outputs a PWM signal (duty cycle 0% -100% adjustable) with an amplitude of 3.3Vdc, for example, and generates a signal of 0-3.3Vdc through the filter circuit 321, and enters the negative input terminal of the first operational amplifier 311. The first operational amplifier 311 is a voltage amplifying circuit with a forward input, and generates an output signal of 0-10Vdc after the voltage amplification.

When the fifth switch S5 is closed, the controller 1 has an input voltage detection function that can detect whether the output voltage is within a required accuracy range and thus adjust the duty cycle of the PWM signal output, thereby adjusting the output voltage. Specifically, the control chip 10 may detect the output voltage at the first terminal T1 through the AD value converted by the AD conversion pin based on the signal from between the first voltage detection resistor R31 and the second voltage detection resistor R32, and adjust the duty ratio of the PWM signal output through the PWM pin based on the detected output voltage at the first terminal T1, thereby adjusting the output voltage.

Fig. 8 discloses a schematic diagram of the configuration of the controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as PWM output. As shown in fig. 8 in combination with reference to table 1, when the channel 20 needs to be configured as an input channel having a PWM output function, i.e., the first terminal T1 of the channel 20 is configured as a PWM output function, the second left switch S21 and the fifth switch S5 may be controlled to be closed, the first switch S1, the second right switch S22 and the fourth switch S4 may be controlled to be opened, and the third left switch S31 and the third right switch S32 may be controlled to be periodically and alternately opened and closed, i.e., the third left switch S31 and the third right switch S32 may be controlled using PWM output.

The third left switch S31 and the third right switch S32 are controlled to be alternately opened and closed periodically so that the output voltage of 0-10Vdc is absent for a while, the inverting input terminal of the first operational amplifier 311 is connected/disconnected with 3.5Vdc, and the first operational amplifier 311 is enabled/disabled, thereby enabling/disabling the output to the terminal, forming a PWM output.

Fig. 9 discloses a schematic structural diagram of the controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as a current output. As shown in fig. 9 and referring to table 1, when the channel 20 needs to be configured as an output channel having a current output function, that is, the first terminal T1 of the channel 20 is configured as a current output function, the second right switch S22, the third right switch S32 and the fifth switch S5 can be controlled to be closed, and the first switch S1, the second left switch S21, the third left switch S31 and the fourth switch S4 can be controlled to be opened. The first operational amplifier 311 amplifies the PWM output signal of the output control chip 10, the second operational amplifier 312 detects the output current, and when the output current is too large, the second operational amplifier 312 outputs a higher level, and the function of the first operational amplifier 311 is turned off.

When the fifth switch S5 is closed, the controller 1 has an input voltage detection function, and the control chip 10 detects the output voltage at the first terminal T1 based on the AD value obtained by AD conversion pin conversion of the signal from between the first voltage detection resistor R31 and the second voltage detection resistor R32.

Fig. 10 discloses a schematic block diagram of output current employing negative feedback control in accordance with one embodiment of the present application. As shown in fig. 10, when the channel 20 is configured as a current output function (typically 0-20 mA), the PWM pin of the control chip 10 outputs different duty cycle signals, so that a voltage is generated at the terminal of the channel 20, and when a certain resistive load is applied to the terminal, a corresponding current is generated. The method mainly comprises two steps:

step S1: at a predetermined (standard/certain) load, a relation between the pure PWM duty cycle and the output current of the terminal is found.

Before the channel 20 is able to realize the current output function, the channel 20 is set to the pure PWM mode (the input voltage detection function is off, i.e. the switch S5 is open, compared to the current output mode of the terminal). Under standard/certain resistive loads (e.g., 150 ohms), a relationship between the pure PWM output duty cycle and the output current of the terminals is obtained as follows:

PWM _{Duty cycle} ＝ Formula (I _o ) (1)

Wherein PWM _{Duty cycle} Represents the pure PWM output duty cycle, I _o The output current of the terminal is represented, and the Formula represents a certain corresponding relation and can be tested in advance.

Step S2: setting the channel 20 back to the current output mode, connecting a certain resistor (the resistance is unknown, but within the allowable working range, such as 10-800 ohms) to the terminal of the channel 20, and setting the target output current of the channel (assuming that the target output current is set to be 15mA here), the control chip 10 will perform closed loop feedback, and output different PWM duty ratios to adjust the output current, gradually approaching the target output current.

The specific process is as follows:

step S2.1: defining a target output current as I _{Target object} I.e. 15mA, two intermediate variables are redefined, I _{Up to date} And I _{Last time} And assigning initial values as follows:

I _{up to date} ＝I _{Last time} ＝I _{Target object} ＝15mA (2)

Step S2.2: finding I according to the relation between the pure PWM output duty ratio and the output current of the terminal under the standard load resistance obtained in the step S1, namely the formula (1) above _{Up to date} A corresponding pure PWM duty cycle and output;

step S2.3: the control chip 10 detects the output voltage between the first terminal T1 and the second terminal T2 of the channel 20 through the first voltage detection resistor R31 and the second voltage detection resistor R32, and is denoted as V _{Terminal for connecting a plurality of terminals} The method comprises the steps of carrying out a first treatment on the surface of the Since the voltage detecting function is turned on when outputting the current, the first voltage detecting resistor R31 and the second voltage detecting resistor R32 consume a small part of the current, denoted as I _Compensation ：

Step S2.4: update I first _{Last time} Re-updating I _{Up to date} The updating method comprises the following steps:

I _{last time} ＝I _{Up to date} (4)

Here I _{Target object} Always 15mA;

step S2.5: if I _{Up to date} And I _{Last time} If the absolute value of the difference is smaller than a preset value (such as 0.001 mA), the target output current is considered to be reached, the regulation is stopped, and the PWM output is kept unchanged. Otherwise, returnReturning to step S2.2.

Fig. 11 discloses a schematic structural diagram of a controller 1 with channel function configurable according to one embodiment of the present application when the channel 20 is configured as a dry-access input. As shown in fig. 11 and referring to table 1, when the channel 20 needs to be configured as an input channel with a dry-contact input function, i.e. the first terminal T1 of the channel 20 is configured as a dry-contact input function, the second right switch S22, the third right switch S32 and the fifth switch S5 can be controlled to be closed, and the first switch S1, the second left switch S21, the third left switch S31 and the fourth switch S4 can be controlled to be opened.

The switch configuration when configured as a dry-contact input function is the same as the switch configuration when configured as a current output function.

When the channel 20 is configured as a dry-contact input function, the controller 1 actively outputs 15-20mA to the channel 20, so that when the input of the dry-contact is shorted, the voltage value of the first terminal T1 is close to 0Vdc. When the input of the dry contact is off, the current output by the first terminal T1 is 0mA, but the voltage value of the first terminal T1 is much larger than 0Vdc.

The controller 1 with the configurable channel function can solve the problem of single channel function of the controller 1, and can flexibly configure the channel function.

The controller 1 with the configurable channel function of the present application can also improve the resolution of AD conversion. The resolution of the AD conversion refers to the resolution capability when the control chip 10 detects an analog signal. The finer the resolution, the higher the resolution, and the more expensive the control chip 10. The resolution is expressed in terms of a number of bits, e.g. 12 bits represents a resolution of the 12 th power of 2. The control chip 10 with general resolution can be used to achieve the final resolution improvement by the method described below.

Fig. 12 discloses a schematic structural diagram of the controller 1 with configurable channel function to improve the resolution of AD conversion according to one embodiment of the present application. As shown in fig. 12, each channel configuration circuit 30 has an access terminal for connection to an AD conversion pin. In some embodiments, the access terminals of the plurality of channel configuration circuits 30 may be connected to the AD conversion pins of the control chip 10 through the multiplexing switch 40.

In some embodiments, each channel configuration circuit 30 may also include a noise circuit 340. Noise circuit 340 in each channel configuration circuit 30 is connected between the access terminal of channel configuration circuit 30 and multiplexing switch 40. The control chip 10 further comprises a plurality of noise circuit control pins NCTRL 1-CTRRn, which can be used to control a plurality of noise circuits 340, respectively.

Some channels, in some functions (such as resistive input mode), require higher resolution than others, such as increasing from 12-bit resolution to 16-bit resolution; or from 16-bit resolution to 20-bit resolution, and thus, it is desirable to increase the resolution of certain channels under certain functions. The control chip 10 of the present application has a function of improving the ADC sampling resolution of the input channel.

Principle of resolution improvement: applying a small amplitude, triangular wave noise with a certain period to a certain voltage input (whether changing or not) of the same channel can cause the voltage waveform to deviate or shake on the original amplitude. Therefore, after the AD conversion pins of the control chip 10 perform AD sampling at different times, different readings (offset may be different) are obtained. The sampling values of the complete periods of the multiple rounds are added and then averaged, so that the value with higher AD digit can be obtained.

For example, the channel 1, the channel 2 and the channel n are all set to be in a resistance input mode, so that resolution is required to be improved; while other channels do not improve resolution. The following description will take three channels 1, 2, and n as examples where resolution is required to be improved.

FIG. 13 is a schematic diagram of input channels that require resolution enhancement in a circular queue according to one embodiment of the present application. As shown in fig. 13, the control chip 10 may form an input channel, which needs to be improved in resolution, into a circular queue in the input channel; while the other channels 20 are formed into another queue that does not require resolution enhancement. For example, lane 1, lane 2, lane n may be grouped into a circular queue, while lane 3 is used as another queue that does not require resolution enhancement.

Fig. 14 discloses a software process diagram of the controller 1 with configurable channel function to increase the resolution of AD conversion according to one embodiment of the present application. As shown in fig. 14, for the circular queue, the control chip 10 may sequentially read a plurality of AD values of one input channel in the circular queue in turn through the AD conversion pins every noise period T (relatively short, μs order), and average the AD value of each input channel for a predetermined time window. Wherein the predetermined time window may comprise a plurality of noise periods T. Thus, an AD value that ultimately improves resolution can be obtained. And for the queue which does not need to improve the resolution, after one round is finished, the AD values of a plurality of channels are read in one noise period T.

The controller 1 with the configurable channel function can improve the resolution of AD conversion of a certain channel according to actual needs without using a control chip 10 with very high resolution, thereby reducing the requirement on the control chip 10 and having the advantages of high measurement precision, low cost and the like.

The application also provides an air conditioner. The air conditioner includes the controller 1 having the channel function configurable as described in the respective embodiments above.

The air conditioner has substantially similar advantageous technical effects as the above-described controller 1 having the configurable channel function, and thus, the description thereof will not be repeated here.

The controller with configurable channel function and the air conditioner provided by the embodiment of the application are described in detail above. Specific examples are applied herein to illustrate the controller and the air conditioner with configurable channel function in the embodiments of the present application, and the description of the above embodiments is only for helping to understand the core ideas of the present application, and is not intended to limit the present application. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made herein without departing from the spirit and principles of the invention, which should also fall within the scope of the appended claims.

Claims

1. A controller with channel function, characterized by: comprising the following steps:

the control chip comprises a PWM output pin, an AD conversion pin and at least one switch control pin;

a channel having a first terminal and a second terminal, the second terminal being grounded;

a channel configuration circuit connected between the control chip and the channel, the channel configuration circuit including a plurality of switches, wherein,

the at least one switch control pin of the control chip is respectively used for controlling the plurality of switches,

the PWM output pin and the AD conversion pin are connected to the first terminal of the channel through the channel configuration circuit,

the control chip is used for realizing the configuration of the input function or the output function of the first terminal by controlling the combination mode of the closing and the opening of the switches, and further realizing the configuration of the input function or the output function of the channel.

2. The controller as set forth in claim 1, wherein: the controller comprises a plurality of channels and a plurality of channel configuration circuits, wherein each channel configuration circuit is used for carrying out functional configuration on the corresponding channel, and the channels comprise a plurality of input channels, a plurality of output channels and/or a plurality of input and output channels.

3. The controller according to claim 1 or 2, wherein: the input functions include functions of resistive input, voltage input, current input, and/or dry-contact input; the output functions include functions of voltage output, PWM output, and/or current output.

4. The controller according to claim 1 or 2, wherein: the plurality of switches comprises a first switch, a second left switch, a second right switch, a third left switch, a third right switch, a fourth switch and a fifth switch, wherein,

the controller is used for realizing the functions of the resistance input, the voltage input, the current input, the voltage output, the PWM output, the current output and the dry contact input of the first terminal by controlling the combination mode of the closing and opening of the first switch, the second left switch, the second right switch, the third left switch, the third right switch, the fourth switch and the fifth switch.

5. The controller as set forth in claim 4, wherein: the at least one switch control pin comprises a first switch control pin, a second switch control pin, a third switch control pin, a fourth switch control pin and a fifth switch control pin, wherein,

The first switch control pin, the fourth switch control pin and the fifth switch control pin are respectively used for controlling the first switch, the fourth switch and the fifth switch,

the second left switch and the second right switch are mutually exclusive switches, wherein the second switch control pin is used for controlling the second left switch and the second right switch,

the third left switch and the third right switch are mutually exclusive switches, wherein the third switch control pin is used for controlling the third left switch and the third right switch.

6. The controller as set forth in claim 4, wherein: the channel configuration circuit comprises a first operational amplifier, a second operational amplifier, a filter circuit, a triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a pull-up resistor, a first voltage detection resistor, a second voltage detection resistor, a first current detection resistor and a second current detection resistor,

the negative input end of the first operational amplifier is connected to the PWM output pin through the filter circuit, the negative input end of the first operational amplifier is connected to a first power supply through the third left switch, and the negative input end of the first operational amplifier is also connected between the first resistor and the second resistor;

The second left switch, the first resistor, the second resistor, the third resistor and the third right switch are sequentially connected in series between the ground and the first terminal, one end of the second right switch is connected between the second resistor and the third resistor, and the other end of the second right switch is grounded;

the base electrode of the triode is connected with the output end of the first operational amplifier, the collector electrode of the triode is connected with a second power supply, and the emitter electrode of the triode is connected between the third resistor and the second right switch through a fourth resistor;

the negative input end and the negative input end of the second operational amplifier are connected to the two ends of the fourth resistor, and the negative input end of the second operational amplifier is connected to the ground through the second left switch;

one end of the pull-up resistor is connected to a third power supply through the fourth switch, and the other end of the pull-up resistor is connected to the first terminal;

the first voltage detection resistor, the second voltage detection resistor and the fifth switch are sequentially connected in series between the first terminal and the ground;

the first current detection resistor, the first switch and the second current detection resistor are sequentially connected in series between the first terminal and the ground; a kind of electronic device with high-pressure air-conditioning system

The connection point of the first voltage detection resistor and the second voltage detection resistor is connected to the AD conversion pin.

7. The controller as set forth in claim 6, wherein: the first terminal is configured as a resistive input function when the fourth switch is closed, the first switch, the third right switch, and the fifth switch are open.

8. The controller as set forth in claim 6, wherein: the first terminal is configured for a voltage input function when the fifth switch is closed and the first, third, right, and fourth switches are open.

9. The controller as set forth in claim 6, wherein: the first terminal is configured as a current input function when the first switch is closed, the third right switch, the fourth switch, and the fifth switch are open.

10. The controller as set forth in claim 6, wherein: the first terminal is configured as a voltage output function when the second left switch, the third right switch, and the fifth switch are closed, and the first switch, the second right switch, the third left switch, and the fourth switch are open.

11. The controller as set forth in claim 10, wherein: when the fifth switch is turned on, the controller has an input voltage detection function, and the control chip detects an output voltage on the first terminal based on an AD value obtained by converting a signal from the first voltage detection resistor and the second voltage detection resistor through the AD conversion pin, and adjusts a duty ratio of a PWM signal output through the PWM pin based on the detected output voltage on the first terminal, thereby adjusting the output voltage.

12. The controller as set forth in claim 6, wherein: the first terminal is configured as a PWM output function when the second left switch and the fifth switch are closed, the first switch, the second right switch, and the fourth switch are open, and the third left switch and the third right switch are periodically alternately open and closed.

13. The controller as set forth in claim 6, wherein: the first terminal is configured as a current output function when the second right switch, the third right switch, and the fifth switch are closed, and the first switch, the second left switch, the third left switch, and the fourth switch are open.

14. The controller as set forth in claim 13, wherein: when the fifth switch is turned on, the controller has an input voltage detection function, and the control chip detects the output voltage on the first terminal based on an AD value obtained by converting the signal between the first voltage detection resistor and the second voltage detection resistor through the AD conversion pin.

15. The controller as set forth in claim 14, wherein: the controller is configured to:

before the channel realizes a current output function, setting the channel into a pure PWM mode, and searching for a relation between a pure PWM duty ratio in the pure PWM mode and an output current of a terminal under a preset load, wherein a fifth switch is opened and an input voltage detection function is closed in the pure PWM mode compared with the current output function; a kind of electronic device with high-pressure air-conditioning system

And setting the channel back to the current output function, and after connecting a resistor with an unknown resistance value to a terminal of the channel, performing closed-loop feedback control by the control chip based on the set target output current and the relation between the obtained pure PWM duty cycle and the output current of the terminal, and outputting different PWM duty cycles to adjust the output current until the target output current is gradually approximated.

16. The controller as set forth in claim 6, wherein: the first terminal is configured as a dry-contact input function when the second right switch, the third right switch, and the fifth switch are closed, and the first switch, the second left switch, the third left switch, and the fourth switch are open.

17. The controller as claimed in claim 2, wherein: each of the channel configuration circuits has an access terminal for connection to the AD conversion pin, and the access terminals of the plurality of channel configuration circuits are connected to the AD conversion pin through a multiway switch.

18. The controller as recited in claim 17, wherein: each channel configuration circuit further comprises a noise circuit, the noise circuit in each channel configuration circuit is connected between the access end and the multi-way switch, and the control chip further comprises a plurality of noise circuit control pins which are respectively used for controlling a plurality of noise circuits.

19. The controller as recited in claim 18, wherein: the control chip has the function of improving the ADC sampling resolution of the input channels, and is used for forming an input channel which needs to be improved in resolution into a circular queue in the input channels,

For the circular queue, the control chip is used for sequentially reading a plurality of AD values of one input channel in the circular queue through the AD conversion pins in turn every noise period, and averaging the AD values of each input channel in a preset time window, wherein the preset time window comprises a plurality of noise periods.

20. An air conditioner, characterized in that: comprising a controller as claimed in any one of claims 1 to 19 having a channel function that is configurable.