CN117425347A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN117425347A CN117425347A CN202210788069.XA CN202210788069A CN117425347A CN 117425347 A CN117425347 A CN 117425347A CN 202210788069 A CN202210788069 A CN 202210788069A CN 117425347 A CN117425347 A CN 117425347A
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 410
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000011229 interlayer Substances 0.000 claims abstract description 51
- 230000008569 process Effects 0.000 claims description 73
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 67
- 229910021332 silicide Inorganic materials 0.000 claims description 60
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 57
- 239000003989 dielectric material Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 6
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- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
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Abstract
A semiconductor structure and method of forming the same, the semiconductor structure comprising: a substrate including a first region and a second region; a floating gate layer on the substrate; the chip resistor structure is positioned on the floating gate layer of the first area; an end interconnection structure on the floating gate layer of the second region; an interlayer dielectric layer which is positioned on the floating gate layer and covers the sheet-shaped resistor structure and the end interconnection structure; and the end plug is positioned in the interlayer dielectric layer on the end interconnection structure and is electrically connected with the end interconnection structure. The technical scheme of the invention can improve the performance of the NAND flash memory device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Currently, flash memory (Flash) is a Non-volatile memory (NVM). The flash memory has the main characteristics of long-term storage of stored information without power up, high integration level, high access speed, easy erasing and rewriting, and the like, so that the flash memory is widely applied to various fields such as microcomputers, automatic control, and the like.
The NAND flash memory device has the advantages of high cell density and storage density, high writing and erasing speeds, and the like, and gradually becomes a structure which is commonly used in a flash memory, and is mainly used in flash memory cards of digital cameras and the like and MP3 players at present.
However, the performance of the existing NAND flash memory device is still to be improved.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a forming method thereof, so as to improve the performance of a formed NAND flash memory device.
In order to solve the above problems, the present invention provides a semiconductor structure, comprising:
a substrate including a first region and a second region;
a floating gate layer on the substrate;
the chip resistor structure is positioned on the floating gate layer of the first area;
an end interconnection structure on the floating gate layer of the second region;
an interlayer dielectric layer which is positioned on the floating gate layer and covers the sheet-shaped resistor structure and the end interconnection structure;
and the end plug is positioned in the interlayer dielectric layer on the end interconnection structure and is electrically connected with the end interconnection structure.
Optionally, the chip resistor structure comprises a first laminated structure and a first metal silicide layer positioned on the top of the first laminated structure; the first lamination structure comprises a first inter-gate dielectric layer and a first control gate layer positioned on the first inter-gate dielectric layer;
the end interconnection structure comprises a second laminated structure and a second metal silicide layer positioned on the top of the second laminated structure; the second lamination structure comprises a second inter-gate dielectric layer and a second control gate layer positioned on the second inter-gate dielectric layer, and the second control gate layer is electrically connected with the floating gate layer.
Optionally, the second inter-gate dielectric layer has an opening exposing the floating gate layer, and the second control gate layer is further located in the opening, such that the second control gate layer contacts the floating gate layer.
Alternatively, the size of the opening is 60nm to 100nm.
Optionally, the end plugs penetrate an interlayer dielectric layer above the end interconnect structure such that the end plugs are in contact with the end interconnect structure.
Optionally, the base comprises a substrate, and the semiconductor structure further comprises:
and a gate insulating layer between the substrate and the floating gate layer.
Optionally, the material of the gate insulating layer includes silicon oxide.
Optionally, the material of the end plug comprises at least one of tungsten and copper.
Optionally, the material of the floating gate layer includes polysilicon.
Optionally, the material of the first control gate layer and the second control gate layer comprises polysilicon.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first region and a second region, and a floating gate layer is formed on the substrate;
forming a chip resistor structure on the floating gate layer of the first region;
forming an end interconnection structure on the floating gate layer of the second region;
forming an interlayer dielectric layer covering the sheet-like resistor structure and the end interconnection structure on the floating gate layer;
an end plug is formed in the interlayer dielectric layer on the end interconnection structure, and the end plug is electrically connected with the end interconnection structure.
Optionally, the step of forming the chip resistor structure and the end interconnect structure includes:
forming a plurality of discrete stacked structures on the floating gate layer; the laminated structure of the first area is a first laminated structure, and the first laminated structure comprises a first inter-gate dielectric layer and a first control gate layer positioned on the first inter-gate dielectric layer; the second region has a laminated structure which comprises a second inter-gate dielectric layer and a second control gate layer positioned on the second inter-gate dielectric layer, and the second control gate layer is electrically connected with the floating gate layer;
and performing a metal silicide process on the top of the first laminated structure and the top of the second laminated structure to form a first metal silicide layer positioned on the top of the first laminated structure and a second metal silicide layer positioned on the top of the second laminated structure, wherein the first laminated structure and the first metal silicide layer form a chip resistor structure, and the second laminated structure and the second metal silicide layer form an end interconnection structure.
Optionally, the second inter-gate dielectric layer has an opening exposing a portion of the floating gate layer, and the second control gate layer is further located in the opening, so that the second control gate layer is electrically connected with the floating gate layer;
the step of forming the first and second stacked structures includes:
forming an inter-gate dielectric material layer on the floating gate layer;
etching the inter-gate dielectric material layer of the second region to form an opening;
after forming the opening, forming a control gate material layer covering the inter-gate dielectric material layer, wherein the control gate material layer also fills the opening;
and patterning the control gate material layer and the inter-gate dielectric material layer to form a first laminated structure and a second laminated structure.
Optionally, the base comprises a substrate;
before forming the floating gate layer, the method further comprises: forming a gate insulating layer on a substrate;
after forming the floating gate layer, the floating gate layer is located on the gate insulator.
Alternatively, the process of forming the gate insulating layer is an atomic layer deposition process.
Optionally, the material of the gate insulating layer includes silicon oxide.
Optionally, the material of the floating gate layer includes polysilicon.
Optionally, the step of forming the end plug comprises:
forming a contact hole above the end interconnection structure in the interlayer dielectric layer;
and filling a conductive medium in the contact hole to form an end plug.
Optionally, the material of the end plug comprises at least one of tungsten and copper.
Optionally, the material of the interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the semiconductor structure provided by the embodiment of the invention comprises: a substrate including a first region and a second region; a floating gate layer on the substrate; the chip resistor structure is positioned on the floating gate layer of the first area; an end interconnection structure on the floating gate layer of the second region; an interlayer dielectric layer which is positioned on the floating gate layer and covers the sheet-shaped resistor structure and the end interconnection structure; and the end plug is positioned in the interlayer dielectric layer on the end interconnection structure and is electrically connected with the end interconnection structure.
It can be seen that the end plugs are formed on the end interconnection structure, so that the end plugs are electrically connected with the floating gate layer through the end interconnection structure, and compared with the scheme of directly forming the end plugs in the interlayer dielectric layer and contacting with the floating gate layer, the height of the end plugs can be reduced, so that the process window for forming the end plugs can be increased, the difficulty in forming the end plugs is reduced, the shape quality of the formed end plugs is improved, and the performance of the formed NAND flash memory device is improved.
Further, the chip resistor structure comprises a first laminated structure and a first metal silicide layer positioned on the top of the first laminated structure, and the end interconnection structure comprises a second laminated structure and a second metal silicide layer positioned on the top of the second laminated structure, so that the end interconnection structure and the chip resistor structure can be formed in the same process step, the influence on the existing process is small, the process is simplified, and the process cost is saved. Meanwhile, the end plug is in direct contact with the second metal silicide layer at the top of the second laminated structure, and compared with the scheme that the source-drain plug is in direct contact with the source-drain doped region, the contact resistance between the end plug and the second metal silicide layer is smaller, so that the performance of the formed NAND flash memory device is improved further.
Drawings
FIG. 1 shows a schematic structure of a semiconductor structure;
fig. 2 to 7 are schematic views of intermediate structures formed by steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in combination with a semiconductor structure.
Fig. 1 shows a schematic structure of a semiconductor structure. Referring to fig. 1, a semiconductor structure includes: a substrate 10, the substrate 10 including a first region I and a second region II, and a gate insulating layer 11 and a floating gate layer 20 on the gate insulating layer 11 being formed on the substrate 10; a chip resistor structure 21 is formed on the floating gate layer 20 in the first region I, and the chip resistor structure 21 comprises an inter-gate dielectric layer 22, a control gate layer 23 positioned on the inter-gate dielectric layer and a metal silicide layer 24 positioned on the control gate layer 23; an interlayer dielectric layer 30 covering the floating gate layer 20 and the chip resistor structure 21; the end plug 40 penetrates the interlayer dielectric layer 30 above the floating gate layer 20 of the second region II.
In the above semiconductor structure, the end plug 40 penetrates through the interlayer dielectric layer 30 disposed above the floating gate layer in the second region II, so that the height of the end plug 40 is larger, resulting in a smaller process window for forming the end plug 40, and increasing the difficulty in forming the end plug 40. Meanwhile, the end plug 40 directly contacts the floating gate layer 20, and the contact resistance is large, which affects the performance of the formed NAND flash memory device.
The semiconductor structure provided by the embodiment of the invention comprises: a substrate including a first region and a second region; a floating gate layer on the substrate; the chip resistor structure is positioned on the floating gate layer of the first area; an end interconnection structure on the floating gate layer of the second region; an interlayer dielectric layer which is positioned on the floating gate layer and covers the sheet-shaped resistor structure and the end interconnection structure; and the end plug is positioned in the interlayer dielectric layer on the end interconnection structure and is electrically connected with the end interconnection structure.
It can be seen that the end plugs are formed on the end interconnection structure, so that the end plugs are electrically connected with the floating gate layer through the end interconnection structure, and compared with the scheme of directly forming the end plugs in the interlayer dielectric layer and contacting with the floating gate layer, the height of the end plugs can be reduced, so that the process window for forming the end plugs can be increased, the difficulty in forming the end plugs is reduced, the shape quality of the formed end plugs is improved, and the performance of the formed NAND flash memory device is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 shows a schematic diagram of a semiconductor structure in an embodiment of the invention. Referring to fig. 7, a semiconductor structure in an embodiment of the present invention includes: a substrate 100, the substrate 100 including a first region I and a second region II; a floating gate layer 200 on the substrate 100; the chip resistor structure 300 is located on the floating gate layer 200 of the first region I, and includes a first stack structure 310 and a first metal silicide layer 320 located on top of the first stack structure 310; the first stack structure 310 includes a first inter-gate dielectric layer 311 and a first control gate layer 312 located on the first inter-gate dielectric layer 311; the end interconnection structure 400 is located on the floating gate layer 200 of the second region II and includes a second stack structure 410 and a second metal silicide layer 420 located on top of the second stack structure 410; the second stack structure 410 includes a second inter-gate dielectric layer 411 and a second control gate layer 412 on the second inter-gate dielectric layer 411, and the second control gate layer 412 of the second stack structure 410 is electrically connected to the floating gate layer 200; an interlayer dielectric layer 500 on the floating gate layer 200 and covering the sheet-like resistive structure 300 and the end interconnection structure 400; an end plug 550 is located in the interlayer dielectric layer 500 on the end interconnect structure 400 and is electrically connected to the end interconnect structure 400.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures. The substrate may be a planar substrate or a three-dimensional substrate according to actual process conditions.
In this embodiment, the substrate 100 is a planar substrate. Specifically, the base 100 includes a substrate.
The substrate provides a process platform for the subsequent formation of flash memory. Specifically, the substrate is used to form a NAND Flash (NAND Flash) device.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 100 includes a first region I and a second region II, where the first region I and the second region II are disposed in parallel, and the second region II is located at two sides of the first region I.
In this embodiment, the first region I is used to form a chip resistor structure in a floating gate chip resistor (Floating Gate Sheet Resistor, FG-RS) structure in a NAND flash memory device, and the second region II is used to form an end interconnect structure and an end plug that electrically pull out the floating gate chip resistor structure.
The floating gate chip resistor structure acts as a resistor for the NAND flash memory device for providing resistance for the logical operation of the NAND flash memory device.
The floating gate layer 200, as part of a floating gate sheet resistance structure, forms a floating gate sheet resistance structure in a NAND flash memory device in conjunction with the sheet resistance structure 300.
In this embodiment, the material of the floating gate layer 200 is polysilicon. In other embodiments, the floating gate layer 200 can also be made of other suitable materials, such as doped polysilicon, and the like.
In this embodiment, the method for forming a semiconductor structure further includes: a gate insulating layer 105 between the substrate 100 and the floating gate layer 200.
The gate insulating layer 105 serves to play an isolating role between the floating gate layer 200 and the substrate to prevent electrons in the floating gate layer 200 from entering the substrate.
In this embodiment, the material of the gate insulating layer 105 is silicon oxide. In other embodiments, the material of the gate insulating layer 105 can also be other dielectric materials such as silicon nitride.
The chip resistor structure 300, as part of a floating gate chip resistor structure, cooperates with the floating gate layer 200 to form a floating gate chip resistor structure in a NAND flash memory device.
The end interconnection structure 400 is used to realize electrical extraction of the floating gate chip resistor structure, so as to realize electrical connection between the floating gate chip resistor structure and other structures.
In this embodiment, the top portions of the end interconnection structure 400 and the chip resistor structure 300 are flush with each other, so that the end plug formed in the interlayer dielectric layer 500 is electrically connected with the floating gate layer 200 through the end interconnection structure 400, which correspondingly reduces the height of the end plug, increases the process window of the end plug, reduces the difficulty in forming the end plug, and makes the formed end plug have better shape quality.
The first stack structure 310 is used as part of a chip resistor structure to make electrical connection with the floating gate layer 200.
In this embodiment, the first control gate layer 311 of the first stacked structure 310 is isolated from the floating gate layer 200 by the inter-gate dielectric layer 312.
The second stack structure 410 serves as part of an end interconnect structure for enabling electrical extraction of the floating gate chip resistor structure.
In this embodiment, the second control gate layer 412 of the second stacked structure 410 is electrically connected to the floating gate layer 200. Specifically, the second inter-gate dielectric layer 411 of the second stacked structure 410 has an opening (not labeled) exposing the floating gate layer 200, and the second control gate layer 412 of the second stacked structure 410 is further located in the opening, so that the second control gate layer 412 of the second stacked structure 410 is in direct contact with the floating gate layer 200, thereby achieving an electrical connection between the second control gate layer 412 of the second stacked structure 410 and the floating gate layer 200.
The size of the opening in the second inter-gate dielectric layer 411 is not too large nor too small. If the opening is too large, the flatness of the second control gate layer 412 formed later will be affected, which is not beneficial to keeping the top of the second control gate layer 412 flush; if the opening is too small, the electrical connection performance between the second control gate layer 412 of the second stacked structure 410 and the floating gate layer 200 is correspondingly affected. For this reason, in the present embodiment, the size of the opening is 60nm to 100nm.
The first metal silicide layer 320 is a part of the floating gate sheet resistance structure for reducing the self resistance of the floating gate sheet resistance structure.
The second metal silicide layer 420 is used as part of the end interconnect structure 400 to enable electrical extraction of the end interconnect structure 400 and thus electrical connection with a subsequently formed end plug.
The contact of the second metal silicide layer 420 with the end plug 550 may reduce the contact resistance between the end interconnect structure 400 and the end plug 550, improve the resistance-capacitance (Resistance Capacitance, RC) delay, and facilitate the performance improvement of the formed floating gate sheet resistance structure, thereby enabling the performance improvement of the formed NAND flash memory device.
In this embodiment, the material of the first metal silicide layer 320 and the second metal silicide layer 420 is nickel silicon compound. In other embodiments, the materials of the first metal silicide layer and the second metal silicide layer can also be cobalt titanium compound or cobalt silicon compound, respectively.
The interlayer dielectric layer 500 is used to achieve electrical isolation between the end interconnect structure 400 and the chip resistor structure 300 and also to provide a process basis for forming end plugs.
In this embodiment, the interlayer dielectric layer 500 covers the end interconnection structure 400 and the chip resistor structure 300 and fills the gap between the end interconnection structure 400 and the chip resistor structure 300.
The interlayer dielectric layer 500 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 500 may be silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 500 is silicon oxide.
In this embodiment, the top of the interlayer dielectric layer 500 is higher than the top of the end interconnection structure 400 and the chip resistor structure 300, thereby providing a good process basis for the formation of the end plugs.
The end plug 550 is electrically connected to the end interconnection structure 400, and the end interconnection structure 400 is electrically connected to the floating gate layer 200, so that the end plug 550 is electrically connected to the floating gate layer 200.
The end plug 550 is electrically connected with the floating gate layer 200 through the end interconnection structure 400, and compared with the scheme that the end plug 550 is directly contacted with the floating gate layer 200, the height of the end plug 550 can be reduced, correspondingly, the process window of the end plug 550 can be increased, the process difficulty for forming the end plug 550 is reduced, and the shape quality of the formed end plug 550 is improved.
In addition, the end plug 550 is directly contacted with the second metal silicide layer 420 on top of the end interconnection structure 400, and the material of the second metal silicide layer 420 is nickel silicon compound, so that compared with the scheme that the end plug 550 is directly contacted with the floating gate layer 200, the contact resistance between the end plug 550 and the second metal silicide layer 420 can be reduced, and the electrical performance is improved.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure. Fig. 2 to 7 are schematic views of intermediate structures formed by steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 100 is provided, the substrate 100 including a first region I and a second region II.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures. The substrate may be a planar substrate or a three-dimensional substrate according to actual process conditions.
In this embodiment, the substrate 100 is a planar substrate. Specifically, the base 100 includes a substrate.
The substrate provides a process platform for the subsequent formation of flash memory. Specifically, the substrate is used to form a nand flash memory device.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 100 includes a first region I and a second region II, where the first region I and the second region II are disposed in parallel, and the second region II is located at two sides of the first region I.
In this embodiment, the first region I is used to form a chip resistor structure in a floating gate chip resistor (Floating Gate Sheet Resistor, FG-RS) structure in a NAND flash memory device, and the second region II is used to form an end interconnect structure and an end plug that electrically pull out the floating gate chip resistor structure.
The floating gate chip resistor structure acts as a resistor for the NAND flash memory device for providing resistance for the logical operation of the NAND flash memory device.
Referring to fig. 3, a floating gate layer 200 is formed on a substrate 100.
The floating gate layer 200 is used to provide a foundation for the subsequent formation of floating gate sheet resistance structures.
In this embodiment, the material of the floating gate layer 200 is polysilicon. In other embodiments, the floating gate layer 200 can also be made of other suitable materials, such as doped polysilicon, and the like.
The process of forming the floating gate layer 200 includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a furnace tube process. In this embodiment, the floating gate layer 200 is formed using a Chemical Vapor Deposition (CVD) process.
The chemical vapor deposition process has good deposition effect, high gap filling capability and capability of reducing gaps in the floating gate layer 200, so that the formed floating gate layer 200 has good appearance quality.
In this embodiment, before forming the floating gate layer 200 on the substrate 100, the method for forming a semiconductor structure further includes: a gate insulating layer 105 is formed on the substrate.
Accordingly, after the gate insulating layer 105 is formed, the floating gate layer 200 is formed on the gate insulating layer 105.
The gate insulating layer 105 serves to play an isolating role between the floating gate layer 200 and the substrate to prevent electrons in the floating gate layer 200 from entering the substrate.
In this embodiment, the material of the gate insulating layer 105 is silicon oxide. In other embodiments, the material of the gate insulating layer 105 can also be other dielectric materials such as silicon nitride.
In this embodiment, the gate insulating layer 105 is formed using a thermal oxidation process. In other embodiments, the gate insulation layer can also be formed using a deposition process or a furnace tube process. The deposition process comprises a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process.
Referring to fig. 4, a plurality of discrete stacked structures (not shown) are formed on the floating gate layer 200, and the stacked structure of the first region I is a first stacked structure 310, and the first stacked structure 310 includes a first inter-gate dielectric layer 311 and a first control gate layer 312 on the first inter-gate dielectric layer 311; the second region II has a second stacked structure 410, where the second stacked structure 410 includes a second inter-gate dielectric layer 411 and a second control gate layer 412 on the second inter-gate dielectric layer 411, and the second control gate layer 412 is electrically connected to the floating gate layer 200.
In this embodiment, the control gate layer of the stacked structure of the first region I is the first control gate layer 311, the inter-gate dielectric layer of the stacked structure of the first region I is the first inter-gate dielectric layer 312, the first control gate layer 311 and the first inter-gate dielectric layer 312 form the first stacked structure 310, and the first control gate layer 311 is isolated from the floating gate layer 200 by the first inter-gate dielectric layer 312.
The first stack structure 310 provides a basis for the subsequent formation of a chip resistor structure that together with the floating gate layer 200 forms an FG-RS structure.
In this embodiment, the control gate layer of the stacked structure of the second region II is a second control gate layer 412, the inter-gate dielectric layer of the stacked structure of the second region II is a second inter-gate dielectric layer 411, the second control gate layer 412 and the second inter-gate dielectric layer 411 form a second stacked structure 410, and the second control gate layer 412 is electrically connected to the floating gate layer 200.
Specifically, the second inter-gate dielectric layer 411 has an opening exposing the floating gate layer 200, and the second control gate layer 412 is further located in the opening, such that the second inter-gate dielectric layer 412 is in direct contact with the floating gate layer 200, thereby achieving electrical connection between the second control gate layer 412 and the floating gate layer 200.
The size of the opening in the second inter-gate dielectric layer 411 is not too large nor too small. If the opening is too large, the flatness of the subsequently formed control gate layer is affected, and the top of the control gate layer is not easy to keep flush; if the opening is too small, the electrical connection performance between the second control gate layer 412 and the floating gate layer 200 is affected accordingly. For this reason, in the present embodiment, the size of the opening is 60nm to 100nm.
The second stack 410 provides a basis for the subsequent formation of end interconnect structures for enabling electrical extraction of the FG-RS structure.
In this embodiment, the first stacked structure 310 and the second stacked structure 410 are formed in the same process step, so as to simplify the process operation and save the process cost.
Specifically, the step of forming the first and second stacked structures 310 and 410 includes: forming an inter-gate dielectric material layer on the floating gate layer 200; etching the inter-gate dielectric material layer of the second region II to form an opening; after forming the opening, forming a control gate material layer on the inter-gate dielectric material layer, wherein the control gate material layer is filled in the opening; the control gate material layer and the inter-gate dielectric material layer are patterned to form a first stack structure 310 on the substrate 100 in the first region I and a second stack structure 410 on the substrate 100 in the second region II.
In this embodiment, the inter-gate dielectric material layer has a multi-layer structure. Specifically, the inter-gate dielectric material layer is a silicon Oxide Nitride-silicon Oxide (ONO) structure.
Accordingly, the step of forming the inter-gate dielectric material layer includes: a first silicon oxide layer on the floating gate layer 200; forming a silicon nitride layer on the first silicon oxide layer; a second silicon dioxide layer is formed over the silicon nitride layer.
In this embodiment, an atomic layer deposition process is used to form an inter-gate dielectric material layer. In other embodiments, the formation of the gate dielectric material layer can also be a chemical vapor deposition process, a physical vapor deposition process, or the like.
In this embodiment, the opening is formed by a dry etching process. The dry etching process has the characteristic of anisotropic etching, so that the etching is more directional by selecting the dry etching process, and the dimensional accuracy of the formed opening is improved.
In this embodiment, the process of forming the control gate material layer is a chemical vapor deposition process. In other embodiments, the control gate material layer can also be formed using a physical vapor deposition process, an atomic layer deposition process, or a furnace tube process.
The step of patterning the control gate material layer and the inter-gate dielectric material layer comprises: forming a patterned mask layer on the control gate material layer; the control gate material layer and the inter-gate dielectric material layer are sequentially etched using the patterned mask layer as a mask to form a first stack structure 310 and a second stack structure 410.
And the process of sequentially etching the control gate material layer and the inter-gate dielectric material layer by taking the patterned mask layer as a mask is a dry etching process. The dry etching process has the characteristic of anisotropic etching, so that the etching is more directional by selecting the dry etching process, and the profile quality and the etching precision of the formed control gate layer and the inter-gate dielectric layer are improved.
Referring to fig. 5, a metal silicide process is performed on top of the first and second stacked structures 310 and 410, forming a first metal silicide layer 320 on top of the first stacked structure 310 and a second metal silicide layer 420 on top of the second stacked structure 410, the first stacked structure 310 and the first metal silicide layer 320 constituting the chip resistor structure 300, and the second stacked structure 410 and the second metal silicide layer 420 constituting the end interconnection structure 400.
The first metal silicide layer 320 is a part of the floating gate sheet resistance structure for reducing the self resistance of the floating gate sheet resistance structure.
The second metal silicide layer 420 is used as part of the end interconnect structure 400 to enable electrical extraction of the end interconnect structure 400 and thus electrical connection with a subsequently formed end plug.
The contact between the second metal silicide layer 420 and the end plug formed later can reduce the contact resistance between the end interconnection structure 400 and the end plug, improve the resistance-capacitance delay, and facilitate the improvement of the performance of the formed floating gate chip resistor structure, thereby improving the performance of the formed NAND flash memory device.
In this embodiment, the step of forming the first metal silicide layer 320 and the second metal silicide layer 420 includes: filling a sacrificial layer (not shown) between the first and second stacked structures 310 and 410, a top surface of the sacrificial layer being lower than top surfaces of the first and second stacked structures 310 and 410; forming a metal layer (not shown) covering the first and second stacked structures 310 and 410 where the sacrificial layer is exposed; performing a first annealing process on the metal layer, so that the first laminated structure 310 and the second laminated structure 410 where the metal layer and the sacrificial layer are exposed react respectively to form a first initial metal silicide layer and a second initial metal silicide layer; after forming the first initial metal silicide layer and the second initial metal silicide layer, removing unreacted residual metal layer; after removing the unreacted remaining metal layer, performing a second annealing process to convert the first and second initial metal silicide layers into the first and second metal silicide layers 320 and 420, respectively; after the first metal silicide layer 320 and the second metal silicide layer 420 are formed, the sacrificial layer is removed.
In this embodiment, the material of the metal layer is nickel. Accordingly, the material of the first metal silicide layer 320 and the second metal silicide layer 420 is nickel silicon compound. In other embodiments, the material of the metal layer is titanium or cobalt, and the material of the first metal silicide layer and the second metal silicide layer can also be cobalt-titanium compound or cobalt-silicon compound, respectively.
After forming the first metal silicide layer 320 and the second metal silicide layer 420, the first stacked structure 310 and the first metal silicide layer 320 on top thereof form the chip resistor structure 300, and the second stacked structure 410 and the second metal silicide layer 420 on top thereof form the end interconnect structure 400.
The chip resistor structure 300 is formed as part of a floating gate chip resistor structure, i.e., the floating gate layer 200 and the chip resistor structure 300 form a floating gate chip resistor structure in a NAND flash memory device.
The end interconnection structure 400 is used to realize electrical extraction of the floating gate chip resistor structure, so as to realize electrical connection between the floating gate chip resistor structure and other structures.
In this embodiment, the top portions of the end interconnection structure 400 and the chip resistor structure 300 are flush with each other, and the end plug formed in the interlayer dielectric layer 500 is electrically connected with the floating gate layer 200 through the end interconnection structure 400, so that the height of the end plug can be reduced correspondingly, the process window for forming the end plug is increased, the difficulty in forming the end plug is reduced, and the formed end plug has better shape and quality.
Referring to fig. 6, an interlayer dielectric layer 500 covering the sheet-like resistive structure 300 and the end interconnection structure 400 is formed on the floating gate layer 200.
The interlayer dielectric layer 500 is used to achieve electrical isolation between the end interconnect structure 400 and the chip resistor structure 300 and also to provide a process basis for forming end plugs.
In this embodiment, the interlayer dielectric layer 500 covers the end interconnection structure 400 and the chip resistor structure 300 and fills the gap between the end interconnection structure 400 and the chip resistor structure 300.
The interlayer dielectric layer 500 is made of an insulating material. Specifically, the material of the interlayer dielectric layer 500 may be silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 500 is silicon oxide.
In this embodiment, the top of the interlayer dielectric layer 500 is higher than the top of the end interconnection structure 400 and the chip resistor structure 300, thereby providing a good process basis for the formation of the end plugs.
The step of forming the interlayer dielectric layer 500 includes: forming an initial interlayer dielectric layer covering the sheet-like resistive structure 300 and the end interconnection structure 400 on the floating gate layer 200; an initial interlayer dielectric layer is formed to have a flat surface by a planarization process, and an interlayer dielectric layer 500 is formed.
In this embodiment, a plasma enhanced chemical vapor deposition process is used to initiate the interlayer dielectric layer. In other embodiments, other types of deposition processes can be used to form the initial interlayer dielectric layer, such as an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or the like.
In this embodiment, the planarization process used to planarize the initial interlayer dielectric layer is a chemical mechanical polishing process. In other embodiments, the planarization process employed to provide the initial interlevel dielectric layer with a planar surface can also be an etch back process or the like.
Referring to fig. 7, an end plug 550 on the end interconnection structure 400 is formed in the interlayer dielectric layer 500, and the end plug 550 is electrically connected to the end interconnection structure 400.
The end plug 550 is electrically connected to the end interconnection structure 400, and the end interconnection structure 400 is electrically connected to the floating gate layer 200, so that the end plug 550 is electrically connected to the floating gate layer 200.
The end plug 550 is electrically connected with the floating gate layer 200 through the end interconnection structure 400, and compared with the scheme that the end plug 550 is directly contacted with the floating gate layer 200, the height of the end plug 550 can be reduced, correspondingly, the process window of the end plug 550 can be increased, the process difficulty for forming the end plug 550 is reduced, and the shape quality of the formed end plug 550 is improved.
In addition, the end plug 550 is directly contacted with the second metal silicide layer 420 on top of the end interconnection structure 400, and the material of the second metal silicide layer 420 is nickel silicon compound, so that compared with the scheme that the end plug 550 is directly contacted with the floating gate layer 200, the contact resistance between the end plug 550 and the second metal silicide layer 420 can be reduced, and the electrical performance is improved.
Specifically, the step of forming end plug 550 includes: forming a contact hole (not shown) in the interlayer dielectric layer 500 on the end portion interconnection structure 400; the contact hole is filled with a conductive medium to form an end plug 550 located in the contact hole.
In this embodiment, the process of forming the end plugs 550 within the contact holes includes a selective deposition process.
By forming the end plugs 550 within the contact holes using a selective deposition process, the volume of the end plugs 550 may be increased, thereby facilitating a reduction in contact resistance and an increase in electrical performance with a continued reduction in device feature size.
Specifically, the selective deposition process is a selective chemical vapor deposition (selective CVD) process. The selective chemical vapor deposition process has better selective deposition effect and higher process stability.
It should be noted that, the material of the end plug 550 is tungsten, so that the end plug 550 can be formed by selective deposition, and the end plug 550 formed by selective deposition can achieve lower self resistance and contact resistance.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
a floating gate layer on the substrate;
a chip resistor structure located on the floating gate layer of the first region;
an end interconnection structure located on the floating gate layer of the second region;
an interlayer dielectric layer on the floating gate layer and covering the chip resistor structure and the end interconnection structure;
and the end plug is positioned in the interlayer dielectric layer on the end interconnection structure and is electrically connected with the end interconnection structure.
2. The semiconductor structure of claim 1, wherein the chip resistor structure comprises a first stack structure and a first metal silicide layer on top of the first stack structure; the first lamination structure comprises a first inter-gate dielectric layer and a first control gate layer positioned on the first inter-gate dielectric layer;
the end interconnection structure comprises a second laminated structure and a second metal silicide layer positioned on the top of the second laminated structure; the second lamination structure comprises a second inter-gate dielectric layer and a second control gate layer positioned on the second inter-gate dielectric layer, and the second control gate layer is electrically connected with the floating gate layer.
3. The semiconductor structure of claim 2, wherein the second inter-gate dielectric layer has an opening therein exposing the floating gate layer, the second control gate layer further being positioned within the opening such that the second control gate layer is in contact with the floating gate layer.
4. The semiconductor structure of claim 3, wherein the opening has a size of 60nm to 100nm.
5. The semiconductor structure of claim 1, wherein the end plug penetrates an interlayer dielectric layer over the end interconnect structure such that the end plug contacts the end interconnect structure.
6. The semiconductor structure of claim 1, wherein the base comprises a substrate, the semiconductor structure further comprising:
and a gate insulating layer between the substrate and the floating gate layer.
7. The semiconductor structure of claim 6, wherein the material of the gate insulating layer comprises silicon oxide.
8. The semiconductor structure of claim 1, wherein the material of the end plug comprises at least one of tungsten and copper.
9. The semiconductor structure of claim 1, wherein the material of the floating gate layer comprises polysilicon.
10. The semiconductor structure of claim 2, wherein the material of the first control gate layer and the second control gate layer comprises polysilicon.
11. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, and a floating gate layer is formed on the substrate;
forming a chip resistor structure on the floating gate layer of the first region;
forming an end interconnection structure on the floating gate layer of the second region
Forming an interlayer dielectric layer covering the chip resistor structure and the end interconnection structure on the floating gate layer;
an end plug is formed in the interlayer dielectric layer on the end interconnection structure, and the end plug is electrically connected with the end interconnection structure.
12. The method of forming a semiconductor structure of claim 11, wherein the step of forming the chip resistor structure and the end interconnect structure comprises:
forming a plurality of discrete laminated structures on the floating gate layer, wherein the laminated structure of the first region is a first laminated structure, and the first laminated structure comprises a first inter-gate dielectric layer and a first control gate layer positioned on the first inter-gate dielectric layer; the second region has a second laminated structure, the second laminated structure comprises a second inter-gate dielectric layer and a second control gate layer positioned on the second inter-gate dielectric layer, and the second control gate layer is electrically connected with the floating gate layer;
and performing a metal silicide process on the tops of the first laminated structure and the second laminated structure to form a first metal silicide layer positioned on the top of the first laminated structure and a second metal silicide layer positioned on the top of the second laminated structure, wherein the first laminated structure and the first metal silicide layer form a chip resistor structure, and the second laminated structure and the second metal silicide layer form an end interconnection structure.
13. The method of claim 12, wherein the second inter-gate dielectric layer has an opening therein exposing a portion of the floating gate layer, the second control gate layer further being located within the opening such that the second control gate layer is electrically connected to the floating gate layer;
the step of forming the first and second stacked structures includes:
forming an inter-gate dielectric material layer on the floating gate layer;
etching the inter-gate dielectric material layer of the second region to form the opening;
forming a control gate material layer covering the inter-gate dielectric material layer after forming the opening, wherein the control gate material layer also fills the opening;
and patterning the control gate material layer and the inter-gate dielectric material layer to form the first laminated structure and the second laminated structure.
14. The method of forming a semiconductor structure of claim 11, wherein the base comprises a substrate;
before forming the floating gate layer, the method further comprises: forming a gate insulating layer on the substrate;
after forming the floating gate layer, the floating gate layer is located on the gate insulator.
15. The method of claim 14, wherein the process of forming the gate insulating layer is an atomic layer deposition process.
16. The method of claim 14, wherein the material of the gate insulating layer comprises silicon oxide.
17. The method of claim 11, wherein the floating gate layer material comprises polysilicon.
18. The method of forming a semiconductor structure of claim 11, wherein forming the end plug comprises:
forming a contact hole above the end interconnection structure in the interlayer dielectric layer;
and filling a conductive medium in the contact hole to form the end plug.
19. The method of claim 11, wherein the material of the end plug comprises at least one of tungsten and copper.
20. The method of claim 11, wherein the interlayer dielectric layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
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