CN117423694B - GaN HEMT device with stable high-frequency through-flow and preparation method thereof - Google Patents
GaN HEMT device with stable high-frequency through-flow and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 229910002704 AlGaN Inorganic materials 0.000 claims description 22
- 238000004140 cleaning Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000004026 adhesive bonding Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 4
- 238000003780 insertion Methods 0.000 claims description 4
- 230000037431 insertion Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000007246 mechanism Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910019080 Mg-H Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
A GaN HEMT device with stable high-frequency through-flow and a preparation method thereof relate to the technical field of semiconductors. The invention ensures that the device has the same working mechanism under the high-frequency and low-frequency conditions, solves the problem that the on-resistance of the device is increased under the high-frequency conditions due to the partial reasons, and ensures that the on-resistance and the current capacity of the device are more stable under the high-frequency and low-frequency conditions.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a GaN HEMT device with stable high-frequency through current and a preparation method thereof.
Background
In the technical field of power electronic devices, a third-generation semiconductor represented by GaN and SiC is more and more paid attention to, wherein GaN has the advantages of large forbidden bandwidth, high critical breakdown field strength, high electron mobility and the like, and has strong application potential in the markets of power devices such as fast charge, data centers, OBC, solar inverters and the like.
The main application form of GaN in power devices is GaN HEMT devices, and the first AlGaN/GaN High Electron Mobility Transistor (HEMT) is manufactured by Khan et al in 1993, and GaN HEMT devices with horizontal structures are receiving attention in terms of electrical performance and lower energy consumption than Si devices.
The GaN HEMT device has better performance than the traditional Si device, wherein the P-GaN enhanced GaN HEMT device takes the dominant role due to the normally-off characteristic of the device, but the current collapse effect of the P-GaN enhanced GaN HEMT device is very serious at high frequency, and the current collapse effect of the P-GaN enhanced GaN HEMT device is greatly influenced by different working mechanisms of the device at high frequency and low frequency.
Disclosure of Invention
Aiming at the problems, the invention provides a GaNHEMT device with stable high-frequency through-flow and a preparation method thereof, which can reduce the high-frequency current collapse effect of a P-GaN enhanced GaN HEMT device and keep the on-resistance of the device stable under high-frequency and low-frequency conditions.
The technical scheme of the invention is as follows:
a GaN HEMT device with stable high-frequency through-flow and a preparation method thereof comprise the following steps:
step S100, preparing a high-resistance GaN layer on an epitaxial wafer by using a passivation technology, and depositing an isolation layer;
step S200, preparing an ISO isolation region on an epitaxial wafer in a passive region;
step S300, preparing a first D electrode groove in a D electrode area of the epitaxial wafer, wherein the section width of the first D electrode groove is smaller than the section width of a P-GaN layer in the D electrode area; preparing an S electrode groove in the S electrode area without retaining the P-GaN layer;
step S400, preparing a first D electrode and a first S electrode respectively in a first D electrode groove and an S electrode groove on an epitaxial wafer;
step S500, preparing a G electrode groove and a second D electrode groove on a G electrode area and a D electrode area on an epitaxial wafer respectively;
step S600, preparing a G electrode, a second D electrode and a second S electrode respectively in a G electrode groove, a first D electrode groove, a second D electrode groove and an S electrode groove on an epitaxial wafer; and finishing the preparation of the whole device.
Specifically, step S100 includes:
step S110, manufacturing an epitaxial wafer by using a Si, siC or GaN substrate;
step S120, through epitaxial wafer cleaning, glue spreading, photoetching and developing, a D, S, G electrode area on the epitaxial wafer is protected by photoresist, and a P-GaN layer passivation is carried out on an area which is not protected by the photoresist and is outside the D, S, G electrode area, so that the P-GaN layer is converted into a high-resistance GaN layer 9, then the photoresist is cleaned, and an isolation layer with corresponding thickness is deposited;
the epitaxial wafer sequentially comprises a substrate, an AlN spacing layer, an Al component gradual change buffer AlGaN layer, a C-doped high-resistance GaN layer, a GaN channel layer, an AlN inserting layer, an AlGaN barrier layer and a P-GaN layer from bottom to top.
Specifically, step S200 includes:
step S210, protecting an active area of a device by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
and S220, using high-energy ions to implant into the inactive region of the epitaxial wafer, destroying the internal lattice structures of the GaN channel layer, the AlN insertion layer and the AlGaN barrier layer in the inactive region, changing the internal lattice structures into a high-resistance state, and preparing an ISO isolation region.
Specifically, step S300 includes:
step S310, cleaning, gluing, photoetching and developing the epitaxial wafer to protect the outer parts of the D electrode area and the S electrode area by using photoresist;
step S320, etching part of the D electrode area and the S electrode area by using ICP dry etching, and preparing a first D electrode groove in the part of the D electrode area, wherein the section width of the first D electrode groove is smaller than the section width of the P-GaN layer of the D electrode area; an S electrode groove is formed in the S electrode area without retaining the P-GaN layer, and then the photoresist is washed away.
Specifically, step 400 includes:
the first D electrode and the first S electrode are prepared in the first D electrode groove and the S electrode groove, respectively, using a metal stripping process or a metal etching process.
Specifically, step 500 includes:
step S510, protecting the G electrode area and the rest D electrode area by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
and step S520, etching the G electrode area and the residual D electrode area by using an ICP dry etching method, respectively preparing a G electrode groove and a second D electrode groove in the G electrode area and the residual D electrode area, and then cleaning the photoresist.
Specifically, step 600 includes:
preparing a G electrode, a second D electrode and a second S electrode in the G electrode groove, the first D electrode groove, the second D electrode groove and the S electrode groove respectively by using a metal stripping process or a metal etching process;
and finishing the preparation of the whole device.
The utility model provides a high frequency through-flow stable gaN HEMT device which characterized in that includes:
epitaxial wafer and isolation layer;
the P-GaN layers outside the G, D, S electrode area on the epitaxial wafer are passivated into high-resistance GaN layers, and the section width of the P-GaN layer in the G, D, S electrode area is equal to that of the P-GaN layer in the G, D, S electrode area;
the passive region on the epitaxial wafer is provided with an ISO isolation region which extends downwards from the upper surface of the isolation layer to the C-doped high-resistance GaN layer;
the epitaxial wafer is provided with a first D electrode groove and an S electrode groove which extend downwards from the upper surface of the isolation layer to the inside of the AlGaN barrier layer, the section width of the first D electrode groove is smaller than the section width of the D electrode area, and the section width of the S electrode groove is equal to the section width of the D electrode area;
the epitaxial wafer is provided with a G electrode groove and a second D electrode groove which extend downwards from the upper surface of the isolation layer to the upper surface of the P-GaN layer, the section width of the G electrode groove is equal to the section width of the G electrode area, and the section width of the second D electrode groove is smaller than the section width of the D electrode area;
the second D electrode groove section width is the P-GaN layer section width reserved in the D electrode area, the P-GaN layer section width reserved in the D electrode area is too small, the gain effect provided by the invention is not obvious, the too large section width can cause the breakdown voltage of the device to be reduced, the section width has a certain range, and the sum of the first D electrode groove section width and the second D electrode groove section width is equal to the section width of the D electrode area;
the first D electrode groove and the first S electrode groove are internally provided with a first D electrode and a first S electrode, the upper surfaces of the first D electrode and the first S electrode are parallel to the upper surface of the P-GaN layer, and good ohmic contact is formed between the first D electrode and the first S electrode and between the first D electrode and the second S electrode and between the first D electrode and the first S electrode and the second D electrode and the second S electrode and the second D electrode and the second S electrode and the first S electrode and the second D electrode and the second electrode and the first S electrode and the second S;
the G electrode groove, the first D electrode groove, the second D electrode groove and the S electrode groove are internally provided with a G electrode, a second D electrode and a second S electrode, the upper surfaces of the G electrode, the second D electrode and the S electrode are parallel to the isolating layer, the lower surface of the G electrode is contacted with the upper surface of the P-GaN layer, the lower surface of the second D electrode, the P-GaN layer and the upper surface of the first D electrode are contacted, and the lower surface of the second S electrode is contacted with the upper surface of the first S electrode;
the G electrode and the P-GaN layer below form Schottky contact, the second D electrode and the P-GaN layer form Schottky contact, electrical interconnection is formed between the second D electrode and the first D electrode, and electrical interconnection is formed between the second S electrode and the first S electrode.
According to the invention, a sum channel is creatively formed in a D electrode area, a Schottky diode is formed by a second D electrode and a P-GaN layer, a PiN diode is formed by a P-GaN layer, an AlGaN barrier layer and a GaN intrinsic layer, under an off-state condition, partial two-dimensional electron gas which is supposed to be attracted to the D electrode under the off-state condition is shunted to the PiN diode formed by the P-GaN layer, the AlGaN barrier layer and the GaN intrinsic layer by a first D electrode high voltage, the partial two-dimensional electron gas which is attracted to the first D electrode under the off-state condition enters the Schottky diode formed by the second D electrode and the P-GaN layer by the second D electrode high voltage, and when the two-dimensional electron gas is stored in the Schottky diode formed by the second D electrode and the P-GaN layer, the P-GaN barrier layer and the PiN intrinsic layer are stored in the PiN diode, compared with the P-GaN layer which is stored in the ohmic metal of the D electrode under the off-state condition, the time constant released under the off-state condition is much larger, and even if the device works under the low-frequency condition, the second D electrode, the P-GaN layer and the P-GaN layer are formed by the Schottky diode under the off-state condition, the on-frequency condition can be more stable, and the on-frequency condition can be solved, and the on-frequency condition of the PiN diode is not formed under the high-frequency condition, and the on-frequency condition is guaranteed.
Drawings
FIG. 1 is a process flow diagram of the present invention;
fig. 2 is a schematic diagram of step S100;
fig. 3 is a schematic diagram of step S200;
fig. 4 is a schematic diagram of step S300;
fig. 5 is a schematic diagram of step S400;
fig. 6 is a schematic diagram of step S500;
fig. 7 is a schematic diagram of step S600;
in the figure, 1 is a substrate, 2 is an AlN spacer layer, 3 is an Al component gradient buffer AlGaN layer, 4 is a C-doped high-resistance GaN layer, 5 is a GaN channel layer, 6 is an AlN insertion layer, 7 is an AlGaN barrier layer, 8 is a P-GaN layer, 9 is a high-resistance GaN layer, 10 is an isolation layer, 11 is an ISO isolation region, 12 is an S electrode slot, 13 is a first D electrode slot, 14 is a first S electrode, 15 is a first D electrode, 16 is a G electrode slot, 17 is a second D electrode slot, 18 is a G electrode, 19 is a second S electrode, and 20 is a second D electrode.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
Embodiments of the present invention are described below with reference to fig. 1-7;
a GaN HEMT device with stable high-frequency through-flow and a preparation method thereof comprise the following steps:
step S100, preparing a high-resistance GaN layer 9 on an epitaxial wafer by using a passivation technology, and depositing an isolation layer 10, as shown in reference to FIG. 2;
step S110, manufacturing an epitaxial wafer by using a Si, siC or GaN substrate;
the epitaxial wafer sequentially comprises a substrate 1, an AlN spacing layer 2, an Al component gradual change buffer AlGaN layer 3, a C-doped high-resistance GaN layer 4, a GaN channel layer 5, an AlN inserting layer 6, an AlGaN barrier layer 7 and a P-GaN layer 8 from bottom to top;
step S120, through epitaxial wafer cleaning, glue spreading, photoetching and developing, a D, S, G electrode area on the epitaxial wafer is protected by photoresist, a P-GaN layer 8 is passivated in an area which is not protected by the photoresist and is outside a D, S, G electrode area, the P-GaN layer 8 is converted into a high-resistance GaN layer 9, then the photoresist is cleaned, and an isolation layer 10 with corresponding thickness is deposited;
correspondingly, the section width of the D, S, G electrode area is determined according to specific electrical design, the section width ranges from 0.1um to 20um, light ions such as H, F and the like can be used for passivating the P-GaN layer 8 outside the D, S, G electrode area without using a photoresist protection area to form the section width of the high-resistance GaN layer 9 among the high-resistance GaN layers 9,D, G and S, G electrode areas, the section width ranges from 1um to 100um according to specific electrical design, the isolation layer 10 mainly plays a role in protection, the thickness meets the condition that the isolation layer 10 has small additional stress on an epitaxial wafer, and the thickness range is set to 10nm to 10000nm.
In this example, the sectional widths of the G electrode region were set to 2um, the sectional widths of the D and S electrodes were set to 5um, the Si-based epitaxial wafer was used, the P-GaN layer 8 was passivated with H ions, mg in the H ions and P-GaN formed Mg-H complex, the P-GaN layer 8 was converted into high-resistance GaN layers 9,D, the widths of the high-resistance GaN layer 9 between the G and S, G electrode regions were 20um and 2.5um, respectively, and Si was used 3 N 4 As the isolation layer 10, si performs isolation and protection functions 3 N 4 The layer thickness is 100nm and figure 2 shows the cross-sectional structure of one repeating unit of the active region of the device after preparing the high-resistance GaN layer 9 and depositing the spacer layer 10.
S200, preparing an ISO isolation region 11 on an epitaxial wafer in a passive region, and referring to FIG. 3;
s210, protecting an active area of a device by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
s220, using high-energy ions to implant into an epitaxial wafer passive region, destroying the internal lattice structures of a GaN channel layer 5, an AlN insertion layer 6 and an AlGaN barrier layer 7 in the passive region, changing the internal lattice structures into a high-resistance state, and preparing an ISO isolation region 11 by taking an electric isolation effect;
correspondingly, H, F plasma can be used for injecting light ions into the passive region of the epitaxial wafer to perform an ISO isolation process, the width of the isolation region can meet the electrical isolation effect of the active region, and the width range is set to be 1-1000um;
in this example, high energy ion F implantation was used at an angle of 7 degrees, three implants were performed at energies and doses of 140 KeV and 1.2e, respectively 14 cm -3 80 KeV and 0.6e 14 cm -3 40 KeV and 0.4e 14 cm -3 The ISO isolation region width is 20um and fig. 3 shows the surface structure of the device after the ISO isolation region 11 is fabricated.
S300, preparing a first D electrode groove 13 in a D electrode area of the epitaxial wafer part, wherein the cross section width of the first D electrode groove 13 is smaller than that of the P-GaN layer 8 in the D electrode area; preparing an S electrode groove 12 in the S electrode region without retaining the P-GaN layer 8, as shown with reference to FIG. 4;
s310, protecting part of the outer parts of the electrode areas D and S by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
s320, etching the partial D electrode area and the partial S electrode area by using ICP dry etching, and preparing a first D electrode groove 13 in the partial D electrode area, wherein the section width of the first D electrode groove 13 is smaller than the section width of the P-GaN layer 8 in the D electrode area; preparing an S electrode groove 12 in the S electrode area without reserving the P-GaN layer 8, and then cleaning photoresist;
accordingly, the depths of the first D electrode groove 13 and the S electrode groove 12 extend downwards from the upper surface of the isolation layer 10 to the inside of the AlGaN barrier layer 7, the cross-sectional width of the first D electrode groove 13 is smaller than the cross-sectional width of the D electrode region, and the cross-sectional width of the S electrode groove 12 is equal to the cross-sectional width of the D electrode region;
this example uses Cl 2 Performing ICP dry etching at etching rate of 10nm/min to ensure etching accuracy, si 3 N 4 The thickness of the layer 10 is 100nm, the thickness of the p-GaN layer 8 is 80nm, the thickness of the AlGaN barrier layer 7 is 20nm, the lower surfaces of the first D electrode groove 13 and the S electrode groove 12 are arranged at the position 10nm below the upper surface of the AlGaN barrier layer 7, so that the groove depth is 100nm+80nm+10nm=190 nm, the etching time is 19min, the etching depth is 190nm, the width of the S electrode groove 12 is 5um, the width of the first D electrode groove 13 is 3um, and fig. 4 shows the cross-sectional structure of one repeating unit of the device active region after the first D electrode groove 13 and the S electrode groove 12 are prepared.
S400, preparing a first D electrode 15 and a first S electrode 14 in the first D electrode groove 13 and the S electrode groove 12 on the epitaxial wafer, respectively, as shown in fig. 5;
s410, optionally, using a metal stripping process, cleaning, gumming, photoetching and developing an epitaxial wafer to protect the areas outside the first D electrode groove 13 and the S electrode groove 12, depositing ohmic contact metal with corresponding thickness in the first D electrode groove 13 and the S electrode groove 12, preparing a first D electrode 15 and a first S electrode 14, and then cleaning the photoresist;
s420, optionally, a metal etching process is used, ohmic contact metal with corresponding thickness is deposited on an epitaxial wafer, photoresist is used for protecting the areas of the first D electrode groove 13 and the S electrode groove 12 through photoresist coating, photoetching and developing of the epitaxial wafer, the metal outside the areas of the first D electrode groove 13 and the S electrode groove 12 is etched by ICP dry etching, the etching depth is not less than the deposited ohmic contact metal with corresponding thickness, the first D electrode 15 and the first S electrode 14 are prepared, and then the photoresist is cleaned;
accordingly, the upper surfaces of the first D electrode 15 and the first S electrode 14 are parallel to the upper surface of the P-GaN layer 8, the cross-sectional widths of the first D electrode 15 and the first S electrode 14 are equal to the cross-sectional widths of the first D electrode groove 13 and the S electrode groove 12, and good ohmic contact is formed with the two-dimensional electron gas below.
In this embodiment, a metal stripping process is used, through epitaxial wafer cleaning, glue spreading, photolithography and developing, photoresist is used to protect the areas outside the first D electrode slot 13 and the S electrode slot 12, 10nmti+80nmal is deposited in the first D electrode slot 13 and the S electrode slot 12 as ohmic contact metal, the first D electrode 15 and the first S electrode 14 are prepared, then the photoresist is cleaned, high-temperature annealing is performed at 850 ℃ for 30S to enable the ohmic contact metal of the first D electrode 15 and the first S electrode 14 to be connected with two-dimensional electron gas below, good ohmic contact is formed, at this time, the upper surfaces of the first D electrode 15 and the first S electrode 14 are parallel to the upper surface of the P-GaN layer 8, the cross-sectional widths of the first D electrode 15 and the first S electrode 14 are 3um and 5um respectively, and fig. 5 shows the cross-sectional structure of one repeating unit of the device active area after the first D electrode 15 and the first S electrode 14 are prepared.
S500, preparing a G electrode groove 16 and a second D electrode groove 17 on the epitaxial wafer in the G electrode area and the residual D electrode area respectively, and referring to FIG. 6;
s510, protecting the G electrode area and the rest D electrode area outside by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
and S520, etching the G electrode area and the residual D electrode area by using ICP dry etching, respectively preparing a G electrode groove 16 and a second D electrode groove 17 in the G electrode area and the residual D electrode area, and then cleaning the photoresist.
Correspondingly, the depths of the G electrode groove 16 and the second D electrode groove 17 extend downwards from the upper surface of the isolation layer 10 to the upper surface of the P-GaN layer 8, the section width of the G electrode groove 16 is equal to the section width of the G electrode area, the section width of the second D electrode groove 17 is smaller than the section width of the D electrode area, the section width of the second D electrode groove 17 is the section width of the P-GaN layer 8 reserved in the D electrode area, the section width of the P-GaN layer 8 reserved in the D electrode area is too small, the gain effect proposed by the invention is not obvious, the breakdown voltage of a device is reduced due to the too large section, the section width range of the P-GaN layer 8 reserved in the D electrode area is set to be 1-5um, and the sum of the section widths of the first D electrode groove 13 and the second D electrode groove 17 is equal to the section width of the D electrode area;
this example uses Cl 2 Performing ICP dry etching at etching rate of 10nm/min to ensure etching accuracy, si 3 N 4 The thickness of the layer 10 is 100nm, the depths of the G electrode trench 16 and the second D electrode trench 17 are 100nm, so that the etching time is 10min, the etching depth is 100nm, the width of the G electrode trench 16 is 2um, the cross-sectional width of the second D electrode trench 17 is 2um, the cross-sectional width of the P-GaN layer 8 reserved in the D electrode region is 2um, and fig. 6 shows the cross-sectional structure of a repeating unit of the device active region after the G electrode trench 16 and the second D electrode trench 17 are prepared.
G electrode 18, second D electrode 20 and second S electrode 19 are respectively prepared in G electrode groove 16, first and second D electrode grooves 13, 17 and S electrode groove 12 on the epitaxial wafer; the whole device is prepared, and the whole device is shown in FIG. 7;
s610, optionally, using a metal lift-off process, cleaning, gumming, photoetching and developing the epitaxial wafer to protect the areas outside the G electrode groove 16, the first and second D electrode grooves 13 and 17 and the S electrode groove 12, depositing schottky contact metals with corresponding thicknesses in the G electrode groove 16, the first and second D electrode grooves 13 and 17 and the S electrode groove 12, respectively preparing the G electrode 18, the second D electrode 20 and the second S electrode 19, and then cleaning the photoresist;
s620, optionally, a metal etching process is used, schottky contact metal with corresponding thickness is deposited firstly, photoresist is used for protecting areas of the G electrode groove 16, the first D electrode groove 13, the second D electrode groove 17 and the S electrode groove 12 through epitaxial wafer gluing, photoetching and developing, metal outside the areas of the G electrode groove 16, the first D electrode groove 13, the second D electrode groove 17 and the S electrode groove 12 is etched by ICP dry etching, the etching depth is not smaller than the deposited schottky contact metal with corresponding thickness, and the G electrode 18, the second D electrode 20 and the second S electrode 19 are respectively prepared, and then the photoresist is cleaned;
correspondingly, the upper surfaces of the G electrode 18, the second D electrode 20 and the second S electrode 19 are parallel to the isolation layer 10, the lower surface of the G electrode 18 is in contact with the upper surface of the P-GaN layer 8, the cross-sectional width is equal to that of the G electrode groove 16, the lower surface of the second D electrode 20 is in contact with the upper surface of the P-GaN layer 8 and the first D electrode 15, the cross-sectional width is equal to the sum of the cross-sectional widths of the first and second D electrode grooves 13 and 17, the lower surface of the second S electrode 19 is in contact with the upper surface of the first S electrode 14, and the cross-sectional width is equal to that of the S electrode groove 12;
in this embodiment, a metal stripping process is used, through epitaxial wafer cleaning, glue spreading, photolithography and developing, photoresist is used to protect the areas outside the G electrode slot 16, the first and second D electrode slots 13 and 17 and the S electrode slot 12, schottky contact metal is made in the G electrode slot 16, the first and second D electrode slots 13 and 17 and the S electrode slot 12 by 40nmni+60nmau, the G electrode 18, the second D electrode 20 and the second S electrode 19 are prepared respectively, then the photoresist is cleaned, at this time, the upper surfaces of the G electrode 18, the second D electrode 20 and the second S electrode 19 are parallel to the isolation layer 10, the lower surface of the G electrode 18 is in contact with the upper surface of the P-GaN layer 8, the cross-sectional width is 2um, the lower surface of the second D electrode 20 is in contact with the upper surface of the P-GaN layer 8 and the first D electrode 15, the cross-sectional width is 5um, the lower surface of the second S electrode 19 is in contact with the upper surface of the first S electrode 14, and the cross-sectional width is 5um;
fig. 7 shows a cross-sectional structure of one repeating unit of the active region of the device after the G electrode 18, the second D electrode 20 and the second S electrode 19 are prepared, after the whole device is prepared.
Further introduce the device structure of this scheme:
referring to fig. 7, a GaN HEMT device with stable high-frequency current, includes:
epitaxial wafer and isolation layer 10;
the P-GaN layers 8 outside the G, D, S electrode area on the epitaxial wafer are passivated to form high-resistance GaN layers 9,G and D, S electrode area P-GaN layers 8, and the section widths of the electrode areas G, D, S are equal;
the passive region on the epitaxial wafer is provided with an ISO isolation region 11 which extends downwards from the upper surface of the isolation layer 10 to the C-doped high-resistance GaN layer 4;
the epitaxial wafer is provided with a first D electrode groove 13 and an S electrode groove 12 which extend downwards from the upper surface of the isolation layer 10 to the inside of the AlGaN barrier layer 7, the section width of the first D electrode groove 13 is smaller than the section width of the D electrode area, and the section width of the S electrode groove 12 is equal to the section width of the D electrode area;
the epitaxial wafer is provided with a G electrode groove 16 and a second D electrode groove 17 which extend downwards from the upper surface of the isolation layer 10 to the upper surface of the P-GaN layer 8, the section width of the G electrode groove 16 is equal to the section width of the G electrode area, and the section width of the second D electrode groove 17 is smaller than the section width of the D electrode area;
the sum of the cross-sectional widths of the first D electrode slot 13 and the second D electrode slot 17 is equal to the cross-sectional width of the D electrode area;
a first D electrode 15 and a first S electrode 14 are arranged in the first D electrode groove 13 and the S electrode groove 12, the upper surfaces of the first D electrode 15 and the first S electrode 14 are parallel to the upper surface of the P-GaN layer 8, and good ohmic contact is formed between the first D electrode 15 and the first S electrode 14 and the lower two-dimensional electron gas;
the G electrode groove 16, the first D electrode grooves 13 and 17 and the S electrode groove 12 are internally provided with a G electrode 18, a second D electrode 20 and a second S electrode 19, the upper surfaces of the G electrode 18 and the P-GaN layer 8 are in contact, the lower surfaces of the second D electrode 20 and the P-GaN layer 8 are in contact with the upper surface of the first D electrode 15, and the lower surfaces of the second S electrode 19 and the first S electrode 14 are in contact;
the G electrode 18 and the underlying P-GaN layer 8 form a schottky contact, the second D electrode 20 and the P-GaN layer 8 form a schottky contact, and the first D electrode 15 form an electrical interconnection, and the second S electrode 19 and the first S electrode 14 form an electrical interconnection.
According to the invention, a sum channel is creatively formed in a D electrode area, a Schottky diode is formed by a second D electrode and a P-GaN layer, a PiN diode is formed by a P-GaN layer, an AlGaN barrier layer and a GaN intrinsic layer, under an off-state condition, partial two-dimensional electron gas which is supposed to be attracted to the D electrode under the off-state condition is shunted to the PiN diode formed by the P-GaN layer, the AlGaN barrier layer and the GaN intrinsic layer by a first D electrode high voltage, the partial two-dimensional electron gas which is attracted to the first D electrode under the off-state condition enters the Schottky diode formed by the second D electrode and the P-GaN layer by the second D electrode high voltage, and when the two-dimensional electron gas is stored in the Schottky diode formed by the second D electrode and the P-GaN layer, the P-GaN barrier layer and the PiN intrinsic layer are stored in the PiN diode, compared with the P-GaN layer which is stored in the ohmic metal of the D electrode under the off-state condition, the time constant released under the off-state condition is much larger, and even if the device works under the low-frequency condition, the second D electrode, the P-GaN layer and the P-GaN layer are formed by the Schottky diode under the off-state condition, the on-frequency condition can be more stable, and the on-frequency condition can be solved, and the on-frequency condition of the PiN diode is not formed under the high-frequency condition, and the on-frequency condition is guaranteed.
The GaN HEMT device with stable high-frequency through current (shown in reference to fig. 7) is compatible with the preparation process of the P-GaN enhanced GaN HEMT device with a normal structure, and no extra process steps are added.
Under the same process conditions, referring to table 1, the high-frequency through-flow stable GaN HEMT device (the device) is more stable in on-resistance and through-flow capacity under the high-frequency condition, and has more obvious advantages than the P-GaN enhanced GaN HEMT device (the comparison device) with a normal structure, wherein the ratio of the dynamic resistance under the 100 KHZ frequency condition to the dynamic resistance under the 10KHZ frequency condition is increased from 1.5 to 1.3, the ratio of the dynamic resistance under the 500KHZ frequency condition to the dynamic resistance under the 10KHZ frequency condition is increased from 1.8 to 1.4, and the device is more stable in on-resistance and through-flow capacity under the high-frequency condition, and is higher in working frequency, so that the application of the P-GaN enhanced GaN HEMT device in the high-frequency field can be promoted effectively.
Table 1:
| Sample | dynamic resistance ratio @100 KHZ VS 10HZ | Dynamic resistance ratio @500 KHZ VS 10HZ |
| The device | 1.3 | 1.4 |
| Contrast device | 1.5 | 1.8 |
For the purposes of this disclosure, the following points are also described:
the drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The preparation method of the GaN HEMT device with the stable high-frequency through-flow is characterized by comprising the following steps of:
step S100, preparing a high-resistance GaN layer (9) on an epitaxial wafer, and depositing an isolation layer (10);
step S200, preparing an ISO isolation region (11) on an epitaxial wafer in a passive region;
step S300, preparing a first D electrode groove (13) in a D electrode area of an epitaxial wafer; preparing an S electrode groove (12) in the S electrode area without reserving a P-GaN layer (8);
step S400, preparing a first D electrode (15) and a first S electrode (14) respectively in a first D electrode groove (13) and an S electrode groove (12) on an epitaxial wafer;
step S500, preparing a G electrode groove (16) in a G electrode area and a second D electrode groove (17) in a D electrode area of the epitaxial wafer;
step S600, preparing a G electrode (18), a second D electrode (20) and a second S electrode (19) respectively in a G electrode groove (16), a first D electrode groove (13), a second D electrode groove (17) and an S electrode groove (12) on an epitaxial wafer; and finishing the preparation of the whole device.
2. The method for manufacturing a high-frequency current-stabilized GaN HEMT device according to claim 1, wherein step S100 comprises:
step S110, manufacturing an epitaxial wafer by using a Si, siC or GaN substrate;
and step S120, cleaning, gluing, photoetching and developing an epitaxial wafer, protecting a D, S, G electrode area on the epitaxial wafer by using photoresist, passivating a P-GaN layer (8) in an area which is not protected by using the photoresist outside a D, S, G electrode area, converting the P-GaN layer (8) into a high-resistance GaN layer (9), then cleaning the photoresist, and depositing an isolation layer (10) with a corresponding thickness.
3. The preparation method of the high-frequency through-flow stable GaN HEMT device according to claim 1 is characterized in that the epitaxial wafer sequentially comprises a substrate (1), an AlN spacing layer (2), an Al component gradual change buffer AlGaN layer (3), a C-doped high-resistance GaN layer (4), a GaN channel layer (5), an AlN inserting layer (6), an AlGaN barrier layer (7) and a P-GaN layer (8) from bottom to top.
4. The method for manufacturing a high-frequency current-stabilized GaN HEMT device according to claim 1, wherein step S200 comprises:
step S210, protecting an active area of a device by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
and S220, using high-energy ions to implant into the epitaxial wafer passive region, destroying the internal lattice structures of the GaN channel layer (5), the AlN insertion layer (6) and the AlGaN barrier layer (7) in the passive region, changing the internal lattice structures into a high-resistance state, and preparing the ISO isolation region (11) by taking the effect of electric isolation.
5. The method for manufacturing a high-frequency current-stabilized GaN HEMT device according to claim 1, wherein step S300 comprises:
step S310, protecting the outer sides of the D electrode area and the S electrode area by using photoresist through a photoetching development process;
step S320, etching the D electrode area and the S electrode area by using ICP dry etching, wherein the D electrode area is provided with a first D electrode groove (13), and the section width of the first D electrode groove (13) is smaller than the section width of the P-GaN layer (8) of the D electrode area; an S electrode trench (12) is prepared in the S electrode region without leaving the P-GaN layer (8), and the photoresist is subsequently washed away.
6. The method for manufacturing the high-frequency through-flow stable GaN HEMT device according to claim 1 is characterized in that a metal lift-off process or a metal etching process is used to manufacture the first D electrode (15) and the first S electrode (14) in the first D electrode groove (13) and the S electrode groove (12), respectively.
7. The method for manufacturing a high-frequency current-stabilized GaN HEMT device of claim 1, wherein step 500 comprises:
step S510, protecting the G electrode area and the rest D electrode area by using photoresist through epitaxial wafer cleaning, gluing, photoetching and developing;
and step S520, etching the G electrode area and the residual D electrode area by using ICP dry etching, respectively preparing a G electrode groove (16) and a second D electrode groove (17) in the G electrode area and the residual D electrode area, and then cleaning the photoresist.
8. The method for manufacturing the high-frequency through-flow stable GaN HEMT device according to claim 1 is characterized in that a metal stripping process or a metal etching process is used to manufacture a G electrode (18), a second D electrode (20) and a second S electrode (19) in the G electrode groove (16), the first D electrode groove (13), the second D electrode groove (17) and the S electrode groove (12), respectively;
and finishing the preparation of the whole device.
9. A high frequency current stabilized GaN HEMT device fabricated by a method of fabricating a high frequency current stabilized GaN HEMT device according to any one of claims 1-8, characterized by comprising an epitaxial wafer and an isolation layer (10);
the P-GaN layer (8) outside the G, D, S electrode area on the epitaxial wafer is passivated into a high-resistance GaN layer (9);
the passive region on the epitaxial wafer is provided with an ISO isolation region (11) extending downwards from the upper surface of the isolation layer (10) to the C-doped high-resistance GaN layer (4);
a first D electrode (15) and a first S electrode (14) which downwards extend from the upper surface of the isolation layer (10) to the inside of the AlGaN barrier layer (7) are arranged on the epitaxial wafer;
the epitaxial wafer is provided with a G electrode groove (16) and a second D electrode groove (17) which extend downwards from the upper surface of the isolation layer (10) to the upper surface of the P-GaN layer (8);
g electrode (18), second D electrode (20) and second S electrode (19) with upper surfaces parallel to the isolation layer (10) are arranged in the G electrode groove (16), the first D electrode groove (13), the second D electrode groove (17) and the S electrode groove (12); the lower surface of the G electrode (18) is in contact with the upper surface of the P-GaN layer (8); the lower surface of the second D electrode (20) is respectively contacted with the upper surfaces of the P-GaN layer (8) and the first D electrode (15); the lower surface of the second S electrode (19) is contacted with the upper surface of the first S electrode (14).
10. The GaN HEMT device of claim 9, wherein said first D electrode (15), said first S electrode (14) and said underlying two-dimensional electron gas form an ohmic contact, said G electrode (18) and said underlying P-GaN layer (8) form a schottky contact, said second D electrode (20) and said P-GaN layer (8) form a schottky contact, and said first D electrode (15) form an electrical interconnection, and said second S electrode (19) and said first S electrode (14) form an electrical interconnection.
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