CN117410401A - LED chip and preparation method thereof - Google Patents
LED chip and preparation method thereof Download PDFInfo
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- CN117410401A CN117410401A CN202311726505.1A CN202311726505A CN117410401A CN 117410401 A CN117410401 A CN 117410401A CN 202311726505 A CN202311726505 A CN 202311726505A CN 117410401 A CN117410401 A CN 117410401A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 126
- 238000005530 etching Methods 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 66
- 230000000903 blocking effect Effects 0.000 claims abstract description 60
- 239000007788 liquid Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 43
- 239000011777 magnesium Substances 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910018885 Pt—Au Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- ZSWFCLXCOIISFI-UHFFFAOYSA-N endo-cyclopentadiene Natural products C1C=CC=C1 ZSWFCLXCOIISFI-UHFFFAOYSA-N 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 claims description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 claims description 4
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000001788 irregular Effects 0.000 abstract description 5
- 229910002601 GaN Inorganic materials 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 7
- 239000010980 sapphire Substances 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses an LED chip and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate; growing an epitaxial layer over a substrate; depositing a barrier layer material with a preset thickness on the P-type semiconductor layer to obtain a material layer, performing yellow light treatment on the material layer, removing at least part of the barrier layer material, and forming a current barrier layer on the P-type semiconductor layer and an etching liquid barrier layer at the edge; manufacturing an ITO film layer on the P-type semiconductor layer to form a transparent conductive layer which is positioned on the P-type semiconductor layer and covers the current blocking layer; patterning the transparent conductive layer to cover the edge of the transparent conductive layer on the outer edge of the etching liquid barrier layer; and manufacturing an electrode to obtain the LED chip. The technical problems that in the prior art, the ITO has crystal structure differences in the annealing process, so that the local etching rates of the edges of the ITO are different, the edges are irregular, the discharge is uneven, and the service life of an LED chip is influenced are solved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an LED chip and a preparation method thereof.
Background
Indium Tin Oxide (ITO) films have good conductivity and high light transmittance (in visible light) and are paid attention to, and domestic and foreign scholars have conducted extensive research on the characteristics of the ITO films and are also widely applied to current spreading layers, namely transparent conductive layers, of LED chips.
The ITO current expansion layer of the LED chip is usually subjected to wet etching process, so that ITO etching liquid is permeated in the wet etching process, an over-etching phenomenon is caused, meanwhile, the difference of local etching rates of edges is caused due to the difference of crystal structures in the annealing process of ITO, and therefore the edges are irregularly shaped, and finally, discharge is uneven, and the service life of the LED chip is influenced.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an LED chip and a preparation method thereof, and aims to solve the technical problems that in the prior art, the ITO has a crystal structure difference in the annealing process, so that the partial etching rates of the edges of the ITO are different, the edges are in an irregular shape, the discharge is uneven, and the service life of the LED chip is influenced.
A first aspect of the present invention provides a method for manufacturing an LED chip, the method comprising:
providing a substrate;
growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;
depositing a barrier layer material with a preset thickness on the P-type semiconductor layer to obtain a material layer, performing yellow light treatment on the material layer, removing at least part of the barrier layer material, and forming a current barrier layer on the P-type semiconductor layer and an etching liquid barrier layer at the edge;
manufacturing an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer which is positioned on the P-type semiconductor layer and covers the current blocking layer;
patterning the transparent conductive layer to cover the edge of the transparent conductive layer on the outer edge of the etching liquid barrier layer;
and respectively manufacturing a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer to obtain the LED chip.
According to one aspect of the above technical solution, the material layer is SiO 2 The process steps of carrying out yellow light treatment on the material layer comprise the following steps:
performing photoresist uniformization on the surface of the P-type semiconductor layer, and exposing and developing the photoresist;
etching to remove at least part of SiO in the material layer 2 The material is used for respectively obtaining a current blocking layer positioned at the upper middle part of the P-type semiconductor layer and an etching liquid blocking layer positioned at the upper peripheral part of the P-type semiconductor layer;
the etching liquid blocking layer is closed and is positioned on the outer side of the current blocking layer.
According to an aspect of the foregoing technical solution, the step of forming an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer that is located on the P-type semiconductor layer and covers the current blocking layer, specifically includes:
manufacturing an ITO film layer on the P-type semiconductor layer by adopting magnetron sputtering;
annealing the ITO film layer;
wherein, when the ITO film layer is annealed, the annealing temperature is 500-600 ℃ and the annealing time is 10-20 min.
According to an aspect of the foregoing technical solution, the step of performing patterning treatment on the transparent conductive layer to cover an edge of the transparent conductive layer at an outer edge of the etching solution barrier layer specifically includes:
coating photoresist on the surface of the transparent conductive layer, and masking the photoresist by using a photoetching mask plate and exposing the photoresist;
removing the photoresist outside the ITO area to be etched through developing solution;
removing the ITO area without photoresist protection by wet etching;
and removing the photoresist coated on the transparent conductive layer by adopting a photoresist removing solution to complete the patterning treatment of the transparent conductive layer.
According to an aspect of the above technical solution, the edge of the pattern of the transparent conductive layer covers the edge of the etching solution barrier layer.
According to an aspect of the foregoing technical solution, the step of fabricating a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer respectively specifically includes:
and respectively evaporating Cr-Al-Ti-Ni-Pt-Ni-Pt-Au layers on the transparent conductive layer and the N-type semiconductor layer to obtain a P-type electrode and an N-type electrode respectively.
According to an aspect of the foregoing technical solution, after the steps of fabricating the P-type electrode and the N-type electrode on the transparent conductive layer and the N-type semiconductor layer, the preparation method further includes:
200nm-600nm of SiO is deposited on the surface of the chip 2 The material is used for obtaining a passivation layer attached to the surface of the chip;
wherein the passivation layer exposes the P-type electrode and the N-type electrode.
According to an aspect of the above technical solution, the step of growing an epitaxial layer on the substrate includes:
high-purity hydrogen is used as carrier gas, high-purity ammonia is used as nitrogen source, trimethyl gallium and triethyl gallium are used as gallium source, trimethyl indium is used as indium source, trimethyl aluminum is used as aluminum source, silane is used as N-type doping agent, and magnesium cyclopentadienyl is used as P-type doping agent, and an epitaxial layer is grown on the substrate;
the N-type semiconductor layer is an N-GaN layer, the P-type semiconductor layer is a P-GaN layer, and the light-emitting layer is a multiple quantum well active layer.
According to one aspect of the above technical scheme, the thickness of the N-type semiconductor layer is 1 μm-3 μm, and the Si doping concentration is 5×10 atm/cm 3 -1×10 19 atms/cm 3 The thickness of the P-type semiconductor layer is 200nm-300nm, and the doping concentration of Mg is 5×10 17 atms/cm 3 -1×10 20 atms/cm 3 The molar ratio of the In component In the light-emitting layer is 10% -35%.
The second aspect of the present invention provides an LED chip, which is prepared by the preparation method described in the above technical solution.
Compared with the prior art, the LED chip and the preparation method thereof have the beneficial effects that:
by depositing SiO over a P-type semiconductor layer 2 A material forming a material layer, removing at least part of SiO in the material layer by performing yellow light treatment 2 The material is used for obtaining the current blocking layer and the etching liquid blocking layer which are positioned on the P-type semiconductor layer, the etching liquid blocking layer is positioned on the outer side of the current blocking layer on the P-type semiconductor layer, after the transparent conducting layer is manufactured on the P-type semiconductor layer, the edge of the transparent conducting layer is positioned on the outer side edge of the etching liquid blocking layer through graphical processing, when the ITO etching liquid is used for etching the transparent conducting layer, the etching liquid blocking layer can block the flow of the ITO etching liquid, the etching of the ITO etching liquid to the transparent conducting layer is effectively controlled, the edge of the transparent conducting layer is kept flush, the irregular edge shape of the edge cannot appear, the discharging of the transparent conducting layer is more uniform and is not easy to burn out, and the service life of the LED chip can be effectively prolonged.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic flow chart of a method for manufacturing an LED chip according to an embodiment of the invention;
FIG. 2 is a top view of an LED chip according to an embodiment of the present invention;
FIG. 3 is an enlarged schematic view of portion A of FIG. 2;
FIG. 4 is a cross-sectional view of an LED chip in an embodiment of the invention;
description of the drawings:
the light emitting device includes a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, a light emitting layer 40, a P-type semiconductor layer 50, a current blocking layer 60, an etching liquid blocking layer 70, a transparent conductive layer 80, an N-type electrode 91, a P-type electrode 92, and a passivation layer 100.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
A first aspect of the present invention provides a method for manufacturing an LED chip, the method comprising:
providing a substrate; the substrate can be sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate; preferably, the substrate is a sapphire substrate, because sapphire is the most commonly used GaN-based LED substrate material at present, and most GaN-based LEDs in the market use sapphire as the substrateThe material is the most excellent of the sapphire substrate, and has the advantages of mature technology, good stability and lower production cost;
growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;
depositing a barrier layer material with a preset thickness on the P-type semiconductor layer to obtain a material layer, performing yellow light treatment on the material layer, removing at least part of the barrier layer material, and forming a current barrier layer on the P-type semiconductor layer and an etching liquid barrier layer at the edge;
manufacturing an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer which is positioned on the P-type semiconductor layer and covers the current blocking layer;
patterning the transparent conductive layer to cover the edge of the transparent conductive layer on the outer edge of the etching liquid barrier layer;
and respectively manufacturing a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer to obtain the LED chip.
Further, the material layer is SiO 2 The process steps of carrying out yellow light treatment on the material layer comprise the following steps:
performing photoresist uniformization on the surface of the P-type semiconductor layer, and exposing and developing the photoresist;
etching to remove at least part of SiO in the material layer 2 The material is used for respectively obtaining a current blocking layer positioned at the upper middle part of the P-type semiconductor layer and an etching liquid blocking layer positioned at the upper peripheral part of the P-type semiconductor layer;
the etching liquid blocking layer is closed and is positioned on the outer side of the current blocking layer.
Further, the step of forming an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer on the P-type semiconductor layer and covering the current blocking layer, specifically includes:
manufacturing an ITO film layer on the P-type semiconductor layer by adopting magnetron sputtering;
annealing the ITO film layer;
wherein, when the ITO film layer is annealed, the annealing temperature is 500-600 ℃ and the annealing time is 10-20 min.
Further, the step of performing patterning treatment on the transparent conductive layer to cover the edge of the transparent conductive layer on the outer edge of the etching solution barrier layer specifically includes:
coating photoresist on the surface of the transparent conductive layer, and masking the photoresist by using a photoetching mask plate and exposing the photoresist;
removing the photoresist outside the ITO area to be etched through developing solution;
removing the ITO area without photoresist protection by wet etching;
and removing the photoresist coated on the transparent conductive layer by adopting a photoresist removing solution to complete the patterning treatment of the transparent conductive layer.
Further, the pattern edge of the transparent conductive layer covers the edge of the etching liquid barrier layer.
Further, the step of manufacturing a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer respectively specifically includes:
and respectively evaporating Cr-Al-Ti-Ni-Pt-Ni-Pt-Au layers on the transparent conductive layer and the N-type semiconductor layer to obtain a P-type electrode and an N-type electrode respectively.
Further, after the steps of manufacturing the P-type electrode and the N-type electrode on the transparent conductive layer and the N-type semiconductor layer, the preparation method further includes:
200nm-600nm of SiO is deposited on the surface of the chip 2 The material is used for obtaining a passivation layer attached to the surface of the chip;
wherein the passivation layer exposes the P-type electrode and the N-type electrode.
Further, the step of growing an epitaxial layer over the substrate includes:
high-purity hydrogen is used as carrier gas, high-purity ammonia is used as nitrogen source, trimethyl gallium and triethyl gallium are used as gallium source, trimethyl indium is used as indium source, trimethyl aluminum is used as aluminum source, silane is used as N-type doping agent, and magnesium cyclopentadienyl is used as P-type doping agent, and an epitaxial layer is grown on the substrate;
the N-type semiconductor layer is an N-GaN layer, the P-type semiconductor layer is a P-GaN layer, and the light-emitting layer is a multiple quantum well active layer.
Further, the N-type semiconductor layer has a thickness of 1 μm to 3 μm and a Si doping concentration of 5×10 18 atms/cm 3 -1×10 19 atms/cm 3 The thickness of the P-type semiconductor layer is 200nm-300nm, and the doping concentration of Mg is 5×10 17 atms/cm 3 -1×10 20 atms/cm 3 The molar ratio of the In component In the light-emitting layer is 10% -35%.
A second aspect of the present invention is to provide an LED chip prepared by the preparation method described in the first aspect.
Compared with the prior art, the LED chip and the preparation method thereof have the beneficial effects that:
by depositing SiO over a P-type semiconductor layer 2 A material forming a material layer, removing at least part of SiO in the material layer by performing yellow light treatment 2 The material is used for obtaining the current blocking layer and the etching liquid blocking layer which are positioned on the P-type semiconductor layer, the etching liquid blocking layer is positioned on the outer side of the current blocking layer on the P-type semiconductor layer, after the transparent conducting layer is manufactured on the P-type semiconductor layer, the edge of the transparent conducting layer is positioned on the outer side edge of the etching liquid blocking layer through graphical processing, when the ITO etching liquid is used for etching the transparent conducting layer, the etching liquid blocking layer can block the flow of the ITO etching liquid, the etching of the ITO etching liquid to the transparent conducting layer is effectively controlled, the edge of the transparent conducting layer is kept flush, the irregular edge shape of the edge cannot appear, the discharging of the transparent conducting layer is more uniform and is not easy to burn out, and the service life of the LED chip can be effectively prolonged.
Example 1
Referring to fig. 1, a first embodiment of the present invention provides a method for manufacturing an LED chip, where the method includes steps S1 to S6:
step S1, a substrate is provided.
In the present embodiment, the substrate is a sapphire substrate, i.e., al 2 O 3 The substrate is the most commonly used GaN-based LED substrate material at present, and the technology is mature, the stability is high, and the material cost and the production cost are low.
And step S2, growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer.
In this embodiment, an epitaxial layer is grown on the substrate, and an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer are epitaxially grown on the substrate in order, wherein the N-type semiconductor layer and the P-type semiconductor layer are both GaN-based material systems, and the N-type semiconductor layer is an N-GaN layer and the P-type semiconductor layer is a P-GaN layer.
In some possible embodiments, a buffer layer is further disposed on the substrate, where the buffer layer is, for example, an AlN buffer layer, and the N-type semiconductor layer, the light emitting layer, and the P-type semiconductor layer are sequentially stacked on the buffer layer, so that dislocation defects of the epitaxy can be better improved by disposing the buffer layer, and crystal growth quality of the epitaxy is improved.
Specifically, when the epitaxial layer is grown, high-purity hydrogen is used as carrier gas, high-purity ammonia is used as nitrogen source, trimethyl gallium and triethyl gallium are used as gallium source, trimethyl indium is used as indium source, trimethyl aluminum is used as aluminum source, silane is used as N-type doping agent, and magnesium cyclopentadienyl is used as P-type doping agent, and the epitaxial layer is grown on the substrate, namely the N-type semiconductor layer, the light-emitting layer and the P-type semiconductor layer are sequentially grown on the substrate.
Wherein the N-type semiconductor layer has a thickness of 1 μm and is doped with Si element as N-type dopant by silane, and the doping concentration of Si element is 5×10 18 atms/cm 3 The thickness of the P-type semiconductor layer is 200nm, which is thinner than that of the N-type semiconductor layer, wherein the P-type dopant is doped with Mg by using magnesium, and the doping concentration of Mg element is 5×10 17 atms/cm 3 The doping concentration is lower than that of the N-type semiconductor layer, and the In component In the light-emitting layer accounts for the molar ratio of10%。
Step S3, depositing a barrier layer material with a preset thickness on the P-type semiconductor layer to obtain a material layer, performing yellow light treatment on the material layer, removing at least part of the barrier layer material, and forming a current barrier layer on the P-type semiconductor layer and an etching liquid barrier layer at the edge;
first, siO is deposited on P-type semiconductor 2 The purpose of the material is different from the prior art in that in the present embodiment, the material is formed by SiO 2 The material is used for forming a current blocking layer used for blocking current below the electrode on the P-type semiconductor layer and is also used for forming an etching liquid blocking layer used for blocking ITO etching liquid from flowing randomly on the P-type semiconductor layer.
In this embodiment, a predetermined thickness of SiO is deposited on the P-type semiconductor layer 2 After the material layer is obtained, yellow light treatment is needed to be carried out on the material layer so as to obtain the current blocking layer and the etching liquid blocking layer which are positioned on the P-type semiconductor layer respectively.
Wherein, the process steps of carrying out yellow light treatment on the material layer comprise:
performing photoresist uniformization on the surface of the P-type semiconductor layer, and exposing and developing the photoresist;
etching to remove at least part of SiO in the material layer 2 The material is used for respectively obtaining a current blocking layer positioned at the upper middle part of the P-type semiconductor layer and an etching liquid blocking layer positioned at the upper peripheral part of the P-type semiconductor layer; the etching liquid blocking layer is closed and is positioned on the outer side of the current blocking layer.
Specifically, 200nm thick SiO is deposited on the surface of the P-type semiconductor layer by adopting PECVD equipment 2 The material is then yellow-light treated on the surface of the material layer, including photoresist-homogenizing exposure, developing and etching, and the current blocking layer of the photomask is modified in the process, so that unlike conventional chip, only the current blocking layer below the current is reserved, the current blocking layer below the electrode is reserved, and a circle of SiO is reserved at the edge of the chip 2 Material to carry out ITOLifting is carried out, a dam-like terrace is cast to block ITO etching liquid, so that the inner seepage of the etching liquid is relieved, and the later-stage non-uniform etching of ITO is avoided.
S4, manufacturing an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer which is positioned on the P-type semiconductor layer and covers the current blocking layer;
in this embodiment, the step of forming the ITO film layer on the P-type semiconductor layer to form the transparent conductive layer on the P-type semiconductor layer and covering the current blocking layer specifically includes:
manufacturing an ITO film layer on the P-type semiconductor layer by adopting magnetron sputtering;
annealing the ITO film layer;
and when the ITO film layer is annealed, the annealing temperature is 550 ℃, and the annealing time is 15min.
After the ITO film layer is annealed, the annealing treatment is the alloying process of the ITO film layer, so that the current can be more uniformly diffused in the transparent conductive layer, and the current is not easy to concentrate at a certain point or a certain area.
The principle that the ITO film layer is annealed to make the current diffusion more uniform is as follows: bombarding the target material by adopting argon (Ar) in an ionization mode, so that the target material is sputtered on the surface of the wafer, and the deposition of the ITO film layer is completed; as the compactness of the ITO film layer after deposition is poor, the crystal arrangement is tidier through annealing, the film layer is more compact, the conductivity is more stable, and the annealing process is that the epitaxial wafer plated with the ITO film layer is put into an annealing equipment cavity at 550 ℃ for annealing treatment for 15 minutes.
And S5, carrying out patterning treatment on the transparent conductive layer to enable the edge of the transparent conductive layer to cover the outer side edge of the etching liquid barrier layer.
In this embodiment, the step of patterning the transparent conductive layer to cover the edge of the transparent conductive layer at the outer edge of the etching solution barrier layer includes:
coating photoresist on the surface of the transparent conductive layer, and masking the photoresist by using a photoetching mask plate and exposing the photoresist;
removing the photoresist outside the ITO area to be etched through developing solution;
removing the ITO area without photoresist protection by wet etching;
and removing the photoresist coated on the transparent conductive layer by adopting a photoresist removing solution to complete the patterning treatment of the transparent conductive layer.
In this embodiment, when patterning the transparent conductive layer, photoresist is uniformly coated on the surface of the wafer, and is masked by a photolithography mask and exposed, then the photoresist at the ITO position to be etched is removed by developing with a developing solution, then the ITO film layer at the place where no photoresist is protected is removed by wet etching, and then the photoresist is removed by photoresist removal, thereby completing the patterning of the ITO film layer.
It is important to note here that the pattern edge of the transparent conductive layer needs to cover the outer edge of the etching solution blocking layer, so that the photoresist after development needs to be guaranteed to just cover the edge by about 1um, and the ITO etching solution can be etched by 1.5 um through the photoresist.
And S6, respectively manufacturing a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer to obtain the LED chip.
Specifically, when manufacturing the electrode, the wafer after the steps is placed on a carrier plate of an electron beam evaporator, an evaporation source emitter is positioned below the carrier plate, and then a Cr-Al-Ti-Ni-Pt-Ni-Pt-Au layer is sequentially evaporated to obtain a P-type electrode positioned on the transparent conductive layer and an N-type electrode positioned on the N-type semiconductor layer.
The P-type electrode is electrically connected with the P-type semiconductor layer through the transparent conductive layer, and the N-type electrode is in contact with the Mesa step of the N-type semiconductor layer to realize electrical connection.
Referring to fig. 2-4, the method for manufacturing an LED chip according to the present embodiment is used to manufacture an LED chip, where the LED chip includes:
a substrate 10;
a buffer layer 20 and an epitaxial layer stacked on the substrate 10, the epitaxial layer including an N-type semiconductor layer 30, a light emitting layer 40 and a P-type semiconductor layer 50;
a current blocking layer 60 and an etching solution blocking layer 70 disposed over the P-type semiconductor layer 50, the etching solution blocking layer 70 being disposed outside the current blocking layer 60 over the P-type semiconductor layer 50;
a transparent conductive layer 80 disposed over the P-type semiconductor layer 50, the transparent conductive layer 80 covering the current blocking layer 60, an edge of the transparent conductive layer 80 being bonded to an edge of the etching liquid blocking layer 70;
and an N-type electrode 91 and a P-type electrode 92 respectively disposed on the N-type semiconductor layer 30 and the transparent conductive layer 80.
In the present embodiment, the thickness of the N-type semiconductor layer 30 is 1 μm, in which Si element is doped as N-type dopant by silane, and the doping concentration of Si element is 5×10 18 atms/cm 3 The thickness of the P-type semiconductor layer 50 is 200nm, which is thinner than that of the N-type semiconductor layer 30, wherein the P-type dopant is doped with Mg by using magnesium, and the doping concentration of Mg element is 5×10 17 atms/cm 3 The doping concentration is also lower than that of the N-type semiconductor layer 30, and the In component In the light-emitting layer 40 accounts for 10 mol%.
Compared with the prior art, the preparation method shown in the embodiment is adopted to prepare the LED chip, and has the beneficial effects that:
by depositing SiO over a P-type semiconductor layer 2 A material forming a material layer, removing at least part of SiO in the material layer by performing yellow light treatment 2 The material is used for obtaining a current blocking layer and an etching liquid blocking layer which are positioned on the P-type semiconductor layer, wherein the etching liquid blocking layer is positioned on the outer side of the current blocking layer on the P-type semiconductor layer, after the transparent conducting layer is manufactured on the P-type semiconductor layer, the edge of the transparent conducting layer is positioned on the outer side edge of the etching liquid blocking layer through patterning treatment, and when the ITO etching liquid is used for etching the transparent conducting layer, the etching liquid is used for forming the transparent conducting layerThe blocking layer can block the flow of the ITO etching liquid, effectively controls the etching of the ITO etching liquid on the transparent conducting layer, enables the edge of the transparent conducting layer to keep flush morphology, prevents irregular morphology of the edge, enables the discharge of the transparent conducting layer to be more uniform, is not easy to burn out, and can effectively prolong the service life of the LED chip.
Example two
The second embodiment of the present invention also provides a method for manufacturing an LED chip, which is substantially similar to the method for manufacturing the LED chip shown in the first embodiment, except that:
in this embodiment, after the N-type electrode and the P-type electrode are respectively fabricated on the N-type semiconductor layer and the transparent conductive layer, the method further includes:
200nm-600nm of SiO is deposited on the surface of the chip 2 The material is used for obtaining a passivation layer attached to the surface of the chip;
wherein the passivation layer exposes the P-type electrode and the N-type electrode.
Referring to fig. 4, by forming the passivation layer 100 on the surface of the LED chip, the scratch resistance of the LED chip can be effectively improved, and water vapor etching can be effectively prevented, and the N-type electrode 91 and the P-type electrode 92 are exposed when the passivation layer 100 covers the surface of the chip.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention, and are described in detail, but are not to be construed as limiting the scope of the invention. It should be noted that it is possible for those skilled in the art to make several variations and modifications without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A method for manufacturing an LED chip, comprising:
providing a substrate;
growing an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;
depositing a barrier layer material with a preset thickness on the P-type semiconductor layer to obtain a material layer, performing yellow light treatment on the material layer, removing at least part of the barrier layer material, and forming a current barrier layer on the P-type semiconductor layer and an etching liquid barrier layer at the edge;
manufacturing an ITO film layer on the P-type semiconductor layer, and forming a transparent conductive layer which is positioned on the P-type semiconductor layer and covers the current blocking layer;
patterning the transparent conductive layer to cover the edge of the transparent conductive layer on the outer edge of the etching liquid barrier layer;
and respectively manufacturing a P-type electrode and an N-type electrode on the transparent conductive layer and the N-type semiconductor layer to obtain the LED chip.
2. The method for manufacturing an LED chip of claim 1, wherein said predetermined thickness is 150nm to 250nm, and said material layer is SiO 2 The process steps of carrying out yellow light treatment on the material layer comprise the following steps:
performing photoresist uniformization on the surface of the P-type semiconductor layer, and exposing and developing the photoresist;
etching to remove at least part of SiO in the material layer 2 Material for respectively obtaining a current blocking layer positioned at the upper middle part of the P-type semiconductor layer and a carving positioned at the upper peripheral part of the P-type semiconductor layerAn etching liquid barrier layer;
the etching liquid blocking layer is closed and is positioned on the outer side of the current blocking layer.
3. The method of manufacturing an LED chip of claim 1, wherein the step of forming an ITO film layer on the P-type semiconductor layer, forming a transparent conductive layer on the P-type semiconductor layer and covering the current blocking layer, specifically comprises:
manufacturing an ITO film layer on the P-type semiconductor layer by adopting magnetron sputtering;
annealing the ITO film layer;
wherein, when the ITO film layer is annealed, the annealing temperature is 500-600 ℃ and the annealing time is 10-20 min.
4. The method of manufacturing an LED chip of claim 1, wherein the step of patterning the transparent conductive layer to cover the edge of the transparent conductive layer at the outer edge of the etching solution barrier layer, specifically comprises:
coating photoresist on the surface of the transparent conductive layer, and masking the photoresist by using a photoetching mask plate and exposing the photoresist;
removing the photoresist outside the ITO area to be etched through developing solution;
removing the ITO area without photoresist protection by wet etching;
and removing the photoresist coated on the transparent conductive layer by adopting a photoresist removing solution to complete the patterning treatment of the transparent conductive layer.
5. The method of manufacturing an LED chip of claim 4, wherein the patterned edge of said transparent conductive layer is covered at the edge of said etching solution barrier layer.
6. The method of manufacturing an LED chip of claim 1, wherein said steps of forming P-type and N-type electrodes on said transparent conductive layer and said N-type semiconductor layer, respectively, comprise:
and respectively evaporating Cr-Al-Ti-Ni-Pt-Ni-Pt-Au layers on the transparent conductive layer and the N-type semiconductor layer to obtain a P-type electrode and an N-type electrode respectively.
7. The method of manufacturing an LED chip of claim 6, further comprising, after the steps of forming P-type and N-type electrodes on said transparent conductive layer and said N-type semiconductor layer, respectively:
200nm-600nm of SiO is deposited on the surface of the chip 2 The material is used for obtaining a passivation layer attached to the surface of the chip;
wherein the passivation layer exposes the P-type electrode and the N-type electrode.
8. The method of manufacturing an LED chip of any of claims 1-7, wherein the step of growing an epitaxial layer over said substrate comprises:
high-purity hydrogen is used as carrier gas, high-purity ammonia is used as nitrogen source, trimethyl gallium and triethyl gallium are used as gallium source, trimethyl indium is used as indium source, trimethyl aluminum is used as aluminum source, silane is used as N-type doping agent, and magnesium cyclopentadienyl is used as P-type doping agent, and an epitaxial layer is grown on the substrate;
the N-type semiconductor layer is an N-GaN layer, the P-type semiconductor layer is a P-GaN layer, and the light-emitting layer is a multiple quantum well active layer.
9. The method of manufacturing an LED chip as set forth in claim 8, wherein the N-type semiconductor layer has a thickness of 1 μm to 3 μm and a Si doping concentration of 5 x 10atm s/cm 3 -1×10 19 atms/cm 3 The thickness of the P-type semiconductor layer is 200nm-300nm, and the doping concentration of Mg is 5×10 17 atms/cm 3 -1×10 20 atms/cm 3 The molar ratio of the In component In the light-emitting layer is 10% -35%.
10. An LED chip, characterized in that the LED chip is prepared by the preparation method according to any one of claims 1 to 9.
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