CN117410384A

CN117410384A - IBC solar cell and preparation method thereof

Info

Publication number: CN117410384A
Application number: CN202311659926.7A
Authority: CN
Inventors: 杨睿; 方理程
Original assignee: Trina Solar Co Ltd
Current assignee: Trina Solar Co Ltd
Priority date: 2023-12-05
Filing date: 2023-12-05
Publication date: 2024-01-16

Abstract

The invention provides an IBC solar cell and a preparation method thereof. The method comprises the following steps: providing a silicon substrate, wherein a first surface of the silicon substrate comprises a first area and a second area surrounding the first area; sequentially forming a tunneling oxide layer, a first polysilicon layer and a barrier layer on the first surface of the silicon substrate; doping the first surface of the silicon substrate by adopting a diffusion process; removing the barrier layer of the first region; etching a preset area of the first surface of the silicon substrate to form a first type area, wherein the area which is not etched is a second type area; removing the damaged layer of the first type region; forming a passivation layer and an antireflection film on one side of the first surface and the second surface of the silicon substrate, which are far away from the silicon substrate; a first electrode is formed in the first type region and a second electrode is formed in the second type region. According to the invention, the blocking layer is arranged in the edge area of the solar cell, so that the process window for removing the damaged layer is widened, the electric leakage proportion of the edge of the cell is reduced, and the reliability of the solar cell is improved.

Description

IBC solar cell and preparation method thereof

Technical Field

The invention relates to the technical field of photovoltaic cells, in particular to an IBC solar cell and a preparation method thereof.

Background

With the rapid development of photovoltaic technology, the conversion efficiency of crystalline silicon solar cells is improved year by year, and the market demand for crystalline solar cells with higher conversion efficiency is more urgent. Currently, the mainstream P-type double-sided PERC battery has encountered an efficiency bottleneck, and various manufacturers have begun to lay out new and efficient batteries. The IBC solar cell has the advantages of higher efficiency, continuity of the process flow and the P-type PERC cell, and the like, and many manufacturers in the industry begin to increase research, development and production investment of the PIBC solar cell.

The IBC solar cell is different from other biggest ones in that the emitter, the surface field and the metal electrode are all arranged on the back of the cell and distributed in an interdigital mode, the front of the cell is free of any grid line shielding, the light absorption area is largest, and therefore the IBC solar cell has high photoelectric conversion efficiency.

At present, under the conventional preparation mode, the edge of the IBC solar cell is more close to the furnace tube in the LPCVD (Low Pressure Chemical Vapor Deposition) and phosphorus diffusion processes, so that the effect of high-temperature accumulation is easily caused, more impurity ions are accumulated in the edge region of the basal layer, the impurity ions are easy to cause electric leakage under the condition that the impurity ions are not removed cleanly, the solar cell is further caused to fail, and the production yield of the IBC is greatly influenced.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide an IBC solar cell and a preparation method thereof, which can reduce the electric leakage proportion of the IBC solar cell and improve the yield of the IBC solar cell.

The embodiment of the invention provides an IBC solar cell and a preparation method thereof, comprising the following steps:

providing a silicon substrate comprising opposing first and second surfaces, the first surface comprising first and second regions, the second region surrounding the first region;

sequentially forming a tunneling oxide layer, a first polysilicon layer and a barrier layer on the first surface of the silicon substrate;

doping the first surface of the silicon substrate by adopting a diffusion process so as to push doping elements into the silicon substrate and form a heavily doped first polysilicon layer;

removing the blocking layer of the first area by adopting laser;

etching a preset area of the first surface of the silicon substrate by adopting laser to form a first type area, wherein an unetched area is a second type area, and the first type area and the second type area are overlapped;

removing the damaged layer of the first type region by adopting a polishing technology;

forming a passivation layer and an antireflection film on one side of the first surface and the second surface of the silicon substrate, which are far away from the silicon substrate;

and forming a first electrode in the first type region and forming a second electrode in the second type region.

In some embodiments, the barrier layer has a thickness of 10 to 50nm.

In some embodiments, the width of the second region is 1 to 15mm.

In some embodiments, the barrier layer is a second polysilicon layer, a microcrystalline silicon layer, a silicon nitride layer, or a silicon oxide layer.

In some embodiments, when the barrier layer is a second polysilicon layer, the tunneling oxide layer, the first polysilicon layer and the barrier layer are sequentially formed on the first surface of the silicon substrate, including the steps of;

forming a tunneling oxide layer on the first surface of the silicon substrate;

and forming a third polysilicon layer on one surface of the tunneling oxide layer, which is far away from the silicon substrate, wherein the thickness of the third polysilicon layer is equal to the sum of the thicknesses of the first polysilicon layer and the second polysilicon layer.

In some embodiments, the tunnel oxide layer is prepared using LPCVD techniques.

In some embodiments, after said providing the silicon substrate, further comprising the steps of:

and polishing and cleaning the two sides of the silicon substrate.

In some embodiments, after etching the preset area of the first surface of the silicon substrate with the laser, the method includes the steps of:

and forming pyramid-like suede structures on the second surface and the first type region by adopting a texturing process.

In some embodiments, the material of the first electrode comprises aluminum and the material of the second electrode comprises silver.

In some embodiments, the passivation layer comprises a silicon oxide layer or an aluminum oxide layer.

In some embodiments, after the removing the damaged layer of the first type region by using the polishing technology, the method further includes the following steps:

and removing the wrapping coating on the second surface of the silicon substrate.

The embodiment of the invention also provides an IBC solar cell, which is prepared by adopting the preparation method of the IBC solar cell.

The IBC solar cell and the preparation method thereof provided by the invention have the following advantages:

according to the invention, the blocking layer is arranged in the edge area of the solar cell, so that the process window for removing the damaged layer is widened, the electric leakage proportion of the edge of the cell is reduced, and the reliability of the solar cell is improved.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings.

FIG. 1 is a flow chart of an IBC solar cell and a method of making the same according to an embodiment of the invention;

FIG. 2 is a schematic plan view of a second surface of a silicon substrate according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of the silicon substrate provided in step S100;

FIG. 4 is a schematic view of the structure of the silicon substrate after step S200;

FIG. 5 is a schematic diagram of the structure of a second region of the silicon substrate after step S400;

fig. 6 is a schematic structural diagram of a first region of a silicon substrate after step S400;

fig. 7 is a schematic structural diagram of a first region of a silicon substrate after step S700;

fig. 8 is a schematic structural diagram of a second region of the silicon substrate after step S800.

Reference numerals:

1. silicon substrate

11. A first surface

111. First region

112. Second region

12. A second surface

2. Tunneling oxide layer

3. First polysilicon layer

4. Barrier layer

5. Passivation layer

6. Antireflection layer

71. First electrode

72. Second electrode

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. "or", "or" in the specification may each mean "and" or ".

In the description of the present application, reference to the terms "one embodiment," "some embodiments," "examples," "particular examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples, and features of the various embodiments or examples, presented herein may be combined and combined by those skilled in the art without conflict.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the context of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In order to solve the technical problems in the prior art, the embodiment of the invention provides a preparation method of an IBC solar cell. Fig. 1 shows a flowchart of a method for manufacturing an IBC solar cell according to an embodiment of the present invention; FIG. 2 shows a schematic plan view of a first surface of a silicon substrate according to an embodiment of the invention; fig. 3 to 8 are schematic structural diagrams of an IBC solar cell according to an embodiment of the present invention formed in an intermediate step. As shown in fig. 1, the method for preparing the IBC solar cell includes the following steps:

step S100: a silicon substrate 1 is provided.

In this step, as shown in fig. 2, the silicon substrate 1 includes a first surface 11 and a second surface 12 opposite to each other, the first surface 11 of the silicon substrate 1 is referred to as a backlight surface, and the second surface 12 of the silicon substrate 1 is referred to as a light-receiving surface. As shown in fig. 3, the first surface 11 includes a first region 111 and a second region 112, and the second region 112 surrounds the first region 111. The first region 111 is herein the middle region of the silicon substrate 1, and the second region 112 is the edge region of the silicon substrate 1.

In the embodiment of the present invention, the material of the silicon substrate 1 may be monocrystalline silicon or polycrystalline silicon material; the silicon substrate 1 may be a P-type silicon substrate or an N-type silicon substrate.

In some embodiments, the width d of the second region 112 is 1 to 15mm, and may be, for example, 3mm, 6mm, 9mm, 12mm, etc., but is not limited thereto. In a preferred embodiment, the width d of the second region 112 is 1 to 6mm.

In order to prepare a film structure with good quality in the subsequent process, the first surface 11 and the second surface 12 of the silicon substrate 1 need to be cleaned to remove the cutting damage layer on the silicon substrate 1. Therefore, after the silicon substrate 1 is provided, step S110 is further included:

both sides of the silicon substrate 1 are polished and cleaned. The specific process can be that the silicon substrate 1 is put into a groove type polishing cleaner for polishing, surface oil stains are removed, and a surface damage layer is removed.

Step S200: a tunnel oxide layer 2, a first polysilicon layer 3 and a barrier layer 4 are sequentially formed on the first surface 11 of the silicon substrate 1, resulting in the structure shown in fig. 4.

In this step, a tunnel oxide layer may be prepared using Low Pressure Chemical Vapor Deposition (LPCVD). In the embodiment of the present invention, the specific type of the tunnel oxide layer 2 is not limited, and for example, the tunnel oxide layer may be a silicon oxide layer. In preparing the first polysilicon layer 3, an amorphous silicon layer is first formed by LPCVD, and then the amorphous silicon layer is formed into a polysilicon layer by high temperature treatment.

The barrier layer 4 may be a second polysilicon layer, a microcrystalline silicon layer, a silicon nitride layer, a silicon oxide layer, or the like. When the barrier layer 4 is a second polysilicon layer, the tunneling oxide layer 2, the first polysilicon layer 3 and the barrier layer 4 are sequentially formed on the first surface 11 of the silicon substrate 1, comprising the following steps:

forming a tunneling oxide layer 2 on a first surface 11 of the silicon substrate 1;

a third polysilicon layer is formed on the surface of the tunnel oxide layer 2 away from the silicon substrate 1. Wherein the thickness of the third polysilicon layer is equal to the sum of the thicknesses of the first polysilicon layer 3 and the second polysilicon layer. That is, when the barrier layer 4 is the second polysilicon layer, the first polysilicon layer 3 and the second polysilicon layer can be generated by adopting a one-step deposition process, so that the process flow is simplified, and the production efficiency is improved.

In some embodiments, the thickness of the barrier layer 4 is 10 to 50nm, and may be, for example, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, and 50nm, but is not limited thereto. In a preferred embodiment, the thickness of the barrier layer 4 is 10-20 nm.

Step S300: doping is performed on the first surface 11 of the silicon substrate 1 by a diffusion process to drive the doping element into the silicon substrate 1 and form a heavily doped first polysilicon layer 3.

In this step, for example, the intermediate obtained in step S200 is placed in a tube-type diffusion furnace, and a phosphorus or boron-containing compound is introduced to perform doping diffusion. Here, the semiconductor type of the silicon substrate 1 is opposite to the semiconductor type obtained after doping with the doping element.

Step S400: the barrier layer 4 of said first region 111 is removed with a laser.

In this step the barrier layer 4 in the first region 111 is removed, while the second region 112 remains in the structure shown in fig. 4. I.e. the film thickness of the middle region (first region 111) of the first surface 11 of the silicon substrate 1 is small at this time, while the film thickness of the edge region (second region 112) of the first surface 11 of the silicon substrate 1 is large.

Step S500: and etching a preset area of the first surface 11 of the silicon substrate 1 by adopting laser to form a first type area, wherein the area which is not etched is a second type area, and the first type area and the second type area are overlapped.

In this step, the second region 112 has the structure shown in fig. 5, and the first region 111 has the structure shown in fig. 6. The semiconductor type of the first type region is the same as the semiconductor type of the silicon substrate 1, and the semiconductor type of the second type region is opposite to the semiconductor type of the silicon substrate 1. As shown in fig. 5 and fig. 6, the etched first type region exposes the silicon substrate 1, the unetched second type region covers the tunnel oxide layer 2 and the first polysilicon layer 3, and the second type region in the second region 112 further includes a barrier layer 4.

In some embodiments, the laser may be selected from green nanoseconds, ultraviolet picoseconds, green picoseconds, or ultraviolet nanoseconds during laser etching.

Step S600: and removing the damaged layer of the first type region by adopting a polishing technology.

In this step, when the first type region is etched by laser, the silicon substrate 1 is damaged by laser energy, and the damage caused by the silicon substrate 1 affects the cell efficiency. In order to ensure the conversion efficiency of the battery, the damaged layer of the silicon substrate 1 caused by the laser etching needs to be removed. In some embodiments, the removal of the damaged layer and impurities may be achieved by alkali polishing or acid polishing the intermediate formed after step S500.

Specifically, the acid polishing may be performed using a mixture of nitric acid and sulfuric acid, but is not limited thereto. The alkali polishing may employ NaOH solution or KOH solution, but is not limited thereto.

It should be noted that the polysilicon reacts with oxygen during the phosphorus or boron doping process to form a PSG or BSG layer, which can be used as a mask to protect the second type region without the need for a polishing process.

The applicant has found that even if a masking layer is present on the second type region, the part of the doped polysilicon layer above the masking layer is still consumed during the removal of the damaged layer, resulting in a reduced thickness of the doped polysilicon layer. In the prior art, when the damaged layer is removed from the silicon substrate, the polysilicon layer in the edge region of the silicon substrate consumes a greater thickness than the polysilicon layer in the central region of the silicon substrate. In order to reduce the consumption of the doped polysilicon layer at the edge of the silicon substrate, the thickness of the doped polysilicon layer can be thickened or the polishing time can be shortened. The polishing time is shortened, impurities or damaged layers at the edge of the silicon substrate can be not removed cleanly, and electric leakage is caused, so that the consumption control range of the doped polysilicon layer in the area of the silicon base edge is small in the polishing time, namely, the process window is narrow, and the anti-electric leakage treatment effect is poor; when the thickness of the doped polysilicon layer is increased through the whole layer, parasitic absorption of light is increased by the increase of the thickness of the doped polysilicon layer, and short-circuit current of the solar cell is reduced, so that photoelectric conversion efficiency is reduced.

In this application, the barrier layer 4 is added to the edge region of the silicon substrate 1, so that the thickness of the heavily doped first polysilicon layer 3 consumed when the damaged layer is removed in the edge region can be reduced while the damaged layer and impurities on the front surface of the first surface of the silicon substrate 1 are removed completely, the thickness uniformity of the heavily doped first polysilicon layer 3 on the first surface of the silicon substrate 1 is improved, the process window for removing the damaged layer is widened, the leakage ratio of the solar cell is reduced, and the conversion efficiency of the solar cell is improved.

When the tunnel oxide layer 2, the first polysilicon layer 3, the barrier layer 4 are prepared on the first surface 11 of the silicon substrate 1 and diffusion doping is performed, the tunnel oxide layer 2 and the first polysilicon layer 3 are plated around the second surface 12 of the silicon substrate 1 to form a plating around layer. To ensure the solar cell function, the wrapping layer on the second surface 12 of the silicon substrate 1 needs to be removed. Therefore, after removing the damaged layer, step S610 is further included:

the wrap-around coating of the second surface 12 of the silicon substrate 1 is removed to expose the second surface 12 of the silicon substrate 1.

In some embodiments, after removing the damaged layer, the exposed silicon substrate 1 is textured, for example, using a texturing process to form pyramid-like textured structures on the second surface 12 of the silicon substrate 1 and the second type region of the silicon substrate 1. The arrangement of the suede structure can reduce the reflection of sunlight, improve the absorptivity of the sunlight, and further improve the conversion efficiency of the solar cell.

Step S700: a passivation layer 5 and an anti-reflection layer 6 are sequentially formed on the first surface 11 and the second surface 12 of the silicon substrate 1.

In this step, a structure as shown in fig. 7 is obtained. Specifically, the passivation layer 5 may be a silicon oxide layer or an aluminum oxide layer, and may be formed by PECVD, ALD, or MOCVD, but is not limited thereto. The passivation layer 5 is used for further providing passivation effect of the solar cell, and the anti-reflection layer 6 is used for increasing light transmission, reducing reflection of sunlight and increasing light conversion effect of the cell.

The anti-reflection layer 6 may be a single layer or a multi-layer silicon nitride layer, and specifically, may be formed by PECVD, ALD, MOCVD, but is not limited thereto.

Step S800: a first electrode 71 is formed in the first type region and a second electrode 72 is formed in the second type region.

In this step, the structure shown in fig. 8 is obtained. Specifically, the first electrode may be an Al electrode, an Ag electrode, but is not limited thereto. In a preferred embodiment, the first electrode 71 may be an Al electrode, and when the silicon substrate 1 is a P-type silicon substrate, the Al electrode may be combined with the silicon substrate to form an Al-si alloy region, thereby forming a p++ junction, and further improving the light conversion efficiency.

Specifically, the second electrode 72 may be an Ag electrode, a Cu electrode, a Ni electrode, or a composite of several metals, but is not limited thereto.

Specifically, the first electrode 71 or the second electrode 72 may be formed by a screen printing technique, but is not limited thereto.

Specifically, a burn-through paste may be used to burn through the anti-reflection layer 6 and the passivation layer 5 so that the first electrode 71 is electrically connected to the silicon wafer and the second electrode 72 is electrically connected to the first polysilicon layer 3.

In another embodiment of the present invention, the anti-reflection layer 6 and the passivation layer 5 of the first type region may be removed using a laser ablation technique, and then the first electrode 71 is formed; the anti-reflection layer 6 and the passivation layer 5 of the second type region are removed using a laser ablation technique, and then the second electrode 72 is formed.

The embodiment of the invention also provides an IBC solar cell which is prepared by adopting the preparation method. As shown in fig. 8, the IBC solar cell comprises a silicon substrate 1, a passivation layer 5 and an anti-reflection layer 6 sequentially provided on a second surface 12 of the silicon substrate 1;

the first surface 11 of the silicon substrate 1 is provided with a first type region and a second type region which are arranged in a crossing manner, the second type region comprises a tunneling oxide layer 2, a first polysilicon layer 3, a passivation layer 5, an anti-reflection layer 6 and a second electrode 72 which are arranged in sequence, the second electrode 72 is electrically connected with the first polysilicon layer 3, the first type region comprises the passivation layer 5, the anti-reflection layer 6 and a first electrode 71 which are arranged in sequence, and the first electrode 71 is electrically connected with the silicon substrate 1.

the preparation method of the IBC solar cell provided by the invention comprises the following steps: a tunneling oxide layer, a first polysilicon layer and a blocking layer are sequentially arranged on the first surface of the silicon substrate; pushing the doping element into the silicon substrate through a diffusion process, and forming a heavily doped first polysilicon layer; removing the barrier layer in the central area of the silicon substrate by adopting laser etching; and forming a first type region on the first surface side of the silicon substrate by adopting laser etching, and removing the damaged layer of the first type region by adopting a polishing technology. By arranging the barrier layer in the edge area of the silicon substrate, the process window for removing the damaged layer can be widened, the damaged layer and impurities on the whole first surface of the silicon substrate can be removed completely, the thickness of the first polysilicon layer on the first surface of the silicon substrate after the damaged layer is removed is uniform, the electric leakage proportion of the edge of the battery is reduced, and the reliability of the solar battery is improved.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. The preparation method of the IBC solar cell is characterized by comprising the following steps:

removing the blocking layer of the first area by adopting laser;

2. The method for manufacturing an IBC solar cell according to claim 1, characterized in that the thickness of the barrier layer is 10-50 nm.

3. The method of claim 1, wherein the width of the second region is 1-15 mm.

4. The method of claim 1, wherein the barrier layer is a second polysilicon layer, a microcrystalline silicon layer, a silicon nitride layer, or a silicon oxide layer.

5. The method for fabricating an IBC solar cell according to claim 4, wherein when the barrier layer is a second polysilicon layer, the tunneling oxide layer, the first polysilicon layer and the barrier layer are sequentially formed on the first surface of the silicon substrate, comprising the steps of;

forming a tunneling oxide layer on the first surface of the silicon substrate;

6. The method of claim 1, wherein the tunnel oxide layer is formed by LPCVD.

7. The method of fabricating an IBC solar cell according to claim 1, further comprising the step, after the providing of the silicon substrate:

and polishing and cleaning the two sides of the silicon substrate.

8. The method of fabricating an IBC solar cell according to claim 1, wherein after etching the predetermined region of the first surface of the silicon substrate using the laser, the method comprises the steps of:

9. The method of claim 1, wherein the material of the first electrode comprises aluminum and the material of the second electrode comprises silver.

10. The method of claim 1, wherein the passivation layer comprises a silicon oxide layer or an aluminum oxide layer.

11. The method of fabricating an IBC solar cell according to claim 1, further comprising the steps of, after removing the damaged layer of the first type region by polishing:

12. An IBC solar cell prepared by the method of any one of claims 1 to 11.