CN117410306A - High-voltage light-emitting chip, manufacturing method thereof and display device - Google Patents

High-voltage light-emitting chip, manufacturing method thereof and display device Download PDF

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Publication number
CN117410306A
CN117410306A CN202310981462.5A CN202310981462A CN117410306A CN 117410306 A CN117410306 A CN 117410306A CN 202310981462 A CN202310981462 A CN 202310981462A CN 117410306 A CN117410306 A CN 117410306A
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layer
chip
sub
substrate
insulating layer
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桑永昌
谭胜友
李健林
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Huizhou Shiwei New Technology Co Ltd
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Huizhou Shiwei New Technology Co Ltd
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Priority to CN202310981462.5A priority Critical patent/CN117410306A/en
Publication of CN117410306A publication Critical patent/CN117410306A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

The embodiment of the application provides a high-voltage light emitting chip, a manufacturing method thereof and a display device, wherein the high-voltage light emitting chip comprises: a substrate; the sub-chip structures are sequentially arranged on the substrate at intervals, and isolation channels are formed between the adjacent sub-chip structures; the insulating layer is arranged on the substrate, covers the plurality of sub-chip structures and fills up the isolation channel, and a plurality of first through holes are formed in the surface of one side, far away from the substrate, of the insulating layer; the serial electrode layer is arranged on one side surface of the insulating layer, which is far away from the substrate, and comprises at least one serial electrode structure, wherein two adjacent sub-chip structures are connected in series through one serial electrode structure, and the serial electrode structure is electrically connected with the sub-chip structures through the first via hole; and the reflecting layer is arranged on the substrate and covers the insulating layer and the series electrode layer.

Description

High-voltage light-emitting chip, manufacturing method thereof and display device
Technical Field
The application relates to the technical field of photoelectric display, in particular to a high-voltage light-emitting chip, a manufacturing method thereof and a display device.
Background
The high-voltage LED chip is a light-emitting chip which uses a light-emitting diode (LED) as a light source and is suitable for direct high-voltage driving. In the related art, a reflection layer is arranged on the surface of the flip-chip high-voltage LED chip; however, the reflective layer is easy to crack, and water vapor in the environment can invade along the crack to cause chip leakage, so that the service life of the chip is shortened.
Disclosure of Invention
The embodiment of the application provides a high-voltage light-emitting chip, a manufacturing method thereof and a display device, which can eliminate or at least reduce the risk of cracks on a reflecting layer, improve the reliability of the chip and ensure the service life of the chip.
In a first aspect, embodiments of the present application provide a high voltage light emitting chip, including: a substrate; the sub-chip structures are sequentially arranged on the substrate at intervals, and isolation channels are formed between the adjacent sub-chip structures; the insulating layer is arranged on the substrate, covers the plurality of sub-chip structures and fills up the isolation channel, and a plurality of first through holes are formed in the surface of one side, far away from the substrate, of the insulating layer; the serial electrode layer is arranged on one side surface of the insulating layer, which is far away from the substrate, and comprises at least one serial electrode structure, wherein two adjacent sub-chip structures are connected in series through one serial electrode structure, and the serial electrode structure is electrically connected with the sub-chip structures through the first via hole; and the reflecting layer is arranged on the substrate and covers the insulating layer and the series electrode layer.
In some embodiments, the reflective layer is provided with a plurality of second vias, the insulating layer is provided with a plurality of third vias, and the second vias and the third vias are equal in number and are communicated in a one-to-one correspondence manner; the high-voltage light-emitting chip comprises a plurality of external electrodes, the external electrodes are respectively arranged on the reflecting layer, and the external electrodes are electrically connected with the sub-chip structure through the second via holes and the third via holes in sequence.
In some embodiments, the reflective layer is a planarization layer, and the plurality of external electrodes are respectively disposed on a surface of the reflective layer, which is far away from the substrate.
In some embodiments, the high-voltage light emitting chip includes an ohmic contact layer disposed between the sub-chip structure and the insulating layer and corresponding to the third via hole, and the external electrode is in contact with the ohmic contact layer through the second via hole and the third via hole.
In some embodiments, the sub-chip structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are sequentially stacked, the N-type semiconductor layer being in contact with the substrate, and the P-type semiconductor layer being in contact with the insulating layer.
In some embodiments, an isolation channel is formed between two adjacent sub-chip structures, and an orthographic projection of a series electrode structure connecting the two adjacent sub-chip structures in series on the substrate covers the isolation channel.
In some embodiments, the orthographic projection of the serial electrode layer on the substrate and the orthographic projection of the sub-chip structure to which the serial electrode layer is connected in series partially overlap on the substrate.
In a second aspect, an embodiment of the present application provides a method for manufacturing a high-voltage light emitting chip, including: sequentially forming a plurality of sub-chip structures at intervals on a substrate, and forming isolation channels between adjacent sub-chip structures; forming an insulating layer on one side of the substrate, which is provided with the plurality of sub-chip structures, wherein the insulating layer covers the plurality of sub-chip structures and fills up the isolation channel, and a plurality of first through holes are formed on the surface of one side of the insulating layer, which is far away from the substrate; forming a series electrode layer on a surface of one side of the insulating layer, which is far away from the substrate, wherein the series electrode layer comprises at least one series electrode structure, and the series electrode structure is electrically connected with the sub-chip structure through the first via hole; and forming a reflecting layer on one side of the substrate, on which the insulating layer is arranged, and covering the insulating layer and the series electrode layer.
In some embodiments, the forming an insulating layer on the side of the substrate on which the plurality of sub-chip structures are disposed includes: forming a first insulating medium layer on one side of the substrate provided with the plurality of sub-chip structures, wherein the first insulating medium layer covers the plurality of sub-chip structures; and carrying out planarization and opening treatment on the first insulating medium layer to form the insulating layer.
In a third aspect, embodiments of the present application provide a display device including the high-voltage light emitting chip provided in any one of the above embodiments.
According to the embodiment of the application, the insulating layer is arranged between the plurality of sub-chip structures and the series electrode layer, so that one side surface of the series electrode structure far away from the insulating layer is a plane area, the section difference formed on the surface of the series electrode structure in the reflecting layer can not be formed, the risk of cracks of the reflecting layer can be eliminated or at least reduced, the reliability of the high-voltage light-emitting chip is improved, and the service life of the high-voltage light-emitting chip is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a cross-sectional block diagram of a high voltage light emitting chip provided in some embodiments of the present application;
FIG. 2 is another cross-sectional block diagram of a high voltage light emitting chip provided in some embodiments of the present application;
FIG. 3 is a first process diagram of forming a plurality of sub-chip structures according to the method for fabricating a high voltage light emitting chip provided in some embodiments of the present application;
FIG. 4 is a second process diagram of forming a plurality of sub-chip structures according to the method for fabricating a high voltage light emitting chip provided in some embodiments of the present application;
FIG. 5 is a third process diagram of forming a plurality of sub-chip structures according to the method for fabricating a high voltage light emitting chip provided in some embodiments of the present application;
fig. 6 is a first process diagram of forming an insulating layer according to a method for manufacturing a high-voltage light emitting chip according to some embodiments of the present application;
fig. 7 is a second process diagram of forming an insulating layer according to a method for manufacturing a high-voltage light emitting chip according to some embodiments of the present application;
fig. 8 is a third process diagram of forming an insulating layer according to a method for manufacturing a high-voltage light emitting chip according to some embodiments of the present application;
fig. 9 is a process diagram of forming a series electrode layer according to a method for manufacturing a high-voltage light emitting chip according to some embodiments of the present application.
Description of main reference numerals:
10-substrate, 20-sub-chip structure, 21-N type semiconductor layer, 22-active layer, 23-P type semiconductor layer, 20' -epitaxial layer, 30-insulating layer, 31-first via hole, 32-third via hole, 30' -first insulating dielectric layer, 301' -filling part, 40-series electrode layer, 41-series electrode structure, 50-reflecting layer, 51-second via hole, 60-ohmic contact layer, 70-isolation channel and 80-external electrode.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.
The use of "adapted" or "configured to" in this application is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.
In this application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
In the related art, a reflection layer is provided on the surface of the flip-chip high-voltage LED chip. However, the area of the reflective layer above the serial electrode is prone to crack, and water vapor in the environment may invade along the crack to cause chip leakage, so that the service life of the chip is shortened.
As shown in fig. 1 to 2, in a first aspect, embodiments of the present application provide a high-voltage light emitting chip, which can eliminate or at least reduce the risk of cracking of the reflective layer 50, improve the reliability of the high-voltage light emitting chip, and ensure the service life of the high-voltage light emitting chip.
The high voltage light emitting chip includes a substrate 10, a plurality of sub-chip structures 20, an insulating layer 30, a series electrode layer 40, and a reflective layer 50. The type of the substrate 10 may be determined according to actual needs, and types such as a glass substrate, a flexible substrate, and the like may be used, which are not limited in the embodiment of the present application. In some embodiments, the substrate 10 may be a sapphire substrate made of a sapphire base material.
The plurality of sub-chip structures 20 are sequentially arranged on the substrate 10 at intervals, so that any two sub-chip structures 20 are not contacted with each other, and isolation channels 70 are formed between adjacent sub-chip structures 20. Here, the epitaxial layer 20 'may be grown and deposited on the substrate 10, and then the epitaxial layer 20' may be divided using patterning process to form the plurality of sub-chip structures 20 described above. The number of the sub-chip structures 20 may be determined according to actual needs, and may be any number of two or more, which is not limited in the embodiment of the present application. The type of the sub-chip structure 20 may be determined according to actual needs, and may be, for example, an LED light emitting structure, which is not limited in the embodiment of the present application.
The insulating layer 30 is disposed on the substrate 10 and covers the plurality of sub-chip structures 20 and fills up the isolation trenches 70. A plurality of first vias 31 are disposed on a surface of the insulating layer 30 away from the substrate 10, and the first vias 31 penetrate through the insulating layer 30 and extend to the surface of the sub-chip structure 20. Since the isolation trench 70 is filled with the insulating layer 30, there is no level difference on the upper surface of the insulating layer 30 corresponding to the region of the isolation trench 70, which is a planar region, and accordingly, the height difference between the region above the sub-chip structure 20 and the region above the isolation trench 70 is eliminated; accordingly, the plurality of first vias 31 may be disposed in the planar region.
Here, the insulating layer 30 may be made of an insulating medium such as silicon oxide, silicon nitride, or the like. In some embodiments, the insulating layer 30 may be a planarized layer that is planarized or partially planarized to be planarized; based on the planarization structure, the insulating layer 30 naturally also fills and covers the isolation trenches 70 between the adjacent sub-chip structures 20, so that the surface of the insulating layer 30 on the side most far from the substrate 10 is a flat surface. Here, the plurality of first vias 31 may be opened on a flat surface of the insulating layer 30.
The serial electrode layer 40 is disposed on a surface of the insulating layer 30, which is far away from the substrate 10, and the plurality of sub-chip structures 20 are sequentially connected in series through the serial electrode layer 40; the serial electrode layer 40 is electrically connected to the plurality of sub-chip structures 20 by contacting the plurality of first vias 31, that is, the serial electrode layer 40 fills the first vias 31 together. The material of the serial electrode layer 40 may be determined according to practical needs, and may be formed of a conductive material such as metal, which is not limited in the embodiment of the present application. Since the serial electrode layer 40 is formed on the planar area on the upper surface of the insulating layer 30, the different areas of the serial electrode layer 40 have uniform height positions, and the height difference between the different areas of the serial electrode layer 40 can be eliminated, so that the surface of the serial electrode layer 40 far from the insulating layer 30 is also a planar area.
Here, the series electrode layer 40 includes at least one series electrode structure 41, and adjacent two sub-chip structures 20 are connected in series by one series electrode structure 41; the series electrode structure 41 is electrically connected to the two sub-chip structures 20 connected in series by the two first vias 31, respectively, i.e. the series electrode structure 41 fills the two first vias 31, respectively. As shown in fig. 2, when the high voltage light emitting chip includes at least three sub-chip structures 20, the tandem electrode layer 40 may include at least two tandem electrode structures 41, the at least two tandem electrode structures 41 being spaced apart to be kept apart, each tandem electrode structure 41 being for connecting two sub-chip structures 20 adjacent thereto in series; here, the at least two tandem electrode structures 41 have the same layer arrangement relationship, and may be formed by processing the substrate of the tandem electrode layer 40 using, for example, a patterning process. Since the surface of the serial electrode layer 40 far from the insulating layer 30 is a planar area, the surface of the serial electrode structure 41 far from the insulating layer 30 is also a planar area, and no height difference exists.
As shown in fig. 1 to 2, a reflective layer 50 is disposed on the substrate 10 and covers the insulating layer 30 and the series electrode layer 40. In other words, the reflective layer 50 covers the region of the insulating layer 30 not covered by the series electrode structures 41, and the outer surface of each series electrode structure 41. The reflective layer 50 can be made of a material with higher reflectivity for the luminescence of the sub-chip structure 20, has better reflective effect for the luminescence of the sub-chip structure 20, and correspondingly improves the light utilization rate and the luminescence brightness of the high-voltage luminescence chip; the structure of the reflective layer 50 may be determined according to practical needs, and may be, for example, a distributed bragg reflector structure (distributed Bragg reflection, DBR for short), a metal mirror layer, or the like, which is not limited in the embodiment of the present application.
Since the surface of the series electrode structure 41 on the side away from the insulating layer 30 is a planar area, and no step is present in the planar area, no step is formed in the portion of the reflective layer 50 formed on the surface of the series electrode structure 41. In this way, it is possible to avoid stress concentration of the reflective layer 50 due to the step difference and thus crack occurrence in the region of the reflective layer 50 located above the series electrode structure 41, thereby avoiding exposure and leakage risk of the series electrode structure 41 due to the crack. Compared with the related art, the high-voltage light-emitting chip provided by the embodiment of the application can eliminate or at least reduce the risk of cracking of the reflecting layer 50, improve the reliability of the high-voltage light-emitting chip and ensure the service life of the high-voltage light-emitting chip.
In some embodiments, the reflective layer 50 may have a plurality of second vias 51 thereon, and the insulating layer 30 may have a plurality of third vias 32 thereon; the second vias 51 and the third vias 32 are equal in number and are correspondingly connected one to another, so that each second via 51 and one third via 32 are connected to form an integral via, and the integral via sequentially penetrates through the reflective layer 50 and the insulating layer 30. Here, the high voltage light emitting chip may include a plurality of external electrodes 80, and the plurality of external electrodes 80 are respectively disposed on the reflective layer 50; each external electrode 80 is electrically connected to the sub-chip structure 20 through a second via 51 and a third via 32 in sequence, i.e. the external electrode 80 is filled with a second via 51 and a third via 32 in sequence. The number of the external electrodes 80 may be determined according to actual needs, and more commonly may be two, so as to be respectively used as an external positive electrode and an external negative electrode, which is not limited in the embodiment of the present application. By providing the external electrode 80, the high-voltage light emitting chip and an external circuit can be electrically connected, and the driving voltage required by the high-voltage light emitting chip can be increased.
The configuration shape of the reflective layer 50 may be determined according to actual needs, and this is not limited in the embodiment of the present application. In some examples, the reflective layer 50 may be a planarization layer, and the plurality of external electrodes 80 are respectively disposed on a surface of the reflective layer 50 away from the substrate 10. Here, the reflective layer 50 may be made of an insulating material having a high reflectivity for light emission of the sub-chip structure 20; and the reflective layer 50 is planarized or partially planarized to be a planarized layer. Based on the planarization structure, when the series electrode layer 40 includes a plurality of series electrode structures 41 spaced apart to keep isolation, the reflective layer 50 also fills and covers the trenches between the adjacent sub-chip structures 20, so that a surface of the reflective layer 50 on a side most far from the substrate 10 is a planar area, and no height difference exists. In this way, the plurality of external electrodes 80 can be formed on the planar area without forming a step, so that the high-voltage light emitting chip has a relatively neat and consistent appearance structure.
In some examples, the high voltage light emitting chip may include an ohmic contact layer 60, the ohmic contact layer 60 being disposed between the sub-chip structure 20 and the insulating layer 30; here, the ohmic contact layer 60 and the third via hole 32 are provided in correspondence, and the external electrode 80 is electrically connected to the ohmic contact layer 60 through the second via hole 51 and the third via hole 32. By providing the ohmic contact layer 60, the external electrode 80 can be better electrically connected to the electrode terminal of the corresponding sub-chip structure 20. The material of the ohmic contact layer 60 may be determined according to practical needs, and may be made of a transparent conductive medium such as Indium Tin Oxide (ITO), which is not limited in this embodiment.
The structure of the sub-chip structure 20 may be determined according to actual needs, which is not limited in the embodiment of the present application. In some embodiments, the sub-chip structure 20 may include an N-type semiconductor layer 21, an active layer 22, and a P-type semiconductor layer 23, which are sequentially stacked. The N-type semiconductor layer 21 is in contact with the substrate 10, and the P-type semiconductor layer 23 is in contact with the insulating layer 30. The materials of the N-type semiconductor layer 21 and the P-type semiconductor layer 23 may be determined according to actual needs, and semiconductor materials such as gallium nitride (GaN) may be used, which is not limited in the embodiment of the present application. In some examples, in two sub-chip structures 20 adjacently disposed and connected in series, one end of the series electrode structure 41 may pass through a first via 31 and be electrically connected to the N-type semiconductor layer 21 of one of the sub-chip structures 20, and the other end may pass through another first via 31 and be electrically connected to the P-type semiconductor layer 23 of the other sub-chip structure 20.
In some embodiments, the orthographic projection of the serial electrode layer 40 on the substrate 10 may cover the corresponding isolation channel 70, so that the serial electrode layer 40 can better extend to contact the two sub-chip structures 20 located at two sides of the isolation channel 70, thereby achieving the serial connection purpose between the two sub-chip structures 20.
In some embodiments, the orthographic projection of the tandem electrode layer 40 on the substrate 10 may overlap with the orthographic projection of the sub-chip structure 20, to which the tandem electrode layer 40 is connected in series, on the substrate 10. By providing as above, the series electrode layer 40 can be extended to the area where the sub-chip structures 20 to be connected in series are located, so as to make contact connection through the first via hole 31.
In a second aspect, an embodiment of the present application provides a method for manufacturing a high-voltage light emitting chip, where the method includes S10 to S40, to manufacture the high-voltage light emitting chip provided in the foregoing embodiment.
S10: as shown in fig. 3 to 5, a plurality of sub-chip structures 20 are sequentially formed on a substrate 10 at intervals, and isolation trenches 70 are formed between adjacent sub-chip structures 20.
In some embodiments, an epitaxial layer 20 'may be formed on the substrate 10 as shown in fig. 3, and then the epitaxial layer 20' may be patterned as shown in fig. 4-5, forming a plurality of sub-chip structures 20 disposed at intervals. Here, the epitaxial layer 20' of a desired thickness may be formed on the substrate 10 by a semiconductor process such as a growth deposition. Here, the epitaxial layer 20 'may be divided by a material removal process such as film etching, laser removal, etc. to obtain a plurality of sub-chip structures 20, so as to achieve the purpose of patterning the epitaxial layer 20'; during this process, material is removed from the region between two adjacent sub-chip structures 20, while the region of the substrate 10 between two adjacent sub-chip structures 20 is exposed, such that isolation trenches 70 are formed between adjacent sub-chip structures 20.
S20: as shown in fig. 6 to 8, an insulating layer 30 is formed on the substrate 10 on the side where the plurality of sub-chip structures 20 are provided, the insulating layer 30 covers the plurality of sub-chip structures 20 and fills up the isolation trench 70, and a plurality of first vias 31 are provided on the surface of the insulating layer 30 on the side away from the substrate 10.
In some embodiments, the insulating layer 30 may be a planarized layer that is planarized or partially planarized to be planarized; based on the planarization structure, the insulating layer 30 naturally also fills and covers the isolation trenches 70 between the adjacent sub-chip structures 20, so that the surface of the insulating layer 30 on the side most far from the substrate 10 is a flat surface.
S30: as shown in fig. 9, a series electrode layer 40 is formed on a side surface of the insulating layer 30 remote from the substrate 10. The series electrode layer 40 comprises at least one series electrode structure 41, the series electrode structure 41 being electrically connected to the sub-chip structure 20 by the first via 31.
S40: as shown in fig. 1 or 2, a reflective layer 50 is formed on the substrate 10 on the side where the insulating layer 30 is provided, the reflective layer 50 covering the insulating layer 30 and the series electrode layer 40.
Compared with the related art, the high-voltage light-emitting chip manufactured by the manufacturing method provided by the embodiment of the application has the advantages that the risk of occurrence of cracks on the reflecting layer 50 is low, the reliability of the high-voltage light-emitting chip can be improved, and the service life of the high-voltage light-emitting chip can be guaranteed.
In some embodiments, S20 may include S201-S202.
S201: as shown in fig. 6, a first insulating dielectric layer 30 'is formed on the side of the substrate 10 where the plurality of sub-chip structures 20 are provided, and the first insulating dielectric layer 30' covers the plurality of sub-chip structures 20. Naturally, the first insulating dielectric layer 30' also fills and covers the isolation trenches 70 between adjacent sub-chip structures 20; the region of the first insulating dielectric layer 30 'filled with the isolation trench 70 is referred to as a filling portion 301', and a surface of the filling portion 301 'on a side away from the substrate 10 is located on a side of the sub-chip structure 20 away from the substrate 10, so that the filling portion 301' is filled to be higher than the top surface of the sub-chip structure 20. Here, the first insulating dielectric layer 30' may be an insulating dielectric such as silicon oxide, silicon nitride, or the like. In some examples, a first insulating dielectric layer 30' may be deposited over the entire side of the substrate 10 on which the plurality of sub-chip structures 20 are disposed.
S202: as shown in fig. 7 to 8, the first insulating dielectric layer 30' is planarized and perforated to form an insulating layer 30. Fig. 7 shows a planarization process of the first insulating dielectric layer 30', and fig. 8 shows an opening process of the first insulating dielectric layer 30'. Here, the planarization may be a full-face planarization or a partial planarization process, which is not limited in the embodiment of the present application. Specifically, a material removal process such as film etching, laser removal, or the like may be used to eliminate the surface level difference of the first insulating dielectric layer 30', so that the surface of the first insulating dielectric layer 30' on the side away from the substrate 10 is a flat surface with a uniform height; further, a plurality of first via holes 31 are formed in the planarized first insulating dielectric layer 30', thereby obtaining an insulating layer 30.
In a third aspect, embodiments of the present application provide a display device including the high-voltage light emitting chip provided in any one of the above embodiments. The type of the display device may be determined according to actual needs, and may be, for example, a product with a display function, such as a television, a display, an intelligent terminal, or a component thereof, which is not limited in the embodiment of the present application.
The high-voltage light emitting chip, the manufacturing method thereof and the display device provided by the embodiment of the application are described in detail, and specific examples are applied to the description of the principle and the implementation mode of the application, and the description of the above examples is only used for helping to understand the method and the core idea of the application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A high voltage light emitting chip, comprising:
a substrate;
the sub-chip structures are sequentially arranged on the substrate at intervals, and isolation channels are formed between the adjacent sub-chip structures;
the insulating layer is arranged on the substrate, covers the plurality of sub-chip structures and fills up the isolation channel, and a plurality of first through holes are formed in the surface of one side, far away from the substrate, of the insulating layer;
the serial electrode layer is arranged on one side surface of the insulating layer, which is far away from the substrate, and comprises at least one serial electrode structure, wherein two adjacent sub-chip structures are connected in series through one serial electrode structure, and the serial electrode structure is electrically connected with the sub-chip structures through the first via hole;
and the reflecting layer is arranged on the substrate and covers the insulating layer and the series electrode layer.
2. The high-voltage light-emitting chip according to claim 1, wherein a plurality of second through holes are formed in the reflecting layer, a plurality of third through holes are formed in the insulating layer, and the plurality of second through holes and the plurality of third through holes are equal in number and are communicated in a one-to-one correspondence manner;
the high-voltage light-emitting chip comprises a plurality of external electrodes, the external electrodes are respectively arranged on the reflecting layer, and the external electrodes are electrically connected with the sub-chip structure through the second via holes and the third via holes in sequence.
3. The high voltage light emitting chip of claim 2, wherein the reflective layer is a planarization layer, and the plurality of external electrodes are respectively disposed on a surface of the reflective layer away from the substrate.
4. The high-voltage light-emitting chip according to claim 2, wherein the high-voltage light-emitting chip includes an ohmic contact layer disposed between the sub-chip structure and the insulating layer and corresponding to the third via hole, and the external electrode is electrically connected to the ohmic contact layer through the second via hole and the third via hole.
5. The high-voltage light-emitting chip according to claim 1, wherein the sub-chip structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are sequentially stacked, the N-type semiconductor layer being in contact with the substrate, and the P-type semiconductor layer being in contact with the insulating layer.
6. The high voltage light emitting chip of claim 1, wherein an isolation channel is formed between two adjacent sub-chip structures, and an orthographic projection of a series electrode structure connecting the two adjacent sub-chip structures in series on the substrate covers the isolation channel.
7. The high voltage light emitting chip of claim 1, wherein the orthographic projection of the tandem electrode layer on the substrate and the orthographic projection of the sub-chip structure in which the tandem electrode layer is tandem on the substrate partially overlap.
8. A method for manufacturing a high-voltage light emitting chip, comprising:
sequentially forming a plurality of sub-chip structures at intervals on a substrate, and forming isolation channels between adjacent sub-chip structures;
forming an insulating layer on one side of the substrate, which is provided with the plurality of sub-chip structures, wherein the insulating layer covers the plurality of sub-chip structures and fills up the isolation channel, and a plurality of first through holes are formed on the surface of one side of the insulating layer, which is far away from the substrate;
forming a series electrode layer on a surface of one side of the insulating layer, which is far away from the substrate, wherein the series electrode layer comprises at least one series electrode structure, and the series electrode structure is electrically connected with the sub-chip structure through the first via hole;
and forming a reflecting layer on one side of the substrate, on which the insulating layer is arranged, and covering the insulating layer and the series electrode layer.
9. The method of manufacturing of claim 8, wherein forming an insulating layer on the side of the substrate on which the plurality of sub-chip structures are provided comprises:
forming a first insulating medium layer on one side of the substrate provided with the plurality of sub-chip structures, wherein the first insulating medium layer covers the plurality of sub-chip structures;
and carrying out planarization and opening treatment on the first insulating medium layer to form the insulating layer.
10. A display device comprising the high-voltage light-emitting chip according to any one of claims 1 to 7.
CN202310981462.5A 2023-08-04 2023-08-04 High-voltage light-emitting chip, manufacturing method thereof and display device Pending CN117410306A (en)

Priority Applications (1)

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CN202310981462.5A CN117410306A (en) 2023-08-04 2023-08-04 High-voltage light-emitting chip, manufacturing method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310981462.5A CN117410306A (en) 2023-08-04 2023-08-04 High-voltage light-emitting chip, manufacturing method thereof and display device

Publications (1)

Publication Number Publication Date
CN117410306A true CN117410306A (en) 2024-01-16

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