CN117410169A - Method for cleaning polycrystalline silicon wafer and method for recovering semiconductor device - Google Patents
Method for cleaning polycrystalline silicon wafer and method for recovering semiconductor device Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 162
- 238000000034 method Methods 0.000 title claims abstract description 91
- 238000004140 cleaning Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 115
- 238000005530 etching Methods 0.000 claims abstract description 82
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 65
- 239000010703 silicon Substances 0.000 claims abstract description 65
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052796 boron Inorganic materials 0.000 claims abstract description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 46
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000004151 rapid thermal annealing Methods 0.000 claims abstract description 25
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 239000011261 inert gas Substances 0.000 claims abstract description 14
- 239000011259 mixed solution Substances 0.000 claims abstract description 13
- 238000004064 recycling Methods 0.000 claims abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims 1
- 239000003153 chemical reaction reagent Substances 0.000 abstract description 11
- 230000008569 process Effects 0.000 description 20
- 238000011084 recovery Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 239000003795 chemical substances by application Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
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- 230000003252 repetitive effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02079—Cleaning for reclaiming
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a method for cleaning a polycrystalline silicon wafer and a method for recycling a semiconductor device, and belongs to the technical field of semiconductors. The method for cleaning the polycrystalline silicon wafer comprises the steps of growing an oxide layer on the surface of a silicon wafer substrate; growing a doped polysilicon layer on the surface of the oxide layer; carrying out rapid thermal annealing treatment on the silicon wafer after a doped polysilicon layer grows in an inert gas environment; and cleaning the silicon wafer after the thermal annealing treatment by using a mixed solution of hydrofluoric acid and nitric acid. According to the invention, the silicon wafer after the growth of the layer of the polysilicon doped with boron is subjected to rapid thermal annealing treatment in the inert gas environment, the selectivity ratio of the etching rate of the polysilicon doped with boron and the etching rate of the silicon oxide layer after the high-temperature thermal annealing treatment are obviously improved, the etching time is shortened, and the thickness of the oxide layer is enough to block the etching of the etching reagent when the excessive etching is performed, so that the silicon wafer substrate is prevented from being corroded.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for cleaning a polycrystalline silicon wafer and a method for recycling a semiconductor device.
Background
Polysilicon thin film is widely used as an interconnect in MOS transistor gates and MOS circuits, it can also be used as a resistor, and ensures ohmic contact of shallow junctions, and polysilicon is compatible with high temperature processing, the interface of thermal process silicon dioxide is very good. Heavily doped polysilicon films can be used for emitter structures of bipolar circuits, lightly doped polysilicon films can also be used as resistors, polysilicon having an extremely important role in the fabrication of semiconductor chips by virtue of its excellent physical and chemical properties.
For the monitoring of the quality of the process, the parameters such as the particle, thickness, resistivity, doping amount and the like of the process can be monitored by using a control wafer, and the control wafer of the polysilicon can be effectively recycled and reused, so that the method has important economic significance and value. Generally, for etching recovery of polysilicon, acidic hydrofluoric acid and nitric acid (i.e., HF/HNO) which are economically inexpensive are used as etching reagents. Referring to fig. 1, fig. 1 is a schematic diagram of a polysilicon wafer structure according to an embodiment. Wherein, 10-silicon chip substrate; 20-silicon oxide layer. Typically, for a polysilicon wafer, an oxide layer, such as silicon oxide layer 20, is grown prior to growing the polysilicon layer on the wafer substrate 10. The silicon oxide layer 20 acts as a buffer layer to reduce the effect of the stress of the polysilicon to some extent and also acts as a barrier layer. The following reaction formula: si+HNO 3 +6HF→H 2 SiF 6 +HNO 2 +H 2 O+H 2 In the reaction process, the silicon wafer substrate 10 is etched by the HF/HNO, so that the silicon oxide layer 20 can be used as a barrier layer to effectively protect the silicon wafer substrate 10 from being further etched in order to prevent the influence on the etching of the silicon wafer substrate 10.
However, the same HF/HNO etch rate may also be different for different types of polysilicon. Referring to fig. 4 to 6, fig. 4 is a schematic diagram showing an etching rate of a polysilicon layer doped with boron. Fig. 5 is a schematic diagram of the etch rate of a polysilicon layer doped with phosphorus. Fig. 6 is a schematic diagram of the etch rate of an undoped polysilicon layer. Wherein 80-is a boron doped polysilicon layer; 90-a polysilicon layer doped with phosphorus; 100-undoped polysilicon layer; 60-comparative legend. Under the condition that the same HF/HNO volume ratio is 1:50 as an etching reagent, according to a comparison diagram 60, the etching rate of the polysilicon layer 80 doped with boron as shown in fig. 4 is generally only about 188.0A/s, and 3sigma of a plurality of measuring points on the polysilicon wafer is 24.8A/s, wherein 3sigma is used for representing the uniformity of etching rate distribution. However, as can be seen from the comparative example 60, the etching rate of the polysilicon layer 90 doped with phosphorus as shown in fig. 5 was higher than 867.0 a/s, and the 3sigma of the plurality of measurement points on the polysilicon wafer was 197.0 a/s. As can be seen from the comparison of the graph 60, the etching rate of the undoped polysilicon layer 100 shown in fig. 6 is about 700 a/s, and the 3sigma of the plurality of measurement points on the polysilicon wafer is 11.70 a/s. And the etch rate of the boron doped polysilicon layer 80, the etch rate of the phosphorous doped polysilicon layer 90, and the selectivity of the undoped polysilicon layer 100 to the etch rate of the silicon oxide layer 20 were at 9, 42.5, and 35, respectively, with large fluctuations.
The difference of the etching rates can cause a certain influence on the process of recovering and etching the silicon wafer. However, for the polysilicon layer 80 doped with boron with relatively low etching rate, since the selectivity of the etching agent to the polysilicon layer 80 doped with boron and the silicon oxide layer 20 is relatively low, when the thicker polysilicon layer 80 doped with boron is removed, a certain etching is caused to the silicon of the silicon wafer substrate 10 due to the influence of excessive etching in the wet etching process, and the silicon oxide layer 20 of the silicon wafer substrate 10 after excessive etching cannot effectively block the corrosion of the etching agent, which can bring irreversible results to the silicon wafer. This is due to the selective ratio of the etch rates of the buffer stop layer (i.e., silicon oxide layer 20) and the boron doped polysilicon layer 80.
It should be noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a method for cleaning a polycrystalline silicon wafer and a method for recycling a semiconductor device, which are used for solving the technical problem that a silicon wafer substrate is corroded due to insufficient thickness of an oxide layer for blocking etching of an etching reagent when the polycrystalline silicon wafer is recycled and excessively etched.
In order to solve the technical problems, the invention provides a method for cleaning a polycrystalline silicon wafer, which comprises the following steps:
growing an oxide layer on the surface of the silicon wafer substrate;
growing a doped polysilicon layer on the surface of the oxide layer;
carrying out rapid thermal annealing treatment on the silicon wafer after a doped polysilicon layer grows in an inert gas environment;
and cleaning the silicon wafer after the thermal annealing treatment by using a mixed solution of hydrofluoric acid and nitric acid.
Preferably, the temperature of the rapid thermal annealing is 800-1050 ℃, and the time of the rapid thermal annealing treatment is 5-15 seconds.
Preferably, the time for cleaning the silicon wafer after the thermal annealing treatment by using the mixed solution of hydrofluoric acid and nitric acid is as follows:
，
wherein n is an excessive etching coefficient, and the value range of n is 1.3-1.6.
Preferably, the doped polysilicon layer is a P-type doped polysilicon layer.
Preferably, the doped polysilicon layer is doped with boron, gallium, or aluminum.
Preferably, the oxide layer is a silicon oxide layer.
Preferably, the thickness of the silicon oxide layer is 500 a-2000 a.
Preferably, when the silicon wafer after the thermal annealing treatment is cleaned by using a mixed solution of hydrofluoric acid and nitric acid, the selectivity K of the doped polysilicon layer and the silicon oxide layer is calculated as follows:
wherein the value range of K is 11-37.
Preferably, the inert gas is nitrogen.
Preferably, the volume ratio of the hydrofluoric acid to the nitric acid is 1:30-1:50, wherein the mass fraction of the hydrofluoric acid is 49%, and the mass fraction of the nitric acid is 70%.
Based on the same inventive concept, the invention also provides a recovery method of the semiconductor device, comprising the following steps:
the polycrystalline silicon wafer is cleaned by the cleaning method of the polycrystalline silicon wafer.
Compared with the prior art, the method for cleaning the polycrystalline silicon wafer has the following advantages:
according to the invention, an oxide layer is grown on the surface of a silicon wafer substrate; growing a doped polysilicon layer on the surface of the oxide layer; carrying out rapid thermal annealing treatment on the silicon wafer after a doped polysilicon layer grows in an inert gas environment; and cleaning the silicon wafer after the thermal annealing treatment by using a mixed solution of hydrofluoric acid and nitric acid. Therefore, according to the method for cleaning the polycrystalline silicon wafer, the silicon wafer after the growth of the layer of the polycrystalline silicon layer doped with boron is subjected to rapid thermal annealing treatment in the inert gas environment, the etching rate of hydrofluoric acid and nitric acid on the polycrystalline silicon layer doped with boron is increased from the original 188A/s to 360A/s, the etching rate of hydrofluoric acid and nitric acid on the buffer layer silicon oxide layer is obviously increased, however, the etching rate of hydrofluoric acid and nitric acid on the buffer layer silicon oxide layer is not obviously changed due to the high-temperature rapid thermal annealing treatment, the selection ratio of the etching rates of the polycrystalline silicon layer doped with boron and the silicon oxide layer after the high-temperature thermal annealing is obviously changed, and the etching time is reduced. And further, the thickness of the oxide layer is enough to block the etching of the etching reagent when the silicon wafer is excessively etched in the cleaning process, so that the silicon wafer substrate is prevented from being corroded. Therefore, the method can use limited resources, reasonably and effectively recycle the polycrystalline silicon chip doped with boron, can be effectively recycled, and has important economic significance and value.
The recovery method of the semiconductor device provided by the invention and the cleaning method of the polycrystalline silicon wafer provided by the invention belong to the same invention conception, so that the recovery method of the semiconductor device provided by the invention has at least all advantages of the cleaning method of the polycrystalline silicon wafer provided by the invention, and is not repeated herein. Further, the recovery method of the semiconductor device provided by the invention comprises the cleaning method of the polycrystalline silicon wafer, so that the thickness of the oxide layer is enough to block etching of the etching reagent in the process of cleaning the silicon wafer and prevent the silicon wafer substrate from being corroded in the process of excessive etching, and therefore, the recovery method of the semiconductor device provided by the invention can prevent the recovered silicon wafer substrate from being corroded in the process of recovering the semiconductor device and improve the recovery yield of the semiconductor device.
Drawings
FIG. 1 is a schematic diagram of a polysilicon wafer in one embodiment.
FIG. 2 is a schematic diagram of a polysilicon wafer in another embodiment.
Fig. 3 is a schematic view of a polysilicon wafer in a third embodiment.
Fig. 4 is a schematic diagram of the etch rate of a boron doped polysilicon layer.
Fig. 5 is a schematic diagram of the etch rate of a polysilicon layer doped with phosphorus.
Fig. 6 is a schematic diagram of the etch rate of an undoped polysilicon layer.
Fig. 7 is a schematic structural view of a polycrystalline silicon wafer provided in the present invention.
Fig. 8 is a top view of a polysilicon wafer after being cleaned without the polysilicon wafer cleaning method provided by the present invention.
Fig. 9 is an enlarged schematic view of the polysilicon wafer of fig. 8.
Fig. 10 is a flowchart of a method for cleaning a polysilicon wafer according to the present invention.
Fig. 11 is a schematic diagram of a polysilicon wafer after cleaning by the cleaning method of the polysilicon wafer provided by the invention.
Fig. 12 is a top view of the polysilicon wafer of fig. 11.
Fig. 13 is a schematic diagram of the etching rate of a boron doped polysilicon layer of a polysilicon wafer without rapid thermal annealing.
Fig. 14 is a schematic diagram showing the etching rate of a boron doped polysilicon layer of a polysilicon wafer subjected to rapid thermal annealing treatment according to the present invention.
Wherein, 10-silicon chip substrate; a 20-silicon oxide layer; a 30-silicon nitride layer; 40-etching the layer; 50-holes; 60-comparative legend; a 70-doped polysilicon layer; 80-a boron doped polysilicon layer; 90-a polysilicon layer doped with phosphorus; 100-undoped polysilicon layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the cleaning method for a polysilicon wafer and the recycling method for a semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It should be understood that the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Specific design features of the invention disclosed herein, including for example, specific dimensions, orientations, positions, and configurations, will be determined in part by the specific intended application and use environment. In the embodiments described below, the same reference numerals are used in common between the drawings to denote the same parts or parts having the same functions, and the repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
One embodiment of a method for cleaning a polysilicon wafer is disclosed with reference to fig. 1-14. The method for cleaning the polycrystalline silicon wafer comprises the following steps S1 to S4. Step S1: growing an oxide layer on the surface of the silicon wafer substrate 10; step S2: growing a doped polysilicon layer 70 on the surface of the oxide layer; step S3: carrying out rapid thermal annealing treatment on the silicon wafer after the doped polysilicon layer 70 is grown in an inert gas environment; step S4: and cleaning the silicon wafer after the thermal annealing treatment by using a mixed solution of hydrofluoric acid and nitric acid.
Referring to fig. 7, the oxide layer in step S1 is a silicon oxide layer 20. The doped element in the doped polysilicon layer 70 in step S2 may be boron, gallium, aluminum, or the like. So long as the doped element can act as a P-type doped polysilicon layer. This embodiment will be explained below taking boron as an example of the doped element.
Referring to fig. 1-9, during a conventional etch of a boron doped polysilicon layer 80, the etch rate is around 188 a/s, where "a/s" represents "the thickness etched per unit time". During the recovery of the silicon wafer, it is often necessary to over etch the wafer. The excessive etching herein means that the time for cleaning the silicon wafer by using HF/HNO is prolonged by 30% -60%, preferably 30% compared with the conventional cleaning time. For example, the original etching time for the silicon wafer is 90 seconds, and when the excessive etching is performed, the actual etching time is 90×1+0.3=117 seconds. When the silicon wafer doped with boron is excessively etched, 100 seconds to 140 seconds, preferably 120 seconds, are required. For the thickness of the buffer oxide layer (i.e., the silicon oxide layer 20), the etching rate of the silicon oxide layer 20 is generally 10A/S-30A/S, preferably 20A/S, which is a thickness that only blocks the etching time of 50S. When the silicon wafer is not cleaned by the cleaning method of the polycrystalline silicon wafer provided in the embodiment, for example, when etching a 16K silicon wafer, an etching layer 40 as shown in fig. 8 is formed on the surface of the silicon wafer substrate 10, and the surface of the etching layer 40 has the rugged holes 50 as shown in fig. 9. The wafer is etched away by the chemical agent (i.e., HF/HNO) during recycling, under conditions of excessive etching, which can give irreversible results to the wafer.
The silicon wafer is also a polycrystalline silicon wafer, and for convenience of distinction, a polycrystalline silicon wafer which has not been cleaned by the cleaning method of a polycrystalline silicon wafer provided in this embodiment is referred to as a silicon wafer, and a silicon wafer which has been cleaned by the cleaning method of a polycrystalline silicon wafer provided in this embodiment is referred to as a polycrystalline silicon wafer.
In order to solve the above technical problems, the influence of the etching rate selection ratio of the silicon oxide layer 20 and the polysilicon layer is alleviated. In the conventional processing manner, referring to fig. 2, one way is to block the corrosion of the silicon wafer substrate 10 by the corrosion inhibitor by increasing the thickness of the silicon oxide layer 20. Referring to fig. 3, another way is to grow a silicon nitride layer 30 on the silicon oxide layer 20, so that the selectivity of the etching agent and the protective film layer can be improved. The third way is to change the original acid etching (such as HF/HNO) into alkaline etching. However, the first and second methods described above require more and more of the original silicon wafer substrate 10, and have certain limitations of use and economic waste. However, the third method has a problem that resources are limited because resources of different types of chemical reagents cannot be efficiently provided in an actual industrial manufacturing plant. Therefore, the method uses limited resources, and reasonably and effectively recycles the silicon chip doped with boron, which has important economic significance and value.
However, in the method for cleaning a polysilicon wafer disclosed in this embodiment, since the polysilicon wafer after growing a layer of polysilicon layer 80 doped with boron is subjected to rapid thermal annealing treatment in an inert gas environment, the etching rate of hydrofluoric acid and nitric acid to the polysilicon layer 80 doped with boron is increased from the original 188.0 a/s to 330.0 a/s to 370.0 a/s, the etching rate is obviously increased, the etching time is reduced, but the etching rates of hydrofluoric acid and nitric acid to the buffer layer silicon oxide layer 20 are not obviously changed due to the treatment of the high-temperature rapid thermal annealing process, and are still 20.0 a/s. Further, the selectivity of the etching rate of the polysilicon layer 80 doped with boron and the silicon oxide layer 20 after the high temperature thermal annealing is obviously changed, and the selectivity of the etching rate of the polysilicon layer 80 doped with boron to the silicon oxide layer 20 after the high temperature rapid thermal annealing process is changed from 9.0 to 17.5 or more, thereby greatly improving the effective selective etching of hydrofluoric acid and nitric acid chemical reagents to the polysilicon layer 80 doped with boron and the silicon oxide layer 20. Further, the thickness of the silicon oxide layer 20 is enough to block the etching of the etching reagent and prevent the silicon substrate 10 from being corroded when the polycrystalline silicon wafer is excessively etched in the cleaning process. Therefore, the method can use limited resources, reasonably and effectively recycle the polycrystalline silicon chip doped with boron, can be effectively recycled, and has important economic significance and value.
Wherein the selectivity K of the etch rates of the doped polysilicon layer 70 and the silicon oxide layer 20 after the high temperature thermal annealing is calculated as follows:
the etching rate of the doped polysilicon layer 70 is 330.0A/S-370.0A/S for the polysilicon layer 80 doped with boron; the etching rate of the silicon oxide layer 20 is 10.0 to 30.0A/s. Substituting the etching rate of the polysilicon layer 80 doped with boron and the etching rate of the silicon oxide layer 20 into the above formula can calculate the selection ratio K, wherein the value range of K is 11-37. The value of K can be any of 11, 18, 20, 25, 37 and 11-37. Preferably, the value range of K is 16-20. Taking the example that the etching rate of the polysilicon layer 80 doped with boron is preferably 350.0 a/s and the etching rate of the silicon oxide layer 20 is preferably 20.0 a/s, substituting the above formula to calculate K is equal to 17.5.
The method for cleaning the polysilicon wafer according to the present embodiment is specifically described below with reference to the accompanying drawings.
Step S1: an oxide layer is grown on the surface of the silicon wafer substrate 10.
Specifically, referring to fig. 7 and 10, a silicon oxide layer 20 is grown on the surface of the silicon wafer substrate 10 by using a chemical vapor deposition method or a thermal oxidation method, and serves as a stress buffer layer to prevent the silicon wafer substrate 10 from being damaged. The thickness of the silicon oxide layer 20 here corresponds to the thickness of the silicon oxide layer 20 shown in fig. 1. That is, the thickness of the silicon oxide layer 20 is not thickened at this point, and the demand for the original silicon wafer substrate 10 is not increased in such a manner, and a certain use limitation and economic waste are avoided. In this embodiment, the thickness of the silicon oxide layer 20 is typically 500 a to 2000 a. Preferably, the thickness of the silicon oxide layer 20 is 500 a to 1000 a.
Step S2: a doped polysilicon layer 70 is grown on the surface of the oxide layer.
Specifically, with continued reference to fig. 10, a boron doped polysilicon layer 80 is deposited on the surface of the silicon oxide layer 20, one method being diffusion, using BCl 3 And N 2 Mixed gas and SiH of composition 4 The gases are heated together to heat the boron dopant with the silicon material to penetrate the boron atoms into the silicon crystal. Boron may thus be doped into the polysilicon layer as a gate. Wherein BCl 3 The volume ratio of the mixed gas is 1%, and the air flow of the mixed gas is 300 sccm-400 sccm. SiH (SiH) 4 The air flow rate is 700sccm to 800sccm. Wherein "sccm" is "volumetric flow rate". The reaction temperature is 450-550 ℃. Another approach is to use ion implantation techniques. Ion implantation techniques achieve doped polysilicon layers by implanting boron ions into the silicon crystal. This method can be performed without heating the silicon material. In this embodiment, the polysilicon layer 80 doped with boron is a P-type doped polysilicon layer.
Step S3: the wafer after growing a doped polysilicon layer 70 is subjected to a rapid thermal annealing process in an inert gas atmosphere.
Specifically, as shown in fig. 10, the polycrystalline silicon wafer doped with the boron polycrystalline silicon layer 80 is placed in a rapid thermal annealing machine, and is subjected to rapid thermal annealing at 800-1050 ℃ in an inert gas environment, and the treatment time is 5-15 seconds. The inert gas may be nitrogen, helium, etc., and in this embodiment, preferably, the inert gas is nitrogen.
Step S4: and cleaning the silicon wafer after the rapid thermal annealing treatment by using a mixed solution of hydrofluoric acid and nitric acid.
Specifically, as shown in fig. 10 to 14, a mixed solution of hydrofluoric acid and nitric acid is disposed in a cleaning tank of a wafer cleaning machine. The specific process for preparing the mixed solution of hydrofluoric acid and nitric acid is as follows: selecting hydrofluoric acid with the mass fraction of 49% and nitric acid with the mass fraction of 70%, adding the hydrofluoric acid and the nitric acid into a cleaning tank according to the volume ratio of 1:30-1:50, mixing, and uniformly stirring. And placing the polycrystalline silicon wafer subjected to the rapid thermal annealing treatment in a cleaning tank for cleaning so as to etch the polycrystalline silicon wafer subjected to the thermal annealing treatment. The time for cleaning the polysilicon wafer after the rapid thermal annealing treatment by using the mixed solution of hydrofluoric acid and nitric acid is prolonged by 30% -60%, preferably by 30%, so as to carry out excessive etching on the polysilicon wafer. That is, the time for cleaning the silicon wafer after the thermal annealing treatment by using the mixed solution of hydrofluoric acid and nitric acid is:
，
where n is the excess etch coefficient. n is generally 1.3 to 1.6. In this embodiment, n is preferably 1.3. In this embodiment, the time for over etching the polysilicon wafer may be 100 seconds to 140 seconds, preferably 120 seconds.
Referring to fig. 13, it can be seen from comparative example 60 that the average etch rate for the boron doped polysilicon layer 80 that is not subjected to the rapid thermal anneal process is about 190.0 a/s. The boron doped polysilicon layer 80 that was not subjected to the rapid thermal anneal process had a 3sigma of 26.0 a/s. The polysilicon layer 80 doped with boron was etched with a hydrofluoric acid/nitric acid etching agent having a volume ratio of hydrofluoric acid to nitric acid of 1:50 for 70 seconds using a hydrofluoric acid of 49% by mass and a nitric acid of 70% by mass, the etched thickness being 13.0K a. Referring to FIG. 14, it can be seen from a comparison of the graph 60 that the average etch rate for the boron doped polysilicon layer 80 subjected to the rapid thermal anneal process is 330A/s-370A/s. The boron doped polysilicon layer 80 is subjected to a rapid thermal anneal process having a 3sigma of 46.0 a/s. The polysilicon layer 80 doped with boron is etched for 70 seconds with a hydrofluoric acid/nitric acid etching agent with a volume ratio of hydrofluoric acid to nitric acid of 1:50 using a hydrofluoric acid with a mass fraction of 49% and a nitric acid with a mass fraction of 70%, and the etched thickness is 25K a. Obviously, the etching rate of the polysilicon layer 80 doped with boron is significantly improved for the polysilicon wafer subjected to the rapid thermal annealing treatment. The selectivity of the etching rate of the boron doped polysilicon layer 80 to the silicon oxide layer 20 after the high temperature rapid thermal annealing process is changed from 9 to 17.5 or more, thereby greatly improving the effective selective etching of the boron doped polysilicon layer 80 and the silicon oxide layer 20 by the hydrofluoric acid and nitric acid chemical reagents. When the polycrystalline silicon chip is excessively etched, only 57S is needed. This gives the buffer layer silicon oxide layer 20 sufficient time to protect the substrate silicon from further etching. Further, the thickness of the silicon oxide layer 20 is enough to block the etching of the etching reagent in the process of cleaning the polycrystalline silicon wafer, so that the silicon wafer substrate 10 is prevented from being corroded, and the recovered polycrystalline silicon wafer is prevented from corroding the silicon wafer substrate 10 under the condition of excessive etching as shown in fig. 12. Therefore, the method can use limited resources, reasonably and effectively recycle the polycrystalline silicon chip, and has important economic significance and value.
The embodiment also discloses a recovery method of the semiconductor device, which comprises the following steps: the polycrystalline silicon wafer is cleaned by the cleaning method of the polycrystalline silicon wafer.
The recovery method of the semiconductor device provided in this embodiment belongs to the same inventive concept as the cleaning method of the polysilicon wafer provided in this embodiment, so the recovery method of the semiconductor device provided in this embodiment has at least all the advantages of the cleaning method of the polysilicon wafer provided in this embodiment, and will not be described in detail herein. Further, since the recovery method of the semiconductor device provided in this embodiment includes the method for cleaning a polysilicon wafer, the thickness of the silicon oxide layer 20 is sufficient to block etching of the etching agent and prevent the silicon wafer substrate 10 from being corroded during the process of cleaning the polysilicon wafer, so that the recovery method of the semiconductor device provided in this embodiment can prevent the recovered silicon wafer substrate 10 from being corroded during the recovery of the semiconductor device, and improve the recovery yield of the semiconductor device.
In summary, the foregoing embodiments describe in detail different configurations of the method for cleaning a polysilicon wafer and the method for recovering a semiconductor device, however, the foregoing description is merely illustrative of preferred embodiments of the present invention, and not limiting to the scope of the present invention, which includes but is not limited to the configurations listed in the foregoing embodiments, and those skilled in the art can make any changes and modifications according to the foregoing disclosure, which are within the scope of the claims.
Claims (10)
1. The method for cleaning the polycrystalline silicon wafer is characterized by comprising the following steps of:
growing an oxide layer on the surface of the silicon wafer substrate;
growing a doped polysilicon layer on the surface of the oxide layer;
carrying out rapid thermal annealing treatment on the silicon wafer after a doped polysilicon layer grows in an inert gas environment;
cleaning the silicon wafer after the thermal annealing treatment by using mixed liquid of hydrofluoric acid and nitric acid;
the temperature of the rapid thermal annealing is 800-1050 ℃, and the time of the rapid thermal annealing treatment is 5-15S.
2. The method for cleaning a polycrystalline silicon wafer according to claim 1, wherein the time for cleaning the silicon wafer after the thermal annealing treatment with a mixed solution of hydrofluoric acid and nitric acid is as follows:
，
wherein n is an excessive etching coefficient, and the value range of n is 1.3-1.6.
3. The method of claim 1, wherein the doped polysilicon layer is a P-type doped polysilicon layer.
4. The method of claim 1, wherein the doped polysilicon layer is doped with boron, gallium, or aluminum.
5. The method of claim 1, wherein the oxide layer is a silicon oxide layer.
6. The method of claim 5, wherein the silicon oxide layer has a thickness of 500 a to 2000 a.
7. The method for cleaning a polycrystalline silicon wafer according to claim 6, wherein the selectivity K of the doped polycrystalline silicon layer and the silicon oxide layer is calculated as follows when the silicon wafer after the thermal annealing treatment is cleaned with a mixed solution of hydrofluoric acid and nitric acid:
wherein the value range of K is 11-37.
8. The method for cleaning a polycrystalline silicon wafer according to claim 1, wherein the volume ratio of hydrofluoric acid to nitric acid is 1:30-1:50, the mass fraction of hydrofluoric acid is 49%, and the mass fraction of nitric acid is 70%.
9. The method for cleaning a polycrystalline silicon wafer according to claim 1, wherein the inert gas is nitrogen.
10. A recycling method of a semiconductor device, comprising:
a method of cleaning a polycrystalline silicon wafer using the cleaning method of a polycrystalline silicon wafer according to any one of claims 1 to 9.
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| US5013675A (en) * | 1989-05-23 | 1991-05-07 | Advanced Micro Devices, Inc. | Method of forming and removing polysilicon lightly doped drain spacers |
| JP2001326273A (en) * | 2000-05-16 | 2001-11-22 | Denso Corp | Method for manufacturing semiconductor device |
| CN115910756A (en) * | 2023-01-09 | 2023-04-04 | 华虹半导体(无锡)有限公司 | Wafer cleaning method |
| CN117059477A (en) * | 2023-10-10 | 2023-11-14 | 粤芯半导体技术股份有限公司 | Method for cleaning multi-layer polysilicon and semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013675A (en) * | 1989-05-23 | 1991-05-07 | Advanced Micro Devices, Inc. | Method of forming and removing polysilicon lightly doped drain spacers |
| JP2001326273A (en) * | 2000-05-16 | 2001-11-22 | Denso Corp | Method for manufacturing semiconductor device |
| CN115910756A (en) * | 2023-01-09 | 2023-04-04 | 华虹半导体(无锡)有限公司 | Wafer cleaning method |
| CN117059477A (en) * | 2023-10-10 | 2023-11-14 | 粤芯半导体技术股份有限公司 | Method for cleaning multi-layer polysilicon and semiconductor device |
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