CN117408210A

CN117408210A - Photoelectric packaging structure and photon computing system

Info

Publication number: CN117408210A
Application number: CN202210796603.1A
Authority: CN
Inventors: 吴建华; 卢正观; 孟怀宇; 达迪.塞蒂亚迪; 罗恩.斯沃岑特鲁伯; 苏湛; 莫.斯坦曼; 陈俊杰; 彭博; 沈亦晨
Original assignee: Nanjing Guangzhiyuan Technology Co ltd
Current assignee: Nanjing Guangzhiyuan Technology Co ltd
Priority date: 2022-07-06
Filing date: 2022-07-06
Publication date: 2024-01-16
Also published as: TW202403372A; WO2024007945A1

Abstract

An optoelectronic package structure and a photonic computing system are provided. The photoelectric packaging structure comprises: a substrate comprising a core layer, an optical interconnect network, and an electrical interconnect network; and a chip array disposed on the first surface of the substrate, including at least one optical chip and at least one electrical chip; the optical chip is optically interconnected through the optical interconnection network, and the electrical chip is electrically interconnected through the electrical interconnection network. Some or all of the at least one optical chip and at least one electrical chip form an electronic-photonic hybrid chip comprising an optical chip and an electrical chip, and the electrical interconnect network comprises one or more second conductive vias through the substrate, the second surface of the substrate having solder structures for soldering to a printed circuit board, the solder structures being electrically connected to the electrical interconnect network.

Description

Photoelectric packaging structure and photon computing system

Technical Field

The present disclosure relates to the field of semiconductors, and more particularly, to an optoelectronic package structure and a photonic computing system.

Background

The development of silicon electronic integrated circuits has benefited from a generation-by-generation improvement in lithography and other manufacturing innovations over several decades, with ever increasing transistor performance and interconnect density. Over time, the performance of silicon electronic integrated circuits has become closer to the physical limits of technology, and the pace of improvement has slowed. Industry professionals have used advanced packaging techniques to overcome this limitation by expanding the available area or volume to electrically connect multiple silicon integrated circuits, or to place multiple silicon integrated circuits side-by-side, or to stack multiple silicon integrated circuits together, or to variously combine the two techniques. While these techniques inject new viability for scalability by polymerizing more silicon, they are still limited by the chip size and available adjacent surfaces or edges for inter-chip communication, and there are problems with cooling and powering the assembled modules.

Disclosure of Invention

In view of the foregoing, the present disclosure provides an optoelectronic package structure and photonic computing system that greatly expands computing and interconnect capabilities by using optical signals on a substrate with higher bandwidth per unit area and more fully connected topology that is not limited by silicon adjacencies.

A first aspect of the present disclosure provides an optoelectronic package structure, comprising: a substrate comprising a core layer, an optical interconnect network, and an electrical interconnect network; and a chip array disposed on the first surface of the substrate, including at least one photonic integrated circuit chip and at least one electronic integrated circuit chip; the photonic integrated circuit chip is optically interconnected through the optical interconnection network, and the electronic integrated circuit chip is electrically interconnected through the electrical interconnection network. Some or all of the at least one photonic integrated circuit chip and the at least one electronic integrated circuit chip form an electronic-photonic hybrid chip including the photonic integrated circuit chip and the electronic integrated circuit chip, and the electrical interconnect network includes one or more second conductive vias through the substrate, the second surface of the substrate having solder structures for soldering to a printed circuit board, the solder structures being electrically connected to the electrical interconnect network.

In some embodiments, a photonic integrated circuit chip in the electronic-photonic hybrid chip has one or more first conductive vias extending therethrough, the one or more first conductive vias electrically connected to the electrical interconnection network, the electronic integrated circuit chip in the electronic-photonic hybrid chip disposed on an upper surface of the photonic integrated circuit chip and electrically connected to the one or more first conductive vias.

In some embodiments, a first optical waveguide is disposed in the photonic integrated circuit chip, the optical interconnect network includes a second optical waveguide, and optical coupling is performed between the photonic integrated circuit chip and the optical interconnect network through the first optical waveguide and the second optical waveguide.

In some embodiments, the first optical waveguide and the second optical waveguide are stacked and spaced apart a predetermined distance in a direction perpendicular to the first surface of the substrate such that the first optical waveguide and the second optical waveguide achieve adiabatic coupling of light.

In some embodiments, the optoelectronic package further comprises: an array of beam redirecting elements disposed in the substrate, each beam redirecting element in the array of beam redirecting elements being configured to redirect a beam of light into an optical coupler of the second/first optical waveguide.

In some embodiments, the photonic integrated circuit chip further comprises an edge coupler connected to the first optical waveguide, the edge coupler of the first optical waveguide and the second optical waveguide being optically coupled by photonic wire bonding.

In some embodiments, the second optical waveguide comprises at least one of: a. one or more layers of optical waveguides embedded in a core layer of the substrate; b. one or more optical waveguides formed on a first surface of a core layer of the substrate; and c, forming a three-dimensional waveguide network in the core layer of the substrate.

In some embodiments, where the second optical waveguide comprises the three-dimensional waveguide network, the photonic integrated circuit chip further comprises a grating coupler connected to the first optical waveguide, the first optical waveguide being coupled to the three-dimensional waveguide network through the grating coupler.

In some embodiments, the optoelectronic package structure further comprises: a light source configured to provide light to the photonic integrated circuit chip.

In some embodiments, the light source is disposed on the first surface of the substrate and the light source provides light to the photonic integrated circuit chip by being aligned with an edge coupler of a first optical waveguide in the photonic integrated circuit chip.

In some embodiments, the light source is disposed in a recess in the first surface of the substrate and the light source provides light to the photonic integrated circuit chip by alignment with an edge coupler of a second optical waveguide in the optical interconnect network.

In some embodiments, the light source is disposed on the first surface of the substrate and the light source couples light into an optical coupler of a first optical waveguide in the photonic integrated circuit chip by photonic wire bonding, thereby providing light to the photonic integrated circuit chip.

In some embodiments, the light source is disposed in a recess in the first surface of the substrate and the light source couples light into an optical coupler of a second optical waveguide in the optical interconnection network by photonic wire bonding, thereby providing light to the photonic integrated circuit chip.

In some embodiments, the light source is disposed on the first surface of the substrate, and the optoelectronic package further comprises: a beam shaping element disposed on the first surface of the substrate between the light source and the photonic integrated circuit chip, wherein the light source couples light through the beam shaping element into an optical coupler of a first optical waveguide of the photonic integrated circuit chip, thereby providing light to the photonic integrated circuit chip.

In some embodiments, the light source is disposed in a recess of the first surface of the substrate, and the optoelectronic package further comprises: a beam shaping element disposed in the recess between the light source and a second optical waveguide in the optical interconnection network, wherein the light source couples light into an optical coupler of the second optical waveguide through the beam shaping element, thereby providing light to the photonic integrated circuit chip.

In some embodiments, the light source comprises: a laser configured to emit light; a temperature controller disposed below the laser and configured to control a wavelength of light emitted by the laser by adjusting a temperature of the laser.

In some embodiments, the electrical interconnect network includes one or more electrical wiring layers disposed on the second surface of the core layer of the substrate.

In some embodiments, the electrical interconnect network further includes one or more electrical wiring layers disposed on the first surface of the core layer of the substrate.

In some embodiments, at least some of the chips in the array of chips are disposed over and cover the grooves on the first surface of the substrate, the electrical interconnect network further includes one or more electrical wiring layers disposed in the grooves, and the optical interconnect network is disposed in an area of the first surface of the substrate not occupied by the grooves.

In some embodiments, the chip array includes one or more memory chips.

In some embodiments, the material of the core layer of the substrate is glass, silicon, or ceramic.

A second aspect of the present disclosure provides a photonic computing system comprising an optoelectronic package structure as previously described, the photonic computing system further comprising: a light source configured to provide light to the optoelectronic package structure; and a printed circuit board configured to carry the optoelectronic package structure and electrically connect with the solder structure on the second surface of the substrate.

A third aspect of the present disclosure provides a photonic computing system comprising an optoelectronic package structure as previously described, the photonic computing system further comprising: a printed circuit board configured to carry the optoelectronic package structure and electrically connect with the solder structure on the second surface of the substrate.

The photoelectric packaging structure provided by the disclosure provides power for next-generation high-performance AI calculation tasks by utilizing the speed, power, efficiency and chip array format of light, and provides a platform for a new calculation paradigm. The platform is expandable based on a panel type, and overcomes the limitation of wafer scribing and wafer size. It will bring a major breakthrough in terms of chip bandwidth, being superior to all existing CPU/GPU bandwidths. The panel substrate proposed in the present disclosure is expandable to 310×310mm ² 、510×510mm ² Even larger, in contrast, current chips can only be extended to 100 x 100mm ² The wafer may also be extended to only 12 inches. Through lightThe optoelectronic package structure presented in this disclosure will provide AI computation at ultra-high speed, low latency and low power consumption, with several orders of magnitude improvement over conventional electronic architectures.

Drawings

Fig. 1 shows a schematic diagram of the overall configuration of an optoelectronic package structure of an embodiment of the present disclosure.

Fig. 2 shows a schematic diagram of an optical waveguide in an optical interconnection network in an optoelectronic package structure in accordance with an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of a first optical coupling mode in an optoelectronic package structure according to an embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of a second optical coupling mode in an optoelectronic package structure according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of a third optical coupling mode in an optoelectronic package structure according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a fourth optical coupling mode in an optoelectronic package structure according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a first light source coupling mode in the optoelectronic package structure according to the embodiment of the disclosure.

Fig. 8 is a schematic diagram of a second light source coupling mode in the optoelectronic package structure according to an embodiment of the present disclosure.

Fig. 9 is a schematic diagram of a third light source coupling mode in the optoelectronic package structure according to the embodiment of the present disclosure.

Fig. 10 is a schematic diagram of a fourth light source coupling mode in the optoelectronic package structure according to the embodiment of the present disclosure.

Fig. 11 is a schematic diagram of a fifth light source coupling mode in the optoelectronic package structure according to the embodiment of the disclosure.

Fig. 12 is a schematic diagram of a sixth light source coupling mode in the optoelectronic package structure according to the embodiment of the present disclosure.

Fig. 13 shows a schematic view of the structure of a light source in the optoelectronic package structure of the embodiment of the present disclosure.

Fig. 14 shows a schematic diagram of a photonic computing system of embodiments of the present disclosure.

FIG. 15 shows a schematic diagram of another photonic computing system of embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. While the drawings illustrate some embodiments of the present disclosure, it should be understood, however, that the present disclosure should not be construed as limited to the embodiments set forth herein, but rather, that these embodiments are provided so that this disclosure will be more thorough and complete. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

It should be understood that the various elements, components recited in the embodiments of the present disclosure may be omitted in some cases, and that embodiments of the present disclosure may include other elements, components. Furthermore, it should be understood that the various elements, components, or couplings described in the various embodiments may be combined with each other unless the context clearly indicates otherwise or clearly does not apply.

Embodiments of the present disclosure provide an optoelectronic package structure. Fig. 1 shows a schematic diagram of the overall configuration of an optoelectronic package structure 100 of an embodiment of the present disclosure. For a clearer understanding of the present disclosure, fig. 1 shows a top view of an optoelectronic package structure 100 of an embodiment of the present disclosure in (a), a cross-sectional view of the optoelectronic package structure 100 in a first direction in (b), a cross-sectional view of the optoelectronic package structure 100 in a second direction in (c), and a partial detailed cross-sectional view of the optoelectronic package structure 100 in (d).

As shown in (a) to (c) of fig. 1, the optoelectronic package structure 100 includes a substrate 110 and a chip array 120.

The substrate 110 is a panel that carries and interconnects the chip array 120 and is for mounting onto a Printed Circuit Board (PCB). The substrate 110 may be made larger in size, for example, to 310 x 310mm ² 、510×510mm ² Even larger, thereby overcoming wafer scribe line limitations and wafer size limitations, and providing a larger package area for the packaging of optoelectronic chips. The substrate 110 of the embodiments of the present disclosure may be directlyThe existing glass plate, ceramic plate or silicon substrate is used, so that a large area is achieved and can be directly mounted on the PCB. While the thickness of the substrate thus formed is mainly dependent on the process of preparing the conductive via, the current process of the conductive via may be made 1 μm, and thus it is preferable that such a substrate may be formed to have a large thickness, for example, equal to or greater than 1 μm, in order to achieve sufficient strength. With the maturity of the process technology for preparing the conductive through holes, the thickness of the substrate can be made larger, and the substrate with larger thickness has the advantages of high rigidity, difficult warping and the like.

As shown in (d) of fig. 1, the substrate 110 may structurally include a core layer 111, an optical interconnection network 112, and an electrical interconnection network 113. The material of the core layer 111 may be, for example, glass, silicon, ceramic, or the like. For example, an optical capping layer material may be laid down on core layer 111 followed by a waveguide material to form optical interconnect network 112. For example, at least one electrical wiring layer may also be disposed on the lower surface of the core layer 111, thereby forming the electrical interconnection network 113.

As shown in fig. 1 (a), the chip array 120 in the optoelectronic package structure 100 may include at least one Photonic Integrated Circuit (PIC) chip and at least one Electronic Integrated Circuit (EIC) chip, which are disposed on a first surface (e.g., an upper surface) of the substrate 110, forming a two-dimensional array of chips.

In the case where the chip array 120 includes a plurality of photonic integrated circuit chips, the plurality of photonic integrated circuit chips may be optically interconnected by the optical interconnect network 112 as described above. Further, in the case where the chip array 120 includes a plurality of electronic integrated circuit chips, the plurality of electronic integrated circuit chips may be electrically interconnected through the electrical interconnection network 113 as described above.

In some embodiments, to further compress the package volume, at least one photonic integrated circuit chip and at least one electronic integrated circuit chip in the chip array 120 may form an electronic-photonic hybrid chip including the photonic integrated circuit chip and the electronic integrated circuit chip, e.g., an EPIC as shown in fig. 1, with (d) in fig. 1 showing a partial cross-sectional view of one EPIC and a corresponding substrate portion.

As shown in fig. 1 (d), the photonic integrated circuit chip PIC in the electronic-photonic hybrid chip EPIC has one or more conductive vias TDV extending therethrough, the one or more conductive vias TDV being electrically connected to the electrical interconnect network 113 (e.g., by TGV in the core layer 111). Furthermore, as shown, an electronic integrated circuit chip EIC in the electronic-photonic hybrid chip EPIC is arranged on the upper surface of the photonic integrated circuit chip PIC and is electrically connected with one or more conductive vias TDV.

It should be noted that the term "electronic-photonic hybrid chip" herein does not mean that chips other than the photonic integrated circuit chip and the electronic integrated circuit chip described above are to be employed, but means that the photonic integrated circuit chip PIC and the electronic integrated circuit chip EIC may be stacked and connected to each other to form an integral structure, such as a chip-let, so that the integral structure is disposed on the substrate 110 as part or all of the chips in the chip array 120.

The "electronic-photonic hybrid chip" itself may be formed in a variety of different ways. For example, a plurality of first electrical connectors may be disposed on an upper surface of the PIC chip, and a plurality of second electrical connectors may be disposed correspondingly on a lower surface of the EIC chip, the PIC chip and the EIC chip being directly bonded through the first electrical connectors and the second electrical connectors, thereby forming an overall structure of an "electronic-photonic hybrid chip". Alternatively, the electronic-photonic hybrid chip may be a monolithic structure comprising one PIC chip and a plurality of EIC chips (e.g., a digital electronic integrated circuit chip (D-EIC) and an analog electronic integrated circuit chip (a-EIC)), and the D-EIC chip, the a-EIC chip, and the PIC chip may be directly bonded by the first electrical connector and the second electrical connector as described above. In addition, the EIC chip may be flip-chip mounted onto the PIC chip using flip-chip bonding to form an electronic-photonic hybrid chip as described above. The formation of the "electron-photon hybrid chip" is not limited to the above manner, but the overall structure of the "electron-photon hybrid chip" may be formed in various other manners, which will not be further elaborated.

Further, as shown in fig. 1 (d), the substrate 110 has a soldering structure 114 on the lower surface thereof for soldering to a printed circuit board, and the soldering structure 114 is electrically connected to the electrical interconnection network 113. For example, the solder structure 114 may be a plurality of LGA pads or BGA solder balls.

The chip array in the optoelectronic package 100 shown in fig. 1 may include other types of chips in addition to the EIC chips, PIC chips, or EPIC chips described above. For example, the optoelectronic package 100 may also include one or more memory chips, such as a high bandwidth memory chip HBM chip as shown in fig. 1. It should be understood that the EIC chips, PIC chips, EPIC chips, and HBM chips shown in fig. 1 are just a few examples of the many chips, and that the optoelectronic package structure 100 according to embodiments of the present disclosure may also include other various types of chips, including but not limited to temperature control chips, power control chips, light source chips, and the like, as desired.

The individual chips of the chip array 120 are electrically interconnected by an electrical interconnection network 113 and optically interconnected by an optical interconnection network 112. In some embodiments, the electrical interconnect network 113 further includes one or more conductive vias through the core layer 111 of the substrate.

For example, as shown in fig. 1 (d), where the core layer material is glass, the one or more conductive vias are Through Glass Vias (TGV) as shown. Alternatively, where the core layer material is ceramic, the one or more conductive vias may be Through Ceramic Vias (TCVs). Alternatively, where the core layer material is silicon, the one or more conductive vias may be Through Silicon Vias (TSVs).

As described above, optical interconnection may be made between the plurality of photonic integrated circuit chips PIC arranged on the substrate 110 through the optical interconnection network 112. Specific implementations of optical interconnection between the plurality of PIC chips via an optical interconnection network will be described in detail below in conjunction with fig. 2-6.

Typically, a first optical waveguide for optical transmission is arranged in the photonic integrated circuit chip PIC, and the optical interconnection network on the substrate typically comprises a second optical waveguide. The photonic integrated circuit chip PIC and the optical interconnection network can be optically coupled through the first optical waveguide and the second optical waveguide, and then the plurality of photonic integrated circuit chips PIC are interconnected together through the optical interconnection network.

It should be noted that the term "second optical waveguide" referred to hereinafter may denote a part or all of the optical interconnection network.

In some embodiments, the second optical waveguide in the optical interconnection network on the substrate may comprise various types of optical waveguides. Fig. 2 shows a schematic diagram of an optical waveguide in an optical interconnection network in an optoelectronic package structure in accordance with an embodiment of the present disclosure.

Fig. 2 (a) shows an embedded optical waveguide embedded in a core layer of a substrate, fig. 2 (b) shows a combined optical waveguide formed on a first surface of the core layer of the substrate, and fig. 2 (c) shows a three-dimensional (3D) inscribed waveguide formed in the core layer of the substrate.

In some embodiments, the second optical waveguide in the optical interconnection network on the substrate may be a single-layer waveguide as shown in (a) - (c) in fig. 2, a multi-layer waveguide as shown in (d) in fig. 2, or a combination of the above types of optical waveguides.

Depending on the different optical waveguide types and the different design requirements, the photonic integrated circuit chip PIC and the optical interconnect network arranged on the substrate may be optically coupled in various ways. There are also a number of ways to arrange or arrange the electrical and optical interconnection networks in the optoelectronic package structure, depending on the different modes of optical coupling.

Fig. 3 shows a schematic diagram of a first optical coupling mode in an optoelectronic package structure 300 in accordance with an embodiment of the present disclosure. For simplicity, fig. 3 shows only a schematic diagram of the coupling between an EPIC chip comprising an EIC chip and a PIC chip and an optical interconnect network on a substrate.

As shown in fig. 3, the photonic integrated circuit chip PIC in the EPIC chip includes a plurality of first optical waveguides WG-1 embedded therein. The optical interconnection network on the substrate comprises a second optical waveguide WG-2 arranged on a core layer of the substrate as shown in fig. 3. In some examples, the material of optical waveguides WG-1 and WG-2 may be silicon or silicon nitride.

Specifically, the first optical waveguide WG-1 may include a first optical coupling portion, and the second optical waveguide may include a second optical coupling portion (not shown in the figure), and for simplicity, for example, the ends of the first optical waveguide WG-1 and the second optical waveguide WG-2 may be regarded as respective optical coupling portions. The photonic integrated circuit chip PIC is attached to the upper surface of the substrate such that the first optical waveguide WG-1 in the PIC chip and the second optical waveguide WG-2 on the core layer of the substrate are close to each other, for example, the optical coupling portions of the first optical waveguide WG-1 and the second optical waveguide WG-2 are stacked in a direction perpendicular to the upper surface of the substrate and spaced apart by a predetermined distance H (for example, less than 600 nm) such that adiabatic coupling of light is enabled between the optical coupling portions of the first optical waveguide WG-1 and the second optical waveguide WG-2.

For example, light from the left second optical waveguide WG-2 may be coupled into the first optical waveguide WG-1 in the PIC chip through the WG-2, and then, after transmission and processing in the PIC chip, again coupled into the second optical waveguide WG-2 on the core layer of the substrate by the right first optical waveguide WG-1, and further, re-coupled into other PIC chips in a similar manner, thereby enabling optical interconnections between the different PIC chips.

The adiabatic coupling between the PIC chip and the optical interconnect network may be applicable to the embedded waveguide and combined waveguide types described above with respect to fig. 2.

Further, it should be noted that, in the case of performing optical coupling between the photonic integrated circuit chip PIC and the optical interconnection network by adiabatic coupling as shown in fig. 3, since adiabatic coupling requires close adhesion between the photonic integrated circuit chip and the optical interconnection network, the electrical interconnection network is not generally disposed on the upper surface of the substrate, but only disposed on the lower surface of the substrate, for example, the electrical interconnection network includes one or more electrical wiring layers 113-1 as shown in fig. 3.

Various configurations of adiabatic coupling between a PIC chip and an optical interconnect network by which optical interconnects between multiple photonic integrated circuit chips may be implemented are described above in connection with fig. 3. Such a package structure that uses adiabatic coupling to optically interconnect multiple photonic integrated circuit chips is beneficial for compressing the overall volume of the package structure due to the close fit between the photonic integrated circuit chips and the substrate.

In addition to adiabatic coupling as described above, a beam-redirecting element may also be used to effect optical coupling between the PIC chip and the optical interconnection network. Fig. 4 shows a schematic diagram of a second optical coupling mode in an optoelectronic package structure 400 in accordance with an embodiment of the present disclosure.

In contrast to the optoelectronic package structure 300 of fig. 3, the optoelectronic package structure 400 as shown in fig. 4 may further include an array of beam redirecting elements 130 (e.g., two beam redirecting elements 130 shown in fig. 4) disposed in the substrate, and the height of the beam redirecting elements 130 is appropriately adjusted (e.g., by grooving the upper surface of the substrate) to align with the second optical waveguides WG-2 in the optical interconnect network, such that each beam redirecting element in the array of beam redirecting elements 130 is configured to redirect a beam of light into an optical coupler of the second/first optical waveguides.

In some embodiments, the light beam redirecting element 130 may be a prism as shown. The prism is arranged in a recess in the upper surface of the core layer of the substrate and its position and height are adjusted such that light from the first optical waveguide WG-1 may enter the second optical waveguide WG-2 by refraction or reflection, or light from the second optical waveguide WG-2 may enter the first optical waveguide WG-1 by refraction or reflection, thereby achieving optical coupling between the PIC chip and the optical interconnection network.

In the case of optical coupling using the light beam redirecting element 130, the optical coupling portion of the first optical waveguide WG-1 and/or the second optical waveguide WG-2 may be configured with a grating coupler GC, so that optical coupling is performed by using the diffraction effect of the grating, and thus the direction of light is changed, and vertical coupling of light is achieved. Fig. 4 shows an example in which an end portion of the first optical waveguide WG-1 is provided with a grating coupler GC.

Fig. 4 shows another different arrangement of optical and electrical interconnection networks, as opposed to the arrangement of the optical interconnection network (e.g., including the second optical waveguide WG-2 of fig. 3) on the upper surface of the substrate and the arrangement of the electrical interconnection network (e.g., including the one or more electrical wiring layers 113-1 of fig. 3) on the lower surface of the substrate opposite the upper surface, as in fig. 3.

For example, as shown in fig. 4, since the optical coupling is not performed by the adiabatic coupling between the photonic integrated circuit chip PIC and the optical interconnection network, in this case, there is no need to control so that the first optical waveguide and the optical interconnection network in the photonic integrated circuit chip PIC are closely spaced, one or more electrical wiring layers 113-2 may be disposed on the upper surface of the substrate as a part of the electrical interconnection network. For example, as shown, the electrical interconnect network may include both one or more electrical wiring layers 113-1 on the lower surface of the core layer of the substrate and one or more electrical wiring layers 113-2 on the upper surface of the core layer of the substrate.

In this case, an optical interconnection network (e.g., including the second optical waveguide WG-2 in fig. 4) may be disposed on the upper surface of the substrate, and the second optical waveguide WG-2 is covered by one or more electrical wiring layers 113-2 in the electrical interconnection network.

In addition to adiabatic coupling and vertical coupling using beam-redirecting elements as described above, optical coupling between the PIC and the optical interconnection network may also be accomplished using photonic wire bonding (also known as PWB). Fig. 5 illustrates a schematic diagram of an optical coupling scheme employing photonic wire bonding in an optoelectronic package structure 500 in accordance with an embodiment of the present disclosure.

As shown in fig. 5, an end portion of a first optical waveguide WG-1 of the photonic integrated circuit chip PIC is provided with an edge coupler EC, and optical coupling is performed between the edge coupler EC of the first optical waveguide WG-1 and a second optical waveguide WG-2 by means of Photonic Wire Bonding (PWB).

In integrated circuits, interconnections between electronic integrated circuit chips are typically made using metal routing methods. By taking the thought of metal routing as a reference, optical wire bonding can be used for realizing interconnection among different photonic integrated circuit chips, the photonic integrated circuit chips and an optical network. In contrast to metal routing, the "wire" that serves as a connection is no longer metal, but rather an optical waveguide. For example, as shown in FIG. 5, the optical outlet in the EC of the first optical waveguide WG-1 of the PIC chip may be optically connected to the inlet of the second optical waveguide WG-2 in the optical interconnection network via the PWB. According to the scheme, the time-consuming alignment adjustment in the traditional scheme is avoided, lenses and the like required by beam shaping are saved, the preparation is simple and quick, and the large-scale production is facilitated.

The vertical coupling and photonic wire bonding approaches described above are also applicable to the embedded waveguide and combined waveguide types described above with respect to fig. 2.

Further, as shown in fig. 5, in the case where optical coupling (to be described later in detail) between the photonic integrated circuit chip PIC and the optical interconnection network is performed using photonic wire bonding, the electrical interconnection network may also be arranged on both upper and lower surfaces of the substrate at the same time. In the case where one or more electrical wiring layers 113-2 of the electrical interconnection network are disposed on the upper surface, in order to facilitate handling of the photonic wire bond, the optical interconnection network (e.g., including the second optical waveguide WG-2 in fig. 5) and the one or more electrical wiring layers 113-2 on the upper surface of the substrate may be disposed at different positions on the upper surface of the substrate, instead of overlaying the electrical wiring layers over the second optical waveguide as shown in fig. 4. For example, one or more electrical wiring layers 113-2 on the upper surface of the substrate may be disposed below and covered by the PIC chip, while the optical interconnect network is disposed in the remaining area of the upper surface of the substrate where no electrical wiring layers are disposed. In this case, the optical interconnect network is also covered by the electrical interconnect network as in fig. 4, both of which are juxtaposed on the upper surface of the substrate.

In some embodiments, the second optical waveguide in the optical interconnection network on the substrate may further comprise a 3D inscribed waveguide as described above with respect to fig. 2, for example as a three-dimensional waveguide network formed in a glass layer, in which case the optical coupling of the photonic integrated circuit chip and the optical interconnection network may also be achieved directly using a grating coupler.

Fig. 6 shows a schematic diagram of a fourth optical coupling mode in an optoelectronic package structure 600 in accordance with an embodiment of the present disclosure.

As shown in fig. 6, the second optical waveguide WG-2 in the optical interconnection network on the substrate is a three-dimensional waveguide network, which is a network structure configured by, for example, inducing a partial glass inside the glass to raise the refractive index of the partial glass. For example, an ultrafast (e.g., femtosecond) laser inscription process can be used to create an embedded three-dimensional waveguide network inside the glass. The photonic integrated circuit chip PIC further comprises a grating coupler GC connected to a first optical waveguide, which is coupled to the three-dimensional waveguide network by the grating coupler GC.

The three-dimensional waveguide network shown in fig. 6 is formed in a glass layer attached to a core layer of a substrate, which is merely illustrative. In some examples, the femtosecond laser may be directly used to irradiate a preset position in the core layer of the substrate, so as to increase the refractive index of the preset position, thereby forming the three-dimensional waveguide network in the core layer.

The three-dimensional waveguide network is beneficial to forming a richer and more efficient three-dimensional optical waveguide path, so that the volume of the photoelectric packaging structure can be further compressed.

Further, as shown in fig. 6, in the case of optical coupling between the photonic integrated circuit chip PIC and the optical interconnect network using a grating coupler in combination with a three-dimensional waveguide network, the optical interconnect network (including, for example, the three-dimensional waveguide WG-2 in fig. 6) and one or more electrical wiring layers 113-2 in the electrical interconnect network may be arranged at different positions on the upper surface of the substrate. In this case, the optical interconnect network and the electrical interconnect network are also juxtaposed at different locations on the upper surface of the substrate.

Various ways of optically coupling between the photonic integrated circuit chip and the optical interconnect network in the optoelectronic package structure, as well as various arrangements of the optical interconnect network and the electrical interconnect network, are described above. The various coupling modes have respective obvious advantages, and different coupling modes can be adopted at different positions of the same package or in different packages according to requirements. For example, adiabatic coupling has a volume that utilizes compression packaging due to the close fit between the photonic integrated circuit chip and the substrate. The vertical coupling mode of the beam redirecting element is adopted to change the propagation direction of light, and the arrangement mode of the chip can be more flexible. The photon lead bonding mode has small insertion loss, has relatively low requirement on device alignment, saves lenses and the like required by beam shaping, is simple and quick to prepare, and is beneficial to large-scale production. The grating coupling of the three-dimensional waveguide network is beneficial to forming a richer and more efficient three-dimensional optical waveguide path, so that the volume of the photoelectric packaging structure can be further compressed. Those skilled in the art can select an appropriate optical coupling means or a combination thereof as desired, and various combinations are likewise within the scope of the present disclosure.

Furthermore, it should be noted that while various arrangements of electrical and optical interconnect networks have been described above in connection with various optical coupling arrangements between photonic integrated circuit chips and optical interconnect networks, this is merely exemplary. In practice, the electrical and optical interconnection networks may be rationally arranged in combination with other factors, thereby further compressing the volume of the optoelectronic package and improving the efficiency of the process while achieving optical and electrical interconnection.

Meanwhile, the specific structure of the electrical interconnection network may also be rationally designed in connection with specific applications, for example, whether one or more electrical wiring layers need to be arranged, whether on one or both side surfaces of the substrate, whether an interconnection structure is required between the multiple wiring layers, and so forth.

For example, where the electrical interconnect network includes multiple electrical wiring layers on one side surface (e.g., upper or lower surface) of the substrate core layer, the electrical interconnect network may also include one or more blind vias that simultaneously connect the multiple electrical wiring layers for electrically interconnecting the multiple electrical wiring layers on one side surface.

Further, in some embodiments, one or more grooves may be provided on the upper surface of the core layer of the substrate for disposing some of the chips in the array of chips therein or thereon. For example, the light source LS as described in fig. 10 may be disposed in a recess of the upper surface of the core layer of the substrate, which will be described in detail later. In addition, one or more electrical wiring layers may be disposed in some of the recesses as part or all of the electrical interconnection network. For example, the electrical interconnect network may also include one or more electrical wiring layers 113-3 disposed in the grooves of the core layer of the substrate as shown in FIG. 10.

In case a recess is arranged on the core layer, at least some of the chips in the array of chips may be arranged above and covering the recess. It is noted that in case of providing grooves on the core layer of the substrate, the optical interconnect network may be arranged, for example, in an area on the first surface (upper surface) of the substrate not occupied by grooves.

For example, as shown in fig. 10, the photonic integrated circuit chip PIC may be disposed over and covering the recess with one or more electrical wiring layers 113-3 disposed therein. The effect of such grooves is that, because the first optical waveguide WG-1 in the PIC and the second optical waveguide WG-2 on the core layer need to be closely attached to achieve adiabatic coupling of light, while the conductive path of the EIC above the PIC is typically located on the lower surface of the PIC, and the upper surface of the substrate needs to form an electrical connection structure such as a conductive bump, the conductive bump after bonding is typically thick, which affects the distance between the first optical waveguide WG-1 and the second optical waveguide WG-2, the formation of the groove below the PIC can accommodate the conductive bump in the groove, thereby solving the problem of excessive distance between the first waveguide WG-1 and the second waveguide WG-2, and electrical wiring can be performed in the groove, thereby increasing the electrical wiring density.

It should be understood that while the electrical interconnect network may include one or more electrical wiring layers in the upper, lower, and upper surface recesses of the core layer of the substrate, the arrangement of the electrical interconnect network is not necessarily an alternative thereto, and may include various arrangements and combinations thereof.

For example, the electrical interconnect network may include only one or more electrical wiring layers on the lower surface of the core layer of the substrate, as shown in fig. 2. Alternatively, the electrical interconnect network may include one or more electrical wiring layers on the lower surface of the core layer of the substrate and one or more electrical wiring layers on the upper surface of the core layer of the substrate, as shown in fig. 4. Alternatively, the electrical interconnect network may include one or more electrical wiring layers on the lower surface of the core layer of the substrate and one or more electrical wiring layers in grooves in the upper surface of the core layer of the substrate, as shown in fig. 10. It is obvious that the electrical interconnection network may also comprise only one or more electrical wiring layers on the upper surface of the core layer of the substrate, may comprise only one or more electrical wiring layers in the grooves of the upper surface of the core layer of the substrate, or may comprise a combination of the above three electrical wiring layers at the same time.

As previously described, the optoelectronic package structure according to embodiments of the present disclosure may also contain other various types of chips as specifically desired, including but not limited to temperature control chips, power control chips, light source chips, and the like. The manner of optical coupling between the light source and the photonic integrated circuit chip in the case of including the light source chip (hereinafter referred to as "light source") will be described below with reference to the accompanying drawings.

Where the optoelectronic package structure of embodiments of the present disclosure includes a light source, the light source is configured to provide light to the photonic integrated circuit chip in the optoelectronic package structure. Fig. 7 to 12 are schematic diagrams showing various light source coupling manners in the photoelectric package structure according to the embodiment of the present disclosure.

The coupling modes of the light sources in the present disclosure can be roughly classified into three types, namely, a self-aligned coupling mode, a photonic wire bonding mode, and a free-space optical coupling mode. The manner of coupling of the light sources of the present disclosure can be further divided into six specific ways as shown in fig. 7-12, depending on whether the light from the light source is directly coupled to the photonic integrated circuit chip or directly coupled into the optical interconnect network.

Fig. 7 shows a schematic diagram of a first light source coupling mode in an optoelectronic package structure 700 of an embodiment of the present disclosure, i.e., coupling a light source into a photonic integrated circuit chip in a self-aligned manner.

As shown in fig. 7, the light source LS is arranged on the upper surface of the substrate and is located near the photonic integrated circuit chip PIC. The light source LS is made to supply light to the photonic integrated circuit chip PIC by adjusting the mounting heights of the light source LS and the photonic integrated circuit chip PIC and the relative positions thereof on the upper surface of the substrate so that the light emitted from the light source LS is self-aligned into the edge coupler EC of the photonic integrated circuit chip PIC.

Similarly, fig. 8 shows a schematic diagram of a second way of coupling a light source in an optoelectronic package structure 800 according to an embodiment of the present disclosure, i.e., coupling the light of the light source into an optical interconnect network in a self-aligned manner, and then coupling the light into a photonic integrated circuit chip again by adiabatic coupling, thereby providing the photonic integrated circuit chip with light.

As shown in fig. 8, the light source LS is also arranged on the upper surface of the substrate, but there is also a second optical waveguide WG-2 in the optical interconnection network between the light source LS and the photonic integrated circuit chip PIC. By adjusting the height of the light source LS and the relative position of the light source LS and the second light guide WG-2 on the upper surface of the substrate, the light emitted by the light source LS is self-aligned into the second light guide WG-2. The second optical waveguide WG-2 is then optically coupled to the first optical waveguide WG-1 in the photonic integrated circuit chip by adiabatic coupling, such that the light source LS provides light to the photonic integrated circuit chip PIC.

It should be understood that the adiabatic coupling of the second optical waveguide WG-2 with the first optical waveguide WG-1 in the photonic integrated circuit chip shown in FIG. 8 is merely exemplary, and that other means of achieving optical coupling between the optical interconnection network and the photonic integrated circuit chip, such as vertical coupling, photonic wire bonding, etc., as described above, may be employed.

The light source self-aligned coupling described in fig. 7-8 requires high device alignment requirements, and requires precise design and layout of the height of each chip, the height of the optical interconnection network, and the layout of the plane. The photoelectric packaging structure has the advantages that lenses and the like required by beam shaping are saved, the structure is compact, and the further compression of the volume of the photoelectric packaging structure is facilitated.

For the occasion of lower alignment precision of the device, the light source coupling can be performed by adopting a photon lead bonding mode. Fig. 9 shows a schematic diagram of a third light source coupling mode in an optoelectronic package 900 according to an embodiment of the present disclosure, that is, coupling light of a light source into a photonic integrated circuit chip in a photonic wire bonding mode.

As shown in fig. 9, the light source LS is also arranged on the upper surface of the substrate, and is located in the vicinity of the photonic integrated circuit chip. The light source LS is caused to provide light to the photonic integrated circuit chip PIC by using the PWB to couple the light emitted by the light source LS directly into the edge coupler EC of the photonic integrated circuit chip PIC.

Similarly, fig. 10 shows a schematic diagram of a fourth light source coupling manner in an optoelectronic package structure 1000 according to an embodiment of the present disclosure, that is, coupling light of a light source into an optical interconnection network in a photonic wire bonding manner, and then coupling the light into a photonic integrated circuit chip again through adiabatic coupling, so as to provide light for the photonic integrated circuit chip.

As shown in fig. 10, in order to maintain the light source LS at approximately the same height as the second optical waveguide WG-2 in the optical interconnection network, the light source may be disposed in a groove on the upper surface of the substrate, the light emitted from the light source LS is directly coupled into the second optical waveguide WG-2 in the optical interconnection network by using the PWB, and then the second optical waveguide WG-2 is optically coupled with the first optical waveguide WG-1 in the photonic integrated circuit chip in an adiabatic coupling manner, so that the light source LS supplies light to the photonic integrated circuit chip PIC.

It should be understood that the adiabatic coupling of the second optical waveguide WG-2 shown in FIG. 10 with the first optical waveguide WG-1 in the photonic integrated circuit chip is merely exemplary, and that other means of achieving optical coupling between the optical interconnection network and the photonic integrated circuit chip, such as vertical coupling, photonic wire bonding, etc., as described above, may be employed.

In addition, the light source can be optically coupled by free space optical coupling. Fig. 11 shows a schematic diagram of a fifth light source coupling mode in an optoelectronic package 1100 according to an embodiment of the present disclosure, that is, coupling light of a light source into a photonic integrated circuit chip using a beam shaping element.

As shown in fig. 11, the light source LS is also arranged on the upper surface of the substrate, and is located in the vicinity of the photonic integrated circuit chip. The beam shaping element 140 is arranged between the light source LS and the photonic integrated circuit chip. The light source LS is made to supply light to the photonic integrated circuit chip PIC by adjusting the mounting heights of the light source LS, the beam shaping element 140 and the photonic integrated circuit chip PIC and the relative positions thereof on the upper surface of the substrate such that the light emitted from the light source LS is aligned into the edge coupler of the photonic integrated circuit chip PIC through the beam shaping element 140.

Similarly, fig. 12 shows a schematic diagram of a sixth light source coupling manner in an optoelectronic package structure 1200 according to an embodiment of the disclosure, in which light from a light source is coupled into an optical interconnection network by a beam shaping element, and then coupled into a photonic integrated circuit chip again by adiabatic coupling, so as to provide light for the photonic integrated circuit chip.

As shown in fig. 12, in order to maintain the light source LS, the beam shaping element 140 and the second optical waveguide WG-2 in the optical interconnection network at substantially the same height, the light source LS and the beam shaping element 140 may be disposed in a recess on the upper surface of the substrate, and the light emitted by the light source LS is aligned into the second optical waveguide WG-2 in the optical interconnection network by using the beam shaping element 140, and then the second optical waveguide WG-2 is optically coupled with the first optical waveguide WG-1 in the photonic integrated circuit chip in an adiabatic coupling manner, so that the light source LS provides light to the photonic integrated circuit chip PIC.

It should be understood that the adiabatic coupling of the second optical waveguide WG-2 shown in FIG. 12 with the first optical waveguide WG-1 in the photonic integrated circuit chip is merely exemplary, and that other means of achieving optical coupling between the optical interconnection network and the photonic integrated circuit chip, such as vertical coupling, photonic wire bonding, etc., as described above, may be employed.

The manner in which the light sources are coupled using free-space optical coupling as shown in fig. 11-12, while also requiring alignment in height and horizontal position of the individual devices, requires less precision in alignment than the self-alignment manner described above with respect to fig. 7-8 due to the use of beam shaping elements (e.g., lenses), and the optical coupling efficiency is greatly improved due to the use of beam shaping elements.

In the embodiment of the light source coupling manner described above with respect to fig. 7 to 12, the light source LS therein may be a light source with a temperature control function as shown in fig. 13. For example, the light source LS may comprise a laser LS-1 configured to emit light; a light source substrate LS-2 for arranging or carrying the laser LS-1; and a temperature controller TEC disposed below the laser LS-1 and the light source substrate LS-2 and configured to control a wavelength of light emitted from the laser LS-1 by adjusting a temperature of the laser LS-1.

It should be understood that the light source with temperature control as described above is merely exemplary and not limiting. The optoelectronic package structure in embodiments of the present disclosure may also include other various types of light sources.

By employing various optoelectronic package structures as described above, various photonic computing systems, for example, for implementing AI computation, can be implemented. Fig. 14 shows a schematic diagram of a photonic computing system 1400 of embodiments of the present disclosure. Fig. 15 shows a schematic diagram of another photonic computing system 1500 of embodiments of the present disclosure.

As shown in fig. 14, when photonic computing system 1400 employs an optoelectronic package structure that does not include an internal light source chip as previously described (e.g., the optoelectronic package structure shown in fig. 1-4), an external light source LS as shown in fig. 14 may be employed to provide light to optoelectronic package structure 1410.

In the photonic computing system 1400 shown in fig. 14, a printed circuit board PCB is configured to carry the optoelectronic package 1410 and other components. As shown, the printed circuit board PCB is electrically connected with the solder structures on the lower surface of the substrate of the optoelectronic package structure 1410.

In addition, the light source LS and other components are also arranged on the printed circuit board PCB. For example, an external light source LS is disposed near the optoelectronic package structure 1410 for providing light to the optoelectronic package structure 1410. Optionally, the external light source LS and the optoelectronic package 1410 may further be provided with similar beam shaping elements 140, so as to collimate the light emitted by the external light source LS, so that it is coupled into the optoelectronic package 1410 with a higher coupling efficiency.

It should be noted that the manner in which the light from the external light source LS is coupled into the PIC in the optoelectronic package 1410 using the beam shaping element shown in fig. 14 is merely exemplary. In the case of the external light source LS, the light source may be coupled to the optoelectronic package 1410 in a similar manner as any of the manners shown in fig. 7 to 12, which will not be described herein.

The photonic computing system 1400 may include other optical or electronic components in addition to the optoelectronic package 1410, external light source LS, beam shaping element 140, and printed circuit board PCB as described above. For example, the photonic computing system 1400 may also include a power controller PC as shown in fig. 14 to control the power consumption of the entire photonic computing system 1400.

In contrast to the photonic computing system 1400 shown in fig. 14, the photonic computing system 1500 shown in fig. 15 may employ an optoelectronic package structure including a built-in light source chip (e.g., the optoelectronic package structure shown in fig. 7-13).

In the photonic computing system 1500 shown in fig. 15, a printed circuit board PCB is configured to carry the optoelectronic package 1510 and other components. As shown, the printed circuit board PCB is electrically connected to the solder structures on the lower surface of the substrate of the optoelectronic package 1510.

In addition, since the optoelectronic package 1510 itself includes an internal light source, no additional external light source may be required to provide light thereto. In addition, other components may also be arranged on the printed circuit board PCB. For example, photonic computing system 1500 may also include a power controller PC as shown in fig. 15 to control the power consumption of the entire photonic computing system 1500.

In the foregoing description, embodiments of the present disclosure have been described with reference to the accompanying drawings. It is to be understood that the above-described embodiments are merely illustrative, and those skilled in the art will understand that constituent elements of the present embodiments may be modified or combined in various ways, and that such modification and combination also fall within the scope of the present disclosure.

Claims

1. An optoelectronic package structure, comprising:

a substrate comprising a core layer, an optical interconnect network, and an electrical interconnect network; and

a chip array disposed on the first surface of the substrate, comprising at least one photonic integrated circuit chip optically interconnected by the optical interconnection network and at least one electronic integrated circuit chip electrically interconnected by the electrical interconnection network, wherein,

some or all of the at least one photonic integrated circuit chip and at least one electronic integrated circuit chip form an electronic-photonic hybrid chip including the photonic integrated circuit chip and the electronic integrated circuit chip, and

the electrical interconnect network includes one or more second conductive vias through the substrate, the second surface of the substrate having solder structures for soldering to a printed circuit board, the solder structures being electrically connected to the electrical interconnect network.

2. The optoelectronic package of claim 1, wherein,

a photonic integrated circuit chip in the electronic-photonic hybrid chip has one or more first conductive vias extending therethrough, the one or more first conductive vias electrically connected to the electrical interconnection network, the electronic integrated circuit chip in the electronic-photonic hybrid chip disposed on an upper surface of the photonic integrated circuit chip and electrically connected to the one or more first conductive vias.

3. The optoelectronic package of claim 1, wherein,

a first optical waveguide is disposed in the photonic integrated circuit chip,

the optical interconnection network includes a second optical waveguide, and

the photonic integrated circuit chip and the optical interconnection network are optically coupled through the first optical waveguide and the second optical waveguide.

4. The optoelectronic package assembly as claimed in claim 3 wherein the first and second optical waveguides are stacked and spaced apart a predetermined distance in a direction perpendicular to the first surface of the substrate such that the first and second optical waveguides achieve adiabatic coupling of light.

5. The optoelectronic package structure of claim 3, further comprising:

an array of beam redirecting elements disposed in the substrate, each beam redirecting element in the array of beam redirecting elements being configured to redirect a beam of light into an optical coupler of the second/first optical waveguide.

6. The optoelectronic package assembly as set forth in claim 3 wherein the photonic integrated circuit chip further includes an edge coupler connected to the first optical waveguide, the edge coupler of the first optical waveguide and the second optical waveguide being optically coupled by photonic wire bonding.

7. The optoelectronic package assembly as set forth in claim 3, wherein the second optical waveguide comprises at least one of:

a. one or more layers of optical waveguides embedded in a core layer of the substrate;

b. one or more optical waveguides formed on a first surface of a core layer of the substrate; and

c. a three-dimensional waveguide network formed within the core layer of the substrate.

8. The optoelectronic package assembly as set forth in claim 7 wherein, in the case where the second optical waveguide includes the three-dimensional waveguide network, the photonic integrated circuit chip further includes a grating coupler connected to the first optical waveguide, the first optical waveguide being coupled to the three-dimensional waveguide network through the grating coupler.

9. The optoelectronic package structure of claim 3, further comprising:

a light source configured to provide light to the photonic integrated circuit chip.

10. The optoelectronic package of claim 9, wherein,

the light source is arranged on the first surface of the substrate, and

the light source provides light to the photonic integrated circuit chip by alignment with an edge coupler of a first optical waveguide in the photonic integrated circuit chip.

11. The optoelectronic package of claim 9, wherein,

the light source is arranged in a groove of the first surface of the substrate, and

the light source provides light to the photonic integrated circuit chip by alignment with an edge coupler of a second optical waveguide in the optical interconnection network.

12. The optoelectronic package of claim 9, wherein,

the light source is arranged on the first surface of the substrate, and

the light source couples light into an optical coupler of a first optical waveguide in the photonic integrated circuit chip by means of photonic wire bonding, thereby providing light to the photonic integrated circuit chip.

13. The optoelectronic package of claim 9, wherein,

the light source couples light into an optical coupler of a second optical waveguide in the optical interconnection network by means of photonic wire bonding, thereby providing light to the photonic integrated circuit chip.

14. The optoelectronic package of claim 9, wherein,

the light source is arranged on the first surface of the substrate, and

the optoelectronic package structure further includes:

A beam shaping element disposed on the first surface of the substrate between the light source and the photonic integrated circuit chip,

wherein the light source couples light into an optical coupler of a first optical waveguide of the photonic integrated circuit chip through the beam shaping element, thereby providing light to the photonic integrated circuit chip.

15. The optoelectronic package of claim 9, wherein,

the optoelectronic package structure further includes:

a beam shaping element arranged in said recess, between said light source and a second optical waveguide in said optical interconnection network,

wherein the light source couples light into the optical coupler of the second optical waveguide through the beam shaping element, thereby providing light to the photonic integrated circuit chip.

16. The optoelectronic package of any one of claims 9-15, wherein the light source includes:

a laser configured to emit light;

a temperature controller disposed below the laser and configured to control a wavelength of light emitted by the laser by adjusting a temperature of the laser.

17. The optoelectronic package of claim 1, wherein the electrical interconnect network comprises one or more electrical wiring layers disposed on the second surface of the core layer of the substrate.

18. The optoelectronic package assembly as set forth in claim 17 wherein the electrical interconnect network further includes one or more electrical wiring layers disposed on the first surface of the core layer of the substrate.

19. The optoelectronic package of claim 1 or 17, wherein,

at least some of the chips in the array of chips are disposed over and cover the grooves on the first surface of the substrate,

the electrical interconnect network further includes one or more electrical wiring layers disposed in the recess, and

the optical interconnect network is disposed on the first surface of the substrate in an area not occupied by the recess.

20. The optoelectronic package assembly as set forth in claim 1, wherein the array of chips includes one or more memory chips.

21. The optoelectronic package assembly as set forth in claim 1, wherein the material of the core layer of the substrate is glass, silicon or ceramic.

22. A photonic computing system comprising the optoelectronic package structure of any one of claims 1 to 8 or 17 to 21, the photonic computing system further comprising:

A light source configured to provide light to the optoelectronic package structure;

a printed circuit board configured to carry the optoelectronic package structure and electrically connect with the solder structure on the second surface of the substrate.

23. A photonic computing system comprising the optoelectronic package structure of any one of claims 9 to 16, the photonic computing system further comprising: