CN117406847A - Chip, power supply circuit thereof and electronic equipment - Google Patents

Chip, power supply circuit thereof and electronic equipment Download PDF

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Publication number
CN117406847A
CN117406847A CN202311717155.2A CN202311717155A CN117406847A CN 117406847 A CN117406847 A CN 117406847A CN 202311717155 A CN202311717155 A CN 202311717155A CN 117406847 A CN117406847 A CN 117406847A
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China
Prior art keywords
power supply
mos tube
module
mos
node
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CN202311717155.2A
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Chinese (zh)
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CN117406847B (en
Inventor
杨志斌
尹欣
王晨皓
虞少平
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Zhejiang Geoforcechip Technology Co Ltd
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Zhejiang Geoforcechip Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The application provides a chip and power supply circuit and electronic equipment thereof, relates to electronic circuit technical field, and power supply circuit includes: the power supply system comprises a power supply source, a first power supply establishing module, a second power supply establishing module and a power supply comparing module; the first power supply building module is used for building a first power supply, and the first power supply is used for driving the chip to work; the second power supply establishing module is used for establishing a second power supply, and the second power supply is used for providing working voltage for the protocol interaction of the chip; the power supply comparison module is used for comparing the voltage of the second node with the voltage of the first power supply and the voltage of the second power supply respectively to obtain a comparison result, and controlling the second power supply establishment module to establish the second power supply according to the comparison result. The power supply device can simultaneously meet the normal work power supply of the chip and the power supply during protocol interaction, and can avoid the phenomenon that the chip is powered down during protocol interaction.

Description

Chip, power supply circuit thereof and electronic equipment
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to a chip, a power supply circuit thereof, and an electronic device.
Background
In the single-wire protocol interaction chip, the power supply pins of the chip are required to supply power for the normal operation of the chip, and the protocol is required to be run when the protocols are interacted, however, the power failure problem easily occurs when the single-wire protocol interaction chip is in the protocol interaction state, so that a new chip power supply circuit is required to be designed.
Disclosure of Invention
In view of this, the purpose of this application is to propose a chip and power supply circuit and electronic equipment thereof, and this application can be targeted solves the problem that current chip loses the power in the interactive in-process of agreement.
In view of the above object, the present application proposes, in a first aspect, a power supply circuit comprising: the power supply system comprises a power supply source, a first power supply establishing module, a second power supply establishing module and a power supply comparing module; the power supply is connected with the first power supply building module through a first node, the power supply is connected with the power supply comparison module through a second node, the power supply is connected with the second power supply building module through a third node, and the power supply comparison module is respectively connected with the first power supply building module and the second power supply building module through different connection ports; the first power supply establishment module is used for establishing a first power supply, and the first power supply is used for driving the chip to work; the second power supply establishing module is used for establishing a second power supply, and the second power supply is used for providing working voltage for the protocol interaction of the chip; the power supply comparison module is used for comparing the voltage of the second node with the voltage of the first power supply and the voltage of the second power supply respectively to obtain a comparison result, and controlling the second power supply establishment module to establish the second power supply according to the comparison result.
In some embodiments, the first power supply setup module includes: the device comprises a level conversion module, a first inverter, a first comparison module, a first MOS tube, a second MOS tube, a third MOS tube and a second inverter; the input end of the level conversion module is respectively connected with a first power-on reset signal, a first power signal and a second power signal, and the output end of the level conversion module is connected with the input end of the first inverter; the output end of the first inverter is connected with the input end of the first comparison module, and the output end of the first comparison module is connected with the first end of the second MOS tube and the second end of the third MOS tube; the input end of the second inverter is connected with the output end of the first inverter, the output end of the second inverter is connected with the first end of the first MOS tube, the second end of the first MOS tube is connected with the first node, the third end of the first MOS tube is connected with the second end of the second MOS tube, the third end of the second MOS tube is connected with the third end of the third MOS tube, and the first end of the third MOS tube is connected with the output end of the first inverter; the first comparison module is used for comparing the voltage between the first node and the first power supply to obtain a first control signal, and the first control signal is used for controlling the on and off of the second MOS tube.
In some embodiments, the power comparison module comprises: the logic processing module is respectively connected with the second comparison module and the third comparison module of the logic processing module; the second comparison module is used for comparing the voltage of the second node with the voltage of the second power supply to obtain a first comparison result; the third comparison module is used for comparing the voltage of the second node with the voltage of the first power supply to obtain a second comparison result; the logic processing module is used for obtaining a second control signal according to the first comparison result and the second comparison result, and the second control signal is used for controlling the second power supply building module to build the second power supply.
In some embodiments, the second comparison module comprises: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; the second end of the fourth MOS tube is connected with the second power supply through an adjusting resistor, the first end of the fourth MOS tube is connected with the first end of the fifth MOS tube, and the first end and the third end of the fourth MOS tube are connected; the second end of the fifth MOS tube is connected with the second node and the first end of the sixth MOS tube, and the second end of the sixth MOS tube is connected with the third end of the fourth MOS tube; the first end of the seventh MOS tube is connected with a hysteresis control signal, the second end of the seventh MOS tube is connected with the third end of the fifth MOS tube, and the third end of the fifth MOS tube outputs the first comparison result; the third end of the sixth MOS tube, the third end of the seventh MOS tube and the third end of the fifth MOS tube are all connected with a bias current source.
In some embodiments the third comparison module comprises: eighth MOS tube, ninth MOS tube, tenth MOS tube, eleventh MOS tube, twelfth MOS tube, thirteenth MOS tube, fourteenth MOS tube; the first end of the eighth MOS tube, the first end of the ninth MOS tube and the second end of the eleventh MOS tube are all connected with the second node, the second end of the eighth MOS tube and the second end of the tenth MOS tube are all connected with the first power supply, and the third end of the eighth MOS tube, the second end of the ninth MOS tube, the second end of the tenth MOS tube, the first end of the tenth MOS tube and the first end of the eleventh MOS tube are all connected; the third end of the eleventh MOS tube is connected with the first end of the twelfth MOS tube, the first end of the thirteenth MOS tube and the second end of the fourteenth MOS tube, the second end of the twelfth MOS tube is connected with the first power supply, and the third end of the twelfth MOS tube is connected with the second end of the thirteenth MOS tube; an output node is arranged between the third end of the twelfth MOS tube and the second end of the thirteenth MOS tube, and the output node outputs the second comparison result; the output node is also connected to the first end of the fourteenth MOS tube; the third end of the ninth MOS tube, the third end of the eleventh MOS tube and the third end of the fourteenth MOS tube are all connected with a bias current source.
In some embodiments, the second power supply setup module includes: the output end of the switch control module is connected with the input end of the clamping module; the switch control module is used for controlling the circuit conduction between the third node and the second power supply according to the second control signal and the second power supply power-on reset signal so as to generate the second power supply; the clamping module is used for clamping the second power supply at a target voltage value.
In some embodiments, the switch control module includes a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, and a nand gate; the first end of the fifteenth MOS tube, the second end of the sixteenth MOS tube and the first end of the seventeenth MOS tube are connected, the third end of the fifteenth MOS tube, the third end of the sixteenth MOS tube and the second end of the seventeenth MOS tube are connected with the third node, the first end of the sixteenth MOS tube is connected with the second control signal, the third end of the seventeenth MOS tube is connected with the second end of the eighteenth MOS tube, the first end of the eighteenth MOS tube is connected with the output end of the NAND gate, and the input end of the NAND gate is connected with the second control signal and the second power-on reset signal; and the third end of the eighteenth MOS tube outputs the second power supply.
In some embodiments, the second power supply setup module further comprises: the MOS transistor comprises an AND gate, a fifteenth MOS transistor, a first pull-down module, a second pull-down module and a current mirror module; the input end of the AND gate is connected with a switching signal and a first power supply power-on reset signal, the output end of the AND gate is connected with the first end of the fifteenth MOS tube, the second end of the fifteenth MOS tube is connected with the second pull-down module, the third end of the fifteenth MOS tube is connected with the first end of the first pull-down module, the second end of the first pull-down module is grounded, the third end of the first pull-down module is connected with the current mirror module, the current mirror module is connected with the switch control module and is used for providing working current for the switch control module, and the current mirror module is also connected with the first pull-down module.
In some embodiments, the second pull-down module includes a nineteenth MOS transistor and a twentieth MOS transistor, a first end of the nineteenth MOS transistor is connected to the second control signal, a second end of the nineteenth MOS transistor is connected to the first end of the twentieth MOS transistor, a third end of the nineteenth MOS transistor and a second end of the twentieth MOS transistor are connected to the third node, and a third end of the twentieth MOS transistor is grounded.
In a second aspect, there is also provided a chip comprising the power supply circuit of any one of the first aspects.
In a third aspect, there is also provided an electronic device comprising the power supply circuit of any one of the first aspects.
Overall, the present application has at least the following benefits:
the power supply circuit provided by the application establishes a first power supply driving chip to work through a first power supply establishing module; comparing the voltage of the second node with the voltage of the first power supply and the voltage of the second power supply respectively through a power supply comparison module to obtain a comparison result, and controlling a second power supply building module to build the second power supply according to the comparison result; establishing a second power supply VDD3P3 through a second power supply establishing module to provide working voltage for the chip to perform protocol interaction; and then can satisfy the power supply of the normal work power supply of chip and the power supply when the agreement is mutual, when supplying power for the agreement of chip is mutual, prevent that the power node of second node department from drawing the electric current of second power department, avoid the electric current to flow backward, avoid the chip to appear losing the power phenomenon when the agreement is mutual, also can not influence the first power simultaneously and supply power for the normal work of chip.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope. Also, like reference numerals are used to designate like parts throughout the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a power supply circuit provided in an embodiment of the present application;
fig. 2 shows a schematic circuit structure of a first power supply building module according to an embodiment of the present application;
fig. 3 shows a schematic structural diagram of a power comparison module provided in an embodiment of the present application;
fig. 4 shows a schematic circuit structure of a second comparison module according to an embodiment of the present application;
fig. 5 shows a schematic circuit structure of a third comparison module according to an embodiment of the present application;
fig. 6 shows a schematic circuit structure of a logic processing module according to an embodiment of the present application;
fig. 7 shows a schematic circuit structure of a second power supply building module according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a chip according to an embodiment of the present disclosure;
Fig. 9 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present application, and thus are only examples, and are not intended to limit the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions.
In the description of the embodiments of the present application, the technical terms "first," "second," etc. are used merely to distinguish between different objects and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, a particular order or a primary or secondary relationship. In the description of the embodiments of the present application, the meaning of "plurality" is two or more unless explicitly defined otherwise.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two), and similarly, "plural sets" refers to two or more (including two), and "plural sheets" refers to two or more (including two).
In the description of the embodiments of the present application, the orientation or positional relationship indicated by the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of describing the embodiments of the present application and for simplifying the description, rather than indicating or implying that the apparatus or element referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present application.
In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; or may be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to the specific circumstances.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
At present, from the development of market situation, the application of the chip is wider, the chip is connected with an external power supply through a power supply pin, and after the power supply enters the chip, the power supply is required to supply power for the normal operation of the chip, and the power supply is required to supply power for the protocol interaction of the chip when the chip and other equipment are in protocol interaction. However, when the chip performs protocol interaction, the chip is easy to generate a power failure problem, especially when the single-wire protocol interaction chip performs protocol interaction, the situation that the power supply flows backwards to draw current is easy to generate a power failure phenomenon in the protocol interaction process.
For convenience of explanation, the following embodiment will be explained by taking the chip as a single-wire protocol interaction chip as an example.
Example 1
Fig. 1 shows a schematic structural diagram of a power supply circuit provided in an embodiment of the present application, and referring to fig. 1, the embodiment of the present application provides a power supply circuit including: the power supply AVIN, the first power supply establishing module 101, the second power supply establishing module 103 and the power supply comparing module 102. The power supply AVIN is connected with the first power supply building module 101 through the first node AVIN3, the power supply AVIN is connected with the power supply comparison module 102 through the second node AVIN2, and the power supply is connected with the second power supply building module 103 through the third node AVIN4, so that the power supply AVIN can be divided into 3 paths, and further, the power supply AVIN can supply power for the work of the chip and the power supply for the protocol interaction of the chip respectively through different branches.
The power supply comparison module 102 is respectively connected with the first power supply establishment module 101 and the second power supply establishment module 103 through different connection ports, wherein the first power supply establishment module 101 is used for establishing a first power supply VDD2P0, and the first power supply VDD2P0 is used for driving the chip to work; the second power supply establishing module 103 is configured to establish a second power supply VDD3P3, where the second power supply VDD3P3 is configured to provide an operating voltage for the chip to perform protocol interaction; the power comparison module 102 is configured to compare the voltage of the second node AVIN2 with the voltage of the first power supply VDD2P0 and the voltage of the second power supply VDD3P3 respectively, obtain a comparison result, and control the second power supply building module 103 to build the second power supply VDD3P3 according to the comparison result, so as to realize that the power supply AVIN flows through the second node AVIN2 to supply power for the protocol of the chip in an interactive manner under the condition that the voltage of the AVIN2 is greater than the voltage of the first power supply VDD2P0 and greater than the voltage of the second power supply VDD3P3, and at this time, because the current of the second node AVIN2 is greater, the power supply node at the second node AVIN2 can be prevented from extracting the current of the second power supply VDD3P3, thereby avoiding current backflow and not affecting the first power supply VDD2P0 to supply power for the normal operation of the chip. That is, the power supply circuit of the embodiment of the application can simultaneously meet the normal work power supply of the chip and the power supply during protocol interaction, and can avoid the power failure phenomenon of the chip during protocol interaction.
In this embodiment, a resistor R11 is further disposed between the power supply AVIN and the first node AVIN3, a resistor R10 is further disposed between the power supply AVIN and the second node AVIN2, a resistor R12 is further disposed between the power supply AVIN and the third node AVIN4, and resistance values of R11, R10 and R12 can be set according to circuit requirements, so as to generate currents with different requirements.
Fig. 2 is a schematic circuit diagram of a first power supply building module according to an embodiment of the present application, and referring to fig. 2, the first power supply building module 101 includes: the Level Shift module Level Shift1, the first inverter INV1, the first comparison module 1010, the first MOS transistor PM18, the second MOS transistor PM19, the third MOS transistor PM20, and the second inverter INV0.
The input end of the Level Shift1 is connected to the first power-on reset signal vdd_por, the first power supply VDD2P0 and the second power supply VDD3P3, respectively, and is used for converting the input voltage into the working voltage of the first power supply building module 101, the output end of the Level Shift1 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the first comparison module 1010, and the output end of the first comparison module 1010 is connected to the first end of the second MOS tube PM19 and the second end of the third MOS tube PM 20.
The input end of the second inverter INV0 is connected with the output end of the first inverter INV1, the signal output by the output end of the first inverter INV1 is vdd_por_n3, the output end of the second inverter INV0 is connected with the first end of the first MOS tube PM18, the signal output by the output end of the second inverter INV0 is vdd_por_p3, the second end of the first MOS tube PM18 is connected with the first node AVIN3, the third end of the first MOS tube PM18 is connected with the second end of the second MOS tube PM19, the third end of the second MOS tube PM19 is connected with the third end of the third MOS tube PM20, and the first end of the third MOS tube PM20 is connected with the output end of the first inverter INV1 to receive vdd_por_n3.
The first comparison module 1010 is configured to compare the voltage between the first node AVIN3 and the first power supply VDD2P0 to obtain a first control signal, where the first control signal is used to control on and off of the second MOS tube PM 19.
As shown in fig. 2, the first comparing module 1010 includes switching transistors NM26 and NM27, current limiting resistors R8 and R9, and comparing MOS transistors PM16 and PM17, wherein a first end of NM26 and a first end of NM27 are both connected to an output end of the first inverter INV1, a second end of NM26 and a second end of NM27 are grounded, a third end of NM26 is connected to a third end of PM16 through R8, a third end of NM27 is connected to a third end of PM17 through R9, a first end of PM16 is connected to a first end of PM17, a second end of PM16 is connected to a first node AVIN3, a second end of PM17 is connected to a first power supply VDD2P0, the first comparing module 1010 forms a comparator, outputs a first control signal through the third end of PM17, and the first control signal may be a high level or a low level.
The circuit principle of the first power supply building block will be described below.
In order to ensure that the chip can normally supply power inside during the protocol transceiving process, in this embodiment, an electric storage capacitor (not shown in the figure) is added outside the VDD2P0, meanwhile, the power-on state of the VDD2P0 needs to be subjected to POR power-on reset detection, the POR power-on reset detection can be performed by a power-on reset detection module, the power-on reset detection module outputs a power-on reset detection signal vdd_por, and when the VDD2P0 is built, the power-on reset detection is completed, the vdd_por is turned to be high, i.e. the vdd_por at the input end of the Level Shift1 is at a high Level.
In the early stage of chip power-up, VDD2P0 is not yet established, and in order to enable VDD2P0 to be established quickly, the embodiment of the present application provides a first power-supply establishing module 101 as shown in fig. 2, so as to charge the storage capacitor of VDD2P0 quickly. Specifically, when VDD2P0 has not been established, vdd_por is 0, the output terminal vdd_por_n3 of the first inverter INV1 is inverted to 1, so that NM26 and NM27 of the first comparing module 1010 are turned on, and the voltages of AVIN3 and VDD2P0 are compared, so VDD2P0 has not been established, VDD2P0 is 0, and the comparison result of the first comparing module 1010 is 0, and pm19 is turned on. Vdd_por_n3 is 1, so that PM20 is turned off. Meanwhile, since vdd_por_n3 is 1, the output signal vdd_por_p3 of the second inverter INV0 is turned to 0, and thus PM18 is turned on, i.e. two devices PM18 and PM19 on the path from AVIN3 to VDD2P0 are turned on, AVIN3 starts to charge the external storage capacitor at the end of VDD2P0, and the first power supply VDD2P0 is established.
The first power supply establishing module provided in this embodiment identifies that VDD2P0 is not established by comparing the magnitude relation between the first node AVIN3 and the first power supply VDD2P0, so as to rapidly establish the first power supply VDD2P0, and ensure that the chip can normally supply power when receiving and transmitting a protocol.
Fig. 3 is a schematic structural diagram of a power comparison module according to an embodiment of the present application, and referring to fig. 3, the power comparison module 102 includes: the logic processing module 1023 is connected with the second comparison module 1021 and the third comparison module 1022 of the logic processing module 1023 respectively; the second comparing module 1021 is configured to compare the voltage levels of the second node AVIN2 and the second power supply VDD3P3 to obtain a first comparison result VDD1_low_avin_h, and the third comparing module 1022 is configured to compare the voltage levels of the second node AVIN2 and the first power supply VDD2P0 to obtain a second comparison result avin_low_vdd_h; the logic processing module 1023 is configured to obtain a second control signal avin_ok_n according to the first comparison result vdd1_low_avin_h and the second comparison result avin_low_vdd_h, where the second control signal avin_ok_n is configured to control the second power supply building module 103 to build the second power supply VDD3P3.
The power comparison module 102 of the present embodiment can determine the establishment of the two power supplies VDD2P0 and VDD3P3, and compare the voltage levels of the second node AVIN2 and VDD2P0 and VDD3P3, respectively, so as to establish the second power supply VDD3P3 through the second node AVIN2 when the voltage of the second node AVIN2 is greater than VDD2P0 and greater than VDD3P3.
Fig. 4 is a schematic circuit diagram of a second comparing module according to an embodiment of the present application, referring to fig. 4, the second comparing module 1021 includes: the second end of the fourth MOS tube PM10 is connected with the second power supply VDD3P3 through the adjusting resistor R7, the first end of the fourth MOS tube PM10 is connected with the first end of the fifth MOS tube PM11, and the first end and the third end of the fourth MOS tube PM10 are connected.
The second end of the fifth MOS tube PM11 is connected with the second node AVIN2 and the first end of the sixth MOS tube NM10, the second end of the sixth MOS tube is connected with the third end of the fourth MOS tube, the first end of the seventh MOS tube NM12 is connected with the hysteresis control signal AVIN_OK_P, the second end of the seventh MOS tube NM12 is connected with the third end of the fifth MOS tube PM11, and the third end of the fifth MOS tube PM11 outputs a first comparison result VDD1_LOW_AVIN_H.
The third end of the sixth MOS transistor NM10, the third end of the seventh MOS transistor NM12, and the third end of the fifth MOS transistor PM11 are all connected to BIAS current sources, as shown in fig. 4, NM10 is connected to BIAS current BIAS through the MOS transistor NM11, NM12 is connected to BIAS current BIAS through the MOS transistor NM14, PM11 is connected to BIAS current BIAS through the MOS transistor NM16, and NM11, NM14, and NM16 are used for providing BIAS current for the second comparison module.
The circuit principle of the second comparing module 1021 is described below.
NM12 is a switch tube, AVIN_OK_P is a hysteresis control signal for comparator hysteresis control, PM10 and PM11 are comparison tubes, a comparison point can be adjusted by adjusting R7 resistance, NM10 is a switch tube, the second comparison module 1021 starts to compare only when AVIN2 is higher than a preset value, when AVIN2 is higher than VDD3P3, AVIN2 is high, VDD1_LOW_AVIN_H is high, when VDD3P3 is higher than AVIN2, VDD3P3 is high, VDD1_LOW_AVIN_H is LOW.
Fig. 5 is a schematic circuit diagram of a third comparing module 1022 according to an embodiment of the present application, and referring to fig. 5, the third comparing module 1022 includes: eighth MOS transistor PM12, ninth MOS transistor NM17, tenth MOS transistor PM13, eleventh MOS transistor PM14, twelfth MOS transistor PM15, thirteenth MOS transistor NM24, fourteenth MOS transistor NM20.
The first end of the eighth MOS transistor PM12, the first end of the ninth MOS transistor NM17 and the second end of the eleventh MOS transistor PM14 are all connected to the second node, the second end of the eighth MOS transistor PM12 and the second end of the tenth MOS transistor PM13 are all connected to the first power supply, and the third end of the eighth MOS transistor PM12, the second end of the ninth MOS transistor NM17, the second end of the tenth MOS transistor PM13, the first end of the tenth MOS transistor PM13 and the first end of the eleventh MOS transistor PM14 are all connected. The third end of the eleventh MOS transistor PM14 is connected to the first end of the twelfth MOS transistor PM15, the first end of the thirteenth MOS transistor NM24, and the second end of the fourteenth MOS transistor NM20, the second end of the twelfth MOS transistor PM15 is connected to the first power supply VDD2P0, and the third end of the twelfth MOS transistor PM15 is connected to the second end of the thirteenth MOS transistor NM 24. An output node is provided between the third end of the twelfth MOS transistor PM15 and the second end of the thirteenth MOS transistor NM24, and the output node outputs the second comparison result avin_low_vdd_h. The output node is also connected to a first end of a fourteenth MOS transistor NM20. The third end of the ninth MOS transistor NM17, the third end of the eleventh MOS transistor PM14, and the third end of the fourteenth MOS transistor NM20 are all connected to a bias current source. As shown in fig. 5, NM17 is connected to BIAS current BIAS through a MOS transistor NM18, PM14 is connected to BIAS current BIAS through a MOS transistor NM19, NM20 is connected to BIAS current BIAS through a MOS transistor NM22, and NM18, NM19, NM22 are used to provide BIAS current for the third comparing module 1022.
The circuit principle of the third comparing module 1022 will be described.
NM17 and PM12 are switch tubes, NM20 is feedback switch tube, the third comparison module 1022 starts to compare only when AVIN2 is higher than the preset value, PM13 and PM14 are comparison tubes, PM15 and NM24 are output integral tubes, when AVIN2 is higher than VDD2P0, AVIN2 is high level, AVIN_LOW_VDD_H is output as LOW level, when VDD2P0 is higher than AVIN2, VDD2P0 is high level, AVIN_LOW_VDD_H is output as high level.
In one example, the logic processing module 1023 is configured to obtain the second control signal avin_ok_n according to the first comparison result vdd1_low_avin_h and the second comparison result avin_low_vdd_h.
Fig. 6 is a schematic circuit diagram of a logic processing module according to an embodiment of the present application, AND referring to fig. 6, a logic processing module 1023 may include a Level Shift2, an AND gate AND0, a NAND gate 3NAND0, AND an inverter INV2, which are sequentially connected. The first comparison result VDD1_low_avin_h and the second comparison result avin_low_vdd_h are processed by the logic processing module 1023, and then output the second control signal avin_ok_n.
The Level Shift2 is connected to a first power-on reset signal vdd_por, a first power supply VDD2P0 AND a second power supply VDD3P3, AND is used for converting an input voltage into a logic processing module 1023 working voltage, vdd_por_3p3 is a second power supply VDD3P3 power-on reset signal, lvsf_vdd3p3_enp is a logic processing module 1023 working voltage enable signal, vdd_por_3p3 AND lvsf_vdd3p3_enp are subjected to AND gate AND0 to obtain VDD1_del_n, the first comparison result VDD1_low_avin_ H, VDD1_del_n, AND the signal vdd_por_p3 output by the output end of the second inverter inv0 are subjected to NAND gate 3NAND0 to obtain signal avin_ok_p, AND avin_ok_p is subjected to inverter INV2 to obtain avin_ok_n.
Fig. 7 is a schematic circuit diagram of a second power supply building module according to an embodiment of the present application, and referring to fig. 7, the second power supply building module 103 includes: the output end of the switch control module 1034 is connected with the input end of the clamp module 1035, and the switch control module 1034 is used for controlling the circuit conduction between the third node and the second power supply according to the second control signal avin_ok_n and the second power supply power-on reset signal vdd_por_3p3 to generate a second power supply VDD3P3, so that the chip is powered under the protocol interaction state. The clamping module 1035 is configured to clamp the second power supply to a target voltage value, thereby preventing the chip from being powered down in the protocol interaction process.
The second power-on reset signal vdd_por_3p3 is obtained according to whether the second power supply VDD3P3 is powered on.
Referring to fig. 7, the switch control module 1034 includes a fifteenth MOS transistor PM4, a sixteenth MOS transistor PM5, a seventeenth MOS transistor PM6, an eighteenth MOS transistor PM7, and a NAND gate NAND1;
the first end of the fifteenth MOS tube PM4, the second end of the sixteenth MOS tube PM5 and the first end of the seventeenth MOS tube PM6 are connected, the third end of the fifteenth MOS tube PM4, the third end of the sixteenth MOS tube PM5 and the second end of the seventeenth MOS tube PM6 are connected with a third node AVIN4, the first end of the sixteenth MOS tube PM5 is connected with a second control signal AVIN_OK_N, the third end of the seventeenth MOS tube PM6 is connected with the second end of the eighteenth MOS tube PM7, the first end of the eighteenth MOS tube PM7 is connected with the output end of the NAND gate NAND1, the input end of the NAND gate NAND1 is connected with a second control signal AVIN_OK_N and a second power-on reset signal VDD_POR_3P3, and the third end of the eighteenth MOS tube PM7 outputs a second power supply VDD3P3.
The circuit principle of the above-described switch control module 1034 is explained below.
PM6, PM7 are the switch tubes of AVIN4 to VDD3P3 passageway, in order to prevent the gate voltage of PM6 from receiving the influence of AVIN4, carry out the clamp to the gate voltage of PM6 through PM4, namely PM4 is VSG clamp tube, PM5 is the switch tube, PM 5's break-make is by AVIN_OK_N control, PM 7's break-make is by the signal control of second control signal AVIN_OK_N and second power on reset signal VDD_POR_3P3 after NAND 1's output, and then can make only when AVIN4 is high, and AVIN4 is higher than VDD3P3 and VDD2P0, PM6 and PM7 just switch on, and then establish second power VDD3P3 through AVIN 4.
Referring to fig. 7, the clamping module in this embodiment may include MOS transistors PM8, PM9, and NM9, the resistors R4, R5, and R6 are connected to the first end and the third end of the PM8, the second end of the PM8 is connected to VDD3P3, the third end of the PM8 is connected to the second end of the PM9, the first end of the PM9 is connected to one end of the resistor R6, the other end of the R6 is connected to VDD2P0, one end of the R6 is grounded through D0, the third end of the PM9 is connected to the second end of the NM9 through R4, the first end of the NM9 is grounded through R5, and the third end of the NM9 is grounded.
In an example, referring to fig. 7, two PMOS transistors are different between vddi 3P3 and VDD2P0, the target voltage value in this embodiment may be vdd2p0+2×vsg, where vsg is the turn-on voltage of PM8 and PM 9.
Referring to fig. 7, the second power supply establishment module 103 further includes: the power-on reset circuit comprises an AND gate AND1, a fifteenth MOS tube NM2, a first pull-down module 1031, a second pull-down module 1032 AND a current mirror module 1033, wherein the input end of the AND gate AND1 is connected with a switch signal SW2 AND a first power-on reset signal VDD_POR, the output end of the AND gate AND1 is connected with the first end of the fifteenth MOS tube NM2, the second end of the fifteenth MOS tube NM2 is connected with the second pull-down module 1032, the third end of the fifteenth MOS tube NM2 is connected with the first end of the first pull-down module 1031, the second end of the first pull-down module 1031 is grounded, the third end of the first pull-down module 1031 is connected with the current mirror module 1033, AND the current mirror module 1033 is connected with the switch control module 1034 AND used for providing working current for the switch control module 1034.
In this embodiment, NM2 is a switching tube, AND the AND gate AND1 is configured to output a control signal of NM2 according to SW2 AND vdd_por, so that when SW2 AND vdd_por are both at a high level, NM2 is triggered to be turned on, AND the second power supply setup module 103 is triggered to operate.
The first pull-down module 1031 is configured to provide a weak pull-down function for the second power supply building module when protocol interactive power is not required, so that AVIN4 is low. In one example, the first pull-down module 1031 may include MOS transistors NM1, NM4, NM6, NM7, NM8 as shown in fig. 7.
The second pull-down module 1032 is a power-down pull-down module, and can increase the power-down speed of the AVIN4 when the power of the AVIN4 is lost. Referring to fig. 7, the second pull-down module 1032 includes a nineteenth MOS transistor PM0 and a twentieth MOS transistor PM21, a first end of the nineteenth MOS transistor PM0 is connected to the second control signal avin_ok_n, a second end of the nineteenth MOS transistor PM0 is connected to the first end of the twentieth MOS transistor PM21, a third end of the nineteenth MOS transistor PM0 and a second end of the twentieth MOS transistor PM21 are connected to the third node AVIN4, and a third end of the twentieth MOS transistor PM21 is grounded.
PM0 and PM21 of the embodiment can realize the pull-down function of AVIN4 under the control of AVIN_OK_N when the chip is powered down, so that the power-down speed of the chip is increased.
The current mirror module 1033 may include mirror current pipes PM1, PM2, PM3 and switching threshold control resistors R1, R2, R3, and may change the current of each branch in the current mirror module by changing the resistance values of R1, R2, R3, and the current mirror module may provide the current to the switching control module.
The second power supply establishing module provided in this embodiment may provide a weak pull-down function for the second power supply establishing module through the first pull-down module 1031 when the chip does not need protocol interaction power supply. When the chip is powered down through the second pull-down module 1032, the power-down speed of the chip is increased. The current is provided to the switch control module by a current mirror module 1033. The second power supply VDD3P3 is established through the switch control module 1034, and the voltage value of the VDD3P3 is clamped at the target voltage value through the clamping module 1035, so that the chip can perform protocol interaction during normal operation, and the phenomenon of power failure of the chip during protocol interaction can be avoided.
Example two
Based on the same concept as the pull-down resistor control system, the present embodiment also provides a chip, and referring to fig. 8, the chip 40 includes the power supply circuit 10 according to the first embodiment.
Specifically, the chip may be a dedicated chip including the above discrete devices, or may be an MCU integrated chip.
The chip 40 provided in this embodiment is based on the same concept as the power supply circuit, so at least the beneficial effects that the power supply circuit can achieve can be achieved, and any implementation of the power supply circuit can be applied to the chip provided in this embodiment, which is not described herein again.
Example III
Based on the same concept of the pull-down resistor control system, referring to fig. 9, the present embodiment further provides an electronic device 50, including the power supply circuit 10 described in the first embodiment.
The electronic device provided in this embodiment is based on the same concept of the power supply circuit, so at least the beneficial effects that the power supply circuit can achieve can be achieved, and any implementation of the power supply circuit can be applied to the electronic device provided in this embodiment, which is not described herein.
It should be noted that:
in the above text, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
The embodiments of the present application have been described above with reference to the accompanying drawings, which are only specific embodiments of the present application, but the present application is not limited to the above-described embodiments, which are only illustrative and not restrictive, and many forms can be made by one of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are protected by the present application.

Claims (11)

1. A power supply circuit, the power supply circuit comprising: the power supply system comprises a power supply source, a first power supply establishing module, a second power supply establishing module and a power supply comparing module;
the power supply is connected with the first power supply building module through a first node, the power supply is connected with the power supply comparison module through a second node, the power supply is connected with the second power supply building module through a third node, and the power supply comparison module is respectively connected with the first power supply building module and the second power supply building module through different connection ports;
the first power supply establishment module is used for establishing a first power supply, and the first power supply is used for driving the chip to work; the second power supply establishing module is used for establishing a second power supply, and the second power supply is used for providing working voltage for the protocol interaction of the chip; the power supply comparison module is used for comparing the voltage of the second node with the voltage of the first power supply and the voltage of the second power supply respectively to obtain a comparison result, and controlling the second power supply establishment module to establish the second power supply according to the comparison result.
2. The power supply circuit of claim 1, wherein the first power supply establishing module comprises: the device comprises a level conversion module, a first inverter, a first comparison module, a first MOS tube, a second MOS tube, a third MOS tube and a second inverter;
the input end of the level conversion module is respectively connected with a first power-on reset signal, a first power signal and a second power signal, and the output end of the level conversion module is connected with the input end of the first inverter; the output end of the first inverter is connected with the input end of the first comparison module, and the output end of the first comparison module is connected with the first end of the second MOS tube and the second end of the third MOS tube;
the input end of the second inverter is connected with the output end of the first inverter, the output end of the second inverter is connected with the first end of the first MOS tube, the second end of the first MOS tube is connected with the first node, the third end of the first MOS tube is connected with the second end of the second MOS tube, the third end of the second MOS tube is connected with the third end of the third MOS tube, and the first end of the third MOS tube is connected with the output end of the first inverter;
The first comparison module is used for comparing the voltage between the first node and the first power supply to obtain a first control signal, and the first control signal is used for controlling the on and off of the second MOS tube.
3. The power supply circuit of claim 1, wherein the power comparison module comprises: the logic processing module is respectively connected with the second comparison module and the third comparison module of the logic processing module;
the second comparison module is used for comparing the voltage of the second node with the voltage of the second power supply to obtain a first comparison result;
the third comparison module is used for comparing the voltage of the second node with the voltage of the first power supply to obtain a second comparison result;
the logic processing module is used for obtaining a second control signal according to the first comparison result and the second comparison result, and the second control signal is used for controlling the second power supply building module to build the second power supply.
4. A power supply circuit according to claim 3, wherein the second comparison module comprises: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube;
the second end of the fourth MOS tube is connected with the second power supply through an adjusting resistor, the first end of the fourth MOS tube is connected with the first end of the fifth MOS tube, and the first end and the third end of the fourth MOS tube are connected;
The second end of the fifth MOS tube is connected with the second node and the first end of the sixth MOS tube, and the second end of the sixth MOS tube is connected with the third end of the fourth MOS tube;
the first end of the seventh MOS tube is connected with a hysteresis control signal, the second end of the seventh MOS tube is connected with the third end of the fifth MOS tube, and the third end of the fifth MOS tube outputs the first comparison result;
the third end of the sixth MOS tube, the third end of the seventh MOS tube and the third end of the fifth MOS tube are all connected with a bias current source.
5. A power supply circuit according to claim 3, wherein the third comparison module comprises: eighth MOS tube, ninth MOS tube, tenth MOS tube, eleventh MOS tube, twelfth MOS tube, thirteenth MOS tube, fourteenth MOS tube;
the first end of the eighth MOS tube, the first end of the ninth MOS tube and the second end of the eleventh MOS tube are all connected with the second node, the second end of the eighth MOS tube and the second end of the tenth MOS tube are all connected with the first power supply, and the third end of the eighth MOS tube, the second end of the ninth MOS tube, the second end of the tenth MOS tube, the first end of the tenth MOS tube and the first end of the eleventh MOS tube are all connected;
The third end of the eleventh MOS tube is connected with the first end of the twelfth MOS tube, the first end of the thirteenth MOS tube and the second end of the fourteenth MOS tube, the second end of the twelfth MOS tube is connected with the first power supply, and the third end of the twelfth MOS tube is connected with the second end of the thirteenth MOS tube; an output node is arranged between the third end of the twelfth MOS tube and the second end of the thirteenth MOS tube, and the output node outputs the second comparison result; the output node is also connected to the first end of the fourteenth MOS tube;
the third end of the ninth MOS tube, the third end of the eleventh MOS tube and the third end of the fourteenth MOS tube are all connected with a bias current source.
6. The power supply circuit of claim 3, wherein the second power supply establishing module comprises: the output end of the switch control module is connected with the input end of the clamping module;
the switch control module is used for controlling the circuit conduction between the third node and the second power supply according to the second control signal and the second power supply power-on reset signal so as to generate the second power supply;
The clamping module is used for clamping the second power supply at a target voltage value.
7. The power supply circuit of claim 6, wherein the switch control module comprises a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, and a nand gate;
the first end of the fifteenth MOS tube, the second end of the sixteenth MOS tube and the first end of the seventeenth MOS tube are connected, the third end of the fifteenth MOS tube, the third end of the sixteenth MOS tube and the second end of the seventeenth MOS tube are connected with the third node, the first end of the sixteenth MOS tube is connected with the second control signal, the third end of the seventeenth MOS tube is connected with the second end of the eighteenth MOS tube, the first end of the eighteenth MOS tube is connected with the output end of the NAND gate, and the input end of the NAND gate is connected with the second control signal and the second power-on reset signal;
and the third end of the eighteenth MOS tube outputs the second power supply.
8. The power supply circuit of claim 6 or 7, wherein the second power supply establishment module further comprises: the MOS transistor comprises an AND gate, a fifteenth MOS transistor, a first pull-down module, a second pull-down module and a current mirror module;
The input end of the AND gate is connected with a switching signal and a first power supply power-on reset signal, the output end of the AND gate is connected with the first end of the fifteenth MOS tube, the second end of the fifteenth MOS tube is connected with the second pull-down module, the third end of the fifteenth MOS tube is connected with the first end of the first pull-down module, the second end of the first pull-down module is grounded, the third end of the first pull-down module is connected with the current mirror module, the current mirror module is connected with the switch control module and is used for providing working current for the switch control module, and the current mirror module is also connected with the first pull-down module.
9. The power supply circuit of claim 8, wherein the second pull-down module comprises a nineteenth MOS transistor and a twentieth MOS transistor, a first end of the nineteenth MOS transistor is connected to the second control signal, a second end of the nineteenth MOS transistor is connected to the first end of the twentieth MOS transistor, a third end of the nineteenth MOS transistor and a second end of the twentieth MOS transistor are connected to the third node, and a third end of the twentieth MOS transistor is grounded.
10. A chip, characterized in that it comprises a supply circuit according to any one of claims 1-9.
11. An electronic device, characterized in that it comprises the supply circuit according to any one of claims 1-9.
CN202311717155.2A 2023-12-14 2023-12-14 Chip, power supply circuit thereof and electronic equipment Active CN117406847B (en)

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